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general description the MAX98372 is a high-efficiency, mono class d audio amplifier featuring dynamic headroom tracking (dht) and brownout protection. dht automatically optimizes the headroom available to the class d amplifier as the power supply voltage varies, due to sudden transients and declining battery life to maintain a consistent listening experience. a wide 5.5v to 18v supply range allows the device to reach 19w into an 8? load. the MAX98372s flexible digital audio interface (dai) supports i 2 s, left-justified, and tdm formats. the digital audio interface accepts 32khz, 44.1khz, 48khz, 88.2khz, and 96khz sample rates with 16-/24-/32-bit data sup - ported for all data formats. in tdm mode, the device can support up to 16 channels of audio data. a unique clock - ing structure eliminates the need for an external mclk signal that is typically needed for pcm communication. this reduces pin count and simplifies board layout. active emissions limiting with edge rate control minimizes emi and eliminates the need for output filtering found in traditional class d devices. an 8-bit pvdd supply voltage adc enables the dynamic headroom tracking circuit. dht optimizes audio program peak behavior as the supply voltage varies and provides flexible user-defined parameters. thermal foldback protection ensures robust behavior when the thermal limits of the device are exercised. the circuit can be enabled to automatically reduce the output power above a user specified temperature. this allows for uninterrupted music playback even at high ambient tem - peratures. traditional thermal protection is also available in addition to robust overcurrent protection. all MAX98372 control is performed using a standard 2-wire, i 2 c interface. one of sixteen slave addresses can be selected through two, four-level address pins. the ic is available in a 0.4mm pitch, 30-bump wlp package. it is specified over the extended, -40c to +85c temperature range. applications tablets notebook computers soundbars beneits and features wide supply range (5.5v to 18v) dynamic headroom tracking maintains a consistent listening experience integrated thermal foldback allows robust operation in a wlp package remote output sensing allows up to 20db thd+n improvement when ferrites are used class d edge rate control enables filterless operation 110db a-weighted dynamic range output power at 1% thd+n: ? 15.7w into 8, v pvdd = 17v ? 13.2w into 4, v pvdd = 12v output power at 10% thd+n ? 19w into 8, v pvdd = 17v ? 15.8w into 4, v pvdd = 12v speaker amplifier efficiency ? 91% at 10w into 8, v pvdd = 12v ? 81% at 15w into 4, v pvdd = 12v alc provides battery brownout protection extensive click-and-pop suppression space saving, 30-bump wlp package (2.2mm x 2.8mm x 0.6mm, 0.4mm pitch) 19-7734; rev 1; 1/16 ordering information appears at end of data sheet. dvdd i 2 c digital audio interface dac class d MAX98372 d v o l dht pvdd thermal foldback dsp p g a alc simpliied block diagram MAX98372 digital input class d amplifier with dht and brownout protection evaluation kit available downloaded from: http:///
www.maximintegrated.com maxim integrated 2 MAX98372 digital input class d ampliier with dht and brownout protection table of contents general description ............................................................................ 1 applications .................................................................................. 1 benefits and features .......................................................................... 1 simplified block diagram ........................................................................ 1 detailed functional diagram ..................................................................... 6 absolute maximum ratings ...................................................................... 7 package thermal characteristics ................................................................. 7 electrical characteristics ........................................................................ 7 i 2 c timing characteristics ...................................................................... 14 typical operating characteristics ................................................................ 15 pin configuration ............................................................................. 22 pin description ............................................................................... 23 detailed description ........................................................................... 24 interrupts ................................................... ............................... 29 status ................................................... ............................... 29 state ................................................... ................................ 29 flag ................................................... ................................ 29 enable ................................................... .............................. 29 clear ................................................... ................................ 29 digital audio interface ................................................... ..................... 42 interface format ................................................... ....................... 43 configuring the dai format ................................................... .............. 43 configuring the digital audio input ................................................... ........ 44 digital passband filtering ................................................... ............... 49 biquad filter ................................................... .......................... 50 signal path delay ................................................... ..................... 50 pvdd adc ................................................... ............................. 51 digital volume control ................................................... .................. 51 output voltage scaling ................................................... ................. 52 dynamic headroom tracking ................................................... ............... 53 dht ballistics .................................................. ............................ 59 limiter .................................................. .................................. 62 thermal adc ................................................... ........................... 62 thermal protection ................................................... ....................... 62 thermal foldback ................................................... ........................ 62 automatic level control (alc) ................................................... .............. 65 dout operation and data format .................................................. ............ 73 interchip communication .................................................. ................... 74 downloaded from: http:///
www.maximintegrated.com maxim integrated 3 MAX98372 digital input class d ampliier with dht and brownout protection table of contents (continued) multiamplifier grouping ................................................... .................... 74 double data drive ................................................... ........................ 75 class d output stage ................................................... ..................... 81 ultra-low emi filterless output stage ................................................... ..... 81 v dvdd and v pvdd uvlo ................................................... .............. 82 click-and-pop suppression ................................................... ................ 82 amplifier current limit .................................................. ..................... 82 thermal shutdown recovery .................................................. ................ 82 output sensing when using ferrites ................................................... ......... 83 clocking architecture ................................................... ..................... 83 reset ................................................... .................................. 83 hardware reset ................................................... ....................... 83 software reset ................................................... ....................... 85 i 2 c serial interface ................................................... ....................... 85 bit transfer ................................................... ........................... 85 start and stop conditions .................................................. ............. 85 early stop conditions .................................................. ................... 86 slave address .................................................. ......................... 86 acknowledge .................................................. .......................... 86 write data format ................................................... ..................... 86 read data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 i 2 c slave addresses ................................................... ...................... 88 applications information ........................................................................ 88 layout and grounding ................................................... ..................... 88 typical application circuit ...................................................................... 90 ordering information .......................................................................... 90 package information .......................................................................... 90 revision history .............................................................................. 91 list of figures figure 1. i 2 s audio interface timing diagram ....................................................... 13 figure 2. left-justified audio interface timing diagram ............................................... 13 figure 3.tdm audio interface timing diagrams ..................................................... 13 figure 4. i 2 c interface timing diagram ............................................................ 15 figure 5. i 2 s digital audio format examples ....................................................... 46 figure 6. left-justified digital audio format examples ............................................... 47 figure 7. tdm digital audio format examples ...................................................... 48 figure 8. example of dynamic headroom tracking in mode 1 opera tion ................................. 53 downloaded from: http:///
www.maximintegrated.com maxim integrated 4 MAX98372 digital input class d ampliier with dht and brownout protection list of tables table 1. MAX98372 control register map ......................................................... 24 table 2. interrupt sources ...................................................................... 29 table 3. interrupt registers ..................................................................... 30 table 4. supported sample rates ................................................................ 42 table 5. supported bclk rates in slave mode ..................................................... 42 table 6. configuration for digital audio interface format .............................................. 43 table 7. pcm receive channel enables ........................................................... 44 table 8. tdm channel selection for mono replay ................................................... 46 table 9. digital highpass filter .................................................................. 49 table 10. biquad filter coefficient registers ........................................................ 50 list of figures (continued) figure 9. example of dynamic headroom tracking in mode 2 opera tion with a high rp ..................... 54 figure 10. example of dynamic headroom tracking in mode 2 ope ration with a low rp .................... 55 figure 11. example of dynamic headroom tracking in mode 3a ope ration ............................... 56 figure 12. example of dynamic headroom tracking in mode 3b ope ration ............................... 57 figure 13. example of dynamic headroom tracking in mode 3b wit h limiter .............................. 58 figure 14. dynamic headroom tracking attack functionality ........................................... 59 figure 15. thermal foldback performance ......................................................... 64 figure 16. alc example 1: battery drops below brownout thres hold and quickly recovers ................. 65 figure 17. alc example 2: battery drops below brownout thres hold and stays low ....................... 66 figure 18. alc example 3: battery drops below brownout thres hold and stays long enough for the amp to mute (non-infinite hold time) ........................................................................ 67 figure 19. alc example 4: battery drops below brownout thres hold and stays long enough for the amp to mute (infinite hold time) ............................................................................ 68 figure 20. alc example 5: immediate attenuation ................................................... 69 figure 21. dout data structure ................................................................. 73 figure 22. single data drive .................................................................... 75 figure 23. double data drive illustration ........................................................... 75 figure 24. typical application circuit with ferrites beads u sed ......................................... 83 figure 25. thd performance improvement enabled by remote se nsing ................................. 83 figure 26. start, stop, and repeated start conditions ......................................... 85 figure 27. acknowledge ........................................................................ 86 figure 28. writing one byte of data to the MAX98372 ............................................... 86 figure 29. n-bytes of data to the MAX98372 ....................................................... 86 figure 30. reading one byte of data from the MAX98372 ............................................ 87 figure 31. reading n-bytes of data from the MAX98372 .............................................. 87 figure 32. MAX98372+ wlp ball dimensions ...................................................... 89 downloaded from: http:///
www.maximintegrated.com maxim integrated 5 MAX98372 digital input class d ampliier with dht and brownout protection list of tables (continued) table 11. signal path delay ..................................................................... 50 table 12. pvdd measurement adc .............................................................. 51 table 13. digital volume ramping and digital volume ................................................ 51 table 14. digital gain settings and output voltage scaling ............................................ 52 table 15. speaker gain minimum voltage .......................................................... 55 table 16. dynamic headroom tracking attack settings ............................................... 60 table 17. dynamic headroom tracking release settings .............................................. 61 table 18. dynamic gain enables ................................................................. 61 table 19. limiter threshold select ................................................................ 61 table 20. manual limiter threshold settings ....................................................... 62 table 21. limiter threshold ..................................................................... 62 table 22. limiter attack and release settings ...................................................... 63 table 23. thermal adc measurements ............................................................ 63 table 24. thermal foldback settings ............................................................. 64 table 25. thermal foldback enable .............................................................. 64 table 26. alc threshold ....................................................................... 70 table 27. alc attack .......................................................................... 71 table 28. alc attenuation and release ........................................................... 71 table 29. alc infinite hold release .............................................................. 72 table 30. alc configuration .................................................................... 72 table 31. dht info ........................................................................... 73 table 33. thermal and dht link enables .......................................................... 73 table 32. therm info ........................................................................ 73 table 34. interchip communication configuration .................................................... 74 table 35. dout double data drive mode ......................................................... 75 table 36. dout dht receive channel configuration ................................................ 76 table 37. dout thermal foldback receive channel configurati on ..................................... 77 table 38. dout transmit channel configuration .................................................... 78 table 39. dout alc receive channel configuration ................................................ 79 table 40. extra bclk cycle configuration ......................................................... 80 table 41. manual high-impedance mode configuration ............................................... 80 table 42. speaker configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 43. spread-spectrum modulation configuration ................................................ 82 table 44. clock monitor configuration ............................................................ 84 table 45. reset register ....................................................................... 84 table 46. global enable register ................................................................ 84 table 47. addr i 2 c address select .............................................................. 88 table 48. recommended external components ..................................................... 89 downloaded from: http:///
detailed functional diagram MAX98372 addr0 scl sda irq bclk lrclk din dgnd dvdd outp outn outp sns outn sns digital audio interface mdll interrupt dispatcher dynamic headroom tracking temperature monitor pvdd adc bi- quad interpolation filter linear regulator speaker amplifier clock monitor i 2 c control registers decimation filter mixer pvdd uvlo dac addr1 reset vol thermal foldback agnd pgnd dvdd uvlo lpf dsp dout v refc pvdd automatic level control www.maximintegrated.com maxim integrated 6 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
pvdd to pgnd ..................................................... -0.3v to +20v out_ to pgnd .................................... -0.3v to (v pvdd + 0.3v) v refc to agnd ................................................... -0.3v to +2.2v dvdd to dgnd .................................................... -0.3v to +2.2v sda, scl, addr_, irq to dgnd ....................... -0.3v to +2.2v bclk, lrclk, din, reset to dgnd .............................. -0.3v to (v dvdd + 0.3v) agnd, dgnd to pgnd ...................................... -0.1v to +0.1v short-circuit duration between outp, outn and pgnd or pvdd ........ continuous between outp and outn .................................. continuous continuous power dissipation (t a = +70c) for multilayer board (derate 27mw/c above +70c) ..................................... 1.9w junction temperature ...................................................... +150c operating temperature range ........................... -40c to +85c storage temperature range ............................ -65c to +150c soldering temperature (reflow) ....................................... +260c junction-to-ambient thermal resistance ( ja ) ............ +37c/w junction-to-board thermal resistance ( jb ) ............. +33.4c/w (note 1) electrical characteristics (v pvdd = 12v, v dvdd = v reset = 1.8v, v gnd = 0v, c pvdd = 1x 220f, 2x 10f, 2x 0.1f, c refc = 1f, c dvdd = 1f, z spk = open, ac measurement bandwidth 20hz to 22khz, f s = 48khz, 24-bit data, t a = t min to t max , unless, otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol condition min typ max units power-supply voltage range v pvdd 5.5 18 v v dvdd 1.14 1.98 v refc regulator output v refc 2.0 v pvdd undervoltage lockout pvdd uvlo 3.65 4.3 4.75 v dvdd undervoltage lockout dvdd uvlo 0.75 v quiescent current i q _ pvdd spk_swclk = 0 472khz 9 12 ma spk_swclk = 1 330khz 7 quiescent current i q _ dvdd 2 2.6 ma software shutdown supply current i shdn _ sw all dai pins pulled low, t a = +25c i pvdd 10 a i dvdd 10 hardware shutdown supply current i shdn _ hw v reset = 0v, t a = +25c i pvdd 5 a i dvdd 1 turn-on time t on from sw_en bit set to full operation volume ramping disabled 10 ms volume ramping enabled 30 turn-off time t off from sw_en bit cleared to shutdown volume ramping disabled 10 ms volume ramping enabled 30 www.maximintegrated.com maxim integrated 7 MAX98372 digital input class d ampliier with dht and brownout protection note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics downloaded from: http:///
electrical characteristics (continued) (v pvdd = 12v, v dvdd = v reset = 1.8v, v gnd = 0v, c pvdd = 1x 220f, 2x 10f, 2x 0.1f, c refc = 1f, c dvdd = 1f, z spk = open, ac measurement bandwidth 20hz to 22khz, f s = 48khz, 24-bit data, t a = t min to t max , unless, otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol condition min typ max units digital filter characterisics (lrclk < 50khz) (note 5) passband cutoff f plp ripple limit cutoff 0.43 x f s hz -3db cutoff 0.47 x f s -6.02db cutoff 0.5 x f s passband ripple f < f plp -0.1 +0.1 db stopband cutoff f slp 0.58 x f s hz stopband attenuation f > f slp 60 db digital filter characterisics (lrclk > 50khz) (note 5) passband cutoff f plp ripple limit cutoff 0.24 x f s hz -3db cutoff 0.31 x f s passband ripple f < f plp -0.1 +0.1 db stopband cutoff f slp 0.417 x f s hz stopband attenuation f > f slp 60 db digital highpass filter characteristics dc attenuation (note 5) 80 db dc blocking cutoff frequency (note 5) across all sample rates dachpf = 0x1 2 hz highpass cutoff frequency across all sample rates dachpf = 0x2 50 hz dachpf = 0x3 100 dachpf = 0x4 200 dachpf = 0x5 400 dachpf = 0x6 800 speaker amplifier electrical characteristics digital volume control digital volume (max) dvol[6:0] = 0x00 0 db digital volume (min) dvol[6:0] = 0x7e -63 db volume control step size 0.5 db output offset voltage vos t a = +25c 1 5 mv click-and-pop level k cp peak voltage, t a = +25c, a-weighted, 32 samples per second, digital audio inputs have zero-code input into shutdown -66 dbv out of shutdown -60 www.maximintegrated.com maxim integrated 8 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
electrical characteristics (continued) (v pvdd = 12v, v dvdd = v reset = 1.8v, v gnd = 0v, c pvdd = 1x 220f, 2x 10f, 2x 0.1f, c refc = 1f, c dvdd = 1f, z spk = open, ac measurement bandwidth 20hz to 22khz, f s = 48khz, 24-bit data, t a = t min to t max , unless, otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol condition min typ max units dynamic range dr v pvdd = 17v, z l = 8 + 33h, measured using the eiaj method, -60dbfs 1khz output signal, referenced to 1% output power a-weighted 110 db integrated output noise e n z l = 8 + 33h a-weighted 35 v rms unweighted 72 output power p out thd+n 1%, f = 1khz z l = 8? + 33h 8.2 w z l = 8? + 33h, v pvdd = 17v 15.7 z l = 4? + 33h 13.2 thd+n 10%, f = 1khz z l = 8? + 33h 10.2 z l = 8? + 33h, v pvdd = 17v 19 z l = 4? + 33h 15.8 eficiency spk f = 1khz p out = 10w, z l = 8 + 33h 91 % p out = 15w, z l = 4 + 33h 81 total harmonic distortion + noise thd+n f = 1khz p out = 4w, z l = 8? + 33h 0.02 % p out = 8w, z l = 4? + 33h 0.03 f = up to 6khz p out = 4w, z l = 8? + 33h 0.1 p out = 8w, z l = 4? + 33h 0.2 maximum frequency response deviation maximum deviation above and below 1khz reference 0.2 db gain error a verror f = 1khz, v o = 2.828v rms -0.5 +0.5 db maximum channel-to-channel phase error (note 3) output phase shift between multiple devices from 20hz to 20khz, across all sample rates and dai operating modes 1 deg pvdd power-supply rejection ratio psrr v pvdd = 5.5v to 18v 85 db f = 20hz to 10khz, v ripple = 100mv p-p 75 f = 10khz to 20khz, v ripple = 100mv p-p 60 www.maximintegrated.com maxim integrated 9 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
electrical characteristics (continued) (v pvdd = 12v, v dvdd = v reset = 1.8v, v gnd = 0v, c pvdd = 1x 220f, 2x 10f, 2x 0.1f, c refc = 1f, c dvdd = 1f, z spk = open, ac measurement bandwidth 20hz to 22khz, f s = 48khz, 24-bit data, t a = t min to t max , unless, otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol condition min typ max units dvdd power-supply rejection ratio psrr f = 1khz, v ripple = 50mv p-p 100 output switching frequency f s constant across all sample rates spk_swclk = 0 472 khz spk_swclk = 1 330 khz output stage on-resistance r on pmos + nmos 0.425 current limit i lim z l = 8 + 33h or z l = 4 + 33h 4.5 6.0 a spread-spectrum bandwidth ssm_modindex=0x01 spk_swclk = 0 32.4 khz spk_swclk = 1 15.4 khz automatic level control (alc) brownout response time from pvdd minimum threshold event to audio attenuation 12 s brownout voltage threshold range 2-cell mode (alc_range = 0) 5.5 7.3 v 3-cell mode (alc_range = 1) 7.8 10.95 v brownout voltage threshold accuracy all brownout voltage threshold settings -2.5 1 +2.5 % thermal foldback attack time 10 s attenuation slope thrm_slope[1:0] = 0x0 0.5 db/c thrm_slope[1:0] = 0x1 1 thrm_slope[1:0] = 0x2 2 max attenuation 12 db release time thrm_rel[1:0] = 0x0 3 ms/db thrm_rel[1:0] = 0x3 300 thermal shutdown trigger point (note 3) 140 150 160 c hysteresis 20 c pvdd adc electrical characteristics resolution 8 bits absolute error 1.2 lsb adc voltage range 5.35 18.15 v adc lowpass filter cutoff frequency -3db limit 0.0875 x f s hz adc lowpass filter stopband frequency -40db limit 0.167 x f s hz www.maximintegrated.com maxim integrated 10 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
electrical characteristics (continued) (v pvdd = 12v, v dvdd = v reset = 1.8v, v gnd = 0v, c pvdd = 1x 220f, 2x 10f, 2x 0.1f, c refc = 1f, c dvdd = 1f, z spk = open, ac measurement bandwidth 20hz to 22khz, f s = 48khz, 24-bit data, t a = t min to t max , unless, otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol condition min typ max units adc programmable lowpass filter pvdd_adc_bw[1:0] = 0x1 2 hz pvdd_adc_bw[1:0] = 0x2 20 pvdd_adc_bw[1:0] = 0x3 200 digital i/o characteristics din, bclk, lrclk, addr_, reset input voltage high v ih 0.7 x v dvdd v input voltage low v il 0.3 x v dvdd v input leakage current i ih , i il -1 +1 a input capacitance c in 3 pf input (sda, scl) input voltage high v ih 0.7 x v dvdd v input voltage low v il 0.3 x v dvdd v input hysteresis v hys 200 mv input capacitance c in 3 pf input leakage current i ih , i il t a = +25c, input high -1 +1 a output (sda, irq ) output low voltage v ol i sink = 3ma 0.4 v output current i ol 13 ma digital audio interface timing characteristics global lrclk frequency range f lrclk all dai operating modes 32 96 khz word length all dai operating modes 16 bits 2432 bclk duty cycle 45 55 % maximum bclk/lrclk input jitter maximum jitter with minimal performance degradation rms jitter below 40khz 0.5 ns rms jitter above 40khz 0.9 www.maximintegrated.com maxim integrated 11 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
electrical characteristics (continued) (v pvdd = 12v, v dvdd = v reset = 1.8v, v gnd = 0v, c pvdd = 1x 220f, 2x 10f, 2x 0.1f, c refc = 1f, c dvdd = 1f, z spk = open, ac measurement bandwidth 20hz to 22khz, f s = 48khz, 24-bit data, t a = t min to t max , unless, otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol condition min typ max units pcm mode (i 2 c, left-justified) lrclk duty cycle 45 55 % lrclk to bclk active edge setup time t syncset 10 ns lrclk to bclk active edge hold time t synchold 10 ns din to bclk active edge setup time t setup 10 ns din to bclk active edge hold time t hold 10 ns bclk period (note 3) t bclk 160 ns bclk frequency (note 3) f bclk 6.25 mhz f s x 32 f s x 48 f s x 64 tdm mode lrclk pulse width pw lrclk measured in number of bclk cycles 511 cycles din frame delay after lrclk edge measured in number of bclk cycles 0 1 cycles bclk period (note 3) t bclk 20 ns bclk frequency (note 3) f bclk all tdm operating modes 50 mhz www.maximintegrated.com maxim integrated 12 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
figure 1. i 2 s audio interface timing diagram lrclk (input) bclk (input) din (input) left msb t hold t setup t bclkh t bclkl t bclk t syncset right msb t synchold vih vil vih vil vih vih vil vil vih vil figure 3.tdm audio interface timing diagrams lrclk (input) bclk (input) din (input) t hold t setup t synchold msb t bclkh t bclkl t bclk t syncset vil vih vil vih vil vih vil vih figure 2. left-justified audio interface timing diagram lrclk (input) bclk (input) din (input) left msb t hold t setup t bclkh t bclkl t bclk t syncset t synchold vih vil vih vil vih vih vil vil vih vil right msb www.maximintegrated.com maxim integrated 13 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
note 2: 100% production tested at t a = +25c. specifications over temperature limits are guaranteed by design. note 3: minimums and/or maximum limits shown are design targets and not 100% production tested. note 4: c b in pf. note 5: digital filter performance is invariant over temperature and production tested at t a = +25 c. i 2 c timing characteristics (v pvdd = 12v, v dvdd = v reset = 1.8v, v gnd = 0v, c pvdd = 1x 220f, 2x 10f, 2x 0.1f, cv refc = 1f, c dvdd = 1f, z spk = open, ac measurement bandwidth 20hz to 22khz, f s = 48khz, 24-bit data, t a = t min to t max , unless, otherwise noted. typical values are at t a = +25c.) (note 2) parameter symbol conditions min typ max units i 2 c timing characteristics serial clock frequency f scl 0 400 khz bus free time between stop and start conditions t buf 1.3 s hold time (repeated) start condition t hd,sta 0.6 s scl pulse-width low t low 1.3 s scl pulse-width high t high 0.6 s setup time for a repeated start condition t su,sta 0.6 s data hold time t hd,dat 0 900 ns data setup time t su,dat 100 ns sda and scl receiving rise time (note 4) t r 20 + 0.1c b 300 ns sda and scl receiving fall time (note 4) t f 20 + 0.1c b 300 ns sda transmitting fall time t f 20 250 ns setup time for stop condition t su,sto 0.6 s bus capacitance c b 400 pf pulse width of suppressed spike t sp 0 50 ns www.maximintegrated.com maxim integrated 14 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
(v pvdd = 12v, v dvdd = 1.8v, v gnd = 0v, spk_gain_max = 0x0b (20.5db), f bclk = 3.072mhz, f lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, t a = t min to t max , unless otherwise noted. typical values are at t a = +25oc.) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.0 1.5 2.0 dvdd sw shutdown current (a) dvdd voltage (v) dvdd software shutdown current vs. dvdd voltage z spk = dai pins = gnd toc03 0.0 0.5 1.0 1.5 2.0 2.5 3.0 1.0 1.5 2.0 dvdd quiescent current (ma) dvdd voltage (v) dvdd quiescent current vs. dvdd voltage z spk = toc01 0 1 2 3 4 5 6 7 8 9 10 5 10 15 pvdd quiescent current (ma) pvdd voltage (v) pvdd quiescent current vs. pvdd voltage z spk = f spk_sw = 472khz f spk_sw = 330khz toc02 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 5 10 15 pvdd sw shutdown current (a) pvdd voltage (v) pvdd software shutdown current vs. pvdd voltage z spk = toc04 figure 4. i 2 c interface timing diagram www.maximintegrated.com maxim integrated 15 MAX98372 digital input class d ampliier with dht and brownout protection typical operating characteristics downloaded from: http:///
(v pvdd = 12v, v dvdd = 1.8v, v gnd = 0v, spk_gain_max = 0x0b (20.5db), f bclk = 3.072mhz, f lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, t a = t min to t max , unless otherwise noted. typical values are at t a = +25oc.) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0001 0.001 0.01 0.1 1 10 thd+n ratio (db) output power (w) thd+n ratio vs. output power z spk = 8 + 68 h v pvdd = 12v 100hz 1khz 6khz toc08 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 1.0 1.5 2.0 dvdd hw shutdown current (a) dvdd voltage (v) dvdd hardware shutdown current vs. dvdd voltage z spk = v rst = 0v toc05 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0001 0.001 0.01 0.1 1 10 100 thd+n ratio (db) output power (w) thd+n ratio vs. output power z spk = 4 + 33 h v pvdd = 12v 100hz 1khz 6khz toc11 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 5 10 15 pvdd hw shutdown current (a) pvdd voltage (v) pvdd hardware shutdown current vs. pvdd voltage z spk = v rst = 0v toc06 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 thd+n ratio (db) frequency (hz) total harmonic distortion plus noise vs. frequency v pvdd = 5.5v z spk = 8 ? + 68h p out = 0.1w p out = 1w toc12 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0001 0.001 0.01 0.1 1 10 thd+n ratio (db) output power (w) thd+n ratio vs. output power z spk = 8 + 68 h v pvdd = 5.5v 100hz 1khz 6khz toc07 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 thd+n ratio (db) frequency (hz) total harmonic distortion plus noise vs. frequency v pvdd = 12v z spk = 8 ? + 68h p out = 1w p out = 4w toc13 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0001 0.001 0.01 0.1 1 10 100 thd+n ratio (db) output power (w) thd+n ratio vs. output power z spk = 8 + 68 h v pvdd = 17v 100hz 1khz 6khz toc09 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0.0001 0.001 0.01 0.1 1 10 thd+n ratio (db) output power (w) thd+n ratio vs. output power z spk = 4 + 33 h v pvdd = 5.5v 100hz 1khz 6khz toc10 maxim integrated 16 www.maximintegrated.com MAX98372 digital input class d ampliier with dht and brownout protection typical operating characteristics (continued) downloaded from: http:///
(v pvdd = 12v, v dvdd = 1.8v, v gnd = 0v, spk_gain_max = 0x0b (20.5db), f bclk = 3.072mhz, f lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, t a = t min to t max , unless otherwise noted. typical values are at t a = +25oc.) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1 10 100 output power (w) load resistance ( ?) output power vs. load resistance v pvdd = 5.5v thd+n = 10% thd+n = 1% toc17 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 thd+n ratio (db) frequency (hz) total harmonic distortion plus noise vs. frequency v pvdd = 17v z spk = 8 ? + 68 h p out = 1w p out = 4w toc14 0 5 10 15 20 25 5 10 15 20 output power (w) pvdd supply voltage (v) output power vs. pvdd supply voltage z spk = 8 ? + 68 h 1% thd+n 10% thd+n toc20 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 thd+n ratio (db) frequency (hz) total harmonic distortion plus noise vs. frequency v pvdd = 5.5v z spk = 4 ? + 33 h p out = 0.1w p out = 1w toc15 0 2 4 6 8 10 12 14 16 18 20 5 7 9 11 13 output power (w) pvdd supply voltage (v) output power vs. pvdd supply voltage z spk = 4 ? + 33 h 1% thd+n 10% thd+n toc21 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 thd+n ratio (db) frequency (hz) total harmonic distortion plus noise vs. frequency v pvdd = 12v z spk = 4 ? + 33 h p out = 1w p out = 8w toc16 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 20 200 2000 20000 normalized gain (db) frequency (hz) normalized gain vs. frequency normalized to 1khz z spk = 8 ? + 68 h f s = 96khz f s = 48khz f s = 44.1khz f s = 32khz toc22 0 2 4 6 8 10 12 14 16 18 20 1 10 100 output power (w) load resistance ( ?) output power vs. load resistance v pvdd = 12v thd+n = 10% thd+n = 1% toc18 0 5 10 15 20 25 1 10 100 output power (w) load resistance ( ?) output power vs. load resistance v pvdd = 17v thd+n = 10% thd+n = 1% toc19 maxim integrated 17 www.maximintegrated.com MAX98372 digital input class d ampliier with dht and brownout protection typical operating characteristics (continued) downloaded from: http:///
(v pvdd = 12v, v dvdd = 1.8v, v gnd = 0v, spk_gain_max = 0x0b (20.5db), f bclk = 3.072mhz, f lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, t a = t min to t max , unless otherwise noted. typical values are at t a = +25oc.) 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 efficiency (%) output power (w) efficiency vs. output power v pvdd = 17v z spk = 8 ? + 68 h f spk = 472khz f spk = 330khz toc26 0 10 20 30 40 50 60 70 80 90 0 5 10 15 20 efficiency (%) output power (w) efficiency vs. output power v pvdd = 12v z spk = 4 ? + 33 h f spk = 472khz f spk = 330khz toc23 0 10 20 30 40 50 60 70 80 90 100 0 2 4 6 8 10 12 efficiency (%) output power (w) efficiency vs. output power v pvdd = 12v z spk = 8 ? + 68 h f spk = 472khz f spk = 330khz toc29 0 10 20 30 40 50 60 70 80 90 0.001 0.01 0.1 1 10 100 efficiency (%) output power (w) efficiency vs. output power v pvdd = 12v z spk = 4 ? + 33 h f spk = 472khz f spk = 330khz toc24 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 100 efficiency (%) output power (w) efficiency vs. output power v pvdd = 12v z spk = 8 ? + 68 h f spk = 472k f spk = 330khz toc30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.001 0.01 0.1 1 10 100 power dissipation (w) output power (w) power dissipation vs. output power v pvdd = 12v z spk = 4 ? + 33 h f spk = 472khz f spk = 330khz toc25 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 power dissipation (w) output power (w) power dissipation vs. output power v pvdd = 12v z spk = 8 ? + 68 h f spk = 472khz f spk = 330khz toc31 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 100 efficiency (%) output power (w) efficiency vs. output power v pvdd = 17v z spk = 8 ? + 68 h f spk = 472khz f spk = 330khz toc27 0.0 0.5 1.0 1.5 2.0 2.5 0.001 0.01 0.1 1 10 100 power dissipation (w) output power (w) power dissipation vs. output power v pvdd = 17v z spk = 8 ? + 68 h f spk = 472khz f spk = 330khz toc28 maxim integrated 18 www.maximintegrated.com MAX98372 digital input class d ampliier with dht and brownout protection typical operating characteristics (continued) downloaded from: http:///
(v pvdd = 12v, v dvdd = 1.8v, v gnd = 0v, spk_gain_max = 0x0b (20.5db), f bclk = 3.072mhz, f lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, t a = t min to t max , unless otherwise noted. typical values are at t a = +25oc.) 0 20 40 60 80 100 120 140 1.1 1.3 1.5 1.7 1.9 psrr(db) dvdd supply voltage (v) power-supply rejection ratio vs. dvdd supply voltage v ripple = 100mv p-p f s =1khz toc35 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 10000 100000 psrr(db) frequency (hz) pvdd power - supply rejection ratio vs. frequency v ripple = 100mv p-p z spk = toc32 scl 1v/div spkout 5v/div toc38 4ms/div v outn v inside v backup software disable turn - off response volume ramping enabled 0 10 20 30 40 50 60 70 80 90 100 5 10 15 20 psrr(db) pvdd supply voltage (v) power- supply rejection ratio vs. pvdd supply voltage v ripple = 100mv p-p f s = 1khz toc33 scl 1v/div spkout 5v/div toc39 2ms/div v outn v inside v backup software disable turn - off response volume ramping disabled 0 20 40 60 80 100 120 140 10 100 1000 10000 100000 psrr(db) frequency (hz) dvdd power-supply rejection ratio vs. frequency v ripple = 100mv p-p toc34 rst 1v/div spkout 5v/div toc40 800s/div v outn v inside v backup hardware reset turn - off response scl 1v/div spkou t 5v/div toc36 4ms/div v outn v inside v backup software enable turn-on response volume ramping enabled scl 1v/div spkout 5v/div toc37 2ms/div v outn v inside v backup software enable turn - on response volume ramping disabled maxim integrated 19 www.maximintegrated.com MAX98372 digital input class d ampliier with dht and brownout protection typical operating characteristics (continued) downloaded from: http:///
(v pvdd = 12v, v dvdd = 1.8v, v gnd = 0v, spk_gain_max = 0x0b (20.5db), f bclk = 3.072mhz, f lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, t a = t min to t max , unless otherwise noted. typical values are at t a = +25oc.) -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 32khz toc44 bclk 2v/div lrclk 1v/div spkout 5v/div toc41 2ms v outn v inside v backup bclk removal turn - off response -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 44.1khz toc47 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68h f s = 32khz toc42 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 48khz toc48 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 32khz toc43 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 48khz toc49 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 44.1khz toc45 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 44.1khz toc46 maxim integrated 20 www.maximintegrated.com MAX98372 digital input class d ampliier with dht and brownout protection typical operating characteristics (continued) downloaded from: http:///
(v pvdd = 12v, v dvdd = 1.8v, v gnd = 0v, spk_gain_max = 0x0b (20.5db), f bclk = 3.072mhz, f lrclk = 48khz, speaker loads (z spk ) connected between outp and outn, t a = t min to t max , unless otherwise noted. typical values are at t a = +25oc.) -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 88.2khz toc53 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 48khz toc50 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 96khz toc56 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 88.2khz toc51 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 88.2khz toc52 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 96khz toc54 -140 -120 -100 -80 -60 -40 -20 0 20 40 0 5000 10000 15000 20000 amplitude (dbv) frequency (hz) inband output spectrum z spk = 8 ? + 68 h f s = 96khz toc55 maxim integrated 21 www.maximintegrated.com MAX98372 digital input class d ampliier with dht and brownout protection typical operating characteristics (continued) downloaded from: http:///
1 a b c d e 2 3 4 5 6 outn sns pvdd pvdd dvdd addr1 scl outn outn pgnd dgnd addr0 sda pgnd pgnd pgnd agnd dout lrclk outp outp pgnd agnd irq din outp sns pvdd pvdd v refc reset bclk digital analog high power top view (bump side down) www.maximintegrated.com maxim integrated 22 MAX98372 digital input class d ampliier with dht and brownout protection pin coniguration downloaded from: http:///
bump name supply rail function a1 outnsns pvdd negative speaker ampliier output sense. if not used, connect to outn. a2, a3 e2, e3 pvdd speaker ampliier power supply. bypass each bump pair to pgnd with a 10f and a 0.1f, and a single 220f per device. a4 dvdd digital core, digital audio interface, and i 2 c control power supply. bypass to dgnd with a 1f. a5 addr1 dvdd four-level i 2 c slave address select input. see the slave address selection section for additional information (table 40). a6 scl dvdd i 2 c control clock input b1, b2 outn pvdd negative speaker ampliier output b3, c1Cc3, d3 pgnd speaker ampliier ground b4 dgnd digital ground b5 addr0 dvdd four-level i 2 c slave address select input. see the slave address selection section for additional information (table 40). b6 sda dvdd i 2 c control data input/output c4, d4 agnd analog ground c5 dout dvdd bidirectional icc link data c6 lrclk dvdd dai left/right clock input. lrclk is the audio sample rate clock and determines whether audio data is routed to the left or right channel. in tdm mode, lrclk is a frame sync pulse with programmable width. d1, d2 outp pvdd positive speaker ampliier output d5 irq dvdd hardware interrupt output. irq can be programmed to pull low when individual bits in the lag registers change value. connect a 10k? pullup resistor for full output swing. d6 din dvdd dai audio data input e1 outpsns pvdd positive speaker ampliier output sense. if not used, connect to outp. e4 v refc pvdd internal regulator decoupling point. bypass to agnd with a 1f. e5 reset dvdd active-low hardware reset. drive low to place the device into low power reset mode and reset the device registers to their power-on-reset (por) states. e6 bclk dvdd dai bit clock input www.maximintegrated.com maxim integrated 23 MAX98372 digital input class d ampliier with dht and brownout protection pin description downloaded from: http:///
detailed description the MAX98372 is a high-efficiency mono class d audio amplifier that features thermal foldback protection and adcs for sensing battery supply voltage and onboard temperature. the MAX98372 can operate over a wide range of supply voltage (pvdd), and has extensive on-board digital signal processing to enable dynamic headroom tracking (dht). this feature automatically adjusts the output signal to fit into the available supply voltage range. the dht can be completely bypassed for operation with fixed, regulated supply voltages. the MAX98372 provides automatic level control (alc) for battery brownout protection. this is achieved by reducing amplifier gain when the battery voltage drops below the selected threshold. alc threshold, maximum attenuation, and attack/release rates are programmable. active emissions limiting edge rate and overshoot control circuitry, together with class d modulation, minimize the electromagnetic interference (emi) traditionally associated with class d amplifiers. in systems that use less than 18in of speaker cable, an output filter is unnecessary to meet standard emi limits. two adcs monitor pvdd supply voltage and die temperature. the pvdd supply voltage value can be read using the i 2 c interface. the temperature adc can be read back through i 2 c, however, accurate readings only occur after the die temperature exceeds +100c. the dai supports i 2 s, left-justified, and tdm formatted data at the following sample rates: 32khz, 44.1khz, 48khz, 88.2khz, and 96khz. audio bit depths of 16, 24, and 32 bits are supported for input data. the dai operates from bclk to allow the device to function without mclk. thermal foldback allows the device to smoothly attenuate the audio output in an effort to prevent destructive thermal behavior. above a set threshold, the gain of the replay path reduces at a (user programmable) db/c rate to a 12db maximum attenuation. thermal monitoring capabilities alert the host when die temperature has triggered the thermal foldback circuit, or is approaching the maximum operating temperature. if maximum die temperature is exceeded, the device shuts down to protect itself. short- circuit protection ensures that accidental shorts or high- current events do not cause damage to the ic. device status is communicated to the host through a hardware interrupt ( irq ) and status registers accessible through the i 2 c interface. the MAX98372 is fully programmable through the i 2 c interface. addr0, addr1 connections select one of sixteen i 2 c slave addresses. shutdown mode is directly controlled through the i 2 c interface, or a hardware shutdown can be asserted through the reset pin. table 1. MAX98372 control register map register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit2 bit1 bit 0 interrupts 0x01 interrupt status 0 r thrmfb_ status thrm wrn_ status thrm shdn_ status 0x00 0x02 interrupt status 1 r iccovc_ status lmtract_ status inval slot_ status dhtact_ status spk curnt_ status pvdd ovfl_ status pvdd uvlo_ status 0x01 0x03 interrupt state 0 r thrmfb_ end_ state thrmfb_ bgn_ state thrm wrn_end _state thrm wrn_bgn _state thrm shdn_end _state thrm shdn_bgn _state 0x00 0x04 interrupt state 1 r iccovc_ state lmtract_ state inval slot_ state dhtact_ state spk curnt_ state pvdd ovfl_ state pvdd uvlo_ state 0x00 0x05 interrupt flag 0 r/w thrmfb_ end_ flag thrmfb_ bgn_ flag thrm wrn_end_ flag thrm wrn_bgn _flag thrm shdn_ end_ flag thrm shdn_ bgn_ flag 0x00 www.maximintegrated.com maxim integrated 24 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 1. MAX98372 control register map (continued) register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit2 bit1 bit 0 0x06 interrupt flag 1 r/w iccovc_ flag lmtract_ flag inval slot_ flag dhtact_ flag spk curnt_ flag pvdd ovfl_ flag pvdd uvlo_ flag 0x00 0x07 interrupt enables 0 r/w thrmfb_ end_ en thrmfb_ bgn_ en thrm wrn_ end_ en thrm wrn_ bgn_ en thrm shdn_ end_ en thrm shdn_ bgn_ en 0x00 0x08 interrupt enables 1 r/w iccovc_ en lmtract_ en inval slot_ en dhtact_ en spk curnt_ en pvdd ovfl_ en pvdd uvlo_ en 0x00 0x09 interrupt clears 0 w thrmfb_ end_clr thrmfb_ bgn_ clr thrm wrn_ end_ clr thrm wrn_ bgn_ clr thrm shdn_ end_ clr thrm shdn_ bgn_ clr 0x00 0x0a interrupt clears 1 w iccovc_ clr lmtract_ clr inval slot_ clr dhtact_ clr spk curnt_ clr pvdd ovfl_clr pvdd uvlo_ clr 0x00 0x0b live status 1 r alcinfh_ status alcact_ status alcmut_ status 0x00 0x0c state 1 r alcinfh_ state alcact_ state alcmut_ state 0x00 0x0d flag 1 r alcinfh_ flag alcact_ flag alcmut_ flag 0x00 0x0e irq enable 1 r/w alcinfh_ en alcact_en alcmut_en 0x00 0x0f irq clear 1 w alcinfh_ clr alcact_ clr alcmut_ clr 0x00 pcm configuration 0x10 pcm clock setup r/w bsel[3:0] 0x02 0x 11 pcm sample rate setup r/w spk_sr[3:0] 0x08 0x14 pcm mode config r/w chansz[1:0] format[2:0] bcledge chansel 0x80 0x15 pcm rx enables a r/w rx_ ch7_en rx_ ch6_en rx_ ch5_en rx_ ch4_en rx_ ch3_en rx_ ch2_en rx_ ch1_en rx_ ch0_en 0x00 0x16 pcm rx enables b r/w rx_ ch15_en rx_ ch14_en rx_ ch13_en rx_ ch12_en rx_ ch11_en rx_ ch10_en rx_ ch9_en rx_ ch8_en 0x00 0x18 monomix channel source r/w dmonomix_ch1_source[3:0] dmonomix_ch0_source[3:0] 0x00 0x19 monomix channel source r/w dmonomix_cfg[1:0] 0x00 www.maximintegrated.com maxim integrated 25 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 1. MAX98372 control register map (continued) register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit2 bit1 bit 0 digital filter parameters 0x1c digital filter r/w pvdd_filt _to_lmtr pvdd_filt _to_dht pvdd_adc_bw[1:0] dachpf[2:0] 0x00 0x1d dac bq b0 r/w dac_bq_b0[23:16] 0x10 0x1e r/w dac_bq_b0[15:8] 0x00 0x1f r/w dac_bq_b0[7:0] 0x00 0x20 dac bq b1 r/w dac_bq_b1[23:16] 0x00 0x21 r/w dac_bq_b1[15:8] 0x00 0x22 r/w dac_bq_b1[7:0] 0x00 0x23 dac bq b2 r/w dac_bq_b2[23:16] 0x00 0x24 r/w dac_bq_b2[15:8] 0x00 0x25 r/w dac_bq_b2[7:0] 0x00 0x26 dac bq a0 r/w dac_bq_a0[23:16] 0x00 0x27 r/w dac_bq_a0[15:8] 0x00 0x28 r/w dac_bq_a0[7:0] 0x00 0x29 dac bq a1 r/w dac_bq_a1[23:16] 0x00 0x2a r/w dac_bq_a1[15:8] 0x00 0x2b r/w dac_bq_a1[7:0] 0x00 0x2d digital volume control r/w dvol_ ramp_byp dvol[6:0] 0x00 0x2e path gain r/w dpga_clip[3:0] spk_gain_max[3:0] 0x0b dynamic gain parameters 0x31 dht rotation point r/w spk_gain_min[3:0] dht_vrot_pnt[3:0] 0x00 0x32 dht attack r/w dht_atk_step[1:0] dht_atk_rate[2:0] 0x18 0x33 dht release r/w dht_rel_step[1:0] dht_rel_rate[2:0] 0x00 0x34 pvdd adc measurement r pvdd_adc[7:0] 0x00 0x36 thermal foldback r/w thrm_hold[1:0] thrm_rel[1:0] thrm_slope[1:0] 0xc0 0x37 thermal adc measurement r thrm_adc_meas[5:0] 0x00 0x38 thermal foldback min temp r/w thrm_min_temp[5:0] 0x00 0x39 thermal foldback low pass filter r/w thrm_filt_sel[2:0] 0x03 www.maximintegrated.com maxim integrated 26 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 1. MAX98372 control register map (continued) register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit2 bit1 bit 0 0x3a pcm2 rxdht enables a r/w rxdht_ ch7_en rxdht_ ch6_en rxdht_ ch5_en rxdht_ ch4_en rxdht_ ch3_en rxdht_ ch2_en rxdht_ ch1_en rxdht_ ch0_en 0x00 0x3b pcm2 rxdht enables b r/w rxdht_ ch15_en rxdht_ ch14_en rxdht_ ch13_en rxdht_ ch12_en rxdht_ ch11_en rxdht_ ch10_en rxdht_ ch9_en rxdht_ ch8_en 0x00 0x3c pcm2 rxthm enables a r/w rxthm_ ch7_en rxthm_ ch6_en rxthm_ ch5_en rxthm_ ch4_en rxthm_ ch3_en rxthm_ ch2_en rxthm_ ch1_en rxthm_ ch0_en 0x00 0x3d pcm2 rxthm enables b r/w rxthm_ ch15_en rxthm_ ch14_en rxthm_ ch13_en rxthm_ ch12_en rxthm_ ch11_en rxthm_ ch10_en rxthm_ ch9_en rxthm_ ch8_en 0x00 0x3e pcm2 tx \ enables a r/w tx_ ch7_en tx_ ch6_en tx_ ch5_en tx_ ch4_en tx_ ch3_en tx_ ch2_en tx_ ch1_en tx_ ch0_en 0x00 0x3f pcm2 tx enables a r/w tx_ ch15_en tx_ ch14_en tx_ ch13_en tx_ ch12_en tx_ ch11_en tx_ ch10_en tx_ ch9_en tx_ ch8_en 0x00 0x40 pcm2 data order select r/w drive_ mode 0x00 0x41 pcm2 hiz manual mode r/w tx_ extra_ hiz 0x00 0x42 pcm2 tx hiz enables a r/w tx_ ch7_hiz tx_ ch6_hiz tx_ ch5_hiz tx_ ch4_hiz tx_ ch3_hiz tx_ ch2_hiz tx_ ch1_hiz tx_ ch0_hiz 0x00 0x43 pcm2 tx hiz enables b r/w tx_ ch15_hiz tx_ ch14_hiz tx_ ch13_hiz tx_ ch12_hiz tx_ ch11_hiz tx_ ch10_hiz tx_ ch9_hiz tx_ ch8_hiz 0x00 enables 0x49 ssm_cfg r/w ssm_modindex[2:0] 0x01 0x4a speaker enable r/w spk_ swclk spk_ssm[1:0] spk_edge[1:0] spk_en 0x00 0x4b dynamic gain enables r/w pvadc_en lmtr_en dht_en 0x00 0x4c thermal foldback enable r/w therm_ fb_en 0x00 0x4d restart behavior r/w cmon_ auto_ restart cmon_ ena ovc_ sel tshdn_ auto_ restart 0x00 0x4e icc link enable r/w thm_ link_en dht_ link_en 0x00 0x50 global enable r/w en 0x00 0x51 software reset w rst 0x00 0x55 limiter attack and release r/w lmtr_rel_rate[2:0] lmtr_atk_rate[2:0] 0x30 www.maximintegrated.com maxim integrated 27 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 1. MAX98372 control register map (continued) register description register contents por state addr name r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit2 bit1 bit 0 0x57 digital filter dither enable r/w auto_ dither_en dfilt_ dith_en 0x03 0x58 limiter threshold select r/w lmtr_th_sel[1:0] 0x00 0x59 limiter manual threshold r/w lmtr_thc[4:0] 0x00 0x5c icc pad control r/w icc_oc_ ena icc_ douten_ extff icc_ dout_ extff icc_pad_ctrl[3:0] 0x00 0x60 pcm2 rxalc enables a r/w pcm2_rxal_ ch7_en pcm2_rxal_ ch6_en pcm2_rxal_ ch5_en pcm2_rxalc_ ch4_en pcm2_rxalc_ ch3_en pcm2_rxal_ ch2_en pcm2_rxal_ ch1_en pcm2_rxal_ ch0_en 0x00 0x61 pcm2 rxalc enables b r/w pcm2_rxal_ ch15_en pcm2_rxal_ ch14_en pcm2_rxal_ ch13_en pcm2_rxalc_ ch12_en pcm2_rxalc_ ch11_en pcm2_rxal_ ch10_en pcm2_rxal_ ch9_en pcm2_rxal_ ch8_en 0x00 0x62 threshold r/w alc_range alc_en alc_th[4:0] 0x06 0x63 alc attack r/w alc_atk_step[3:0] alc_atk_rate[2:0] 0x00 0x64 alc atten and rls r/w alc_max_atten[3:0] alc_rls_rate[2:0] 0x80 0x65 alc infinite hold release r/w alc_rls_cfg[1:0] alc_rls_ tgr 0x00 0x66 alc configuration r/w alc_mute_ en alc_mute_dly[2:0] alc_rls_dbt[2:0] 0x92 0xff rev id r revid[7:0] 0x41 www.maximintegrated.com maxim integrated 28 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
interrupts the MAX98372 supports programmable interrupts for sending feedback to the host about events that have occurred on-chip. table 2 lists the available interrupt sources. interrupts are output on irq , an active-low open- drain output.status each interrupt source has 1 bit to indicate the real-time status of the source. this bit is read only. state each interrupt source has a state bit that is set when - ever a rising edge occurs on the associated status bit regardless of the state of the associated enable bit. this bit is read only. flag each interrupt source has a flag bit to indicate that a ris - ing edge has occurred on the associated status bit and the associated enable bit is set. this bit is read only. enable each interrupt source has an enable bit to indicate that the associated flag bit is set whenever the state bit is set. this bit is read/write. clear each interrupt has a clear bit that clears the associated state and flag bits when a 1 is written. writing a 0 has no effect. this bit is write only. table 2. interrupt sources name description overtemperature begin event indicates when the die overtemperature threshold has been exceeded. overtemperature end event indicates when the die overtemperature threshold is no longer exceeded including 20c of hysteresis. thermal warning begin event indicates when the thermal warning threshold has been exceeded. thermal warning end event indicates that the die temperature was previously above the thermal warning threshold and has now dropped below the threshold. speaker current event indicates when the speaker ampliier current limit has been exceeded. invalid slot event indicates that a slot has been selected that is not available due to one or more of the following reasons: the (number of bits per channel) x (channels per frame) does not allow for the selected slot (i 2 s mode only). the number of bclk cycles per frame does not allow for the selected slot (tdm mode only). thermal foldback event indicates that the thermal foldback limiter is operating in the attack or release phase. thermal foldback end event indicates that the die temperature was previously above the thermal threshold and has now dropped below the threshold. v pvdd overlow event indicates that the v pvdd supply voltage has reached the v pvdd adcs maximum input level. pvdd uvlo event indicates that pvdd has dropped below the minimum allowed voltage. dht active event indicates that the dht circuit is applying compression to the signal. limiter active event indicates that the limiter circuit is applying a hard limit (ininite compression) to the signal. icc overcurrent event indicates that an overcurrent event is in progress on dout. alc active event indicates that alc is operating in attack, hold, or release phase. alc mute event indicates that alc has entered mute. alc ininite hold event indicates that the alc has entered ininite hold mode. www.maximintegrated.com maxim integrated 29 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers interrupt status0interrupt status bits relect real-time fault conditions. if the fault condition is less than 3-4 lrc lk cycles, the live status bit holds high for 3C4 lrclk cycles. address bit name description 0x01 7 0 unused: read back is 0. 6 0 unused: read back is 0. 5 thermfb_status die thermal foldback status 0: the die temperature is below the thermal warning threshold. 1: the die temperature is above the thermal warning threshold and the signal is being dynamically attenuated. 4 0 unused: read back is 0. 3 thermwrn_status die overtemperature warning status 0: the die temperature is below the thermal warning threshold. 1: the die temperature is above the thermal warning threshold. 2 0 unused: read back is 0. 1 thermshdn_status die overtemperature status 0: the die temperature is below the maximum die temperature. 1: the die temperature exceeds the maximum die temperature. 0 0 unused: read back is 0. www.maximintegrated.com maxim integrated 30 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers (continued) interrupt status1interrupt status bits relect real-time fault conditions. if the fault condition is less than 3C4 lrc lk cycles, the live status bit holds high for 3C4 lrclk cycles. address bit name description 0x02 7 0 unused: read back is 0. 6 iccovc_status icc overcurrent status 0: no overcurrent event on the dout is in progress. 1: overcurrent event on the dout is in progress. 5 lmtract_status limiter active status 0: limiter is not active. 1: limiter is active. 4 invalslot_status invalid slot status 0: slot is valid. 1: slot is invalid, one or more possible error conditions apply: a. the (number of bits per channel) * (channels per frame) does not allow for the selected slot. (i2s mode only) b. the number of bclk cycles per frame does not allow for the selected slot.(tdm mode only). 3 dhtact_status dht active status 0: dynamic headroom tracking is not attacking or releasing. 1: dynamic headroom tracking is active and is attacking or releasing. 2 spkcurnt_status speaker overcurrent status0: speaker current is below the current limit. 1: speaker current is above the current limit. 1 pvddovfl_status pvdd supply voltage monitor overlow status 0: the pvdd supply voltage is below the pvdd adcs maximum input level. 1: the pvdd supply voltage has exceeded the pvdd adcs maximum input level 0 pvdduvlo_status pvdd supply voltage undervoltage status 0: the pvdd supply voltage is above the pvdd uvlo level. 1: the pvdd supply voltage is below the pvdd uvlo threshold, and the part is shutdown. www.maximintegrated.com maxim integrated 31 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers (continued) interrupt state 0 address bit name description 0x03 7 0 unused: read back is 0. 6 0 unused: read back is 0. 5 thermfb_end_state die thermal foldback state end event0: no falling edge on thermal foldback status is detected. 1: a falling edge on thermal foldback status is detected. note: write a 1 to thermfb_end_clr to reset. 4 thermfb_bgn_state die thermal foldback state end event0: no rising edge on thermal foldback status is detected. 1: a rising edge on thermal foldback status is detected. note: write a 1 to thermfb_bgn_clr to reset. 3 thermwrn_end_state thermal warning status end event 0: no falling edge on thermwrn_status is detected. 1: a falling edge on thermwrn_status is detected. note: write a 1 to thermwrn_end_clr to reset. 2 thermwrn_bgn_state thermal warning status begin event 0: no rising edge on thermwrn_ status is detected. 1: a rising edge on thermwrn_status is detected. note: write a 1 to thermwrn_bgn_clr to reset. 1 thermshdn_end_state thermal shutdown end event 0: no falling edge on thermshdn_status is detected. 1: a falling edge on thermshdn_status is detected. note: write a 1 to thermshdn_end_clr to reset. 0 thermshdn_bgn_state thermal shutdown begin event 0: no rising edge on thermshdn_status is detected. 1: a rising edge on thermshdn_status is detected. note: write a 1 to thermshdn_bgn_clr to reset. www.maximintegrated.com maxim integrated 32 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers (continued) interrupt state 1 address bit name description 0x04 7 0 unused: read back is 0. 6 iccovc_state icc overcurrent event 0: no rising edge on iccovc_status is detected. 1: a rising edge on iccovc_status is detected. note: write a 1 to iccovc_clr to reset. 5 lmtract_state limiter active event 0: no rising edge on lmtract_status is detected. 1: a rising edge on lmtract_status is detected. note: write a 1 to lmtract_clr to reset. 4 invalslot_state invalid slot event 0: no rising edge on invalslot_status is detected. 1: a rising edge on invalslot_status is detected. note: write a 1 to invalslot_clr to reset. 3 dhtact_state dht active event 0: no rising edge on dhtact_status is detected. 1: a rising edge on dhtact_status is detected. note: write a 1 to dhtact_status to reset. 2 spkcurnt_state speaker overcurrent event 0: no rising edge on spkcurnt_status is detected. 1: a rising edge on spkcurnt_status is detected. note: write a 1 to spkcurnt_clr to reset. 1 pvddovfl_state pvdd adc overlow event 0: no rising edge on pvddovfl_status is detected. 1: a rising edge on pvddovfl_status is detected. note: write a 1 to pvddovfl_clr to reset. 0 pvdduvlo_state pvdd supply voltage undervoltage lockout event 0: no rising edge on pvdduvlo_status is detected. 1: a rising edge on pvdduvlo_status is detected. note: write a 1 to pvddovfl_clr to reset. www.maximintegrated.com maxim integrated 33 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers (continued) interrupt flag 0 address bit name description 0x05 7 0 unused: read back is 0. 6 0 unused: read back is 0. 5 thermfb_end_flag die thermal foldback end flag0: no thermal foldback end interrupt is generated. 1: thermal foldback end interrupt is generated. 4 thermfb_bgn_flag die thermal foldback begin flag0: no thermal foldback begin interrupt is generated. 1: thermal foldback begin interrupt is generated. 3 thermwrn_end_flag thermal warning end flag 0: no thermal warning end is interrupt generated. 1: thermal warning end interrupt is generated. 2 thermwrn_bgn_flag thermal warning begin flag 0: no thermal warning begin interrupt is generated. 1: thermal warning begin interrupt is generated. 1 thermshdn_end_flag thermal shutdown end flag 0: no thermal shutdown end interrupt is generated. 1: thermal shutdown end interrupt is generated. 0 thermshdn_bgn_flag thermal shutdown begin flag0: no thermal shutdown begin interrupt is generated. 1: thermal shutdown begin interrupt is generated. www.maximintegrated.com maxim integrated 34 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers (continued) interrupt flag 1 address bit name description 0x06 7 0 unused: read back 0. 6 iccovc_flag icc overcurrent flag0: no icc overcurrent interrupt is generated. 1: icc overcurrent interrupt is generated. 5 lmtract_flag limiter active flag 0: no limiter active interrupt is generated. 1: limiter active interrupt is generated. 4 invalslot_flag invalid slot flag 0: no invalid slot interrupt is generated. 1: invalid slot interrupt is generated. 3 dhtact_flag dht active flag 0: no dynamic headroom tracking active slot interrupt is generated. 1: dynamic headroom tracking active slot interrupt is generated. 2 spkcurnt_flag speaker overcurrent flag0: no speaker overcurrent interrupt is generated. 1: speaker overcurrent interrupt is generated. 1 pvddovfl_flag pvdd adc overlow flag 0: no pvdd adc overlow interrupt is generated. 1: pvdd adc overlow interrupt is generated. 0 pvdduvlo_flag pvdd supply voltage undervoltage lockout flag 0: no pvdd uvlo interrupt is generated. 1: pvdd uvlo interrupt is generated. www.maximintegrated.com maxim integrated 35 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers (continued) interrupt enable 0 address bit name description 0x07 7 0 unused: read back is 0. 6 0 unused: read back is 0. 5 thermfb_end_en die thermal foldback end interrupt enable0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when thermfb_end_flag transitions from 0 to 1. 4 thermfb_bgn_en die thermal foldback begin interrupt enable0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when thermfb_end_flag transitions from 0 to 1. 3 thermwrn_end_ en thermal warning end interrupt enable 0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when thermwrn_end_ flag transitions from 0 to 1. 2 thermwrn_bgn_ en thermal warning begin interrupt enable 0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when thermwrn_bgn_ flag transitions from 0 to 1. 1 thermshdn_end_ en thermal shutdown end interrupt enable0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when thermshdn_end_ flag transitions from 0 to 1. 0 thermshdn_bgn_ en thermal shutdown begin interrupt enable0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when thermshdn_bgn_ flag transitions from 0 to 1. www.maximintegrated.com maxim integrated 36 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers (continued) interrupt enable 1 address bit name description 0x08 7 0 unused: read back is 0. 6 iccovc_en icc overcurrent enable0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when iccovc_flag transitions from 0 to 1. 5 lmtract_en limiter active interrupt enable 0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when lmtract_flag transitions from 0 to 1. 4 invalslot_en invalid slot interrupt enable0: interrupt is disabled (default). 1: interrupt enabled. irq is pulled low when invalslot_flag transitions from 0 to 1. 3 dhtact_en dht active interrupt enable 0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when dhtact_flag transitions from 0 to 1. 2 spkcurnt_en speaker overcurrent interrupt enable0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when spkcurnt_flag transitions from 0 to 1. 1 pvddovfl_en pvdd adc overlow interrupt enable 0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when pvddovfl_flag transitions from 0 to 1. 0 pvdduvlo_en pvdd supply voltage undervoltage lockout interrupt enable 0: interrupt is disabled (default). 1: interrupt is enabled. irq is pulled low when pvdduvlo_flag transitions from 0 to 1. www.maximintegrated.com maxim integrated 37 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers (continued) interrupt clear 0 address bit name description 0x09 7 0 unused: read back is 0. 6 0 unused: read back is 0. 5 thermfb_end_clr die thermal foldback end interrupt clear 0: no effect. 1: clears the thermfb_end_state and thermfb_end_flag. 4 thermfb_bgn_clr die thermal foldback begin interrupt clear 0: no effect. 1: clears the thermfb_bgn_state and thermfb_bgn_flag. 3 thermwrn_end_clr thermal warning end interrupt clear 0: no effect. 1: clears the thermwrn_end_state and thermwrn_end_flag. 2 thermwrn_bgn_clr thermal warning begin interrupt clear 0: no effect. 1: clears the thermwrn_bgn_state and thermwrn_bgn_flag. 1 thermshdn_end_clr thermal shutdown end interrupt clear 0: no effect. 1: clears the thermshdn_end_state and thermshdn_end_flag. 0 thermshdn_bgn_clr thermal shutdown begin interrupt clear 0: no effect. 1: clears the thermshdn_bgn_state and thermshdn_bgn_flag. www.maximintegrated.com maxim integrated 38 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers (continued) interrupt clear 1 address bit name description 0x0a 7 0 unused: read back is 0. 6 iccovc_clr icc overcurrent clear 0: no effect. 1: clears the iccovc_state and iccovc_flag. 5 lmtract_clr limiter active interrupt clear 0: no effect. 1: clears the lmtract_state and lmtract_flag. 4 invalslot_clr invalid slot interrupt clear 0: no effect. 1: clears the invalslot_state and invalslot_flag. 3 dhtact_clr dht active interrupt clear 0: no effect. 1: clears the dhtact_state and dhtact_flag. 2 spkcurnt_clr speaker overcurrent interrupt clear 0: no effect. 1: clears the spkcurnt_state and spkcurnt_flag. 1 pvddovfl_clr pvdd adc overlow interrupt clear 0: no effect. 1: clears the pvddovfl_state and pvddovfl_flag. 0 pvdduvlo_clr pvdd supply voltage undervoltage lockout interrupt clear 0: no effect. 1: clears the pvdduvlo_state and pvdduvlo_flag. live status 1 address bit name description 0x0b 7 0 unused: read back 0. 6 0 unused: read back 0. 5 0 unused: read back 0. 4 0 unused: read back 0. 3 alcinfh_status alc ininite hold event 0: alc is not in ininite hold state 1: alc is in ininite hold state 2 alcact_status alc active status 0: alc is not reducing the gain of the pga 1: alc is reducing the gain of the pga due to low battery event 1 alcmut_status alc mute status 0: alc has not muted the audio path 1: alc has muted the audio path 0 0 unused: read back 0. www.maximintegrated.com maxim integrated 39 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers (continued) state 1 address bit name description 0x0c 7 0 unused: read back is 0. 6 0 unused: read back is 0. 5 0 unused: read back is 0. 4 0 unused: read back is 0. 3 alcinfh_state alc ininite hold event 0: no rising edge on alcinfh_status is detected. 1: a rising edge on alcinfh_status is detected. 2 alcact_state alc activated event 0: no rising edge on alcact_status is detected. 1: a rising edge on alcact_status is detected. 1 alcmut_state alc mute event 0: no rising edge on alcmut_status is detected. 1: a rising edge on alcmut_status is detected. 0 0 unused: read back is 0. flag 1 address bit name description 0x0d 7 0 unused: read back is 0. 6 0 unused: read back is 0. 5 0 unused: read back is 0. 4 0 unused: read back is 0. 3 alcinfh_flag alc ininite hold flag 0: no interrupt generated.1: interrupt generated. 2 alcact_flag alc activated flag 0: no interrupt generated.1: interrupt generated. 1 alcmut_flag alc mute flag 0: no interrupt generated.1: interrupt generated. 0 0 unused: read back is 0. www.maximintegrated.com maxim integrated 40 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 3. interrupt registers (continued) irq enable 1 address bit name description 0x0e 7 0 unused: read back is 0. 6 0 unused: read back is 0. 5 0 unused: read back is 0. 4 0 unused: read back is 0. 3 alcinfh_en alc ininite hold interrupt enable 0: interrupt disabled (default)1: interrupt enabled. irq is pulled low when alcinfh transitions from 0 to 1. 2 alcact_en alc activated interrupt enable 0: interrupt disabled (default)1: interrupt enabled. irq is pulled low when alcact transitions from 0 to 1. 1 alcmut_en alc mute interrupt enable 0: no interrupt generated1: interrupt enabled. irq is pulled low when alcmut transitions from 0 to 1. 0 0 unused: read back is 0. irq clear 1 address bit name description 0x0f 7 0 unused: read back is 0. 6 0 unused: read back is 0. 5 0 unused: read back is 0. 4 0 unused: read back is 0. 3 alcinfh_clr clear alc ininite hold interrupt 0: no effect 1: clears alcfinh_state and alcinfh_flag 2 alcact_clr clear alc activated interrupt 0: no effect 1: clears alcact_state and alcact_flag 1 alcmut_clr clear alc mute interrupt 0: no effect 1: clears alcmut_state and alcmut_flag 0 0 unused: read back is 0. www.maximintegrated.com maxim integrated 41 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
digital audio interface the digital audio interface (dai) is highly flexible, supporting common sample rates ( table 4 ) with 16/24/ 32-bit depth for i 2 s/left-justified data as well as up to 16 slots in a time division multiplexed (tdm) format. operating in slave mode only, the MAX98372 eliminates the need for the external mclk signal that is typically used in i 2 s applications by generating mclk internally. this reduces emi and improves the rf immunity of the ic. table 5 lists the supported bclk frequencies when operating in this mode. table 4. supported sample rates table 5. supported bclk rates in slave mode address bit name description 0x 11 3 spk_sr[3:0] speaker path sample rate select0000C0101: reserved 0110: 32khz 0111: 44.1khz 1000: 48khz 1001: reserved 1010: 88.2khz 1011: 96khz 1100C1111: reserved 21 0 address bit name description 0x10 3 bsel[3:0] selects the number of bclks/lrclk0000: not supported 0001: not supported 0010: 32 bclks 0011: 48 bclks 0100: 64 bclks 0101: 96 bclks 0110: 128 bclks 0111: 192 bclks 1000: 256 bclks 1001: 384 bclks 1010: 512 bclks 1011C1111: not supported 21 0 www.maximintegrated.com maxim integrated 42 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
interface format the MAX98372 supports standard i 2 s, left-justified, and tdm data formats. i 2 s and left-justified formats support two audio channels of 16-, 24- or 32-bit depth. tdm supports up to 16 audio channels of 16-, 24-, or 32-bit depth. the ic supports slave operation only, and the lrclk and bclk pins operate as inputs. i 2 s ( figure 5 ) and left-justified ( figure 6 ) modes configure the lrclk signal to transition before each channel. with the default i 2 s settings lrclk low indicates left channel while lrclk high indicates the right channel. the msb of the audio word is latched on the second active bclk edge after an lrclk transition. in left-justified mode, the msb of the audio word is latched on the first active bclk edge after an lrclk transition. tdm mode ( figure 7 ) uses a frame sync pulse instead of a 50% duty cycle frame clock. the frame sync pulse (applied to the lrclk pin) is equal to one bclk period as a minimum, although the interface operates with longer periods; the rising edge of lrclk is used to indicate the start of a new frame. the falling edge can occur at any time as long as it does not violate the setup time requirements of the lrclk rising edge. in tdm, latch the msb of the first audio word on the first or second active bclk edge after an lrclk rising edge. coniguring the dai format specify the format by configuring the lrclk invert, bclk active edge, data delay, and tdm mode configuration bits ( table 6 ). table 6. configuration for digital audio interface format address bit name description 0x14 7 chansz[1:0] conigures channel word length 00: 8 bits 10: 24 bits 01: 16 bits 11: 32 bits 65 format[2:0] pcm format select000: i 2 s mode 001: left-justiied010: right-justiied 011: tdm mode 1 100: tdm mode 2 101C111: reserved 43 2 bcledge active bclk edge select0: data captured and valid on rising edge of bclk 1: data captured and valid on the falling edge of bclk 1 chansel non-tdm lrclk starting edge 0: falling lrclk indicates the start of a stereo pair. channel 0 when lrclk is low, channel 1 when lrclk is high. 1: rising lrclk indicates the start of a stereo pair. channel 0 when lrclk is high, channel 1 when lrclk is low. 0 0 0 www.maximintegrated.com maxim integrated 43 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
coniguring the digital audio input the dai may be configured to accept a mono pcm input, placed from anywhere from slots 1 to 16 of digital audio in tdm mode. in i 2 s and left-justified modes, two channels are available. route mono data directly to the speaker amplifier. if the input is stereo, input the right channel to the device and mix with the left channel if desired. sum left and right channels with the amplitude divided by 2 to reduce the dac input and avoid saturation. stereo summing and l or r choices are limited to 2 adjacent slots on the tdm bus. table 7. pcm receive channel enables address bit name description 0x15 7 rx_ch7_en receive channel enable0: receive channel 7 is disabled. 1: receive channel 7 is enabled. 6 rx_ch6_en receive channel enable0: receive channel 6 is disabled. 1: receive channel 6 is enabled. 5 rx_ch5_en receive channel enable0: receive channel 5 is disabled. 1: receive channel 5 is enabled. 4 rx_ch4_en receive channel enable0: receive channel 4 is disabled. 1: receive channel 4 is enabled. 3 rx_ch3_en receive channel enable0: receive channel 3 is disabled. 1: receive channel 3 is enabled. 2 rx_ch2_en receive channel enable0: receive channel 2 is disabled. 1: receive channel 2 is enabled. 1 rx_ch1_en receive channel enable0: receive channel 1 is disabled. 1: receive channel 1 is enabled. 0 rx_ch0_en receive channel enable0: receive channel 0 is disabled. 1: receive channel 0 is enabled. www.maximintegrated.com maxim integrated 44 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 7. pcm receive channel enables (continued) address bit name description 0x16 7 rx_ch15_en receive channel enable0: receive channel 15 is disabled. 1: receive channel 15 is enabled. 6 rx_ch14_en receive channel enable0: receive channel 14 is disabled. 1: receive channel 14 is enabled. 5 rx_ch13_en receive channel enable0: receive channel 13 is disabled. 1: receive channel 13 is enabled. 4 rx_ch12_en receive channel enable0: receive channel 12 is disabled. 1: receive channel 12 is enabled. 3 rx_ch11_en receive channel enable 0: receive channel 11 is disabled. 1: receive channel 11 is enabled. 2 rx_ch10_en receive channel enable0: receive channel 10 is disabled. 1: receive channel 10 is enabled. 1 rx_ch9_en receive channel enable0: receive channel 9 is disabled. 1: receive channel 9 is enabled. 0 rx_ch8_en receive channel enable0: receive channel 8 is disabled. 1: receive channel 8 is enabled. www.maximintegrated.com maxim integrated 45 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 8. tdm channel selection for mono replay figure 5. i 2 s digital audio format examples address bit name description 0x18 7 dmonomix_ch1_source[3:0] digital monomix source selection0000: channel 1 gets pcm rx channel 0. 0001: channel 1 gets pcm rx channel 1. 0010: channel 1 gets pcm rx channel 2. 0011: channel 1 gets pcm rx channel 3. 1111: channel 1 gets pcm rx channel 15. 65 4 3 dmonomix_ch0_source[3:0] digital monomix source selection0000: channel 0 gets pcm rx channel 0. 0001: channel 0 gets pcm rx channel 1. 0010: channel 0 gets pcm rx channel 2. 0011: channel 0 gets pcm rx channel 3. 1111: channel 0 gets pcm rx channel 15. 21 0 0x19 1 dmonomix_cfg[1:0] monomix coniguration00: output of monomix is channel 0. 01: output of monomix is channel 1. 10: output of monomix is (channel 0 + channel 1)/2. 11: reserved 0 www.maximintegrated.com maxim integrated 46 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
figure 6. left-justified digital audio format examples www.maximintegrated.com maxim integrated 47 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
figure 7. tdm digital audio format examples tdm mode 1, 16 32-bit channels latched on falling edge of bclk, pcm_bcledge = 1, pcm_format = 011 lrclk bclk dout d 30 d1 d0 d 31 d 30 din d 31 hi-z hi-z d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 30 d1 d0 d 31 d 30 d 31 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 lrclk bclk dout d 30 d1 d0 d 31 d 30 din d 31 hi-z hi-z d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 30 d1 d0 d 31 d 30 d 31 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 tdm mode 1, 16 32-bit channels latched on rising edge of bclk, pcm_bcledge = 0, pcm_format = 011 bclk dout d 30 d1 d0 d 31 d 30 din d 31 hi-z hi-z d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 30 d1 d0 d 31 d 30 d 31 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 lrclk tdm mode 2, 16 32-bit channels latched on falling edge of bclk, pcm_bcledge = 1, pcm_format = 100 lrclk bclk dout d 30 d1 d0 d 31 d 30 din d 31 hi-z hi-z d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 30 d1 d0 d 31 d 30 d 31 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 d 31 d 30 d1 d0 tdm mode 2, 16 32-bit channels latched on rising edge of bclk, pcm_bcledge = 0, pcm_format = 100 www.maximintegrated.com maxim integrated 48 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
digital passband filtering the MAX98372 features an optional highpass filter with selectable corner frequency (50hz, 100hz, 200hz, 400hz, and 800hz), or a dc-blocking filter with a cutoff frequency of 2hz (80db attenuation). the MAX98372 supports 5 sample rates: 32khz, 44.1khz, 48khz, 88.2khz, or 96khz. for 32khz, 44.1khz, and 48khz, a linear phase, half-band filter effectively defines the response. for 96khz operation, a different filter characteristic is employed with a smooth roll off above 20khz. set the digital highpass filter corner frequency though the dachpf bits in control register 0x1c ( table 9 ). create user-programmed filtering through the biquad filter coefficients by setting the dachpf[2:0] bits to 111. see the biquad filter section. the MAX98372 also features a configurable pvdd adc filter. this cutoff frequency of this filter can be adjusted by setting the pvdd_adc_bw bits in register 0x1c. these filtered pvdd adc measurements can be fed to the dht or limiter. filtered or unfiltered pvdd adc readings can be sent to the dht and limiter. to send filtered data to the limiter or dht, set the pvdd_filt_to_lmtr or pvdd_ filt_to_dht bits, respectively. see table 9 . table 9. digital highpass filter address bit name description 0x1c 7 pvdd_filt_to_lmtr 0: uniltered pvdd adc measurements are sent to the limiter. 1: lowpass iltered pvdd adc measurements are sent to limiter. 6 pvdd_filt_to_dht 0: uniltered pvdd adc measurements are sent to dht. 1: lowpass iltered pvdd adc measurements are sent to dht. 5 pvdd_adc_bw[1:0] pvdd adc lowpass filter selection 00: pass through, ilter off 01: 2hz cutoff 10: 20hz cutoff 11: 200hz cutoff 4 3 0 0 2 dachpf[2:0] digital highpass filter 000: pass through, ilter off 001: dc blocker is enabled. 010: 50hz hpf is enabled. 011: 100hz hpf is enabled. 100: 200hz hpf is enabled. 101: 400hz hpf is enabled. 110: 800hz hpf is enabled. 111: user programmable using dac_bq_b[0C2] and dac_bq_a[1C2] registers 10 www.maximintegrated.com maxim integrated 49 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
biquad filter the digital biquad filter has five user-programmable coefficients (b0, b1, b2, a1, and a2), and each individual coefficient is 3 bytes (24 bits) long (a0 is fixed at 1). they occupy 15 consecutive registers ( table 10 ) and each set of three registers (per coefficient) must be programmed consecutively for the settings to take effect. the coeffi- cients are stored using a twos complement format where the first 4 bits are the integer portion and the last 20 bits are the decimal portion that results in an approximate +8 to -8 range for each coefficient. the digital biquad coefficients are uninitialized at power- up, and if the filter is going to be used, the coefficients must be programmed before the device and biquad filter are enabled. the transfer function is: ++ = ++ -1 2 01 2 -1 -2 12 - b b *z b *z h( z ) 1 a *z a *z signal path delaydelay through the signal path is minimized by use of efficient signal processing and hardware dsp. delay is affected by the configuration of various blocks and filters in the signal path. typical delay, listed in number of audio samples, is shown in table 11 . table 11. signal path delay table 10. biquad filter coefficient registers reg reg name r/w bit name value 0x1d biquad coeficient b0 r/w b0[23:16] 0x00 0x1e r/w b0[15:8] 0x00 0x1f r/w b0[7:0] 0x00 0x20 biquad coeficient b1 r/w b1[23:16] 0x00 0x21 r/w b1[15:8] 0x00 0x22 r/w b1[7:0] 0x00 0x23 biquad coeficient b2 r/w b2[23:16] 0x00 0x24 r/w b2[15:8] 0x00 0x25 r/w b2[7:0] 0x00 0x26 biquad coeficient a1 r/w a1[23:16] 0x00 0x27 r/w a1[15:8] 0x00 0x28 r/w a1[7:0] 0x00 0x29 biquad coeficient a2 r/w a2[23:16] 0x00 0x2a r/w a2[15:8] 0x00 0x2b r/w a2[7:0] 0x00 sample rate (k) delay (samples) 32 19 44.1 19 48 18 88.2 15 96 14 www.maximintegrated.com maxim integrated 50 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
pvdd adc the pvdd adc has an effective 8khz sample rate, 8-bit resolution and full scale input of 18v. the bandwidth of the output is user programmable to reject both high frequency and audio band noise from the supply, and to tradeoff reaction time to follow the supply accurately. the pvdd_adc values are used to by the dht and limiter circuits. these values can be read back over i 2 c through the pvdd_adc register located at 0x34. see table 12 . the pvdd adc readback is real time and is dependant on the pvdd_adc_bw register setting in register 0x1c. digital volume control a user-controlled digital volume control with an attenuation range of 0db to -63db in 0.5db steps, as well as a mute setting is available. volume ramping is available and configurable with through the dvol_ramp_byp bit in the digital volume control register. see table 13 . table 12. pvdd measurement adc table 13. digital volume ramping and digital volume address bit name description 0x34 7 pvdd_adc[7:0] 0: 5.35v1: 5.40v 2: 5.45v 3: 5.50v 253: 18.05v 254: 18.10v 255: 18.15v 65 4 3 2 1 0 address bit name description 0x2d 7 dvol_ramp_byp digital volume ramp bypass 0: ramping is enabled at startup, shutdown and all volume changes. 1: all volume ramping is disabled. 6 dvol[6:0] digital volume control 0: 0db 1: -0.5db 2: -1.0db 3: -1.5db 125: -62.5db 126: -63.0db 127: digital mute 54 3 2 1 0 www.maximintegrated.com maxim integrated 51 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
output voltage scaling the MAX98372 operates over a large supply voltage range. as a result, the part must be configured to scale the output signals across possible pvdd supply range. spk_gain_max applies gain after the dac to achieve this voltage scaling. digital gain can be applied before the dac by using the dpga_clip register. in conjunction with the spk_gain_max setting, the overall full-scale behavior of the device is set. the dpga and spk_gain_max register settings are shown in table 14 . gain through the signal path is referenced to the full-scale output of the dac, which is 2.1dbv. the MAX98372 output level can be calculated based on the digital input signal level and selected amplifier gain. output signal level (dbv) = input signal level (dbfs) + 2.1dbv + spk_gain_max (db) where 0dbfs is referenced to 0dbv. table 14. digital gain settings and output voltage scaling address bit name description 0x2e 7 dpga_clip[3:0] digital gain settings (db) 0000: 0 0110: 3.0 0001: 0.5 0111: 3.5 0010: 1.0 1000: 4.0 0011: 1.5 1001: 5.0 0100: 2.0 1010: 6.0 0101: 2.5 1011C1111: 0 65 4 3 spk_gain_max[3:0] speaker no-load output voltage maximum sets the output voltage level (v p ) of 0dbfs. 0000: 5.37 (9.5db) guaranteed no clipping0001: 6.03 (10.5db) best near 5.5v (min) operating 0010: 6.77 (11.5db) 0011: 7.59 (12.5db) 0100: 8.52 (13.5db) 2-cell li-ion operation 0101: 9.56 (14.5db) 0110: 10.72 (15.5db) 0111: 12.03 (16.5db) 12v nominal 1000: 13.5 (17.5db) 3-cell li-ion operation 1001: 15.15 (18.5db) 1010: 16.99 (19.5db) optimum for 16.5v pvdd operation 1011: 19.07 (20.5db) 1100C1111: reserved 21 0 www.maximintegrated.com maxim integrated 52 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
dynamic headroom tracking the MAX98372 features dynamic headroom tracking (dht) to preserve consistant dynamic range in the pres - ence of a varying supply. dht maintains consistent vol - ume and listening levels up to a predefined point, below full scale. dht maintains the headroom of the amplifier at signal peaks that occur above this level (referred to as the rotation point or rp) up to full scale to ensure consistent, smooth compression of these signals in the presence of supply variations. a key element in tracking available headroom is the pvdd adc. the output of the adc feeds the dht cir - cuitry with the necessary inputs to calculate the amount of compression (if any) applied to signal peaks. filtering can be applied to the pvdd adc readings used by the dht by using the pvdd_filt_to_dht bit ( table 9 ). the dynamic headroom tracking function relies heav - ily on two parameters to be effective. the first is the spk_gain_max setting explained in the output voltage scaling section. this sets the maximum no-load peak output voltage (v mpo) that the class d amplifier repro - duces when fed with a full-scale (0dbfs) signal. the second parameter is the rotation point (rp). the rotation point sets the level in dbfs above which compression is applied to the output signal, if the pvdd voltage level drops below v mpo . dht uses a parameter called spk_gain_min to control the maximum compression ratio. this parameter can enable the addition of a second inflection point on the transfer function. the behavior of dht has 3 modes, depending on the measured value of v pvdd by the pvdd adc: mode 1: pvdd voltage is greater than maximum peak output voltage. if v pvdd is greater than v mpo then there is no action taken by the dht block. there is sufficient headroom for the amplifier to linearly represent any signal up to and including 0dbfs; the signal transfer function is unaffected. figure 8. example of dynamic headroom tracking in mode 1 operation v mpo 0 -6 rotation point (rp) set by user output voltage level (v p ) input signal level (dbfs) pvdd > v mpo v exp_rp www.maximintegrated.com maxim integrated 53 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
mode 2: v pvdd is less than v mpo , and greater than the output voltage as set by the rotation point register set - ting (v exp_rp ). for example, if the rp is set for -6dbfs, then the peak voltage on the output (v exp_rp ) would be v mpo /2). if this is the case, the transfer function for signals below the rp is reproduced exactly as in mode 1. any signals between rp and 0dbfs are now subject to an audio compression function, acting in the dsp block of the MAX98372. this acts with appropriate attenuation for peaks over the rp in magnitude with programmable attack and release times (see the dht ballistics section). figure 9 and figure 10 show the effect on the transfer function. the compression ratios in mode 2 are effectively defined by the combination of: pvdd, rp, spk_gain_max, and spk_gain_min settings. the ballistics of the compressor (in both mode 2 and mode 3) are set by the parameters in table 16 and figure 21 . mode 3a: pvdd voltage is less than the rotation points maximum output voltage, v exp_rp . when the rotation point is set to a high value (for example -6dbfs) this mode applies. if v pvdd is less than v exp_rp , then hard limiting is applied to peaks and the effective rp is now set by the need to fit peak signals into the available pvdd range. the MAX98372 automatically determines a new rp based on the pvdd adc. normally, rp is set so that this mode is never used, and the v exp_rp as set by the rp and spk_gain_max combination should reflect the lowest pvdd value expected. in this mode, the spk_gain_min parameter is set to be well below the v exp_rp . figure 9. example of dynamic headroom tracking in mode 2 operation with a high rp v mpo input (dbfs) 0 -6 v exp_rp peak output scaled to fit available pvdd compression ratio is scaled to fit transfer function automatically between rotation point and theoretical peak output voltage (as determined by pvdd adc block) decreasing pvdd output voltage level (v p ) input signal level (dbfs) pvdd < v mpo rp set by user spk_gain_max www.maximintegrated.com maxim integrated 54 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 15. speaker gain minimum voltage figure 10. example of dynamic headroom tracking in mode 2 operation with a low rp v mpo 0 -30 v exp_rp peak output scaled to fit available pvdd compression ratio is scaled to fit transfer function automatically between rotation point and theoretical peak output voltage (as determined by pvdd adc block) decreasing pvdd pvdd < v mpo output voltage level (v p ) input signal level (dbfs) rp set by user spk_gain_min spk_gain_max address bit name description 0x31 7 spk_gain_min[3:0] speaker gain min (v p ): 0000: 5.37 (9.5db) 0111: 12.03 (16.5db) 0001: 6.03 (10.5db) 1000: 13.5 (17.5db) 0010: 6.77 (11.5db) 1001: 15.15 (18.5db) 0011: 7.59 (12.5db) 1010: 16.99 (19.5db) 0100: 8.52 (13.5db) 1011: 18.0 (20.0db) 0101: 9.56 (14.5db) 1100C1111: reserved 0110: 10.72 (15.5db) 65 4 3 dht_vrot_pnt[3:0] dht rotation point (dbfs)0000: -0.5 1000: -10 0001: -1 1001: -12 0010: -2 1010: -15 0011: -3 1011: -18 0100: -4 1100: -20 0101: -5 1101: -22 0110: -6 1110: -25 0111: -8 1111: -30 21 0 www.maximintegrated.com maxim integrated 55 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
mode 3b: pvdd voltage is less than the speaker gain minimum output voltage. when the rotation point is set to a low value (for example -30dbfs) this mode applies. if v pvdd is less than spk_gain_min, the dht cannot compress the signal any further. so the compression ratio stays fixed, and as pvdd decreases below spk_gain_ min, the output signal starts to clip. this clipping can be eliminated if the limiter is enabled in addition to the dht. figure 11. example of dynamic headroom tracking in mode 3a operation v mpo 0 -6 decreasing pvdd rp set by user output voltage level (v p ) input signal level (dbfs) v exp_rp pvdd < v exp_rp when pvdd < v exp_rp a new rotation point is automatically determined and infinite compression is applied. spk_gain_max www.maximintegrated.com maxim integrated 56 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
figure 10 and figure 12 show an additional param - eter, spk_gain_min, on the transfer function plots. this parameter is useful when a lower rp is selected. spk_gain_min provides a means to create a maximum compression ratio. when the input signal reaches the maximum output voltage that pvdd can provide, the output signal starts to clip ( figure 12 ). this behavior may not be desirable, but the clipping can be eliminated by enabling the limiter. see figure 13 . figure 12. example of dynamic headroom tracking in mode 3b operation v mpo 0 -30 v exp_rp decreasing pvdd pvdd < spk_gain_min output voltage level (v p ) input signal level (dbfs) rp set by user spk_gain_min compression clipping spk_gain_max www.maximintegrated.com maxim integrated 57 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
the transfer function shown in figure 13 is typically preferable to the transfer function shown in figure 12 . when dht and the limiter are used together, it allows for creation of a second inflection point on the transfer function. this second inflection point reduces the transition from compression to limiting and minimizes the audible impact of signal manipulation by the dht. figure 13. example of dynamic headroom tracking in mode 3b with limiter v mpo 0 -30 v exp_rp decreasing pvdd pvdd < spk_gain_min output voltage level (vp) input signal level (dbfs) rp set by user spk_gain_min compression limiting the performance shown in this figure is the result of the dht and the limiter working in concert spk_gain_max www.maximintegrated.com maxim integrated 58 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
dht ballistics when an input signal exceeds the rotation point, dht applies attenuation to the signal over some amount of time (this is configurable through the dht_atk_rate register 0x32). the instant that the large signal is input to the MAX98372, the output tries to reproduce that signal without any attenuation from the dht. over time, the dht applies compression to ensure that the signal can fit within the available pvdd voltage. if a large enough input signal is applied there can be hard clipping on the output for a short time ( figure 14 ). however, after the full attack time has completed, there should be no clipping. hard clipping can also be prevented by using the limiter. see the limiter section . observing the output waveform, notice that the amount of attenuation applied increases up to when vin(dbfs) = pvdd (dbfs). once vin(dbfs) is greater than pvdd(dbfs) the amount of attenuation observed in the output waveform appears to decrease. this is a result of the output clipping against the pvdd voltage level. the dht still takes the same amount of time to apply the compression as though it had the headroom to reproduce the signal. the amount of compression applied by dht depends on a few parameters: spk_gain_max, pvdd, input signal amplitude, and the rotation point. to establish where pvdd is relative to speaker gain max, use the following equation: figure 14. dynamic headroom tracking attack functionality v mpo input (dbfs) 0 -10 v exp_rp -3 db output voltage level (v p ) input signal level (dbfs) v pvdd = 8.4v rp set by user spk_gain_max -3 attack the attack arrow demostrates the transistion from an unattenuated signal to the compressed signal that occurs over the total attack time. www.maximintegrated.com maxim integrated 59 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
equation 1 mpo pvdd(v) pvdd(dbfs) 20log v ?? = ???? where pvdd(v) is the voltage readback from the pvdd adc, and v mpo is the maximum peak output voltage (v mpo ), see figure 14 . for example, if v pvdd = 12v and v mpo = 12v, then pvdd(dbfs) = 0dbfs. it should be noted that 0dbfs is the maximum value for pvdd(dbfs). if solving equation 1 returns a value greater than 0 then 0dbfs should be used for further calculations. this is important as dht only ever applies attenuation and never positive gain. if v pvdd = 8.4v and v spk_gain_max = 12v, then solving eq 1 gives -3.098dbfs. this is pvdds level relative to spk_gain_max in db. to find the expected compressed output voltage, use the following equation: equation 2 ?? = + ???? rp -pvdd(dbfs) attenuation(db) pvdd(dbfs) input(dbfs) v (dbfs) when pvdd(dbfs) = 0, the pvdd and the fraction term drop out, which gives attenuation equal to zero. this makes sense because when pvdd(dbfs) = 0, there is sufficient headroom to playback any signal input into the MAX98372 and no compression is applied. a nontrivial case might be if v pvdd = 8.4v, v mpo = 12v, rotation point = -10dbfs, and the input signal level is -5dbfs. next, we solve equation 3 with these values: equation 3 ?? = + ???? ?? = + ?? ?? = rp -pvdd(dbfs) pvdd(dbfs) input(dbfs) v (dbfs) 3.098dbfs -3.098dbfs -5dbfs -10dbfs -1.54dbfs for this example, the total amount of compression applied by dht 1.54db. dht attack rate and dht attack step can be configured to apply the 1.54db of attenuation of over a programmable amount of time. as a rule of thumb, attack times (product of attack rate, attack step, and number of steps) faster than 600s are not achievable. this is independent of sample rate. input data is rectified, filtered and converted to the log domain. the dsp compares the input data with filtered data from the pvdd adc then compression is applied within the dsp. the compressed data must be converted back to lin - ear scale and then output. the large number of complex computations required in the dsp requires a fixed 600s to complete the compression algorithm. as a result, attack times faster than 600s are not possible. see table 16 . continuing the same example when the input signal size decreases below the rotation point dht releases the 1.54db of attenuation it applied to the signal. the release time for dht is configurable through register 0x33. see table 17 . table 16. dynamic headroom tracking attack settings address bit name description 0x32 4 dht_atk_step[1:0] dht attack step size 00: 0.25db 01: 0.5 db 10: 1.0db 11: 2.0db (default) 32 dht_atk_rate[2:0] dht compressor attack rate all attack times in s/step 000: 17.5 (default) 001: 35 010: 70 011: 140 100: 280 101: 560 110: 1120 111: 2240 10 www.maximintegrated.com maxim integrated 60 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 19. limiter threshold select table 17. dynamic headroom tracking release settings table 18. dynamic gain enables address bit name description 0x4b 2 pvadc_en 0: pvdd adc is disabled. 1: pvdd adc is enabled. 1 lmtr_en 0: limiter is disabled.1: limiter is enabled. 0 dht_en 0: dynamic headroom tracking is disabled.1: dynamic headroom tracking is enabled. address bit name description 0x58 1 lmtr_th_sel[1:0] limiter threshold select00: user-programmable threshold (contents of register 0x59). 01: threshold is set by spk_gain_max. 10C11: threshold is set by pvdd level. 0 address bit name description 0x33 4 dht_rel_step[1:0] dht release step size00: 0.25db 01: 0.5db 10: 1.0db 11: 2.0db (default) 32 dht_rel_rate[2:0] dht compressor release rateall release times in ms/step 000: 45 (default) 001: 225 010: 450 011: 1150 100: 2250 101: 3100 110: 4500 111: 6750 10 www.maximintegrated.com maxim integrated 61 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
limiter the MAX98372 features a programmable limiter that is used to compress large near full-scale signals. the input signal level where the attenuation is applied varies based on how the limiter threshold select register is set. when lmtr_th_sel is set to 00, the limiter threshold is user configurable through register lmtr_thc. see table 20 . when lmtr_th_sel is set to 01, the threshold is determined by spk_gain_max. table 21 provides the threshold values. when lmtr_th_sel is set to 10 or 11, the part looks at the pvdd adc and the spk_gain_max setting and determines the maximum output swing that the part can deliver without clipping. input signals that require more voltage than is available on pvdd are limited to prevent clipping. filtering can be applied to the pvdd adc read - ings used by the limiter with the pvdd_filt_to_lmtr bit ( table 9 ). the limiter attack and release rates are measured in abso - lute time and are independent of sample rate. the limiter has its own set of configurable ballistics ( figure 26 ). thermal adc the MAX98372 features a die temperature monitoring adc. this 6-bit adc with a 100khz sample rate reports the die temperature from +100c to +163c. thrm_min_ temp sets the temperature at which the thermal foldback circuit initially activates. the measurements from the thermal adc can be filtered before they are used by the thermal foldback circuit, or the values can pass directly without being filtered. thrm_filt_sel controls the filter selection. thermal protection the MAX98372 continuously monitors die temperature to ensure that the temperature does not exceed the maxi - mum of +150c (typ). the device can warn the host if die temperature is approaching the limit and turns off the speaker amplifier if the limit is exceeded. the interrupt registers are maintained to ensure that host is alerted of the overtemperature event. thermal recovery behavior of the device is determined by the state of tdhsn_auto_ restart bit in the restart behavior (0x4d) register. if tshdn_auto_restart is reset, a drop in the die temperature below the thermal foldback threshold trig - gers an interrupt to the host, indicating that it is safe to turn on the speaker amplifier and resume audio playback. if tshdn_auto_restart is set, the device will turn on the speaker amplifier when the die temperature drops below the thermal foldback threshold setting. thermal foldback to allow a smoother audio response to high temperature events, the MAX98372 features a thermal foldback loop. as the die temperature rises above a threshold of set by thrm_min_temp register (+120c by default), the audio path is subjected to increasing attenuation, up to a maximum of -12db. see table 23 . table 20. manual limiter threshold settings table 21. limiter threshold address bit name description 0x59 4 lmtr_thc[4:0] manual limiter threshold setting (input referred) 00000: 0dbfs 00001: -1dbfs 00010: -2dbfs 00011: -3dbfs 11101: -29dbfs 11110: -30dbfs 11111: -31dbfs 32 1 0 spk_gain_max setting lmtr_threshold (db) 0x0b 0 0x0a -1 0x09 -2 0x08 -3 0x01 -10 0x00 -11 www.maximintegrated.com maxim integrated 62 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 22. limiter attack and release settings table 23. thermal adc measurements address bit name description 0x55 5 lmtr_rel_rate[2:0] limiter release time total time required for limiter to fully release 000: 15ms 001: 40ms 010: 70ms 011: 160ms 100: 300ms 101: 450ms 110: 600ms 111: 850ms 43 2 lmtr_atk_rate[2:0] limiter attack time total time required for limiter to fully attack 000 - 100: 160s 101: 320s 110: 640s 111: 1280s 10 address bit name description 0x37 5 thrm_adc_meas[7:0] 0: 100c1: 101c 62: 162c 63: 163c 43 2 1 0 0x38 5 thrm_min_temp[6:0] 0: 100c1: 101c 20: 120c (default) 39: 139c 40-63: 140c 43 2 1 0 0x39 2 thrm_filt_sel[2:0] 000: thrm adc lpf ilter on f c = 0.55khz 001: thrm adc lpf ilter on f c = 2.15khz 010: thrm adc lpf ilter on f c = 4.55khz 011: bypass ilter (default) 100: thrm adc peak detect ilter on f c = 0.55khz 101: thrm adc peak detect ilter on f c = 2.15khz 110: thrm adc peak detect ilter on f c = 4.55khz 111: bypass ilter 10 www.maximintegrated.com maxim integrated 63 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
the thermal foldback feature can be turned on through the thrm_fb_en bit, default is off ( table 25 ). the release rate of the attenuation and the slope of the effect can be set by the user ( table 24 ), the attack time is fixed at 10s/db. thrm_hold controls how long the temperature must stay on one side of the hysteresis threshold. thrm_rel controls the release rate of the attenuation applied by the thermal foldback circuit. thrm_slope controls the amount of attenuation per c. see table 24 . regardless of whether the thermal foldback feature is enabled, the thermal warning bit in the interrupt registers assert and generate an interrupt through the interrupt mask register when thermal foldback threshold tempera - ture is crossed. table 24. thermal foldback settings table 25. thermal foldback enable figure 15. thermal foldback performance address bit name description 0x36 7 thrm_hold[1:0] thermal foldback hold settings00: 0ms 01: 20ms 10: 40ms 11: 80ms (default) 6 5 0 - 4 0 - 3 thrm_rel[1:0] thermal foldback release times 00: 3ms/db 01: 10ms/db 10: 100ms/db 11: 300ms/db 21 thrm_slope[1:0] thermal foldback slope settings00: 0.5db/c 01: 1.0db/c 10: 2.0db/c 11: reserved 0 address bit name description 0x4c 0 thrm_fb_en thermal foldback enable 0: thermal foldback disabled 1: thermal foldback enabled www.maximintegrated.com maxim integrated 64 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
automatic level control (alc) the MAX98372 automatic level control feature (alc) reduces the amplifier gain at the pga if the battery volt - age drops below a programmable brownout threshold preventing battery collapse. alc compares pvdd to the programmable brownout threshold set by alc_th and alc_range. when pvdd drops below the brownout threshold the alc reduces amplifier gain at a program - mable attack rate and step size set by alc_atk_rate and alc_atk_step. the gain change occurs immedi - ately even when zero-cross detection is enabled. pga gain reduction is programmable from 1db to 9db in 1db steps below the nominal setting of the gain register (reg - ister 0x64, alc_max_atten). if gain reductions cause the battery voltage to rise above the brownout threshold, the gain reduction stops to a level where pvdd again drops below the brownout threshold after a programmable debounce time set by alc_rls_dbt. the rate at which the gain is restored is set by alc_rls_rate and alc_ rls_cfg. if the battery supply voltage remains below the brownout threshold after the amplifier gain has been reduced by programmed setting, the speaker amplifier is, by default, muted after a programmable delay time set by alc_mute_dly. the battery debounce time alc_rls_ dbt is the time the battery must be above the threshold before moving to the release state either from the mute state or the hold state. the transition to mute can be disabled by resetting the alc_mute_en bit. if alc_rls_dbt is set to infinite hold, the gain remains either muted or at the programmed reduction level below the nominal pga gain setting until the als_rls_tgr bit is set. when alc_mute_en bit is set the gain remains at programmed reduction value below the pga gain setting until pvdd rises above the brownout threshold. alc gain reductions are independent of the minimum attenuation setting of the pga. if enabled, gain ramping has no effect on alc attack, release or mute actions. figure 16 C figure 19 provide examples of how the alc behaves in four scenarios. if pvdd is held close to the alc threshold, alc will be stuck in a state of intermedi - ate attenuation. intermediate attenuation means that alc started to reduce gain but never reaches the programmed maximum attenuation. gain is constant in this state, in- between original gain and maximum attenuation as alc is neither attacking of releasing. figure 20 shows an example of alc intermediate attenuation. figure 16. alc example 1: battery drops below brownout threshold and quickly recovers v pvdd programmable threshold speaker gain attack rate per attack step release de-bounce time release rate v pvdd drops below threshold 14db 5db mute max attenuation (0db to 9db) alcth t t www.maximintegrated.com maxim integrated 65 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
figure 17. alc example 2: battery drops below brownout threshold and stays low v pvdd programmable threshold speaker gain attack rate per attack step mute delay v pvdd drops below threshold 14db 5db mute max attenuation (0db to 9db) alcth mute enabled tt www.maximintegrated.com maxim integrated 66 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
figure 18. alc example 3: battery drops below brownout threshold and stays long enough for the amp to mute (non-infinite hold time) v pvdd programmable threshold speaker gain attack rate per attack step v pvdd drops below threshold 14db 5db mute max attenuation (0db to 9db) alcth mute enabled, non-infinite hold t t release rate release de-bounce time www.maximintegrated.com maxim integrated 67 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
figure 19. alc example 4: battery drops below brownout threshold and stays long enough for the amp to mute (infinite hold time) v pvdd programmable threshold speaker gain attack rate per attack step v pvdd drops below threshold 14db 5db mute max attenuation (0db to 9db) alcth mute enabled, infinite hold t t release rate host triggers release www.maximintegrated.com maxim integrated 68 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
figure 20. alc example 5: immediate attenuation v pvdd programmable threshold speaker gain attack rate per attack step release de-bounce time release rate v pvdd drops below threshold 14db 5db mute max attenuation (0db to 9db) alcth t t www.maximintegrated.com maxim integrated 69 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 26. alc threshold address bit name description 0x62 7 0 0 6 alc_range 0: 2-cell operation1: 3-cell operation 5 alc_en 0: alc is not enabled (default) 1: alc is enabled. 4 alc_th[4:0] value (hex) alc_range = 0 alc_range = 1 00 7.80 01 7.95 02 8.10 03 5.5 8.25 04 5.6 8.40 3 05 5.7 8.55 06 5.8 8.70 07 5.9 8.85 08 6.0 9.00 09 6.1 9.15 2 0a 6.2 (default) 9.30 (default) 0b 6.3 9.45 0c 6.4 9.60 0d 6.5 9.75 1 0e 6.6 9.90 0f 6.7 10.05 10 6.8 10.20 11 6.9 10.35 0 12 7.0 10.50 13 7.1 10.65 14 7.2 10.80 15 7.3 10.95 www.maximintegrated.com maxim integrated 70 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 27. alc attack table 28. alc attenuation and release address bit name description 0x63 7 alc_atk_step[3:0] alc attack step 0: -1 db step (default) 1: -2 db step 2: -3 db step 3: -4 db step 4: -5 db step 5: -6 db step 6: -7 db step 7: -8 db step 8: -9 db step f: -9 db step 65 4 3 0 0 2 atk_rate alc attack rate 000: 10 m s/step (default) 001: 20 m s/step 010: 40 m s/step 011: 80 m s/step 100: 160 m s/step 101: 320 m s/step 110: 640 m s/step 111: 1280 m s/step 10 address bit name description 0x64 7 alc_max_atten[3:0] alc maximum gain reduction setting (db)0000: -1 0001: -2 0010: -3 0011: -4 0100: -5 0101: -6 0110: -7 0111: -8 1000: -9 (default) 65 4 3 0 0 2 atk_rls_rate[2:0] alc release rates (ms/db)000: 10 (default) 001: 50 010: 100 011: 250 100: 500 101: 750 110: 1000 111: 1500 10 www.maximintegrated.com maxim integrated 71 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 29. alc infinite hold release table 30. alc configuration address bit name description 0x65 7 alc_rls_cfg[1:0] 00: uses alc_rls_rate[2:0] as deined 01: 8x faster release rate 10: 64x faster release rate 11: 512x faster release rate 6 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 alc_rls_tgr 0: register is self-clearing and always read back as 0 1: if ininite hold is enabled, write a 1 to unlock the release phase. if ininite hold is enabled and a 1 is written while a battery low event is occurring, the gain is not released address bit name description 0x66 7 alc_mute_en 0: alc cannot mute the channel path 1: alc can mute the channel path (default) 6 alc_mute_dly[2:0] delay before onset of mute000: 0.3ms 001: 0.6ms (default) 010: 1ms 011: 3ms 100: 4.5ms 101: 6ms 110: 15ms 111: 30ms 54 3 0 0 2 alc_rls_dbt[2:0] battery debounce time (ms) 000: 10 001: 100 010: 250 (default) 011: 500 100: 0.01 101: 0.1 110: 1 111: ininite hold 10 www.maximintegrated.com maxim integrated 72 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
note: x are padding bits and zeros that make up the remaining bits in the rest of the frame. dout operation and data format the MAX98372 features a bidirectional dout pin to provide feedback data to the applications processor and other MAX98372s. the data output from dout shares the status of amplifier dht, thermal foldback adjustments, and alc status. the data format used to frame the data carried on dout is the same as the data format of the input data on the din pin. the dout pin only drives out during the slot assigned to the amplifier by tx_ch#_en bit. at all other times, the pin is an input (to allow other devices to drive the dout signal). the data output on the dout pin is structured as shown in figure 21 . where dht_info[7:0] contains the dht attenuation (in db), therm_info [5:0] contains the thermal foldback attenuation, and alc[0] contains transmitter devices alc comparator status broadcast out to other amplifiers on the same bus. it is decoded as shown in figure 21 . table 31. dht info table 32. therm info table 33. thermal and dht link enables figure 21. dout data structure dht_info[7:0] slot 1 slot 2 slot 3 slot 4 therm_info[5:0] x alc value decode ( db) 0 -95.625 1 -95.25 2 -94.875 0.375 (steps) 253 -0.750 254 -0.375 255 0 value decode (c) 0 no thermal adjustment needed 1 +1 2 +2 1 (steps) 61 +61 62 +62 63 +63 address bit name description 0x4e 1 thrm_link_en 0: disable thrm link. 1: enable thrm link. 0 dht_link_en 0: disable dht link. 1: enable dht link. www.maximintegrated.com maxim integrated 73 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
the thrm_link_en, dht_link_en, and alc_link_ en are intended to be used as the global enables of receive data function of the icc. it should also be noted that for the icc to function properly icc_oc_ena bit in register 0x5c must be set to 1 so that the overcurrent protection on dout is enabled. interchip communication the MAX98372 features an interchip communication (icc) bus that facilitates synchronized gain adjustments between groups of MAX98372 amplifiers. multiampliier grouping by setting registers 0x3a through register 0x3f, registers 0x60 and 0x61, it is possible to group MAX98372 ampli - fiers so that any gain adjustments due to dht and/or thermal foldback and/or alc status are synchronized. each amplifier is configured by a register setting to moni - tor dout during certain slots. the slots selected define to which group each amplifier belongs. therefore, each amplifier in a group must have the same settings for rx enables. each individual amplifier must also have only one tx_ch# enable set as well as the corresponding rx_ch# enable. for example, if there are four amplifiers and two groups are needed, then one configuration may be that amplifiers 1 and 3 would belong to one group and amplifiers 2 and 4 belong to another. assign amplifier 1 to broadcast on slot 0 through the tx_ch0_en bit enable and amplifier 3 to broadcast on slot 2 through the tx_ch2_en bit. then configure both amplifiers to enable rx enable to listen to both slots 0 and 2, so both amplifiers would have rx_ dht_ch0_en and rx_dht_ch2_en enabled. while this configuration groups the amplifier in the same dht group, there is another set of grouping registers for ther - mal foldback. these registers can be configured identi - cally or differently to accommodate the desired behavior. to configure the second group, set amplifier 2 to broad - cast on slot 1 through tx_ch1_en and set amplifier 4 to broadcast on slot 3 through tx_ch3_en. then configure both amplifiers to enable rx enable to listen to both slots 1 and 3, so both amps would have rx_dht_ch1_en and rx_dht_ch3_en enabled. by definition, the minimum size of a group is two ampli - fiers, so the maximum number of groups that is supported is eight. a group can contain as many as 16 amplifiers, but then only one group is supported. it is a requirement of the host processor to ensure that the rx register bits are set to the same values across all amplifiers intended to be used in a group. devices in the same dht group must also be configured with the same dht parameters (spk_gain_max, rp, and ballistics) to achieve a balanced response across the group. the same is true of the therm group and alc group. table 34. interchip communication configuration address bit name description 0x5c 6 icc_oc_ena 0: disable overcurrent protection on dout. 1: enable overcurrent protection on dout. 5 icc_douten_extff 0: disable faster drive enable of the dout. 1: enable faster drive enable of the dout for the icc with bclk rate greater than 12.288mhz. 4 icc_dout_extff 0: disable faster drive of the dout. 1: enable faster drive of the dout for the icc with bclk rate greater than 12.288mhz. 3 icc_pad_ctrl[3:0] dout drive strength control0000: 1 (default) 0001 and 0010: 7/8 0011 and 0100: 3/4 0101 and 0110: 5/8 0111 and 1000: 1/2 1001 and 1010: 3/8 1011 and 1100: 1/4 1101: 1/8 1110: 1/8 with miller slew rate reduction (improves emi) 1111: off 21 0 www.maximintegrated.com maxim integrated 74 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
double data drive if the shared dout trace has a high capacitance that needs to be driven at high speed then the double-data drive feature can be used. this gives a longer drive time for each device. when the bclk is less than or equal to 25mhz, dout can be clocked with standard clocking: data changes on the falling edge and is valid on the rising edge of each bclk ( table 35 ). when the bclk is greater than 25mhz, dout should be clocked using a double-data drive method: data changes on the falling edge and is valid on the second rising edge. in this way, the dout data transfer rate is effectively half of the bclk speed. this is accomplished by setting drive_mode = 1. this has implications for the supported slot lengths. when double-data drive is enabled, only 32-bit slot lengths are permitted. additional MAX98372 devices correctly interpret the double-data drive format (if enabled). any other attached hardware, such as an applications processor, which is expecting standard timing, needs to ensure that it omits away the information captured on the nonvalid rising edge each time and reconstruct the samples accordingly. table 35. dout double data drive mode figure 22. single data drive 31 30 29 28 27 26 25 24 23 22 dht [7] dht [6] dht [5] dht [4] dht [3] dht [2] dht [1] dht [0] thm [5] thm [4] thm [3] thm [2] thm [1] thm [0] 21 20 19 18 17 drive data on falling edge receive data on rising edge three-state data at end of slot alc [0] 16 figure 23. double data drive illustration 31 30 29 28 27 26 25 dht [7] dht [6] dht [5] dht [4] 24 t drive address bit name description 0x40 3 drive_mode 0: single data drive (default)1: double data drive www.maximintegrated.com maxim integrated 75 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 36. dout dht receive channel configuration address bit name description 0x3a 7 rxdht_ch7_en 0: dht receive channel 7 is disabled. 1: dht receive channel 7 is enabled. 6 rxdht_ch6_en 0: dht receive channel 6 is disabled. 1: dht receive channel 6 is enabled. 5 rxdht_ch5_en 0: dht receive channel 5 is disabled. 1: dht receive channel 5 is enabled. 4 rxdht_ch4_en 0: dht receive channel 4 is disabled. 1: dht receive channel 4 is enabled. 3 rxdht_ch3_en 0: dht receive channel 3 is disabled. 1: dht receive channel 3 is enabled. 2 rxdht_ch2_en 0: dht receive channel 2 is disabled. 1: dht receive channel 2 is enabled. 1 rxdht_ch1_en 0: dht receive channel 1 is disabled. 1: dht receive channel 1 is enabled. 0 rxdht_ch0_en 0: dht receive channel 0 is disabled. 1: dht receive channel 0 is enabled. 0x3b 7 rxdht_ch15_en 0: dht receive channel 15 is disabled. 1: dht receive channel 15 is enabled. 6 rxdht_ch14_en 0: dht receive channel 14 is disabled. 1: dht receive channel 14 is enabled. 5 rxdht_ch13_en 0: dht receive channel 13 is disabled. 1: dht receive channel 13 is enabled. 4 rxdht_ch12_en 0: dht receive channel 12 is disabled. 1: dht receive channel 12 is enabled. 3 rxdht_ch11_en 0: dht receive channel 11 is disabled. 1: dht receive channel 11 is enabled. 2 rxdht_ch10_en 0: dht receive channel 10 is disabled. 1: dht receive channel 10 is enabled. 1 rxdht_ch9_en 0: dht receive channel 9 is disabled. 1: dht receive channel 9 is enabled. 0 rxdht_ch8_en 0: dht receive channel 8 is disabled. 1: dht receive channel 8 is enabled. www.maximintegrated.com maxim integrated 76 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 37. dout thermal foldback receive channel configuration address bit name description 0x3c 7 rxthm_ch7_en 0: thrm fb receive channel 7 is disabled. 1: thrm fb receive channel 7 is enabled. 6 rxthm_ch6_en 0: thrm fb receive channel 6 is disabled. 1: thrm fb receive channel 6 is enabled. 5 rxthm_ch5_en 0: thrm fb receive channel 5 is disabled. 1: thrm fb receive channel 5 is enabled. 4 rxthm_ch4_en 0: thrm fb receive channel 4 is disabled. 1: thrm fb receive channel 4 is enabled. 3 rxthm_ch3_en 0: thrm fb receive channel 3 is disabled. 1: thrm fb receive channel 3 is enabled. 2 rxthm_ch2_en 0: thrm fb receive channel 2 is disabled. 1: thrm fb receive channel 2 is enabled. 1 rxthm_ch1_en 0: thrm fb receive channel 1 is disabled. 1: thrm fb receive channel 1 is enabled. 0 rxthm_ch0_en 0: thrm fb receive channel 0 is disabled. 1: thrm fb receive channel 0 is enabled. 0x3d 7 rxthm_ch15_en 0: thrm fb receive channel 15 is disabled. 1: thrm fb receive channel 15 is enabled. 6 rxthm_ch14_en 0: thrm fb receive channel 14 is disabled. 1: thrm fb receive channel 14 is enabled. 5 rxthm_ch13_en 0: thrm fb receive channel 13 is disabled. 1: thrm fb receive channel 13 is enabled. 4 rxthm_ch12_en 0: thrm fb receive channel 12 is disabled. 1: thrm fb receive channel 12 is enabled. 3 rxthm_ch11_en 0: thrm fb receive channel 11 is disabled. 1: thrm fb receive channel 11 is enabled. 2 rxthm_ch10_en 0: thrm fb receive channel 10 is disabled. 1: thrm fb receive channel 10 is enabled. 1 rxthm_ch9_en 0: thrm fb receive channel 9 is disabled. 1: thrm fb receive channel 9 is enabled. 0 rxthm_ch8_en 0: thrm fb receive channel 8 is disabled. 1: thrm fb receive channel 8 is enabled. www.maximintegrated.com maxim integrated 77 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 38. dout transmit channel configuration address bit name description 0x3e 7 tx_ch7_en 0: transmit channel 7 is disabled. 1: transmit channel 7 is enabled. 6 tx_ch6_en 0: transmit channel 6 is disabled. 1: transmit channel 6 is enabled. 5 tx_ch5_en 0: transmit channel 5 is disabled. 1: transmit channel 5 is enabled. 4 tx_ch4_en 0: transmit channel 4 is disabled. 1: transmit channel 4 is enabled. 3 tx_ch3_en 0: transmit channel 3 is disabled. 1: transmit channel 3 is enabled. 2 tx_ch2_en 0: transmit channel 2 is disabled. 1: transmit channel 2 is enabled. 1 tx_ch1_en 0: transmit channel 1 is disabled. 1: transmit channel 1 is enabled. 0 tx_ch0_en 0: transmit channel 0 is disabled. 1: transmit channel 0 is enabled. 0x3f 7 tx_ch15_en 0: transmit channel 15 is disabled. 1: transmit channel 15 is enabled. 6 tx_ch14_en 0: transmit channel 14 is disabled. 1: transmit channel 14 is enabled. 5 tx_ch13_en 0: transmit channel 13 is disabled. 1: transmit channel 13 is enabled. 4 tx_ch12_en 0: transmit channel 12 is disabled. 1: transmit channel 12 is enabled. 3 tx_ch11_en 0: transmit channel 11 is disabled. 1: transmit channel 11 is enabled. 2 tx_ch10_en 0: transmit channel 10 is disabled. 1: transmit channel 10 is enabled. 1 tx_ch9_en 0: transmit channel 9 is disabled. 1: transmit channel 9 is enabled. 0 tx_ch8_en 0: transmit channel 8 is disabled. 1: transmit channel 8 is enabled. www.maximintegrated.com maxim integrated 78 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 39. dout alc receive channel configuration address bit name description 0x60 7 rxalc_ch7_en 0: alc fb receive channel 7 is disabled. 1: alc fb receive channel 7 is enabled. 6 rxalc_ch6_en 0: alc fb receive channel 6 is disabled. 1: alc fb receive channel 6 is enabled. 5 rxalc_ch5_en 0: alc fb receive channel 5 is disabled. 1: alc fb receive channel 5 is enabled. 4 rxalc_ch4_en 0: alc fb receive channel 4 is disabled. 1: alc fb receive channel 4 is enabled. 3 rxalc_ch3_en 0: alc fb receive channel 3 is disabled. 1: alc fb receive channel 3 is enabled. 2 rxalc_ch2_en 0: alc fb receive channel 2 is disabled. 1: alc fb receive channel 2 is enabled. 1 rxalc_ch1_en 0: alc fb receive channel 1 is disabled. 1: alc fb receive channel 1 is enabled. 0 rxalc_ch0_en 0: alc fb receive channel 0 is disabled. 1: alc fb receive channel 0 is enabled. 0x61 7 rxalc_ch15_en 0: alc fb receive channel 15 is disabled. 1: alc fb receive channel 15 is enabled. 6 rxalc_ch14_en 0: alc fb receive channel 14 is disabled. 1: alc fb receive channel 14 is enabled. 5 rxalc_ch13_en 0: alc fb receive channel 13 is disabled. 1: alc fb receive channel 13 is enabled. 4 rxalc_ch12_en 0: alc fb receive channel 12 is disabled. 1: alc fb receive channel 12 is enabled. 3 rxalc_ch11_en 0: alc fb receive channel 11 is disabled. 1: alc fb receive channel 11 is enabled. 2 rxalc_ch10_en 0: alc fb receive channel 10 is disabled. 1: alc fb receive channel 10 is enabled. 1 rxalc_ch9_en 0: alc fb receive channel 9 is disabled. 1: alc fb receive channel 9 is enabled. 0 rxalc_ch8_en 0: alc fb receive channel 8 is disabled. 1: alc fb receive channel 8 is enabled. www.maximintegrated.com maxim integrated 79 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 40. extra bclk cycle configuration table 41. manual high-impedance mode configuration address bit name description 0x41 1 tx_extra_hiz 0: extra bclk cycles are driven to zero.1: extra bclk cycles are driven to high impedance. address bit name description 0x42 7 tx_ch7_hiz 0: transmit channel 7 outputs data/zeros. 1: transmit channel 7 outputs high impedance. 6 tx_ch6_hiz 0: transmit channel 6 outputs data/zeros. 1: transmit channel 6 outputs high impedance. 5 tx_ch5_hiz 0: transmit channel 5 outputs data/zeros. 1: transmit channel 5 outputs high impedance. 4 tx_ch4_hiz 0: transmit channel 4 outputs data/zeros. 1: transmit channel 4 is enabled. 3 tx_ch3_hiz 0: transmit channel 3 outputs data/zeros. 1: transmit channel 3 outputs high impedance. 2 tx_ch2_hiz 0: transmit channel 2 outputs data/zeros. 1: transmit channel 2 outputs high impedance. 1 tx_ch1_hiz 0: transmit channel 1 outputs data/zeros. 1: transmit channel 1 outputs high impedance. 0 tx_ch0_hiz 0: transmit channel 0 outputs data/zeros. 1: transmit channel 0 outputs high impedance. 0x43 7 tx_ch15_hiz 0: transmit channel 15 outputs data/zeros. 1: transmit channel 15 outputs high impedance. 6 tx_ch14_hiz 0: transmit channel 14 outputs data/zeros. 1: transmit channel 14 outputs high impedance. 5 tx_ch13_hiz 0: transmit channel 13 outputs data/zeros. 1: transmit channel 13 outputs high impedance. 4 tx_ch12_hiz 0: transmit channel 12 outputs data/zeros. 1: transmit channel 12 outputs high impedance. 3 tx_ch11_hiz 0: transmit channel 11 outputs data/zeros. 1: transmit channel 11 outputs high impedance. 2 tx_ch10_hiz 0: transmit channel 10 outputs data/zeros. 1: transmit channel 10 outputs high impedance. 1 tx_ch9_hiz 0: transmit channel 9 outputs data/zeros. 1: transmit channel 9 outputs high impedance. 0 tx_ch8_hiz 0: transmit channel 8 outputs data/zeros. 1: transmit channel 8 outputs high impedance. www.maximintegrated.com maxim integrated 80 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
class d output stage the MAX98372 class d output stage with active emis - sions limiting and spread spectrum provides optimum suppression and control of output switching harmonics that most directly contribute to emi and radiated emis - sions. programmable speaker edge rate control is avail - able to help tweak emi performance. as the edge rate increases the efficiency goes up slightly, and as the edge rate slows the efficiency goes down. set the speaker edge rate with bits spk_edge bits in register 0x4a. the default class d output switching frequency is 472khz for the best thd performance. to trade off thd perfor - mance for higher efficiency the output switching frequency can be set to 330khz by setting spk_swclk to 1. to achieve the lower power consumption the output switching of the class d amplifier the part can be dis - abled through the spk_en bit. see table 42 for speaker configuration. ultra-low emi filterless output stage traditional class d amplifiers require the use of external lc filters, or shielding, to meet electromagnetic-interfer - ence (emi) regulation standards. the active emissions limiting edge-rate control circuitry reduce emi emissions so that with 18in of speaker cable the MAX98372 passes the en55022b standard without the need for external filtering components. maxims spread-spectrum modulation mode lattens wideband spectral components while proprietary techniques ensure that the cycle-to-cycle variation of the switching period does not degrade audio reproduction or eficiency. the ics spread-spectrum modulator randomly varies the switching frequency by as much as 18.6khz around 330khz center frequency, or by 39.4khz around 478.75khz center frequency. above 10mhz, the wideband spectrum looks like noise for emi purposes. table 42. speaker configuration address bit name description 0x4a 7 spk_swclk class d output switching frequency select0: speaker switching frequency is set to 472khz. 1: speaker switching frequency is set to 330khz. 6 5 spk_ssm[1:0] speaker spread spectrum modulation control00: ssm is disabled 10: ssm is enabled 43 spk_edge[1:0] programmable speaker edge rate control00: nominal edge rate 01: +15% faster edge rate 10: -40% slower edge rate 11: -20% slower edge rate 2 1 0 spk_en speaker ampliier enable 0: speaker ampliier is disabled (default). 1: enable www.maximintegrated.com maxim integrated 81 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
v dvdd and v pvdd uvlo the MAX98372 monitors both dvdd and pvdd for low voltage conditions that would prevent the speaker ampli - fier from operating normally. if the voltage on dvdd drops below the dvdd-uvlo threshold (v dvdd-uvlo ), the device is placed in hardware shutdown. all the i 2 c internal registers reset to their default values. the device can be commanded to leave this state through the i 2 c command if the voltage on dvdd later exceeds the v dvdd-uvlo threshold. if the voltage pvdd drops below the pvdd-uvlo thresh - old, the audio output is muted to prevent the pvdd supply from being used by the amplifier. if the voltage on pvdd later exceeds the v pvdd-uvlo threshold, the device can be commanded to unmute through the i 2 c command. click-and-pop suppression the MAX98372 speaker amplifier features maxims com - prehensive click-and-pop suppression. during power-up and power-down, the click-and-pop suppression circuitry reduces any audible transient sources internal to the device. at startup, the pga gain is automatically ramped from mute to the desired setting at a rate of 200s/db. similarly, the gain is ramped down to mute at shutdown at the same rate. for faster startup and shutdown, disable gain ramping. during normal operation, any requested gain changes are ramped from the old value to the new value at a value determined by the ballistics within the volume control block. ampliier current limit the MAX98372 features current limit protection that pro - tects the device against shorts. if the output current of the speaker amplifier exceeds the current limit (6a typ) the ic disables the outputs for approximately 100s. after 100ms, the outputs are reenabled. if the fault condition still exists, the ic continues to disable and reenable the outputs until the fault condition is removed. set ovc_sel low to disable this behavior ( table 44 ). the current limit protects against both high-current and short-circuit events.thermal shutdown recovery when the temperate of the die exceeds +150c, the part enters thermal shutdown. however, the MAX98372 features a configurable thermal shutdown autorecov - ery mode. when the die temperate has decreased by 30c from the thermal shutdown event, the MAX98372 attempts to resume the previous operating state. set tshdn_auto_restart high to enable autorecovery mode ( table 44 ). table 43. spread-spectrum modulation configuration address bit name description 0x49 7 6 5 4 3 2 ssm_modindex spread spectrum modulation index selection ssm_modindex modulation 0x0 7.7% & 3.8% 0x1 (default) 6.4% & 3.8% 1 0x2 5.1% & 2.6% 0x3 3.8% & 2.6% 0 0x4 2.6% & 1.3% 0x5 1.3% & 1.3% www.maximintegrated.com maxim integrated 82 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
output sensing when using ferrites the MAX98372 features two remote sensing pins outn_ sns and outp_sns. remotely sensing the voltage at the load provides a thd+n advantage over sens - ing at the dut output when ferrite beads are used ( figure 25 ).the remote sense lines connect the output signal at the load to the inverting terminal of the internal error amplifier of the class d ( figure 24 ). ferrites are highly nonlinear so sensing at the load versus at the out - put pins ensures that any signal degradation caused by the filtering components is appropriately compensated. however, in many applications, there may not be a need to filter the output with a ferrite bead. clocking architecture the MAX98372 includes a flexible clocking architecture and operation with no mclk input. a configurable internal clock monitor circuit monitors the internal clock source (bclk) and automatically places the device in software shutdown if the clock source is removed. set cmon_ena high to enable the clock monitor. this prevents unwanted signals from being applied to the speaker during a fault condition. when cmon_auto_restart is high, the device automati - cally returns to normal operation when the clock source is subsequently reapplied ( table 44 ). reset the MAX98372 features an active-low hardware reset. when the voltage-on reset is pulled low, the part enters global shutdown. to reenable the part, the reset pin must be pulled high and a global enable i 2 c command must be issued.hardware reset when the reset pin is pulled low, the device is in its lowest power-down state and communication over i 2 c is not possible. after exiting reset mode, all registers are set to their default por values. also, if dvdd is removed while pvdd is still applied, the device goes into a hardware shutdown mode and communication through i 2 c is not possible. figure 24. typical application circuit with ferrites beads used MAX98372 outp outn outp sns outn sns fb fb speaker amplifier figure 25. thd performance improvement enabled by remote sensing www.maximintegrated.com maxim integrated 83 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
table 44. clock monitor configuration table 45. reset register table 46. global enable register address bit name description 0x50 0 en global enable:0: disabled 1: enabled address bit name description 0x4d 3 cmon_auto_restart 0: device does not restart after a clock monitor event.1: device restarts automatically when bclk is restarted. 2 cmon_ena 0: clock monitor is disabled (default).1: clock monitor is enabled. 1 ovc_sel 0: current limit recovery is in manual mode.1: current limit recovery is in autorecovery mode. 0 tsdhn_auto_restart 0: thermal-protection recovery is in manual mode. 1: thermal-protection recovery is in autorecovery mode. address bit name description 0x51 0 rst reset0: no action is taken. 1: reset. all registers return to their por (default) values. www.maximintegrated.com maxim integrated 84 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
software reset write 1 to bit 0 of register 0x51 to trigger a software reset. software reset is used to return most registers to their default (por) states. biquad equalizer coefficients are not reset. the software reset register is a write only register. as a result, a read of this register always returns 0x00. writing logic-high to rst triggers a software register reset, while writing a logic-low to rst has no effect. also if pvdd is removed while dvdd is still applied the device goes into software shutdown mode where all blocks are disabled except i 2 c control block. i 2 c serial interface the MAX98372 features an i 2 c 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate communication between the ic and the master at clock rates up to 400khz. figure 26 shows the 2-wire interface timing diagram. the master generates scl and initiates data transfer on the bus. the master device writes data to the ic by transmitting the proper slave address followed by the register address and then the data word. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted to the ic is 8 bits long and is followed by an acknowledge clock pulse. a master reading data from the ic transmits the proper slave address followed by a series of nine scl pulses. the ic transmits data on sda in sync with the master- generated scl pulses. the master acknowledges receipt of each byte of data. each read sequence is framed by a start (s) or repeated start (sr) condition, a not acknowledge, and a stop (p) condition. sda oper - ates as both an input and an open-drain output. a pullup resistor, typically greater than 500?, is required on sda. scl operates only as an input. a pullup resistor, typically greater than 500?, is required on scl if there are mul - tiple masters on the bus, or if the single master has an open-drain scl output. series resistors in line with sda and scl are optional. series resistors protect the digital inputs of the ic from high voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals. bit transfer one data bit is transferred during each scl cycle. the data on sda must remain stable during the high period of the scl pulse. changes in sda while scl is high are con - trol signals. see the start and stop conditions section. start and stop conditions sda and scl idle high when the bus is not in use. a mas - ter initiates communication by issuing a start condition. a start condition is a high-to-low transition on sda with cl high. a stop condition is a low-to-high transition on sda while scl is high ( figure 26 ). a start condition from the master signals the beginning of a transmission to the ic. the master terminates transmission, and frees the bus, by issuing a stop condition. the bus remains active if a repeated start condition is generated instead of a stop condition. figure 26. start, stop, and repeated start conditions www.maximintegrated.com maxim integrated 85 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
early stop conditions the ic recognizes a stop condition at any point during data transmission except if the stop condition occurs in the same high pulse as a start condition. for proper operation, do not send a stop condition during the same scl high pulse as the start condition. slave address the slave address is defined as the seven most signifi - cant bits (msbs) followed by the read/write bit. for the ic, the seven most significant bits are programmable through the addr1 and addr0 bumps. setting the read/write bit to 1 configures the ic for read mode. setting the read/ write bit to 0 configures the ic for write mode. the slave address is the first byte of information sent to the ic after the start condition. acknowledge the acknowledge bit (ack) is a clocked 9th bit that the ic uses to handshake receipt each byte of data when in write mode figure 27 . the ic pulls down sda during the entire master-generated 9th clock pulse if the previous byte is successfully received. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master reattempts communication. the master pulls down sda during the 9th clock cycle to acknowledge receipt of data when the ic is in read mode. an acknowledge is sent by the master after each read byte to allow data transfer to continue. a not-acknowledge is sent when the master reads the final byte of data from the ic, followed by a stop condition. write data format a write to the ic includes transmission of a start con - dition, the slave address with the r/w bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a stop condition. figure 28 illustrates the proper frame format for writing one byte of data to the ic. figure 29 illustrates the frame format for writing n-bytes of data to the ic. figure 27. acknowledge figure 28. writing one byte of data to the MAX98372 a 0 slave address register address data byte acknowledge from slave r/ w 1 byte autoincrement internal register address pointer acknowledge from slave acknowledge from slave b1 b0 b3 b2 b5 b4 b7 b6 s a a p figure 29. n-bytes of data to the MAX98372 1 byte autoincrement internal register address pointer acknowledge from slave acknowledge from slave b1 b0 b3 b2 b5 b4 b7 b6 a a 0 acknowledge from slave r/ w s a 1 byte acknowledge from slave b1 b0 b3 b2 b5 b4 b7 b6 p a slave address register address data byte 1 data byte n www.maximintegrated.com maxim integrated 86 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
the slave address with the r/w bit set to 0 indicates that the master intends to write data to the ic. the ic acknowledges receipt of the address byte during the master-generated 9th scl pulse. the second byte transmitted from the master configures the ics internal register address pointer. the pointer tells the ic where to write the next byte of data. an acknowl - edge pulse is sent by the ic upon receipt of the address pointer data. the third byte sent to the ic contains the data that is writ - ten to the chosen register. an acknowledge pulse from the ic signals receipt of the data byte. the address pointer autoincrements to the next register address after each received data byte. this autoincrement feature allows a master to write to sequential registers within one continu - ous frame. the master signals the end of transmission by issuing a stop condition. read data format send the slave address with the r/w bit set to 1 to initiate a read operation. the ic acknowledges receipt of its slave address by pulling sda low during the 9th scl clock pulse. a start command followed by a read command resets the address pointer to register 0x00. the first byte transmitted from the ic is the content of register 0x00. transmitted data is valid on the rising edge of scl. the address pointer autoincrements after each read data byte. this autoincrement feature allows all registers to be read sequentially within one continuous frame. a stop condition can be issued after any number of read data bytes. if a stop condition is issued followed by another read operation, the first data byte to be read is from register 0x00. the address pointer can be preset to a specific register before a read command is issued. the master presets the address pointer by first sending the ics slave address with the r/w bit set to 0 followed by the register address. a repeated start condition is then sent followed by the slave address with the r/w bit set to 1. the ic then trans - mits the contents of the specified register. the address pointer autoincrements after transmitting the first byte. the master acknowledges receipt of each read byte during the acknowledge clock pulse. the master must acknowl - edge all correctly received bytes except the last byte. the final byte must be followed by a not acknowledge from the master and then a stop condition. figure 30 illustrates the frame format for reading one byte from the ic. figure 31 illustrates the frame format for reading multiple bytes from the ic. figure 30. reading one byte of data from the MAX98372 acknowledge from slave 1 byte autoincrement internal register address pointer acknowledge from slave a a a 0 acknowledge from slave r/ w s r/ w repeated start sr 1 slave address register address slave address data byte p figure 31. reading n-bytes of data from the MAX98372 acknowledge from slave 1 byte autoincrement internal register address pointer acknowledge from slave a a a 0 acknowledge from slave r/ w s r/ w repeated start sr 1 slave address register address slave address data byte p www.maximintegrated.com maxim integrated 87 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
i 2 c slave addresses the MAX98372 is configured using the i 2 c control bus. the addresses effectively allow unique audio endpoint des - tinations in systems that use multiples of the device. the ic uses hardware select slave addresses determined by the configuration of addr0, addr1 as shown in table 47 . see the i 2 c serial interface section for a complete interface description. applications information layout and grounding proper layout and grounding are essential for optimum performance. use at least 4 pcb layers, and add thermal vias to the ground/power plane close to the MAX98372 to ensure good thermal performance and high-end out - put power. good grounding improves audio performance and prevents switching noise from coupling into the audio signal. ground the power signals and the analog signals of the ic separately at the system ground plane, to prevent switching interference from corrupting sensi - tive analog signals. place the recommended supply decoupling capacitors as close as possible to the ic. the pvdd-to-pgnd connection must be kept short and should have minimum trace length and loop area to ensure optimumal performance. use wide, low-resistance output, supply and ground traces. as load impedance decreases, the current drawn from the device outputs increase. at higher current, the resistance of the output traces decreases the power delivered to the load. for example, if 2w is delivered from the speaker output to a 4? load through a 100m? trace, 49mw is consumed in the trace. if power is deliv - ered through a 10m? trace, only 5mw is consumed in the trace. wide output, supply, and ground traces also improve the power dissipation of the device. the MAX98372 is inherently designed for excellent rf immunity. for best performance, add ground fills around all signal traces on the top and bottom pcb planes. it is generally advisable to follow the layout of the MAX98372 evaluation kit as closely as is practical in the application. thermal and performance measurements shown in this data sheet were measured with a 6-layer board with 2 signal layers and 4 ground layers. as a result, the ev kit performance is likely better than what can be achieved with a jedec standard board. table 47. addr i 2 c address select addr1 addr0 i 2 c write address select addr1 connected to dvdd addr0 connected to dgnd 0x62 addr1 connected to dgnd addr0 connected to dgnd 0x64 addr1 connected to sda addr0 connected to dgnd 0x66 addr1 connected to scl addr0 connected to dgnd 0x68 addr1 connected to dvdd addr0 connected to sda 0x6a addr1 connected to dgnd addr0 connected to sda 0x6c addr1 connected to sda addr0 connected to sda 0x6e addr1 connected to scl addr0 connected to sda 0x70 addr1 connected to dvdd addr0 connected to dvdd 0x72 addr1 connected to dgnd addr0 connected to dvdd 0x74 addr1 connected to sda addr0 connected to dvdd 0x76 addr1 connected to scl addr0 connected to dvdd 0x78 addr1 connected to dvdd addr0 connected to scl 0x7a addr1 connected to dgnd addr0 connected to scl 0x7c addr1 connected to sda addr0 connected to scl 0x7e addr1 connected to scl addr0 connected to scl 0x80 www.maximintegrated.com maxim integrated 88 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
wlp applications information for the latest application details on wlp construction, dimensions, tape carrier information, pcb techniques, bump-pad layout, and recommended reflow temperature profile, as well as the latest information on reliability test - ing results, refer to the application note 1891: wafer-level packaging (wlp) and its applications. see figure 32 for the recommended pcb footprint of the MAX98372. table 48. recommended external components figure 32. MAX98372+ wlp ball dimensions 0.31mm 0.21mm printed circuit board pcb pad MAX98372 0.26mm ubm bump value (f) size voltage rating (v) dielectric pvdd 10 0603 50 x5r pvdd 10 0603 50 x5r pvdd 0.1 0402 25 x5r pvdd 0.1 0402 25 x5r pvdd 220 35 alum-elec v refc 1 0201 6.3 x5r dvdd 1 0201 6.3 x5r irq 10 0201 www.maximintegrated.com maxim integrated 89 MAX98372 digital input class d ampliier with dht and brownout protection downloaded from: http:///
+denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. typical application circuit MAX98372 scl irq dvdd pvdd 10k 1 f 1 f 1.14v to 1.98v 220 f 10 f 0.1 f 5.5v to 18v control interface sda addr1 v refc reset bclk lrclk din digital audio interface dgnd pgnd agnd outp outn outp sns outn sns refer to application information addr2 10 f 0.1 f dout 10k 10k part temp range pin-package MAX98372ewv+ -40c to +85c 30 wlp MAX98372ewv+t -40c to +85c 30 wlp package type package code outline no. land pattern no. 30 wlp w302g2+1 21-100002 refer to application note 1891 www.maximintegrated.com maxim integrated 90 MAX98372 digital input class d ampliier with dht and brownout protection package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information downloaded from: http:///
revision history revision number revision date description pages changed 0 9/15 initial release 1 1/16 updated electrical characteristics table din frame delay after lrclk edge parameter, replaced figure 7 12, 48 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ? 2016 maxim integrated products, inc. 91 MAX98372 digital input class d ampliier with dht and brownout protection for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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