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preliminar y ttp258 tontouch tm 16?/04/06 page 1 of 44 ver.: 1.2 patenten 1. p atent : ?e u
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??? pat no. m375250 (taiwan) pat no. zl 2010 2 0302392. 4 (china) general description: ttp258 mcu is an easy-used 4-bit cpu base microcontroller. it contains 1984-word rom e 144-nibble ram e timer/counter e interrupt service e io control hardware e lvr and touch pad feature for specified applications. the device is also suitable for diverse simple applications in control appliance and consumer product. features: 1. tontek risc 4-bit cpu core 2. total 26 crucial instructions and two addressing mode 3. most instructions need 1 word an d 1 machine cycle(2 system clocks) except read table instruction(rtb) 4. advance cmos process 5. working memory with 1984*16 program rom and 144*4 sram 6. 2-level stacks 7. operating voltage: 5.5v~3.1v (ldo on) i 5.5v~2.5v (ldo off e lvr on) i 5.5v~2.2v (ldo off e lvr off) i 8. system operating freq uency: (at vdd=5v ) . high-speed system oscillator (osch): ? built-in rc oscillat or: 4mhz(typical) .low speed peripheral oscillator (oscl): ? built-in rc oscillator: 16khz(typical)
preliminar y ttp258 tontouch tm 16?/04/06 page 2 of 44 ver.: 1.2 9. offer 3 io+10 touch pad or 13 general programmable i/o ? io port built-in key wake-up feat ure enable by software setting ? providing external interrupt inputs ? offering internal signal outputs, like buzzer(pwm) 10. one 8-bit tcp1 auto-reload time r/counter & onetime base counter ? 4 timer clock sources selected by software ? time base offers 2 various period interrupt request 11. one 8-bit tcp2 auto-reload timer/ counter, can improve pwm function ? 4 timer clock sources selected by software 12. built-in 3 set 8-bit pwm output 13. mcu system protection and power saving controlled mode: ? built-in watch dog timer (wdt) circuit ? rom code error detection ? out of user program?s range detection ? providing high/low sy stem operating speed e sleep mode for power saving control ? built-in low voltage reset (lvr) function 14. 10 pins with touch pad detection 15. built-in ldo voltage 2.7v 16. provides 8 interrupt sources ? external: int0, int1 shared with io pad ? internal: two timer/counter, two time base timer ? two touchpad?s interrupt 17. provide package types ? sop 16
preliminar y ttp258 tontouch tm 16?/04/06 page 3 of 44 ver.: 1.2 applications: 1. household electric appliances 2. consumer products 3. measurement controller package description: 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 pc3/tp3 pc2/tp2 pc1/tp1 pc0/tp0 vdd vreg pa1/int1/pwm1 pa0/int0/pwm0 pd0/tp4 pd1/tp5 pd2/tp6 pd3/tp7 pb0/tp8 pb1/tp9 cap vss 16-sop-b pc3/tp3 pc2/tp2 pc1/tp1 pc0/tp0 vdd pa2/pwm2 pa1/int1/pwm1 pa0/int0/pwm0 pd0/tp4 pd1/tp5 pd2/tp6 pd3/tp7 pb0/tp8 pb1/tp9 cap vss 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 16-sop-a
preliminar y ttp258 tontouch tm 16?/04/06 page 4 of 44 ver.: 1.2 block diagram: system control unit rom st426 mcu ram base timer interrupt reset lvr 8 bit timer/counter osch & oscl pwm 0, 1, 2 wdt 8 bit timer/counter pd3~pd0 pc3~pc0 pb1~pb0 pa2~pa0 rstb i/ o touch pad detection cap
preliminar y ttp258 tontouch tm 16?/04/06 page 5 of 44 ver.: 1.2 pin description: pin name share pin i/o pin no . mask option pin description v dd - power +1 - positive power supply v ss - power +1 - negative power supply, ground rstb - i +1 - external reset input, active low, 50k ? pull-up( v dd =5v) pa0 pa1 pa2 int0/pwm0/vpp int1/pwm1 pwm2 io io io +3 - i/o port with external interrupt input and pwm output (pa0,pa1). pa2 is shared with internal pwm2 output. pb0 pb1 tp8 tp9 io/i io/i +2 - io port or touch pad input. pc0 pc1 pc2 pc3 tp0 tp1 tp2 tp3 io/i io/i io/i io/i +4 - io port or touch pad input. pd0 pd1 pd2 pd3 tp4 tp5 tp6 tp7 io/i io/i io/i io/i +4 - io port or touch pad input. cap - o +1 - touch signal output vreg power +1 - ldo voltage output 18 -
preliminar y ttp258 tontouch tm 16?/04/06 page 6 of 44 ver.: 1.2 io cell type description: pin name i/o type description pa1 figure io-d std io with internal output & external input pa0 figure io-e std io with internal output & external input pa2 figure io-b std io with internal output pb0~pb1 figure io-a std io with external input pc0~pc3 figure io-a std io with external input pd0~pd3 figure io-a std io with external input absolute maximum ratings: item symbol rating unit operating temperature top
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storage temperature tst
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otp supply voltage vpp 744_744 7 input voltage vin 744_7%% 7 human body mode esd ,7 /puf744tzncpmj[ftgpstztufnhspvoe
preliminar y ttp258 tontouch tm 16?/04/06 page 7 of 44 ver.: 1.2 dc & ac characteristics dc characteristics: (test condition at room temperature=25 o c) parameter symbol test condition min. typ. max. unit operating voltage vdd ldo on i lvr on 3.1 - 5.5 v ldo on i lvr off 3.1 - 5.5 ldo off i lvr on 2.5 - 5.5 ldo off i lvr off 2.2 - 5.5 low voltage reset (lvr) v lvr1 lvr select 2.2v 2.0 2.2 2.4 v ldo voltage v ldo1 ldo select 2.7v 2.4 2.7 3.0 v operating current (normal mode, cpu working, i/o no load ) i nd1 vdd=5.0v, no load, f osch =4mhz, - 2.5 3.0 ma i nd2 vdd=5.0v, no load, f oscl on, f osch off, lvr off, ldo off - 30 50 ua operating current (sleep mode, cpu stop, i/o no load) i sd1 vdd=5.0v, no load, f osch =4mhz, - 0.7 1.0 ma i sd2 vdd=3.0v, no load, f oscl on, f osch off, lvr off, ldo off - 5 10 ua lvr current i lvr vdd=5.0v - 55 - ua ldo current i ldo vdd=5.0v - 100 - ua input ports v il input low voltage 0 - 0.2 vdd input ports v ih input high voltage 0.8 - 1.0 vdd rstb & int v il input low voltage 0 - 0.3 vdd rstb & int v ih input high voltage 0.7 - 1.0 vdd pa0 sink current i ol vdd=5.0v, vol=0.6v - 2 - ma pa0 source current i oh vdd=5v, voh=vdd-0.7v - -1 - ma output port sink current (exclude pa0) i ol vdd=5.0v, vol=0.6v - 8 - ma output port source current (exclude pa0) i oh vdd=5v, voh=vdd-0.7v - -4 - ma i/o port pull-up resistor r ph vdd=5.0v 100 150 200 k ? rstb pull-up resistor r ph vdd=5.0v 30 50 80 k ? band gap voltage v bgap 1.0 1.12 1.23 v
preliminar y ttp258 tontouch tm 16?/04/06 page 8 of 44 ver.: 1.2 ac characteristics: (test condition at room temperature=25 o c) wake up input low active pulse width t wkup, application de-bounce should be manipulated by user? software 2 - - oscl s tartup period of oscillators t osch (built-in rc) wake-up from off mode 8 - - f osch t oscl (built-in rc) wake-up from off mode 8 - - f oscl parameter test condition min. typ. max. unit external reset low active pulse width tres 2 - - cpu clock interrupt input low active pulse width tint 2 - - system oscillator frequency f osch (built-in rc) vdd=5.0v - 4m - hz peripheral oscillator frequency built-in f oscl (rc) vdd=5.0v 12k 16k 21k hz stable time of system clock switching t osch ( built-in rc) oscl ? osch & osch off 8 - - f osch (if h/l=0 then osch stop) t oscl ( built-in rc) osch ? oscl & oscl on 8 - - f oscl timer/counter input clock frequency input frequency rating, no de-bounce circuit built-in ,at vdd=5v dc - 4m hz system stable time after power up after power up, the system needs to initialize the configured state and ost. - - 40 ms
preliminar y ttp258 tontouch tm 16?/04/06 page 9 of 44 ver.: 1.2 file registers: address symbol r/w default description 000 h (dp1) r/w - indirect addressin g re g ister 001 h acc r/w - accumulator & read table 1 st data 002 h t b1 r/w - read table 2 nd data 003 h t b2 r/w - read table 3 rd data 004 h t b3 r/w - read table 4 th data 005 h dpl r/w - data pointer low nibble 006 h dpm r/w - data pointer middle nibble 007 h dph r/w - data pointer hi g h nibble peripheral registers: interrupt request flag register address symbol r/w default description 008 h ps r/w 0100 cpu power savin g control re g iste r 009 h psp r/w 0000 peripheral power savin g control re g iste r 00a h intc r/w 0000 interrupt enable control re g iste r 00b h intf r/w 0000 interrupt request fla g re g iste r 00c h intc1 r/w 0000 extended interrupt enable re g iste r 00d h intf1 r/w 0000 extended interrupt request fla g re g iste r 00e h pwmc r/w 0000 pwm control re g iste r 00f h pwm0l r/w xxxx pwm0 duty low nibble data re g iste r 010 h pwm0h r/w xxxx pwm0 duty hi g h nibble data re g iste r 011 h - - - 012 h pac r/w 1111 i/o port a control re g iste r 013 h pa r/w 1111 i/o port a data re g iste r 014 h pbc r/w 1111 i/o port b control re g iste r 015 h pb r/w 1111 i/o port b data re g iste r memory map: rom address ram address function block 000 h ~7bf h - program rom [ 1984 *16] - 000 h ~ 007 h file registers - 008 h ~01f h peripheral registers (i) - 020 h ~0af h working ram [144*4] - 200 h ~304 h peripheral registers (ii) interrupt vectors: interrupt vectors function description $000 hardware reset $001 hardware irq
preliminar y ttp258 tontouch tm 16?/04/06 page 10 of 44 ver.: 1.2 016 h pcc r/w 1111 i/o port c control re g iste r 017 h pc r/w 1111 i/o port c data re g iste r 018 h pdc r/w 1111 i/o port d control re g iste r 019 h pd r/w 1111 i/o port d data re g iste r 01a h pwm1l r/w xxxx pwm1 duty low nibble data re g iste r 01b h pwm1h r/w xxxx pwm1 duty hi g h nibble data re g iste r 01c h pwm2l r/w xxxx pwm2 duty low nibble data re g iste r 01d h pwm2h r/w xxxx pwm2 duty hi g h nibble data re g iste r 01e h t pintc r/w 0000 t ouchpad interrupt enable control re g ister 01f h t pintf r/w 0000 t ouchpad interrupt request fla g re g iste r 200 h t cp1c r/w 0000 t cp1 t imer/counter control re g iste r 201 h t cp1l r/w xxxx t cp1 timer/counter data low re g iste r 202 h t cp1h r/w xxxx t cp1 timer/counter data hi g h re g iste r 203 h t cp2c r/w 0000 t cp2 timer/counter control re g iste r 204 h t cp2l r/w xxxx t cp2 timer/counter data low re g iste r 205 h t cp2h r/w xxxx t cp2 timer/counter data hi g h re g iste r 206 h pai r ---- port a pad data readin g address 207 h pbi r ---- port b pad data readin g address 208 h pci r ---- port c pad data readin g address 209 h pdi r ---- port d pad data readin g address 20a h - - - - 20b h - - - - 20c h t cpfs r/w 0000 t cp clock source fs pre-scale re g iste r 20d h t bc r/w 1111 t ime base cont r ol re g iste r 20e h mcks r/w 0111 modulation clock selector re g iste r 20f h t pchs0 r/w 0000 t ouch pad channel selector re g iste r 210 h t pchs1 r/w 0000 t ouch pad channel selector re g iste r 211 h t pchs2 r/w 0000 t ouch pad channel selector re g iste r 212 h t pctl r/w 0000 t ouch pad control re g iste r 213 h t pct0 r/w xxxx t ouch pad duty counter 1st nibble 214 h t pct1 r/w xxxx t ouch pad duty counter 2nd nibble 215 h t pct2 r/w xxxx t ouch pad duty counter 3rd nibble 216 h ldoflag r/w 0000 ldo fail fla g 217 h csa r/w 0000 t ouch pad c load 218 h spcon0 r/w 0000 special control re g ister 0 219 h spcon1 r/w 0000 special control re g ister 1 21a h odata r/w 0000 t ouchkey output re g ister for special function 300 h resetf r/w 0000 reset fla g 301 h t brb w xxxx t ime base counter clear address 302 h mro w xxxx mask option re g ister write enable address 303 h clrwdt w xxxx clear wdt 2nd instruction 304 h lvren r/w 0000 lvren re g ister note: a. default means initial value after power on or reset. b. r is ?read? only, w is ?write? only, r/w is both of ?read? & ?write?.
preliminar y ttp258 tontouch tm 16?/04/06 page 11 of 44 ver.: 1.2 system function description: s-1: system oscillator the high-speed oscillator is operat ed in built-in rc mode. built-in rc oscillator is fixed 4mhz s-2: peripheral oscillator the low speed oscillator was built-in an in ternal rc oscillator that is for low power consumption consideration and fixe d peripheral device timing control. built-in rc oscillator an d the frequency range be tween 12 khz ~ 21 khz. s-3: cpu clock the cpu clock comes from system/peripheral oscillat or which was controlled by h/l bit in ps register. in the normal operation, the system clock comes from high-speed system oscill ator (osch/2). the low sp eed operation frequency (oscl/2) comes from rc oscillator. figure: system oscillator & cpu clock sources figure: system high speed oscillator rc oscillator oscen osch 16 k hz ( buil t -in rc ) 1 0 cpu machine h/l m u x peripheral clock oscl (16k hz) osc tbck /2
preliminar y ttp258 tontouch tm 16?/04/06 page 12 of 44 ver.: 1.2 s-4: power saving mode (sleep mode) the cpu enters sleep mode is operated by writing cpu power saving register (ps). during the power saving mode, cp u holds the internal status of the system. s-5: mcu system operation modes the mcu has 3 operating modes, includ ing high-speed oper ation, low speed operation, sleep modes. after power on reset, the mcu will go into high-speed operation mode automatica lly. after wake up from sleep mode, the mcu will resume the last operation mode. * power saving mode condition & release modes sleep mode high speed oscillator stopped as h/l=0 high speed oscillator keep operating as h/l=1 cpu clock stopped cpu internal status stop & retain the status memory, flag, register, i/o retain the status program counter hold the next executed address peripherals: time base, timers, interrupts keep operating watch dog timer disable & cleared release condition reset, external and internal int sources, input wake-up figure: system operation state diagram sleep/ wake up sleep/ wake up h/l reset reset release reset high speed operating mode osch on & oscl on reset low speed operating mode osch off & oscl on sleep mode cpu stop reset
preliminar y ttp258 tontouch tm 16?/04/06 page 13 of 44 ver.: 1.2 s-6: watch dog timer (wdt) the clock of watchdog timer comes from time base overflow (tb1ov). user can use the time up signal to preven t a software malfunction or abnormal sequence from jumping to an unknown me mory location causing a system fatal failure. normally, if the watchdog timer ti me up signal active that will reset the chip. at the same time, program and ha rdware can be initialized and resume system under normal operation. the chip also provides 2 st eps clear watchdog command as the programmer writ es intf with $f data fi rst that will enable the wdt clear, and then writes clear wdt 2nd register ($303h) after. completely finishes the two write & read steps will clear the watchdog timer. user should well arrange the two command steps fo r avoiding the de ad lock loop. user should keep in minds th at always reset wdt at main program and never clear the wd t in the interrupt routine. the max period of wdt =(tb1ov cycle time) * 8 s-7: low voltage reset (lvr) the low voltage reset (lvr) forces th e mcu in reset state during power failure, especially as mcu working in ac power application, preventing from abnormal state is the ke y issue. the control bit lvren is in independent register. it can prevent lvren change by unexpected program. the lvr can select always on or control by register by metal trim and lvr voltage is 2.2v. q qb wdt overflow tff tff tff por+reset sleep intf write $f first then write $303h after dff tb1ov as clock figure: watch dog timer control circuit write intf first & write $303h after
preliminar y ttp258 tontouch tm 16?/04/06 page 14 of 44 ver.: 1.2 s-8: reset the chip has four kinds of reset sources: por (power on reset), external reset, watch dog timer reset, lvr (low voltage reset). the reset feature can be divided into 2 kind groups that one is system reset and the other is cpu reset. the system reset will initialize the cpu an d peripheral device wi th default state. the cpu reset only initializes the cpu st ate and keeps the pe ripheral state no change. .por (power on reset) the chip provides automatic reset functi on when the power is turned on. the vdd should be below 1.6v and its risi ng slope (from 0.1v dd up to 0.9vdd) needs less than 10ms. .external reset (rstb) this is one kind of system resetting signal, but only forced externally. when the chip acknowledged th e low level from the pin rstb exceed 1 us, it will generate the reset procedure to reset cp u & all the peripheral back to their initial state (default values). .burn out reset (program sequence abnormal) as cpu out of program area, the cpu ca n detect the abnormal condition and generate a system reset request. .watch dog timer reset the reset signal will generate automa tically when the watchdog timer runs overflow. if the watchdog timer is clea red regularly by users? program, no watchdog reset will occur. unless the mc u is forced into ab normal state, the software-controlled procedure is di srupted and causing watchdog timer overflow, then it will generate reset sign al to initializes th e chip returning to normal operation. .low voltage reset (lvr) the lvr function is used to monitor the supply voltage of mcu, it will generate a reset signal (with 4*o scl de-bounce time) to reset the microcontroller as the vdd power falls below the default setting level v lvr . it can also be enabled or disabled by pr ogramming ?lvren? bit in lvren register (304h). user write $5h to this register , it can enable lvren, write $ah can disable lvren. if user writes other va lue to lvren register, it cannot change lvren bit. ? resetf[300h]: reset source flag register[r/w], power on value [0000] r e g ister bit3 bit2 bit1 bit0 bit name romf bof lvrf wdtf read/write r/w r/w r/w r/w wdtf: watch dog timer overflow reset flag (0: no active; 1: active) lvrf: low voltage reset flag (0: no active; 1: active) bof: burn out flag (0: no active; 1: active) romf: rom fail flag (0: no active; 1: active) (the resetf is cleared by power on reset and external reset)
preliminar y ttp258 tontouch tm 16?/04/06 page 15 of 44 ver.: 1.2 s-9. power saving control register ? ps[008h]: power saving register[r/w] , default value [0100] register bit3 bit2 bit1 bit0 bit name - h/l sleep - read/write - r/w r/w - sleep: into sleep mode. (0: inactive; 1: active) h/l: system clock selection. (1: system clock; 0: peripheral clock) the sleep bits will be cleared to ?0? automatically, when the release conditions occur from reset, interrupt, or input wake up. ? psp[009h]: peripheral power saving register[r/w] , default value [0000] register bit3 bit2 bit1 bit0 bit name ldoen - - - read/write r/w - - - ldoen: ldo enable. (0: disable; 1: enable) ? lvren[304h]: lvr enable control register[r/w] , default value [0000] register bit3 bit2 bit1 bit0 bit name - - - lvren read/write - - - r/w lvren: low voltage reset enable, (0: disable, 1: enable), when write $5 to this address, lvren is set to 1 , write $a to this address, lvren is clear to 0. ? ldoflag[216h] : ldo falg register[r/w] , default value [0000] register bit3 bit2 bit1 bit0 bit name - - - ldofail read/write - - - r/w ldofail: when vdd voltage is small then ldo vo ltage, ldofail will be set. this bit can be clear by write 0.
preliminar y ttp258 tontouch tm 16?/04/06 page 16 of 44 ver.: 1.2 s-10. special control register ? spcon0 [218h]: special control register 0 [r/w] , default value [0000] register bit3 bit2 bit1 bit0 bit name cdsc2 cdsc1 cdsc0 vrefs read/write r/w r/w r/w r/w vrefs: voltage reference selection for touch sens or detect (0: 1/2 vdd; 1: 2/3 vdd), use in tpni select comparator output signal mode. cdsc: charge and discharge sequence control for touch sensor function cdsc2 ~ cdsc0 sequence chan g e cloc k 000 off 001 8 010 12 011 16 100 24 101 32 110 reserve 111 reserve ? spcon1 [219h]: special control register 1 [r/w] , default value [0000] register bit3 bit2 bit1 bit0 bit name intts - - - read/write r/w - - - intts: int0 interrupt input type selection (0: schmitt; 1: comparator) compare reference voltage use band gap voltage the system oscillator generates the system control timing for cpu core or peripheral devices with fixed control phase, so the waveform of oscillator becomes sensitive to noise, abnormal duty especially fatal for cpu. any switching of clock source needs oscillation stable time (ost) to make sure the oscillation is stab le and synchronized with cpu timing phase. the relative ost for different oscillator with reference value as below table: ost from stop state oscillating unit system clock(osch) 8 8 osch clock rc peripheral clock(oscl) 8 8 oscl rc clock
preliminar y ttp258 tontouch tm 16?/04/06 page 17 of 44 ver.: 1.2 s-11. interrupts the cpu provides on ly 1 interrupt vector ($001h ) and no priority, but can expand to multi-sources. interrupt sour ce includes external interrupts (int0, int1), timer/counter interrupts (tcp1, tcp2), time base timer interrupt (tbxint) or other peripheral device in terrupt request (perint). the interrupt control registers (intc or intc1) contai n the interrupt control bits to enable and disable corresponding interrupt re quest and the corresponding interrupt request flags in the (intf or intf1) regi sters. before finishing the int service routine, another int request will keep waiting until program return from interrupt routine. if the interrupt request needs se rvice, the programmer may set the corresponding int enable bi t to allow interrupt active . external interrupts are triggered by both falling and rising e dge trigger and set the related interrupt request flag (intfx). the internal time r/counter interrupt is setting the tcpxf to 1, resulting from the ti mer/counter overflow. the time base interrupt tbxint was provided 2 periodic interrupt request cycles for user op erating a periodic routine. when the correspondin g interrupt enable and flag bits is set to 1, the cpu will active the interrupt service routin e. then cpu reads th e service flag and check the request priority then proceeds with the relative interrupt service. after cpu writes the corresponding bits to 0 in the intfx re gister, the service flag will be cleared to 0(using stx #n, $m instruction) . the intf & intf1 registers? bit can only write ?0? to clear th e flag. user writes ?1 ? to flag bit with no effect. int0 input type can select schmitt or comparator by spcon1 register, if comparator select then the comparator reference voltage is the band gap voltage(1.12+-10%), it will consumptio n more current than schmitt because band gap turn on. it can be used to detect vdd voltage for battery low and so on.
preliminar y ttp258 tontouch tm 16?/04/06 page 18 of 44 ver.: 1.2 intc[00ah]: interrupt control regi ster [r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tb2ie tcp2ie tcp1ie tb1ie read/write r/w r/w r/w r/w tb1ie: enable time base 1st interrupt. (0: disable; 1: enable) tcp1ie: enable interrupt of tcp1 timer/counter. (0: disable; 1: enable) tcp2ie: enable interrupt of tcp2 timer/counter. (0: disable; 1: enable) tb2ie: enable time base 2nd interrupt. (0: disable; 1: enable) ? intf[00bh]: interrupt request flag register [r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tb2f tcp2f tcp1f tb1f read/write r/w r/w r/w r/w tb1f: time base timer 1st interrupt request flag. (0: inactive; 1: active) tcp1f: tcp1 timer/counter interrupt request flag. (0: inactive; 1: active) tcp2f: tcp2 timer/counter interrupt request flag. (0: inactive; 1: active) tb2f: time base 2nd interrupt request flag. (0: inactive; 1: active) ? intc1[00ch]: extended interrupt control register [r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name - - int1ie int0ie read/write - - r/w r/w int0ie: enable int0 external interrupt. (0: inactive; 1: active) int1ie: enable int1 external interrupt. (0: inactive; 1: active) ? intf1[00dh]: extended interrupt request fla g register [r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name - - int1f int0f read/write - - r/w r/w int0f: int0 external interrupt request flag. (0: inactive; 1: active) int1f: int1 external interrupt request flag. (0: inactive; 1: active) intxs1 intxs0 t ri gg er type 00 low active 01 fallin g ed g e 10 risin g ed g e 11 dual ed g e tri gg er note: intxf trigger type are selected by mask option ? tpintc[01eh]: touchpad interrupt control register [r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tpctie tpcmpie - - read/write r/w r/w - - tpcmpie: capacitor overcharge interrupt enable. (0: disable; 1: enable) tpctie: duty counter overflow interrupt enable. (0: disable; 1: enable) ? tpintf[01fh]: touchpad request flag register [r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tpctf tpcmpf - - read/write r/w r/w - - tpcmpf: capacitor overcharge?s flag. (0: inactive; 1: active) tpctf: duty counter?s overflow flag. (0: inactive; 1: active)
preliminar y ttp258 tontouch tm 16?/04/06 page 19 of 44 ver.: 1.2 peripheral function description: p-1: system clock pre-scale the system clock almost is the most high frequency of mcu. for various peripherals, application needs different clock source divide d from system clock. tcpfs register is a selector for choosing su itable frequency (fs). ? tcpfs[20ch]: system clock pre-scale register[r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name - fs2 fs1 fs0 read/write - r/w r/w r/w fs2~fs0: the selector value of tcpfs register fs2 ~ fs0 fs fs2 ~ fs0 fs 0 osch/1 4 osch/16 1 osch/2 5 osch/32 2 osch/4 6 osch/64 3 osch/8 7 osch/128
preliminar y ttp258 tontouch tm 16?/04/06 page 20 of 44 ver.: 1.2 p-2: time base counter the time base counter has 2 interrupt sources and both of them come from the peripheral internal rc oscillator. the time base 1st overflow output (tb1ov) can cause interrupt and the period is selected by tb 1s2~tb1s0 in tbc register. the time base 2nd overflow output (tb2 ov) also offers two sample frequency options by tb2s bit in the tbc register. ? tbc[20dh]: time base control regi ster[r/w], default value [1111] register bit3 bit2 bit1 bit0 bit name tb2s tb1s2 tb1s1 tb1s0 read/write r/w r/w r/w r/w tb1s2 ~ tb1s0: base timer1 overflow frequency selection bits. tb2s: base timer2 overflow frequency selection (0: 32hz; 1:16hz) (every time writing the tbrb will clear the time base counter) tb2s base timer overflow frequency (tb1ov) t b2ov ( if oscl=16khz ) 0 t bck/512 32hz 1 t bck/1024 16hz tb1s2 tb1s1 tb1s0 base timer overflow frequency (tb1ov) t b1ov ( if oscl=16khz ) 0 0 0 t bck 16khz 0 0 1 t bck/2 8khz 0 1 0 t bck/16 1khz 0 1 1 t bck/64 256hz 1 0 0 t bck/256 64 hz 1 0 1 t bck/2048 8hz 1 1 0 t bck/8192 2hz 1 1 1 t bck/16384 1hz tbck tbck/2 tbck/16 tbck/64 tbck/256 tbck/2048 tbck/8192 tbck/16384 tb2ov tb2s tb1ov tb1s2~tb1s0 14 bit binary counter tbck (if oscl=16khz) 16 khz 8 khz 1 khz 256hz 64hz 8hz 2hz 1hz mux write tbrb & clear counter
preliminar y ttp258 tontouch tm 16?/04/06 page 21 of 44 ver.: 1.2 p-3: 8 bits timer/counter (tcp) for tcp1 one 8-bit timer/counters (tcp) with 4 kind clock sources and preload data buffer can implement as a timer or coun ter feature. the clock sources of tcp1 are selected by tcp1s0 & tcp1s1 two bits of the timer control registers (tcp1c). tcp1ov is the timer or counter overflow signal an d the rising edge will set the relative int flag. ? tcp1c[200h]: tcp1 timer/counter contro l register[r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tcp1ld tcp1s1 tcp1s0 tcp1en read/write r/w r/w r/w r/w tcp1en: tcp1 counting enabled. (0: disable; 1: enable) tcp1ld: tcp1 auto-reload enabled. (0: disable; 1: enable) tcp1s1 & tcp1s0: tcp1 clock source selection bits. t cp1s1 t cp1s0 selected cloc k source 0 0 ck0 0 1 ck1 1 0 ck2 1 1 ck3 ? tcp1l[201h]: tcp1 low nibble data register[r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tcp1_3/tcp1d3 tcp1_2/tcp1d2 tcp1_1/tcp1d1 tcp1_0/tcp1d0 read/write r/w r/w r/w r/w tcp1_3~tcp1_0: reading the counter low nibble data. tcp1d3~tcp1d0: writing tcp1d low nibble of data buffer. ? tcp1h[202h]: tcp1 high nibble data register[r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tcp1_7/tcp1d7 tcp1_6/tcp1d6 tcp1_5/tcp1d5 tcp1_4/tcp1d4 read/write r/w r/w r/w r/w tcp1_7~tcp1_4: reading the counter high nibble data. tcp1d7~tcp1d4: writing tcp1d high nibble of data buffer. * tcp1d: like a 8 bit tcp1 data register[r/w], default value [00h] tcp1d bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit name tcp1d7 tcp1d6 tcp1d5 tcp1d4 tcp1d3 tcp1d2 tcp1d1 tcp1d0 the special r/w function for tcp1 has different target, as writing tcp1h/l registers that are updating preload da ta of the tcp1d. as read tcp1h/l registers that are the bran d new tcp1 counter value.
preliminar y ttp258 tontouch tm 16?/04/06 page 22 of 44 ver.: 1.2 p-4: 8 bits timer/counter/pwm for tcp2 one 8-bit timer/counters (t cp2) with 4 kind clock sources and preload data buffer can implement as a ti mer or counter feature. the clock sources of tcp2 are selected by tcp2s0 & tcp2s1 two bits of the timer control registers (tcp2c). tcp2ov is the timer or counter overflow signal an d the rising edge will set the relative int flag. ? tcp2c[203h]: tcp2 timer/counter/pwm cont rol register[r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tcp2ld tcp2s1 tcp2s0 tcp2en read/write r/w r/w r/w r/w tcp2en: tcp2 counting enabled. (0: disable; 1: enable) tcp2ld: tcp2 auto-reload enabled. (0: disable; 1: enable) tcp2s1 & tcp2s0: tcp2 clock source selection bits. t cp2s1 t cp2s0 selected clock source 0 0 ck0 0 1 ck1 1 0 ck2 1 1 ck3 ? tcp2l[204h]: tcp2 low nibble data register[r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tcp2_3/tcp2d3 tcp2_2/tcp2d2 tcp2_1/tcp2d1 tcp2_0/tcp2d0 read/write r/w r/w r/w r/w tcp2_3~tcp2_0: reading the counter low nibble data. tcp2d3~tcp2d0: writing tcp2d low nibble of data buffer. ? tcp2h[205h]: tcp2 low high data re gister[r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tcp2_7/tcp2d7 tcp2_6/tcp2d6 tcp2_5/tcp2d5 tcp2_4/tcp2d4 read/write r/w r/w r/w r/w tcp2_7~tcp2_4: reading the counter high nibble data. tcp2d7~tcp2d4: writing tcp2d high nibble of data buffer. * tcp2d: like a 8 bit tcp2 data register[r/w], default value [00h] tcp2d bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit name tcp2d7 tcp2d6 tcp2d5 tcp2d4 tcp2d3 tcp2d2 tcp2d1 tcp2d0 the special r/w function for tcp2 has different target, as writing tcp2h/l registers that are updating preload data of the tcp2d. as read tcp2h/l registers that are the brand new tcp2 counter value.
preliminar y ttp258 tontouch tm 16?/04/06 page 23 of 44 ver.: 1.2 p-5: 16 bits timer/counter two sets tcp can be cascaded to fo rm a 16-bit timer/counter when tcp2 chooses tcp1ov as clock source (tcp2s 1=1 & tcp2s0=1). in the 16-bit timer application, data load is controlled by writing tcp1en=1 , then user should enable the tcp2en at first, then usin g tcp1en to control the starting or stopping counting of 16-bit timer/counter. the rising tcp2ov will reload the contents in the pre-load register into timer/counter, if tcp1ld in tcp1c & tcp2ld in tcp2c are enabled. the interrupt feature is different, in this case, the tcp1 int will be inhibit when tcp1 ov occur, the tcp2 int is normally. .timer when tcpx works as a timer, user n eeds give the preload data tcpxd for periodic interrupt. after initial setting, user starts the tcpx counting by setting tcpxen=1, the tcpx cycle period is: tc = (selected clock cycle) * (256) if tcpxd=00h tc = (selected clock cycle) * (tcpxd) otherwise when 16 bits timer/counter: tc = (selected clock cycle) * (6 5536) if tcp1d=00h & tcp2d=00h tc = (selected clock cycle) * (tcp2d*256+tcp1d) otherwise when user writes data to the tcpxd, th e data just keep in tcpxl/h. during the tcpxen=1 command executed, the tcpxd?s complement value will load into counter tcpx as initial value an d start the timer function. necessary tcpxld=1, timer run with reload feature as tcpx up counts and reaches the value of ?ff h ? or 255 for tcpx. at the same ti me, interrupt request flag tcpxf will set activated, if software enables the corresponding interrupt enable bit, int hardware will cause mcu in terrupt service routine. figure: 16 bit timer/counter configuration
preliminar y ttp258 tontouch tm 16?/04/06 page 24 of 44 ver.: 1.2 .counter counter feature is implem ented only by tcpxld=0, the tcpxd can be zero or not that depends on software needs. user starts & stops the counter by changing the tcpxen bit value. on th e save side, reading the counter value after stopping the count by disable tc pxen=0, if reading the counter value during value changing that means cloc k in happening at the same time. the reading of counter value may disrupt for transient state. if 8 bit counter is not enough for counting, user can enable the interrupt an d using the data ram as software counter for extend ing the counter stage. fs: system scaled frequency. tbck: peripheral clock source, 16khz in the rc mode. (typical) tb1ov: time base 1 st overflow output. pwm0~2: tcp2 cycle time with pwmxd duty output signal tcp1ov: timer/counter1?s overflow output. tcp1s1 tcp1s0 tcp1 ck0 0 0 fs ck1 0 1 osch ck2 1 0 tbck ck3 1 1 tb1ov pwm output tcp2 pwm0,1,2 tcp2s1 tcp2s0 tcp2 ck0 0 0 fs ck1 0 1 osch ck2 1 0 tbck ck3 1 1 tcp1ov tcp2s1 tcp2s0 tcp2ov ck0 ck1 ck2 ck3 timer/counter m u x preload data data bus data bus figure: timer/counter/pwm tcp2l tcp2en pwmx circuit
preliminar y ttp258 tontouch tm 16?/04/06 page 25 of 44 ver.: 1.2 .pwm the pwm period generated from tc p2. when pwmxen (pwmc<0> or pwmc<1> or pwmc<2>) enable, and pwmout pin (pa0, pa1, or pa2 the pax must be output mode and select normal io by mask option) change to output mode, pwmx signal will ou tput to pwmout pin. the duty of pwmx value is store in pwmxl and pwmxh, user write pwmxh first, last write pwmxl. when write th e pwmxl the 8 bits duty value will be load to pwmxd at the same time. pwm? s duty value cannot bigger than tcp2 pre-load data. if not, pwmout is an unexpected signal. user can select pwmout pin start with 1 or start with 0 by option. when tcp2 enable, timer start increment, if timer/counter value bigger than pwm?s duty value, pwmout will change stat e. the pwmout back to start state, when tcp2 is overflow. user does not use pwm in 16 bits ti mer/counter mode. if not, pwmout is an unexpected signal. user does not use tcp2d=00h. if not, pwmout is an unexpected signal. ? pwmc[00eh]: pwm control register[r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name - pwm2en pwm1en pwm0en read/write - r/w r/w r/w pwm0en: pwm0 output enabled. (0: disable; 1: enable) pwm1en: pwm1 output enabled. (0: disable; 1: enable) pwm2en: pwm2 output enabled. (0: disable; 1: enable) ? pwm0l[00fh]: pwm0 duty low nibble data register[r/w], default value [----] register bit3 bit2 bit1 bit0 bit name pwm0d3 pwm0d2 pwm0d1 pwm0d0 read/write r/w r/w r/w r/w pwm0d3~0: pwm0 duty low nibble data ? pwm0h[010h]: pwm0 duty high nibble data register[r/w], default value [----] register bit3 bit2 bit1 bit0 bit name pwm0d7 pwm0d6 pwm0d5 pwm0d4 read/write r/w r/w r/w r/w pwm0d7~4: pwm0 duty high nibble data ? pwm1l[01ah]: pwm1 duty low nibble data register[r/w], default value [----] register bit3 bit2 bit1 bit0 bit name pwm1d3 pwm1d2 pwm1d1 pwm1d0 read/write r/w r/w r/w r/w pwm1d3~0: pwm1 duty low nibble data
preliminar y ttp258 tontouch tm 16?/04/06 page 26 of 44 ver.: 1.2 ? pwm1h[01bh]: pwm1 duty high nibble data register[r/w], default value [----] register bit3 bit2 bit1 bit0 bit name pwm1d7 pwm1d6 pwm1d5 pwm1d4 read/write r/w r/w r/w r/w pwm1d7~4: pwm1 duty high nibble data ? pwm2l[01ch]: pwm2 duty low nibble data register[r/w], default value [----] register bit3 bit2 bit1 bit0 bit name pwm2d3 pwm2d2 pwm2d1 pwm2d0 read/write r/w r/w r/w r/w pwm2d3~0: pwm2 duty low nibble data ? pwm2h[01dh]: pwm2 duty high nibble data register[r/w], default value [----] register bit3 bit2 bit1 bit0 bit name pwm2d7 pwm2d6 pwm2d5 pwm2d4 read/write r/w r/w r/w r/w pwm2d7~4: pwm2 duty high nibble data pwmxd pwm duty note 0 (0 * clock cycle) / tcp2 timer ? s period all of f 1 (1 * clock cycle) / tcp2 timer ? s period 2 (2 * clock cycle) / tcp2 timer ? s period ?. ?. n ((n) * clock cycle) / tcp2 timer ? s period ?. ?. t cp2d ((tcp2d) * clock cycle) / tcp2 timer ? s period all on note: 1. pwmxd cannot bigger than tcp2d 2. tcp2 timer?s period = (tcp2d) * clock cycle. 3. pwm can start 0 or start 1 by option. table: pwm duty fi g ure: timer/counter/pwm dut y com p are 8- b its dut y hi g h dut y tm p write pwmxh low dut y hi g h dut y pwmxo pwmxen pwmx tcp2 count write pwmxl tcp2ov 8- b its dut y pwmxd
preliminar y ttp258 tontouch tm 16?/04/06 page 27 of 44 ver.: 1.2 . i/o pad cell structure & function description input port the input port can be programmed as in put with pull-up resistor and input data can read by port re ading command. then a wake-u p function also offers the system wake up feature for keys or special external triggers then a wake-up function also offers the system wake up feature for keys or special external triggers. input data pull-up read data wake-up 0 r 0 active 0 no 0 inhibited 1 r 1 non-active 1 no 1 inhibited floating r 1 non-active floating no ? inhibited r: pull-up resistor x: don?t care the value ?: unknown figure io-e: input port pull-high r data pad wake-up read p external input
preliminar y ttp258 tontouch tm 16?/04/06 page 28 of 44 ver.: 1.2 i/o port with external input the input/output port has the i/o cont rol register for switching input or output mode and output data register stor es the output data in output mode. if control register=1 and output data=1, the i/o port is programmed as input with pull-up resistor and al so actives the wake-up function. user intends to read the port data with differed read instruction. the read pi is reading data comes from pad input data. the data register reading result will have the same value with output register data. software can performs a configuration (data=0, changing the control 0 or 1) for open dr ain type that specifies suitable for key scan application. an additi onal feature supports the in terrupt input triggers and timer external clock sources. i/o control data out p ut data pull-u p r wake-u p feature external in p uts 0 x no no no 1 0 no no enable 1 1 enable enable enable x: don ? t care the value i/o control data mode pad 0 out p ut mode out p ut re g ister data 1 in p ut mode in p ut data read pi read in p ut data 0 out p ut re g ister data 1 pad in p ut data figure io-a: standard io port with wake-up/interrupt/timer clock inputs pad timer/counter external clock output data register write external interrupt i/o control register write 0 1 pull-up r data bus wake-up pr read p n s d q ck qb s d q ck qb p m u x n n read pi
preliminar y ttp258 tontouch tm 16?/04/06 page 29 of 44 ver.: 1.2 i/o port with internal output the standard input/output port has th e i/o control register for switching input or output mode and ou tput data register stores the output data in output mode. if control data=1 and output da ta=1, the i/o port is programmed as input with pull-up resistor and also ac tives the wake-up function. user intends to read the port data with differed read instruction. the read pi is reading data comes from pad input data. the data regist er reading result will have the same value with output register data. if enab le internal output, the internal output will control by output data (on/off) and outputs to pad. i/o control data internal out p ut pad 0 enable out p ut internal data 0 disable out p ut re g ister data 1 x pad in p ut data x: don ? t care the value read pi mode read in p ut data 0 out p ut mode out p ut re g ister data 1 in p ut mode pad in p ut data i/o control data out p ut data pull-u p wake-u p 0 x no no 1 0 no no 1 1 enable enable x: don ? t care the value figure io-b: standard i/o port with internal output signal out p ut enable ( pwmen ) i/o ctrl registe r write 0 1 pull-up r data bus wake-up data register write pr read pad p n s d q ck qb s d q ck qb p m u x n n mux internal out p ut si g nal read pi
preliminar y ttp258 tontouch tm 16?/04/06 page 30 of 44 ver.: 1.2 standard i/o port the standard input/output port has th e i/o control register for switching input or output mode and ou tput data register stores the output data in output mode. if control data=1 and output da ta=1, the i/o port is programmed as input with pull-up resistor and also ac tives the wake-up function. user intends to read the port data with differed read instruction. the read pi is reading data comes from pad input data. the data regist er reading result will have the same value with output register data. software can performs a configuration (data=0, changing the control 0 or 1) for open dr ain type that specifies suitable for key scan application. i/o control data out p ut data pull-u p wake-u p 0 x no no 1 0 no no 1 1 enable enable x: don ? t care the value read pi read in p ut data 0 out p ut re g ister data 1 pad in p ut data i/o control data mode pad 0 out p ut mode out p ut re g ister data 1 in p ut mode in p ut data figure io-c: standard i/o port output data register write i/o control register write 0 1 pull-high r data bus wake-up pr read pad p n s d q ck qb s d q ck qb p m u x n n r ead pi
preliminar y ttp258 tontouch tm 16?/04/06 page 31 of 44 ver.: 1.2 i/o port with internal output & external input the standard input/output port has th e i/o control register for switching input or output mode and ou tput data register stores the output data in output mode. if control data=1 and output da ta=1, the i/o port is programmed as input with pull-up resistor and also ac tives the wake-up function. user intends to read the port data with differed read instruction. the read pi is reading data comes from pad input data. the data regist er reading result will have the same value with output register data. if enab le internal output, the internal output will control by output data (on/off) and outputs to pad. i/o control data out p ut data pull-u p wake-u p 0 x no no 1 0 no no 1 1 enable enable x: don ? t care the value i/o control data internal out p ut pad 0 enable out p ut internal data 0 disable out p ut re g ister data 1 x pad in p ut data x: don ? t care the value read pi mode read in p ut data 0 out p ut mode out p ut re g ister data 1 in p ut mode pad in p ut data figure io-d: standard i/o port with internal output signal & external input external interrup t timer/counter external cloc k i/o ctrl registe r write 0 1 pull-up data bus wake-up data register write pr read pad p n s d q ck qb s d q ck qb p m u x n n mux output enable internal output signal (pwm) read pi
preliminar y ttp258 tontouch tm 16?/04/06 page 32 of 44 ver.: 1.2 external interru p t i/o ctrl register write 0 1 pull-up r data bus wake-up data register write pr read pad p n s d q ck qb s d q ck qb r m u x n n mux output enable (pwmen) internal output signal (pwm) read pi figure io-e: standard i/o port with i nternal output signal & external input mux intts v bgap
preliminar y ttp258 tontouch tm 16?/04/06 page 33 of 44 ver.: 1.2 3. i/o pad cells the main features of pad cell are including esd/ eft protection and general i/o access. a general i/o pad cell can be configured as input with or without pull-up resistor, or working as a cmos or nmos output driver. the input pad cell must have pull-up resistor for avoiding a floating state when user doesn?t care or not be used. for concer ning the standby curr ent, user can use data register or i/o control register to fit the application. . i/o file register ? pac[012h]: port a i/o control register [r/w], default value [1111] register bit3 bit2 bit1 bit0 bit name - pac2 pac1 pac0 read/write - r/w r/w r/w pac2~pac0: port a i/o control data ? pa[013h]: port a data register [r/w], default value [1111] register bit3 bit2 bit1 bit0 bit name - pa2 pa1 pa0 read/write - r/w r/w r/w pa2~pa0: port a data ? pbc[014h]: port b i/o control regi ster [r/w], default value [1111] register bit3 bit2 bit1 bit0 bit name - - pbc1 pbc0 read/write - - r/w r/w pbc1~pbc0: port b i/o control data ? pb[015h]: port b data register [r/w], default value [1111] register bit3 bit2 bit1 bit0 bit name - - pb1 pb0 read/write - - r/w r/w pb1~pb0: port b data ? pcc[016h]: port c i/o control regi ster [r/w], default value [1111] register bit3 bit2 bit1 bit0 bit name pcc3 pcc2 pcc1 pcc0 read/write r/w r/w r/w r/w pcc3~pcc0: port c i/o control data
preliminar y ttp258 tontouch tm 16?/04/06 page 34 of 44 ver.: 1.2 ? pc[017h]: port c data register [r/w], default value [1111] register bit3 bit2 bit1 bit0 bit name pc3 pc2 pc1 pc0 read/write r/w r/w r/w r/w pc3~pc0: port c data ? pdc[018h]: port d i/o control regi ster [r/w], default value [1111] register bit3 bit2 bit1 bit0 bit name pdc3 pdc2 pdc1 pdc0 read/write r/w r/w r/w r/w pdc3~pdc0: port d i/o control data. ? pd[019h]: port d data register [r/w], default value [1111] register bit3 bit2 bit1 bit0 bit name pd3 pd2 pd1 pd0 read/write r/w r/w r/w r/w pd3~pd0: port d data ? pai[206h]: port a pad data reading address [r], default value [----] register bit3 bit2 bit1 bit0 bit name - pai2 pai1 pai0 read/write - r r r pai2~pai0: port a pad data ? pbi[207h]: port b pad data reading address [r], default value [----] register bit3 bit2 bit1 bit0 bit name - - pbi1 pbi0 read/write - - r r pbi1~pbi0: port b pad data ? pci[208h]: port c pad data reading address [r], default value [----] register bit3 bit2 bit1 bit0 bit name pci3 pci2 pci1 pci0 read/write r r r r pci3~pci0: port c pad data ? pdi[209h]: port d pad data reading address [r], default value [----] register bit3 bit2 bit1 bit0 bit name pdi3 pdi2 pdi1 pdi0 read/write r r r r pdi3~pdi0: port d pad data
preliminar y ttp258 tontouch tm 16?/04/06 page 35 of 44 ver.: 1.2 . io port?s special function when specio?s is selected by mask op tion, pa0~pa2 is special function. it can ouput odata register to user. odat a can be store key touch information by software. pa0 is input port, pa2 & pa3 is output. user can use this function to get key touch information. ? odata[21ah]: touchkey output register for special function [r/w], default value [0000 ] register bit3 bit2 bit1 bit0 bit name odata3 odata2 odata1 odata0 read/write r/w r/w r/w r/w odata3~0: touchkey information pa0 (input) pa1 (output) pa2(output) 1 odata0 odata 1 0 odata2 odata 3
preliminar y ttp258 tontouch tm 16?/04/06 page 36 of 44 ver.: 1.2 10 non-contact inputs touch pad detector the touch pad detector applies the ch arge sharing concep tion. the inputs share the pad with io ports. built-in charge sharing co ntrol, duty detector and de-bounce feature can respon se the input with varied output refresh rate that dependant on the system request. for power saving concern, auto power off function and wake up de-bounce capability can support a lower average operating current. parameters tar g et value remark t ouch pad osc 4mhz or 16khz (typ.) usin g osch or oscl modulation clock osch/n or oscl n=1,2,4,8,16,32,64,oscl duty counte r 12 bits with int reload data latch 12 bit write only t ouch pads 1~10 keys mask option key de-bounce time s/w implements by application or cover thickness sensitivity level offset value by s/w resolution=1 modulation cloc k 12 bits duty counter & reload data latch ch0 ch1 : : : : ch8 ch9 key scan & timing control figure: 10 keys touch pad detector edge detector data bus tpcmpf clock gating modulation clock selector osch/ oscl touch pad selector touch available pad tpctf
preliminar y ttp258 tontouch tm 16?/04/06 page 37 of 44 ver.: 1.2 the state machine of sequ ence control is simplified as: wait ? ---- |___no__| | | | initial c reload duty counter (clear tpctf & tpcmpf) | | enable counter | wake-up condition (tpcmpf=1 | tpctf=1 ) --- ? wake up | wait
preliminar y ttp258 tontouch tm 16?/04/06 page 38 of 44 ver.: 1.2 ? tpintc[01eh]: touchpad interrupt control register [r/w], default value [0000] tpintc bit3 bit2 bit1 bit0 bit name tpctie tpcmpie - - read/write r/w r/w - - tpcmpie: capacitor overcharge interrupt enable. (0: disable; 1: enable) tpctie: duty counter overflow interrupt enable. (0: disable; 1: enable) ? tpintf[01fh]: touchpad request flag register [r/w], default value [0000] tpintf bit3 bit2 bit1 bit0 bit name tpctf tpcmf - - read/write r/w r/w - - tpcmpf: capacitor overcharge?s flag. (0: inactive; 1: active) tpctf: duty counter?s overflow flag. (0: inactive; 1: active) ? tpct0[213h]: touch pad duty counter & latch da ta register 0 [r], default value [xxxx] register bit3 bit2 bit1 bit0 bit name tpct3/ct3 tpct2/ ct2 tpct1/ct1 tpct0/ct0 read/write r/w r/w r/w r/w tpct3~tpct0: duty counter 1st nibble for counter read ct3~ct0: 1st nibble of reload latch data ? tpct1[214h]: touch pad duty counter & latch da ta register 1 [r], default value [xxxx] register bit3 bit2 bit1 bit0 bit name tpct7/ct7 tpct6/ ct6 tpct5/ct5 tpct4/ct4 read/write r/w r/w r/w r/w tpct7~tpct4: duty counter 2nd nibble for counter read ct7~ct4: 2nd nibble of reload latch data ? tpct2[215h]: touch pad duty counter & latch da ta register 2 [r], default value [xxxx] register bit3 bit2 bit1 bit0 bit name tpct11/ct11 tpct10/ct10 tpct9/ct9 tpct8/ct8 read/write r/w r/w r/w r/w tpct11~tpct8: duty counter 3rd nibble for counter read ct11~ct8: 3rd nibble of reload latch data duty counter value= tp ct2*256 +tpct1*16+tpct0 the duty counter will be enabled by writing the tpchs0 register and will set the tpctf flag if duty counter over flow. as writing any of the tpchs0 addresses will reload the 12 bit co unters and clear the tpctf & tpcmpf.
preliminar y ttp258 tontouch tm 16?/04/06 page 39 of 44 ver.: 1.2 ? mcks[20eh]: modulation clock selector register [r/w], default value [0111] register bit3 bit2 bit1 bit0 bit name - mcks2 mcks1 mcks0 read/write - r/w r/w r/w mcks2~mcks0: modulation clock selector the tpcmpf will be set as no modulation clock going into duty counter with de-bounce feature and will also call the interrupt as tpcmpie=1 . ? tpchs0[20fh]: touch pad channel selector register0 [r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tpen3 tp en2 tpen1 tpen0 read/write r/w r/w r/w r/w tpen3~tpen0: touch pad channel selector 1st nibble ? tpchs1[210h]: touch pad channel selector register1 [r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name tpen7 tp en6 tpen5 tpen4 read/write r/w r/w r/w r/w tpen7~tpen4: touch pad channel selector 2nd nibble ? tpchs2[211h]: touch pad channel selector register2 [r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name - - tpen9 tpen8 read/write - - r/w r/w tpen9~tpen8: touch pad channel selector 3rd nibble as program writes the tpchs0 register hardware automatically discharges the external capacitor and enables the sensor clock input until period end. mcks2 ~ mcks0 sam p le time mcks2 ~ mcks0 sam p le time 000 osch/1 100 osch/16 001 osch/2 101 osch/32 010 osch/4 110 osch/64 011 osch/8 111 oscl
preliminar y ttp258 tontouch tm 16?/04/06 page 40 of 44 ver.: 1.2 when tpchs0 is writing, tpctl will be set tp run mode, and touchpad begin to scan touchpad users can enable multi-ch annel by setting correspo nding bit 1, which will turn on all enable cha nnel at the same time. ? tpctl[212h]: touch pad control regist er [r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name - tpctl2 tpctl1 tpctl0 read/write - r/w r/w r/w tpctl2~tpctl0: touch pad control selector as program writes the tpctl register hardware automatically discharges the external capacitor and en ables the sensor clock in put until period end. tp stop: stop the touch pad feature and release pad for io port tp run: tp run is touchpad scan start signal, its scan the channel by tpchs2~0 select. inner key: select switch select inner key. inne r key is reference key, this pad is no bounding to package. discharge: discharge can hold touchpad in discharge state, to avoid discharge time too short. as touch pad analog switch keeps on, the relative io port should be disabled as tri-state by hardware. in user selection table, the availabl e touch pads will be generated a rom code in option rom. channel enable state tpchs0 tpen3~0 tpchs1 tpen7~4 tpchs2 tpen9~8 tp0 0001 0000 00 tp1 0010 0000 00 tp2 0100 0000 00 tp3 1000 0000 00 tp4 0000 0001 00 tp5 0000 0010 00 tp6 0000 0100 00 tp7 0000 1000 00 tp8 0000 0000 01 tp9 0000 0000 10 tpctl2 ~ tpctl0 channel enable state 000 tp stop 001 tp run 010 - 011 discharge 100 inner key 101 - 110 - 111 -
preliminar y ttp258 tontouch tm 16?/04/06 page 41 of 44 ver.: 1.2 ? csa[217h]: select capacity load re gister [r/w], default value [0000] register bit3 bit2 bit1 bit0 bit name csa3 csa2 csa1 csa0 read/write r/w r/w r/w r/w csa3~csa0: select capacity for touch pad csa3 ~csa0 capacity load csa3 ~ csa0 capacity load 0000 0 pf 1000 4.0 pf 0001 0.5 pf 1001 4.5 pf 0010 1.0 pf 1010 5.0 pf 0011 1.5 pf 1011 5.5 pf 0100 2.0 pf 1100 6.0 pf 0101 2.5 pf 1101 6.5 pf 0110 3.0 pf 1110 7.0 pf 0111 3.5 pf 1111 7.5 pf
preliminar y ttp258 tontouch tm 16?/04/06 page 42 of 44 ver.: 1.2 mask option table: all the otp mask option regi ster can open for user to reset the initial value, but should enable the mro. user writes mro addre ss first then changes the target mask option register data. the mro enable will be cleared with other writing address. ? mop0: option register [r/w], default value [0000] mask option bit3 bit2 bit1 bit0 bit name - - - - read/write - - - - ? mop1: pwm start level option register [r/w], default value [0000] mask option bit3 bit2 bit1 bit0 bit name - pwm2s pwm1s pwm0s read/write - r/w r/w r/w ? mop2: int trigger option register [r/w], default value [0000] mask option bit3 bit2 bit1 bit0 bit name int1s1 int1s0 int0s1 int0s0 read/write r/w r/w r/w r/w ? mop3: option register [r/w], default value [0000] mask option bit3 bit2 bit1 bit0 bit name - - - - read/write - - - - ? mop4: lvr power on option register [r/w], default value [0000] mask option bit3 bit2 bit1 bit0 bit name lvren - - - read/write r/w - - - ? mop5: touch pad pin option register [r/w], default value [0000] mask option bit3 bit2 bit1 bit0 bit name - - specio tpnis read/write - - r/w r/w
preliminar y ttp258 tontouch tm 16?/04/06 page 43 of 44 ver.: 1.2 the following table shows the mask option in this chip. all the mask options must be defined clearly and ensure to meet user?s proper function. no. mask option function descriptions +1 pwm0s 0 start 0 1 start 1 +1 pwm1s 0 start 0 1 start 1 +1 pwm2s 0 start 0 1 start 1 +2 int0f trigger type int0s1,int0s0 00 low level trigger 01 falling edge trigger 10 rising edge trigger 11 dual edge trigger +2 int1f trigger type int1s1,int1s0 00 low level trigger 01 falling edge trigger 10 rising edge trigger 11 dual edge trigger +1 tpnis 0 tpni use schmitt trig output signal 1 tpni use comparator output signal +1 lvren select 0 lvren disable 1 lvren enable +1 specio 0 pa0~pa2 is normal io port 1 pa0~pa2 is special function
preliminar y ttp258 tontouch tm 16?/04/06 page 44 of 44 ver.: 1.2 application circuit vdd vss cap pa0~pa2 pb0~pb1 pc0~pc3 pd0~pd3 ldo c1 c2 cs io data out /pwm touch pad package & pad information: ordering form: package type lvren lvr ldo TTP258RD-AOBN 16-sop-a by register 2.2v 2.7v ttp258od-fobn 16-sop-b always on 2.2v 2.7v modified record: body: 2014/05/20 j 1 st version 2015/10/01 j ver. 1.1 (operating voltage) 2016/04/06 j ver. 1.2 (page 8 oscl & test condition i page 20 if oscl=16khz i page 24 e 36 j typical condition)

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