rt9746 ? ds9746-00 march 2016 www.richtek.com 1 ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. applications ? cellular phone ? smart handheld device vbus ovp with a ptvs diode general description the rt9746 is an overvoltage protection devices feature a low 35m (typ) ron internal fet with ptvs diode. the ptvs also protects the devices from surges up to 100v. when the input voltage exceeds the overvoltage threshold, the internal fet is turned off to prevent damage to the protected down stream components. the internal over voltage thresholds (ovp) are preset to 6.8v typical. the rt9746 also feature an over-current protection and up to 4.5a. the rt9746 is offered in a small wl-csp-12b (bsc) package provides small pcb area applications. marking information features ? ? ? ? ? ptvs diode embedded for vbus surge protection ? ? ? ? ? warning indicator for ovp or uvp ? ? ? ? ? 28v maximum rating for dc adapter ? ? ? ? ? integrated over-voltage and over current protection fet on vbus for fault isolation ordering information note : richtek products are : ? rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ? suitable for use in snpb or pb-free soldering processes. pin configurations (top view) wl-csp-12b 1.92x1.27 (bsc) gnd_ ptvs vout gnd vout wrnb gnd_ ptvs vout vin vin ovpfb vin gnd_ ptvs a3 a4 a1 a2 b3 b4 b1 b2 c3 c4 c1 c2 3cw 3c : product code w : date code rt9746wsc package type wsc : wl-csp-12b 1.92x1.27 rt9746 ovp threshold option default : 6.8v a : 11.5v b : 14.5v c : 6.2v rt9746 vout gnd_ptvs vin wrnb ovpfb r2 r1 c in adaptor charger processor vddio gnd c out r3 simplified application circuit
rt9746 2 ds9746-00 march 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram pre- regulator digital control ocp vout ovpfb gnd_ptvs vin por i/o buffer otp uvlo external & internal ovp power fet ovp sel gnd wrnb operation the rt9746 is a vbus ovp protector switch. the ovp function is optimized to protect low voltage system from abnormal high input voltage (up to 28v) in handheld application. rt9746 is also embedded power-tvs diode (ptvs) on vbus pin for surge protection. if surge waveform is above 30v, it will be clamped to 30v due to ptvs diode. when plugging in vbus, the ocp will be soft-start in 8ms in order to reduce in rush current and internal vout deglitch time is 16/32/64/128ms which is set by fuse. the ocp after soft-start is up to 4.5a for high current application. functional pin description pin no pin name pin function a1 gnd common ground of internal circuits. a2, a3, b2 vout output from vbus load-switch. b1 wrnb inverse warning signal (ocp,otp, ovp, uvlo) flag output (open-drain). a4, b4, c4 gnd_ptvs common ground of power tvs diode. b3, c2, c3 vin vbus from power adaptor. c1 ovpfb external ovp adjustment setting. (if no used, be surely tied to gnd)
rt9746 3 ds9746-00 march 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) ? vin, ovpfb ---------------------------------------------------------------------------------------------------------------- ? 0.3v to 28v ? vout ------------------------------------------------------------------------------------------------------------------------- ? 0.3v to 15v ? system level with air discharger, vin, gnd ----------------------------------------------------------------------- 15kv ? system level with contact discharger, vin, gnd ----------------------------------------------------------------- 8kv ? all other inputs ------------------------------------------------------------------------------------------------------------ ? 0.3v to 6v ? power dissipation, p d @ t a = 25 c wl-csp-12b 1.92x1. 27 (bsc ) ---------------------------------------------------------------------------------------- 1.67w ? package thermal resistance (note 2) wl-csp-12b 1.92x1.27 (bsc), ja ---------------------------------------------------------------------------------- 59.6 c/w ? junction temperature ----------------------------------------------------------------------------------------------------- 150 c ? lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c ? storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c ? esd susceptibility (note 3) hbm (human body model) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine model) ----------------------------------------------------------------------------------------------------- 200v cdm (charged device model) ------------------------------------------------------------------------------------------ 2kv ? surge (vin) ----------------------------------------------------------------------------------------------------------------- 100v recommended operating conditions (note 4) ? usb supply input voltage, vin ---------------------------------------------------------------------------------------- 3v to 6.7v ? i/o supply voltage (v ddio ) ---------------------------------------------------------------------------------------------- 1.8v to 3.6v ? vout capacitors ---------------------------------------------------------------------------------------------------------- 1 f to 10 f ? junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c ? ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c electrical characteristics (v in = 5v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit dc characteristics input clamp voltage v in_clamp i in = 10ma, t a = 25c -- 31 -- v vin supply current i vbus_s v bus = 5v, i out = 0ma -- 130 180 ? a vin por threshold only for vout v por rising 2.5 2.7 2.9 v vbus por hysteresis only for vout v por_hys falling -- 100 -- mv deglitch time of por only for vout t por by efuse setting (16/32/64/128ms) -- 32 -- ms ovp threshold voltage v ovp rising rt9746 6.6 6.8 7 v rt9746a 11.15 11.5 11.85 rt9746b 14 14.5 15 rt9746c 6 6.2 6.4
rt9746 4 ds9746-00 march 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. guaranteed by design. parameter symbol test conditions min typ max unit ovp hysteresis v ovp_hys falling -- 150 -- mv ovp propagation delay to turn off vbusout t ovp_pd v bus = 5v to 10v, (6v/ ? s) -- 0.18 0.25 ? s ovp recover delay t ovp_rd v bus = 10v to 5v -- 8 -- ms ocp threshold current i ocp -- 4.5 5 a ocp blanking time t ocp_b -- 180 -- ? s ocp recover delay t ocp_rd -- 64 -- ms otp threshold to turn off only for vbus_out t otp_fet rising (note5) -- 160 -- c otp threshold hysteresis only for vbus_out t otp_fet_hys falling (note5) -- 20 -- c otp recover delay t otd_rd -- 8 -- ms ocp soft-start time tss -- 8 -- ms fet on resistance r on_fet i bus_out = 1000ma, v bus = 5v t a = 25c -- 35 42 m ? external ovp set threshold v ref_ext -- 1.2 -- v external ovp adjustment range v ovp_ext 4 -- 20 v external ovp select threshold (rising) v ovp_sel -- 0.3 -- v external ovp select threshold hysteresis -- 100 -- mv wrnb open-drain impedance v bus = 5v -- -- 15 ?
rt9746 5 ds9746-00 march 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit rt9746 a2, a3, b2 vout gnd_ptvs vin b1 b3, c2, c3 wrnb ovpfb c1 r2 r1 0.1f adaptor 1f charger processor vddio gnd a4, b4, c4 a1 c in c out r3
rt9746 6 ds9746-00 march 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics input supply current vs. supply voltage 80 90 100 110 120 130 140 150 160 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 supply voltage (v) input supply current ( a ) 85 c 25 c ? 40 c input supply current vs. temperature 120 125 130 135 140 145 150 -50 -25 0 25 50 75 100 125 150 temperature (c) input supply current ( a) 1 v in = 5v normalized v ovp vs. temperature 0.94 0.96 0.98 1.00 1.02 1.04 1.06 -50 -25 0 25 50 75 100 125 150 temperature (c) normalized v ovp normalized r ds(on) vs. output current 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 00.511.5 22.53 output current (a) normalized r ds(on) v in = 5v normalized r ds(on) vs. temperature 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -50 -25 0 25 50 75 100 125 150 temperature (c) normalized r ds(on) v in = 5v, i out = 1a time (5ms/div) power up v out (2v/div) v in (2v/div) v in = 5v, i out = 0a, c l = 100 f
rt9746 7 ds9746-00 march 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (10 s/div) 80v surge with rt9746 v in (20v/div) time (10 s/div) 80v surge without rt9746 v in (20v/div) time (5ms/div) power up v out (2v/div) v in (2v/div) v in = 5v, i out = 0a, c l = 1000 f
rt9746 8 ds9746-00 march 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information power up the rt9746 has a threshold of 2.7v power on reset (por) with a built-in hysteresis of 100mv. before the input voltage reaches the por threshold, the rt9746 is off. when the input voltage is over the por threshold, the vout of rt9746 will delay for 32ms which includes soft-start time of 8ms. the 32ms delay allows the transient at the input during a hot insertion of the power supply to settle down before the ic starts to operate. during the soft-start transition, the rt9746 slowly turns on the internal mosfet to reduce the inrush current. over temperature protection (otp) the rt9746 monitors its internal temperature to prevent thermal failures. the chip turns off the mosfet when the junction temperature reaches 160 c. the ic will resume after the junction temperature is cooled down 20 c. input over-voltage protection the rt9746 provides input over-voltage protection via internal or external resistor to set ovp level. if ovpfb is connected to gnd, the rt9746 uses the internal ovp level setting. if an external resistor-divider is connected to ovpfb and v ovpfb exceeds the vovp_sel voltage, the rt9746 will adopt external ovp level setting. the ovp level vovp is set as below. ?? ?? ?? ovp ref_ext r2 v = v x 1+ r1 when the input volatge exceeds the ovp level, the rt9746 will turn off internal mosfet around 0.18us to prevent the high input volatge from damaging the end system. when the input volatge returns to normal operation volatge range with hysteresis (internal 150mv, external 100mv), the rt9746 will turn on the mosfet to re-enable output. over-current protection (ocp) the rt9746 monitors the output current to prevent the output short or the charging of the battery with an excessive current. the rt9746 has a built-in 180 s delay time to prevent any transient noise triggering the ocp. if the ocp situation keeps for 180 s, the internal mosfet will be turned off. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for wl-csp-12b 1.92x1.27 (bsc) package, the thermal resistance, ja , is 59.6 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (59.6 c/w) = 1.67w for wl-csp-12b 1.92x1.27 (bsc) package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curve in figure 1 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
rt9746 9 ds9746-00 march 2016 www.richtek.com ? copyright 2016 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. 0.0 0.4 0.8 1.2 1.6 2.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb figure 1. derating curve of maximum power dissipation
rt9746 10 ds9746-00 march 2016 www.richtek.com richtek technology corporation 14f, no. 8, tai yuen 1 st street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. outline dimension wl-csp-12b 1.92x1.27 (bsc) min. max. min. max. a 0.500 0.600 0.020 0.024 a1 0.170 0.230 0.007 0.009 b 0.240 0.300 0.009 0.012 d 1.220 1.320 0.048 0.052 d1 e 1.870 1.970 0.074 0.078 e1 e symbol dimensions in millimeters dimensions in inches 0.800 0.031 1.200 0.047 0.400 0.016
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