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| 1. features ? a single chip solution integrates 100/10 base-t fast ethernet mac, phy and pmd. ? microsoft pc97, 98, 99 and novell 4.11/5.0 certified. ? support dmi 2.0 management. ? support intel pxe remote boot device. ? fully comply to ieee 802.3u specification ? operates over 100 meters of stp and category 5 utp cable ? fully comply to pci spec. 2.1 with clock frequency up to 33mhz ? fully comply to advanced configuration and power interface (acpi) rev 1.1 ? fully comply to pci bus power management inter- face spec. rev 1.1 ? support full and half duplex operations in both 100 base-tx and 10 base-t mode ? supports 3 kinds of wake up events defined in net- work device class power management spec 1.0. including: - magic packet tm - link change(link-on) - wake up frame ? supports ieee802.3x frame based flow control scheme in full duplex mode. ? supports early interrupt on both transmit and receive operations. ? 100/10 base-t nway auto negotiation function ? large on-chip fifos for both transmit and receive operations without external local memory ? bus master architecture with linked host buffers deliv- ers the most optimized performance ? 32-bit bus master dma channel provides ultra low cpu utilization, best fit in server and windows appli- cation. ? proprietary adaptive network throughput control (antc) technology to optimize data integrity and throughput ? support up to 64k bytes boot rom interface ? three levels of loopback diagnositic capability ? support a variety of flexible address filtering modes with 16 cam address and 128 bits hash ? microwire interface to eeprom for customer's ids and configuration data ? single +5v power supply, cmos technology, 128-pin pqfp package/lqpf package ( magic packet technology is a trademark of advanced micro de- vice corp. ) 2. general descriptions the MX98715aec-e controller is an ieee802.3u com- pliant single chip 32-bit full duplex, 10/100mbps highly integrated fast ethernet combo solution, designed to address high performance local area networking (lan) system application requirements. MX98715aec-e's pci bus master architecture delivers the optimized performance for future high speed and powerful processor technologies. in other words, the MX98715aec-e not only keeps cpu utilization low while maximizing data throughput, but it also optimizes the pci bandwidth providing the highest pci bandwidth uti- lization. to further reduce maintenance costs the MX98715aec-e uses drivers that are backward com- patible with the original mxic mx98713 series control- lers. the MX98715aec-e contains a pci local bus glueless interface, a direct memory access (dma) buffer man- agement unit, an ieee802.3u-compliant media access controller (mac), large transmit and receive fifos, and an on-chip 10 base-t and 100 base-tx transceiver simplifying system design and improving high speed sig- nal quality. full-duplex operation are supported in both 10 base-t and 100 base-tx modes that increases the controller's operating bandwidth up to 200mbps. equipped with intelligent ieee802.3u-compliant auto-ne- gotiation, the MX98715aec-e-based adapter allows a single rj-45 connector to link with the other ieee802.3u- compliant device without re-configuration. in MX98715aec-e, an innovative and proprietary de- sign "adaptive network throughput control" (antc) is built-in to configure itself automatically by mxic's driver based on the pci burst throughput of different pcs. with this proprietary design, MX98715aec-e can always optimize its operating bandwidth, network data integrity and throughput for different pcs. the MX98715aec-e features remote-power-on and re- mote-wake-up capability and is compliant with the ad- vanced configuration and power interface version 1.0 1 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e single chip fast ethernet nic controller - enhanced version advanced information
2 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 3. pin configurations (acpi). this support enables a wide range of wake-up capabilities, including the ability to customize the con- tent of specified packet which pc should be responded to, even when it is in a low-power state. pcs and work- stations could take advantage of these capabilities of being waked up and served simultaneously over the net- work by remote server or workstation. it helps organi- zations reduce their maintenance cost of pc network. the 32-bit multiplexed bus interface unit of MX98715aec-e provides a direct interface to a pci lo- cal bus, simplifing the design of an ethernet adapter in a pc system. with its on-chip support for both little and big endian byte alignment, MX98715aec-e can also ad- dress non-pc applications. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 bpa4 bpa3 bpa2 bpa1(eedi) bpa0(eeck) eecs bpd0(eed0) bpd1 bpd2 bpd3 bpd4 bpd5 bpd6 bpd7 gnd vdd ad0 ad1 gnd ad2 ad3 vdd ad4 ad5 gnd ad6 vdd gnd gnd vdd gnd vcc gnd pmeb intab rstb pciclk gntb reqb ad31 ad30 gnd ad29 ad28 vdd ad27 gnd ad26 ad25 gnd ad24 cbeb3 idsel gnd ad23 ad22 gnd ad21 ad20 vdd ad19 ad18 gnd ad17 ad16 cbeb2 frameb gnd irdyb trdyb devselsb stopb vdd perrb serrb pa r cbeb1 ad15 gnd ad14 ad13 vdd ad12 ad11 ad10 gnd ad9 ad8 cbeb0 ad7 rtx rtx2eq nc gnd txop txon vdd gnd gnd vdd rxip rxin vdd gnd vdd gnd gnd ckref/xi vdd rda gnd vdd led1 led0 bpa15 bpa14 bpa13 gnd vdd bpa12 bpa11 bpa10 bpa9 boeb bpa8 bpa7 bpa6 bpa5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 MX98715aec-e 3 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 4. pin description ( 128 pin pqfp ) ( t/s : tri-state, s/t/s : sustended tri-state, i : input, o : output, o/d : open drain ) pin name type pin no 128 pin function and driver ad[31:0] t/s 116, 117 pci address/data bus: shared pci address/data bus lines. little or big endian 119,120, byte ordering are supported. 122,124, 125,127, 3,4,6,7,9, 10,12,13, 26,28,29, 31-33,35, 36,38,39, 41,42,44, 45,47,48 cbe[3:0] t/s 128,14 pci command and byte enable bus: shared pci command byte enable bus, 25,37 during the address phase of the transaction, these four bits provide the bus command. during the data phase, these four bits provide the byte enable. frameb s/t/s 15 pci frameb signal: shared pci cycle start signal, asserted to indicate the beginning of a bus transaction. as long as frameb is asserted, data transfers continue. trdyb s/t/s 18 pci target ready: issued by the target agent, a data phase is completed on the rising edge of pciclk when both irdyb and trdyb are asserted. irdyb s/t/s 17 pci master ready: indicates the bus master's ability to complete the current data phase of the transaction. a data phase is completed on any rising edge of pciclk when both irdyb and trdyb are asserted. devselb s/t/s 19 pci slave device select: asserted by the target of the current bus access. when 98715a is the initiator of current bus access, the target must assert devselb within 5 bus cycles, otherwise cycle is aborted. idsel i 1 pci initialization device select: target specific device select signal for configuration cycles issued by host. pciclk i 113 pci bus clock input: pci bus clock range from 16mhz to 33mhz. rstb i 112 pci bus reset: host system hardware reset. pmeb o 110 power management event:when low indicating a power management event occures, such as detection of a magic packet, a wake up frame, or link change. intab o/d 111 pci bus interrupt request signal: wired to intab line. serrb o/d 23 pci bus system error signal: if an address parity error is detected and cfcs bit 8 is enabled, serrb and cfcs's bit 30 will be asserted. perrb s/t/s 22 pci bus data error signal: as a bus master, when a data parity error is detected and cfcs bit 8 is enabled, cfcs bit 24 and csr5 bit 13 will be asserted. as a bus target, a data parity error will cause perrb to be asserted. 4 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e pin name type pin no 128 pin function and driver par t/s 24 pci bus parity bit: shared pci bus even parity bit for 32 bits ad bus and cbe bus. stopb s/t/s 20 pci target requested transfer stop signal: as bus master, assertion of stopb cause MX98715aec-e either to retry, disconnect, or abort. reqb t/s 115 pci bus request signal: to initiate a bus master cycle request gntb i 114 pci bus grant acknowledge signal: host asserts to inform MX98715aec-e that access to the bus is granted bpa1 o 61 boot prom address bit 1(eecs=0): together with bpa[15:0] to access (eedi) external boot prom up to 256kb. eeprom data in(eecs=1): eeprom serial data input pin. bpa0 o 60 boot prom address bit 0(eecs=0): together with bpa[15:0] to access (eeck) external boot prom up to 256kb. eeprom clock(eecs=1): eeprom clock input pin bpa[15:0] o 78-76, 73-70, boot prom address line. 68-60 bpd0 t/s 58 boot prom data line 0(eecs=0): boot prom or flash data line 0. (eedo) eeprom data out(eecs=1): eeprom serial data outpin(during reset initialization). bpd[7:0] t/s 51-58 boot prom data lines: boot prom or flash data lines 7-0. eecs o 59 eeprom chip select pin. boeb o 69 boot prom output enable. rda o 83 connecting an external resistor to ground, resistor value=10k ohms rtx o 102 connecting an external resistor to ground, resistor value=560 ohms rtx2eq o 101 connecting an external resistor to ground, resister value=1.4k ohms nc i 100 no connection. rxip i 92 twisted pair receive differential input: support both 10 base-t and 100 base-tx receive differential input. rxin i 91 twisted pair receive differential input: support both 10 base-t and 100 base-tx receive differential input txop o 98 twisted pair transmit differential output: support both 10 base-t and 100 base-tx transmit differential output txon o 97 twisted pair transmit differential output: support both 10 base-t and 100 base-tx transmit differential output xi/ckref i 85 reference clock: 25mhz oscillator clock input. for crystal application, this pin is xi. led0 o 79 programmable led pin 0: csr9.28=1 set the led as link speed (10/100) led. csr9.28=0 set the led as activity led. default is activity led after reset. 5 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e pin name type pin no 128 pin function and driver led1 o 80 programmable led pin 1: csr9.29=1 set the led as link/activity led. csr9.29=0 set the led as good link led. default is good link led after reset. vdd i 8,21,30,43, power pins. 49,74,81,84, 88,90,93,96, 103,106,108, 121 gnd i 2,5,11,16,27 ground pins. 34,40,46,50 75,82,86,87 89,94,95,99 104,105,107 109,118,123, 126 6 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5. programming interface 5.1 pci configuration registers: 5.1.1 pci id register ( pfid ) ( offset 03h-00h ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 device id (bit 31:16) vendor id (bit 15:0) 5.1.2 pci command and status register ( pfcs ) ( offset 07h-04h ) the bit content will be reset to 0 when a 1 is written to the corresponding bit location. bit 0 : io space access, set to 1 enable io access bit 1 : memory space access, set to 1 to enable memory access bit 2 : master operation, set to 1 to support bus master mode bit 5-3 : not used bit 6 : parity error response, set to 1 to enable assertion of csr<13> bit if parity error detected. bit 7 : not used bit 8 : system error enable, set to 1 to enable serr# when parity error is detected on address lines and cbe[3:0]. bit 20 : new capability. set to support pci power management. bit 22-bit19 : not used bit 23 : fast back-to back, always set to accept fast back-to-back transactions that are not sent to the same bus device. this register can be loaded from external serial eeprom or use a mxic preset value of "10d9" and "0531" for vendor id and device id respectively. word location 3eh and 3dh in serial eeprom are used to configure customer's vendor id and device id respectively. if location 3eh contains"ffff" value then mxic'svendor id and device id will be set in this register, otherwise both 3eh and 3dh will be loaded into this register from serial eeprom. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 detect party error signal system error data parity report new capability receive master abort receive target abort device select timing fast back-to-back system error enable parity error response master operation memory space access io space access 7 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.1.3 pci revision register ( pfrv ) ( offset 0bh-08h ) bit 3 - 0 : step number, range from 0 to fh. bit 7 - 4 : revision number, fixed to 2h for MX98715aec-e bit 15 - 8 : not used bit 23 - 16 : subclass, fixed to 0h. bit 31 - 24 : base class, fixed to 2h. 5.1.4 pci latency timer register ( pflt ) (offset 0fh-0ch) bit 0 - bit 7 : system cache line size in units of 32 bit word, device driver should use this value to program csr0<15:14>. bit 8 - bit 15 : configuration latency timer, when MX98715aec-e assert frame#, it enables its latency timer to count. if MX98715aec-e deasserts frame# prior to timer expiration, then timer is ignored. otherwise, after timer expires, MX98715aec-e initiates transaction termination as soon as its gnt# is deasserted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base class step number subclass revision number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 configuration latency timer system cache line size pflt register (0fh-0ch) bit 24:data parity report, is set to 1 only if perr# active and pfcs<6> is also set. bit 26-25:device select timing of devselb pin. bit 27:not used bit 28:receive target abort, is set to indicate a transaction is terminated by a target abort. bit 29:receive master abort, is set to indicate a master transaction with master abort. bit 30:signal system error, is set to indicate assertion of serr#. bit 31:detected parity error, is set whenever a parity error detected regardless of pfcs<6>. 8 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.1.5 pci base io address register ( pbio ) ( offset 13h-10h ) bit 0 : io/memory space indicator, fixed to 1 in this field will map into the io space. this is a read only field. bit 7 - 1 : not used, all 0 when read bit 31 - 8 : defines the address assignment mapping of MX98715aec-e csr registers. 5.1.6 pci base memory address register ( pbma ) ( offset 17h-14h ) bit 0 : memory space indicator, fixed to 0 in this field will map into the memory space. this is a read only field. bit 6 - 1 : not used, all 0 when read bit 31 - 7 : defines the address assignment mapping of MX98715aec-e csr registers. 5.1.7 pci subsystem id register ( psid ) ( offset 2ch-2fh ) this register is used to uniquely identify the add-on board or subsystem where the nic controller resides. values in this register are loaded directly from external serial eeprom after system reset automatically. word location 36h of eeprom is subsystem vendor id and location 35h is sub-system id. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 configuration base memory address memory spec indicator 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 subsystem id (31:16) subsystem vendor id (bit 15:0) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 configuration base io address io/memory spec indicator 9 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.1.8 pci base expansion rom address register ( pber ) ( offset 33h-30h ) bit 0 : address decode enable, decoding will be enabled if only both enable bit in pfcs<1> and this expansion rom register are 1. bit 10 - 1 : not use bit 31 - 11 : defines the upper 21 bits of expansion rom base address. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 expansion rom base address (upper 21 bit) address decode enable 0 0 0 0 0 0 0 5.1.10 interrupt register ( pfit ) ( offset 3fh-3ch ) bit 7 - 0 : interrupt line, system bios will writes the routing information into this field, driver can use this information to determine priority and interrupt vector. bit 15 - 8 : interrupt pin, fixed to 01h which use inta#. bit 31 - 24 : max_lat which is a maximum period for a access to pci bus. bit 23 - 16 : min_gnt which is the maximum period that MX98715aec-e needs to finish a brust pci cycle. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 min-gnt interrupt pin max_lat 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 interrupt line 5.1.9 pci capability pointer register ( pfcp ) ( offset 37h-34h ) bit 7- 0 : capability pointer (cap_ptr) is set to 44h if pmeb is connected to pci bus, otherwise 00. bit 31- 8 : reserved 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 capability pointer (set to 44h) 10 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.1.11 pci driver area register ( pfda ) ( 43h-40h ) bit 29 : board type bit 15 - 8 : driver is free to read and write this field for any purpose. bit 7 - 0 : not used. 5.1.12 pci power management capability register ( ppmc ) ( 47h-44h ) bit 31- 27 : pme_support, read only indicates the power states in which the function may assert lanwake pin. bit 31 ---- pme_d3cold (value=1) bit 30 ---- pme_d3warm (value=1) bit 29 ---- pme_d2 (value=1) bit 28 ---- pme_d1 (value=1) bit 27 ---- pme_d0 (value=1) bit 26 : d2 mode support, read only, set to 1. bit 25 : d1 mode support, read only, set to 1. bit 24-22 : aux_i bits. auxiliary current field, set to 100. bit 21 : dsi, read only, set to 0. bit 20 : auxiliary power source, set to 1. this bit only valid when bit 15 is a '1'. bit 19 : pme clock, read only, set to 0. bit 18-16 : pci power management version, set to 001, read only. bit 15-8 : next pointer, all bits set to 0. bit 7-0 : capability id, read only, a 1 indicates that the data structure currently being pointed to is the pci power managment data structure. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 d2_support d1_support pme_support 0 0 0 0 0 0 0 0 aux_i dsi auxiliary power source pme clock version next pointer capability id 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 board type driver special use 11 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.1.13 pci power management command and status register ( ppmcsr ) ( 4bh-48h ) bit 1-0 : power_state, read/write, d0 mode is 00, d1 mode is 01, d2 mode is 10, d3 hot mode is 11. bit7-2 : all 0. reserved. bit8 : pme_en, set 1 to enable lanwake. set 0 to disable lanwake assertion. bit 12-9 : data_select for report in the data register located at bit 31:24. bit 14-13 : data_scale, read only. bit 15 : pme_status independent of the state of pme_en. when set, indicates a assertion of lanwake pin. (support d3 cold). write 1 to clear the lanwake signal. write 0, no effect. bit 21-16 : reserved. bit 22 : b2_b3#, b2_b3 support for d3 hot, meaningful only if bpcc_en = 1, read only. bit 23 : bpcc_en, bus power/clock control enable, read only. bit 31-24 : data, read only. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bridge extension support pme_status data data_scale data_select pme_en reserved power state 0 0 0 0 0 0 12 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2 host interface registers MX98715aec-e csrs are located in the host i/o or memory address space. the csrs are double word aligned and 32 bits long. definitions and address for all csrs are as follows : csr mapping register meaning offset from csr base address ( pbio and pbma ) csr0 bus mode 00 csr1 tr ansmit poll demand 08h csr2 receive poll demand 10h csr3 receive list demand 18h csr4 tr ansmit list base address 20h csr5 interrupt status 28h csr6 operation mode 30h csr7 interrupt enable 38h csr8 missed frame counter 40h csr9 serial rom and mii management 48h csr10 reserved 50h csr11 general purpose timer 58h csr12 10 base-t status port 60h csr13 sia reset register 68h csr14 10 base-t control port 70h csr15 w atchdog timer 78h csr20 auto compensation a0h csr21 flow control register a8h csr22 mac id byte 3-0 b0h csr23 magic id 5, 4 / mac id byte 5, 4 b8h csr24 magic id byte 3-0 c0h csr25 filter 0 byte mask c8h csr26 filter 1 byte mask d0h csr27 filter 2 byte mask d8h csr28 filter 3 byte mask e0h crs29 filter offset e8h csr30 filter 1&0 crc-16 f0h csr31 filter 3&2 crc-16 f8h 13 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.1 bus mode register ( csr0 ) field name description 0 swr software reset, when set, MX98715aec-e resets all internal hardware with the exception of the configuration area and port selection. 1 bar0 internal bus arbitration scheme between receive and transmit processes. the receive channel usually has higher priority over transmit channel when receive fifo is partially full to a threshold. this threshold can be selected by programming this bit. set for lower threshold, reset for normal threshold. 6:2 dsl descriptor skip length, specifies the number of longwords to skip between two descrip- tors. 7 ble big/little endian, set for big endian byte ordering mode, reset for little endian byte order- ing mode, this option only applies to data buffers 13:8 pbl programmable burst length, specifies the maximum number of longwords to be trans- ferred in one dma transaction. default is 0 which means unlimited burst length, possible values can be 1,2,4,8,16,32 and unlimited . 15:14 cal cache alignment, programmable address boundaries of data burst stop, MX98715aec-e can handle non-cache- aligned fragement as well as cache-aligned fragment efficiently. 18:17 tap tr ansmit auto-polling time interval, defines the time interval for MX98715aec-e to per- forms transmit poll command automatically at transmit suspended state. 21 rme pci memory read multiple command enable, indicates bus master may intend to fetch more than one cache lines disconnecting. 23 rle pci memory read line command enable, indicating bus master intends to fetch a com- plete cache line. 24 wle pci memory write and invalidate command enable, guarantees a minimum transfer of one complete cache. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tap-transmit automatic polling wie-write and invalidate enable rle-read line enable rme-read multiple enable zero-must be zero dsl-descriptor skip length swr-software reset cal-cache alignment pbl-programmable burst length ble-big/little endian bar0-bus arbitration bit 0 14 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.2 transmit poll command ( csr1 ) field name description 31:0 tpc w rite only, when written with any value, MX98715aec-e read transmit descriptor list in host memory pointed by csr4 and processes the list. 5.2.3 receive poll command ( csr2 ) field name description 31:0 rpc wr ite only, when written with any value, MX98715aec-e read receive descriptor list in host memory pointed by csr3 and processes the list. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 transmit poll command 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 receive poll command table 5.2.0 transmit auto polling bits csr<18:17> time interval 00 no transmit auto-polling, a write to csr1 is required to poll 01 auto-poll every 200 us 10 auto-poll every 800 us 11 auto-poll every 1.6 ms 15 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.4 descriptor list address ( csr3, csr4 ) csr3 receive list base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 start of receive list address csr4 transmit list base address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 start of transmit list address 16 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.5 status register ( csr5 ) field name description 28 wkupi wake up event interrupt. valid only if csr16<22> bit is set. 27 lc 100 base-tx link status has changed either from pass to fail or fail to pass. read csr12<1> for 100 base-tx link status. 25:23 eb error bits, read only, indicating the type of error that caused fatal bus error. 22:20 ts transmit process state, read only bits indicating the state of transmit process. 19:17 rs receive process state, read only bits indicating the state of receive process. 16 nis normal interrupt summary, is the logical or of csr5<0>, csr5<2> and csr5<6> and csr5<28>. 15 ais abnormal interrupt summary, is the logical or of csr5<1>, csr5<3>, csr5<5>, csr5<7>, csr5<8>, csr5<9>, car5<10>, csr5<11> and csr5<13>, csr5<27>. 14 eri early receive interrupt, indicating the first buffer has been filled in ring mode, or 64 bytes has been received in chain mode. 13 fbe fatal bus error, indicating a system error occured, MX98715aec-e will disable all bus access. 12 lf link fail, indicates a link fail state in 10 base-t port. this bit is valid only when csr6<18>=0, csr14<8>=1, and csr13<3>=0. 11 gte general purpose timer expired, indicating csr11 counter has expired. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rs-receive process state nis-normal interrupt summary lf-link fail eti-early transmit interrupt ais-abnormal interrupt summary eri-early receive interrupt fbe-fatal bus error gte-general purpose timer expired wkupi-wake up event interrupt lc-link change rps-receive process stopped ri-receive interrupt eb-error bits ts-transmit process state rwt-receive watchdog timeout ru-receive buffer unavailable lpanci-link pass/autonegotiation completed interrupt unf-transmit underflow tjt-transmit jabber timeout tu-transmit buffer unavailable tps-transmit process stopped ti-transmit interrupt 17 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e field name description 10 eti early transmit interrupt, indicating the packet to be transmitted was fully transferred to internal tx fifo. csr5<0> will automatically clear this bit. 9 rwt receive watchdog timeout, reflects the network line status where receive watchdog timer has expired while the other node is still active on the network. 8 rps write only, when written with any value, MX98715aec-e reads receive descriptor list in host memory pointed by csr4 and processes the list. 7 ru receive buffer unavailable, the receive process is suspended due to the next descriptor in the receive list is owned by host. if no receive poll command is issued, the reception process resumes when the next recognized incoming frame is received. 6 ri receive interrupt, indicating the completion of a frame reception. 5 unf transmit underflow, indicating transmit fifo has run empty before the completion of a packet transmission. 4 lpanci when autonegotiation is not enabled ( csr14<7>=0 ), this bit indicates that the 10 base-t link integrity test has completed successfully, after the link was down. this bit is also set as as a result of writing 0 to csr14<12> ( link test enable ). when autonegotiation is enabled ( csr14<7> =1 ) , this bit indicates that the autonegotiation has completed ( csr12<14:12>=5 ). csr12 should then be read for a link status report. this bit is only valid when csr6<18>=0, i.e. 10 base-t port is selected link fail interrupt ( csr5<12> ) will automatically clears this bit. 3 tjt transmit jabber timeout, indicating the MX98715 has been excessively active. the transmit process is aborted and placed in the stopped state. tdes0<1> is also set. 2 tu transmit buffer unavailable, transmit process is suspended due to the next descriptor in the transmit list is owned by host. 1 tps transmit process stopped. 0 ti transmit interrupt. indicating a frame transmission was completed. 18 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e table 5.2.1 fatal bus error bits csr5<25:23> process state 000 parity error for either serr# or perr#, cleared by software reset. 001 master abort 010 target abort 011 reserved 1xx reserved table 5.2.2 transmit process state csr5<22:20> process state 000 stopped- reset or transmit jabber expired. 001 fetching transmit descriptor 010 waiting for end of transmission 011 filling transmit fifo 100 reserved 101 setup packet 110 suspended, either fifo underflow or unavailable transmit descriptor 111 closing transmit descriptor table 5.2.3 receive process state csr5<19:17> process state 000 stopped- reset or stop receive command. fetching receive descriptor 010 checking for end of receive packet 011 waiting for receive packet 100 suspended, receive buffer unavailable 101 closing receive descriptor 110 purging the current frame from the receive fifo due to unavailable receive buffer 111 queuing the receive frame from the receive fifo into host receive buffer 19 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.6 operation mode register ( csr6 ) field name description 24 scr scrambler mode, default is set to enable scrambler function. not affected by software reset. 23 pcs default is set to enable pcs functions. csr6<18> must be set in order to operate in symbol mode. 22 ttm transmit threshold mode, set for 10 base-t and reset for 100 base-tx. 21 sf store and forward, when set, transmission starts only if a full packet is in transmit fifo. the threshold values defined in csr6<15:14> are ignored 19 hbd heartbeat disable, set to disable sqe function in 10 base-t mode. 18 ps port select, deafult is 0 which is 10 base-t mode, set for 100 base-tx mode. a software reset does not affect this bit. 17 coe collision offset enable, set to enable a modified backoff algorithm during low collision situation, reset for normal backoff algorithm. 15:14 tr threshold control bits, these bits controls the selected threshold level for MX98715a- e's transmit fifo, transmission starts when frame size within the transmit fifo is larger than the selected threshold. full frames with a length less than the threshold are also transmitted. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 coe-collision offset enable fc-force collision mode lom-loopback operation mode tr-threshold control bits st-start/stop transmission command ttm-transmit threshold mode sf-store and forward pr-promiscuous mode hbd-hearbeat disable ps-port select fd-full duplex mode pm-pass all multicast sb-start/stop backoff counter if-inverse filtering pb-pass bad frame ho-hash-only filtering mode sr-start/stop receive hp-hash/perfect receive filtering mode pcs-pcs function scr-scrambler mode 20 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e field name description 13 st start/stop transmission command, set to place transmission process in running state and will try to transmit current descriptor in transmit list. when reset, transmit process is placed in stop state. 12 fc force collision mode, used in collision logic test in internal loopback mode, set to force collision during next transmission attempt. this can result in excessive collision reported in tdes0<8> if 16 or more collision. 11:10 lom loopback operation mode, see table 5.2.6. 9 fd full-duplex mode, set for simultaneous transmit and receive operation, heart beat check is disabled, tdes0<7> should be ignored, and internal loopback is not allowed. this bit controls the value of bit 6 of link code word . 7 pm pass all multicast, set to accept all incoming frames with a multicast destination address are received. incoming frames with physical address are filtered according to the csr6<0> bit. 6 pr promiscuous mode, any incoming valid frames are accepted, default is reset and not affected by software reset. 5 sb start/stop backoff counter, when reset, the backoff timer is not affected by the network carrier activity. otherwise, timer will start counting when carrier drops. 4 if inverse filtering, read only bit, set to operate in inverse filtering mode, only valid during perfect filtering mode. 3 pb pass bad frames, set to pass bad frame mode, all incoming frames passed the address filtering are accepted including runt frames, collided fragments, truncated frames caused by fifo overflow. 2 ho hash-only filtering mode , read only bit, set to operate in imperfect filtering mode for both physical and multicast addresses. 1 sr start/stop receive, set to place receive process in running state where descriptor acquisition is attempted from current position in the receive list. reset to place the receive process in stop state. 0 hp hash/perfect receive filtering mode, read only bit, set to use hash table to filter multicast incoming frames. if csr6<2> is also set, then the physical addresses are imperfect address filtered too. if csr6<2> is reset, then physical addresses are perfect address filtered, according to a single physical address as specified in setup frame. 21 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e table 5.2.4 transmit threshold csr6<21> csr6<15:14> csr6<22>=0 csr6<22>=1 (threshold bytes) (for 100 base-tx) (for 10 base-t) 0 00 128 72 0 01 256 96 0 10 512 128 0 11 1024 160 1 xx ( store and forward ) table 5.2.5 data port selection csr14<7> csr6<18> csr6<22> csr6<23> csr6<24> port 1 0 x x 1 nway auto-negotiation 0 0 1 x 0 10 base-t 0 1 0 1 x 100 base-tx table 5.2.6 loopback operation mode csr6<11:10> operation mode 00 normal 01 internal loopback at fifo port 11 internal loopback at the phy level 10 external loopback at the pmd level table 5.2.7 filtering mode csr6<7> csr6<6> csr6<4> csr6<2> csr6<0> filtering mode 0 0 0 0 0 16 perfect filtering 0 0 0 0 1 128-bit hash + 1 perfect filtering 0 0 0 1 1 128-bit hash for multicast and physical addresses 0 0 1 0 0 inverse filtering x 1 0 0 x promiscuous 0 1 0 1 1 promiscuous 1 0 0 0 x pass all multicast 1 0 0 1 1 pass all multicast 22 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.7 interrupt mask register ( csr7 ) field name description 28 wkupie wake up event interrupt enable, enables csr5<28>. 27 lce link changed enable, enables csr5<27>. 16 nie normal interrupt summary enable, set to enable csr5<0>, csr5<2>, csr5<6>. 15 aie abnormal interrupt summary enable, set to enbale csr5<1>, csr5<3>, csr5<5>, csr5<7>, csr5<8>, csr5<9>, csr5<11> and csr5<13>. 14 erie early receive interrupt enable 13 fbe fatal bus error enable, set together with with csr7<15> enables csr5<13>. 12 lfe link fail interrupt enable, enables csr5<12> 11 gpte general purpose timer enable, set together with csr7<15> enables csr5<11>. 10 etie early transmit interrupt enable, enables csr5<10> 9 rwe receive watchdog timeout enable, set together with csr7<15> enables csr5<9>. 8 rse receive stopped enable, set together with csr7<15> enables csr5<8>. 7 rue receive buffer unavailable enable, set together with csr7<15> enables csr5<7>. 6 rie receive interrupt enable, set together with csr7<16> enables csr5<6>. 5 une underflow interrupt enable, set together with csr7<15> enables csr5<5>. 4 lpancie link pass/autonegotiation completed interrupt enable 3 tje transmit jabber timeout enable, set together with csr7<15> enables csr5<3>. 2 tue transmit buffer unavailable enable, set together with csr7<16> enables csr5<2>. 1 tse transmit stop enable, set together with csr7<15> enables csr5<1>. 0 tie transmit interrupt enable, set together with csr7<16> enables csr5<0>. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nie-normal interrupt summary enable fbe-fatal bus error enable lfe-link fail enable aie-abnormal interrupt summary enable erie-early receive interrupt enable etie-early transmit interrupt enable rie-receive interrupt enable rwe-receive watchdog enable rse-receive stopped enable gpte-general-purpose timer enable rue-receive buffer unavailable enable une-underflow interrupt enable lpancie-link pass /nway complete interrupt enable tje-transmit jabber timeout enable tue-transmit buffer unavailable enable tse-transmit stopped enable tie-transmit interrupt enable lce-link changed enable wkupie-wake up event interrupt enable 23 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.8 missed frame counter ( csr8 ) field name description 16 mfo missed frame overflow, set when missed frame counter overflows, reset when csr8 is read. 15:0 mfc missed frame counter, indicates the number of frames discarded because no host receive descriptors were available. 5.2.9 non-volatile memory control register ( csr9 ) field name description 31 led3sel 0:def ault value. set led3 as rx led. 1:set led3 as f/h duplex led. (led3 is not bonded to pin) 30 led2sel 0: def ault value. set led2 as speed led. 1: set led2 as collision led (led2 is not bonded to pin) 29 led1sel 0:def ault value. set led1 as good link led. 1: set led1 as link/activity led. 28 led0sel 0:default value. set led0 as activity led. 1: set led0 as link speed (10/100) led. 24 *led4sel 0: def ault value. set led4 as collison led. 1: set led4 as pmeb led. (led4 is not bonded to pin) 14 rd boot rom read operation when boot rom is selected. 26:25 wkfact wake up frame catenation option bits. crs21<4> csr<26> csr<25> wake up event 0 x x ch0+ch1+ch2+ch3 1 0 0 (ch0.ch1)+(ch2.ch3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 missed frame overflow missed frame counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 br-boot rom select data-boot rom data or serial rom control led1sel led4sel led2sel led3sel led0sel wkfcat rd-read operation reload sr-serial rom select 24 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.10 general purpose timer ( csr11 ) field name description 16 con when set,the general purpose timer is in continuous operating mode. when reset, the timer is in one-shot mode. 15:0 timer value contains the timer value in a cycle time of 204.8us. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 con-continuous mode timer value 1 0 1 (ch0.ch1)+ch2+ch3 1 1 0 (ch0.ch1.ch2)+ch3 1 1 1 ch0.ch1.ch2.ch3 13 reload eeprom re-load operation select bit. operation definition: rd reload operation 1 0 boot rom/eeprom read 1 1 eeprom re-load operation (sr=1) 12 br boot rom select, set to select boot rom only if csr9<11>=0. 11 sr serial rom select, set to select serial rom for either read or write operation. field name description 7:0 data if boot rom is selected ( csr9<12> is set ), this field contains the data to be read from and written to the boot rom. if serial rom is selected , csr9<3:0> are defined as follows : 3 sdo serial rom data out from serial rom into MX98715a-c. 2 sdi serial rom data input to serial rom from MX98715a-c. 1 sclk serial clock output to serial rom. 0 scs chip select output to serial rom. warning : csr9<11> and csr9<12> should be mutually exclusive for correct operations. 01 led0sel act speed led1sel link link/act led2sel speed col led3sel rx full/half led4sel* col pmeb 25 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.11 10 base-t status port ( csr12 ) field name decription 31:16 lpc link partner's link code word, where bit 16 is s0 ( selector field bit 0 ) and bit31 is np ( next page ). effective only when csr12<15> is read as a logical 1. 15 lpn link partner negotiable, set when link partner support nway algorithm and csr14<7> is set. 14:12 ans autonegotiation arbitration state, arbitration states are defined 000 = autonegotiation disable 001 = transmit disable 010 = ability detect 011 = acknowledge detect 100 = complete acknowledge detect 101 = flp link good; autonegotiation complete 110 = link check when autonegotiation is completed, an anc interrupt ( csr5<4>) is generated, write 001 into this field can restart the autonegotiation sequence if csr14<7> is set. otherwise, these bits should be 0. 11 trf transmit remote fault 3 aps autopolarity state, set when polarity is positive. when reset, the 10base-t polarity is negative. the received bit stream is inverted by the receiver. 2 ls10b set when link status of 10 base-t port link test fail. reset when 10 base-t link test is in pass state. 1 ls100b link state of 100 base-tx, this bit reflects the state of sd pin, effective only when csr6<23>= 1 ( pcs is set ). set to indicate a fail condition .i.e. sd=0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lpc-link partner's link code word lpn-link partner negotiable ans-autonegotiation arbitration state trf-transmit remote fault aps-autopolarity state ls10b-link status of 10 base-t ls100b-link status of 100 base-tx *software reset has no effect on this register 26 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.12 sia reset register (csr13) field name decription 0 nway reset while writing 0 to this bit, resets the csr12 & csr14. 1 100base-tx reset write a 1 will reset the internal 100 base-tx phy module 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100 tx reset- 100 base-tx phy level reset nway reset- nway and 10 base-t phy level reset 5.2.13 10 base-t control port (csr14) field name decription 19 pause bit 10 of link code word for 100 base-tx pause mode. 18 t4 bit 9 of link code word for t4 mode. 17 txf bit 8 of link code word for 100 base-tx full duplex mode. 16 txh bit 7 of link code word for 100 base-tx half duplex mode. meaningful only when csr14<7> ( ane ) is set. 12 lte link test enable, when set the 10 base-t port link test function is enabled. 8 rsq receive squelch enable for 10 base-t port. set to enable. 7 ane autonegotiation enable, . 6 hde half-duplex enable, this is the bit 5 of link code word, only meaningful when csr14<7> is set. 2 pwd10b reset to power down 10 base-t module, this will force both tx and rx port into tri-state and prevent ac current path. set for normal 10 base t operation. 1 lbk loop back enable for 10 base-t mcc. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 t4-100 base-t4 (link code word) pause-pause (link code word) txf-100 base-tx full duplex (link code word) txh-100 base-tx half duplex (link code word) lte-link test enable rso-receive squelch enable ane-autonegotiation enable hde-half duplex enable) pwd10b-power down 10 base-t lbk-loopback (mcc) *the software reset bit (bit0 of csr0) has no effect to this register. 27 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.14 watchdog timer ( csr15) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mbz-must be zero rwr-receive watchdog release pwd-receive watchdog disable jck-jabber clock huj-host unjabber jab-jabber disable field name description 5 rwr defines the time interval no carrier from receive watchdog expiration until reenabling the receive channel. when set, the receive watchdog is release 40-48 bit times from the last carrier deassertion. when reset, the receive watchdog is released 16 to 24 bit times from the last carrier deassertion. 4 rwd when set, the receive watchdog counter is disable. when reset, receive carriers longer than 2560 bytes are guaranted to cause the watchdog counter to time out. packets shorter than 2048 bytes are guaranted to pass. 2 jck when set, transmission is cut off after a range of 2048 bytes to 2560 bytes is transmitted, when reset, transmission for the 10 base-t port is cut off after a range of 26 ms to 33ms. when reset, transmission for the 100 base-tx port is cut off after a range of 2.6ms to 3.3ms. 1 huj defines the time interval between transmit jabber expiration until reenabling of the transmit channel. when set, the transmit channel is released immediately after the jabber expiration. when reset, the jabber is released 365ms to 420 ms after jabber expiration for 10 base-t port. when reset, the jabber is released 36.5ms to 42ms after the jabber exporation for 100 base-tx port. 0 jbd jabber disable, set to disable transmit jabber function. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ds130 ds120 5.2.15 auto compensation register (csr20) field name description 22 reop default = 1 for ic revision h, for all older revisions, this bit = 0 as default. 16 penpro it should be set to the same value as reop bit. 14 ds130 when set, the auto-compensation circuit in transceiver is enable. 9 ds120 when set, the auto-compensation circuit in transceiver is enable. 28 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.16 flow control register (csr21) field name description 31:16 tmval timer value in the flow control frame for receive flow control. 15 test test the flow control timer. 14 restart set the receive flow control into the restart mode, the rxfcen should be asserted. the default value is 0. 13 restop set the receive flow control into the restop mode, the rxfcen should be asserted. the default value is 0. 12 txfcen transmit flow control enable. the default value is 1. 11 rxfcen receive flow control enable. the default value is 0. 10 rufcen send flow control frame control when the receive descriptor is unavailable, the rxfcen should be asserted. the default value is 0. 9 stoptx indicate the transmit status. if the receive flow control stop the transmission, this bit is set. after recovering transmission, this bit is clear. 8 rejectfc abort the receive flow control frame when set. the default value is 0. 7 fcth1 receive flow control threshold 1. 6 fcth0 receive flow control threshold 0. 5 nfcen accept flow control from the auto-negotiation result. 4 wkfcaten enable the wake up frame catenation feature. see csr9, loadable from eeprom 3 lnkchgdis set to disable link change to trigger pme#, loadable from eeprom 2 mphitdis set to disable magic packet address matching, loadable from eeprom receive flow control threshold table fcth1 1110 fcth1 1000 threshold value (byte) 512 256 128 overflow 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tmval-flow control timer value test-test flow counter timer restart-set reset mode restop-set restop mode txfcen-transmit flow control enable rxfcen-receive flow control stoptx-indicate the transmit is stoped rejectfc-abort the receive flow control frame fcth1-flow control thresold 1 fcth0-flow control thresold 0 rufcen-receive flow control enable while receive descriptor is unavailable nfcen-nway flow control wkfcaten-wake up frame catenation enable lnkchgdis - link change indication disable mphitdis - magic packet hit disable 29 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.17 mac id byte 3-0 register (csr22) 5.2.18 magic id byte 5,4/ mac id byte 5,4 (csr23) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mac id byte 3 mac id byte 2 mac id byte 0 mac id byte 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 magic id byte 5 magic id byte 4 mac id byte 4 mac id byte 5 5.2.19 magic id byte 3-0 (csr24) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 magic id byte 3 magic id byte 2 magic id byte 0 magic id byte 1 5.2.20 filter 0 byte mask register 0 (csr25) filter 1 byte mask register 1 (csr26) filter 2 byte mask register 2 (csr27) filter 3 byte mask register 3 (csr28) csr25 filter n (n=0 to 3) byte mask register n (n=0 to 3) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 byte mask field name description 31:0 byte mask if bit number j of the byte mask is set, byte number (offset+j) of the incoming frame is checked. 30 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.2.21 filter offset register (csr29) field name description 6:0 pattern 0 offset the offset defines the location of first byte that should be checked by filter 0 in the frame. offset is always greater than 12. 7 filter 0 enable this bit is set to enable the filter 0. if it is reset, filter 0 is disabled for the wake-up frame checking. 14:8 pattern 1 offset the offset defines the location of first byte that should be checked by filter 1 in the frame. offset is always greater than 12. 15 filter 1 enable this bit is set to enable the filter 1. if it is reset, filter 1 is disabled for the wake-up frame checking. 22:16 pattern 2 offset the offset defines the location of first byte that should be checked by filter 2 in the frame. offset is always greater than 12. 23 filtre 2 enable this bit is set to enable the filter 2. if it is reset, filter 2 is disabled for the wake-up frame checking. 30:24 pattern 3 offset the offset defines the location of first byte that should be checked by filter 3 in the frame. offset is always greater than 12. 31 filter 3 enable this bit is set to enable the filtre 3. if it is reset, filter 3 is disabled for the wake-up frame checking. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 filter 3 offset filter 3 enable filter 2 enable filter 2 offset filter 1 enable filter 1 offset filter 0 enable filter 0 offset 31 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e field name description 15:0 filter 0 crc-16 the 16-bit crc value is programmed by the driver to be matched against the current result from the crc-16's remainder at the location specified by filter 0 offset and filter 0 byte mask register. if matched, the incoming frame is a wakeup frame. 31:0 filter 1 crc-16 same description as filter 0 crc-16. 5.2.22 filter 1 and 0 crc-16 register (csr30) 5.2.23 filter 2 and 2 crc-16 register (csr31) field name description 15:0 filter 2 crc-16 same description as filter 0 crc-16. 31:0 filter 3 crc-16 same description as filter 0 crc-16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 filter 1 crc-16 filter 0 crc-16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 filter 3 crc-16 filter 2 crc-16 32 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 5.3 acpi power management support the advanced configuration and power interface (acpi) specification defines a flexible and abstract fardware interface for a wide varity of pc systems to implement power and thernal management functions. this chip is fully compliant with the onnow network device class power management spec. rec.1.0, the pci power man- agement interface spec. rev.1.0 and the acpi spec. rev.1.0. four power states defined for a pci function are: * d0-fully on. the device is completely active and respon- sive. * d1-light sleep. save a little power than d0 state. the pci clock is running. * d2-deeper sleep: save more power than d1 state. the pci clock can be stopped. * d3 hot -deepest sleep: save more power than d2 state. the pci clock is stopped. * d3 cold -power down: in this state, the main system power is removedfrom the chip but will preserve their pme context when transitioning from the d3 cold to the d0 state. such function requires an auxiliary power source other than main sys- tem power plane. this chip also supports the onnow network device class specification based on the acpi specification defines the power management requirements of a net- work device. it defines the following wake-up events: * reception of a magic packet. * reception of a network wake-up frame. * detection of change in the network link state. to put MX98715/725 into the sleep mode and enable the wake-up events detection are done as following: 1. write 1 to ppmcsr[8] to enable power management feature. 2. write the value to ppmcsr[1:0] to determine which power state to enter. if d1, d2 or d3 hot state is set, the pc is still turned on and is commonly called entering the remote wake-up mode. otherwise if the main power on a pc is totally shut off, we call that it is in the d3 cold state or remote power-on mode. to sustain the operation of the lan card, a 5v standby power is required. once the pc is turned on, MX98715/725 loads the magic id from eeprom and set it up automatically. no registers is needed to be programmed. after then, simply turn of pc to enter d3 cold state. in either remote wake-up mode or remote power-on mode. the transceiver and the rx block are still alive to monitor the network activity. if one of the three wake-up events occured, the following status is changed: 1. ppmcsr[15] (pme status) is set to 1. 2. crs5[28] (wkupi) is set to 1. 3. pci interrupt pin inta# is asserted low. 4. pmeb pin is asserted low. 5. in mx98725, extstartb and lanwake are also asserted. 5.3.1 magic packet the magic packet (tm) technology, proposed by amd, is used to remotely wake up a sleeping or powered off pc on a network. this is accomplished by sending a spe- cific packet, called magic packet, to a node on the net- work. when a nic capable of recognizing the specific frame goes to sleep (entering d1, d2 ro d3 state), it scans all incoming frames addressed to the node for a specific data sequence, which indicates to the control- ler that this is a magic packet frame. the specific se- quence consists of 16 duplications of the ieee address of this node, with no breaks or interruptions. this se- quence can be located anywhere within the packet, but must be preceded by a synchronization stream. the synchronization stream is defined as 6 bytes of ffh. for example, if the ieee address for a particular node on the network was 11h 22h 33h 44h 55h 66h, then the magic packet for this node would be: da sa misc. ff ff ff ff ff ff 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 misc. crc. 33 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e this chip can automatically loads the ieee address into the internal registers from eeprom while booting up. the magic packet detection scheme is not active while chip is in normal running state (d0). after entering into the sleep mode(d1, d2, d3) by host, the chip begins to scan the incoming packet but does not load the packet into rx fifo. if a magic packet is detected, the pmeb is asserted to notify the host. magic packet event occurs when the following condi- tions are approved: * the destination address of the received packet matches. * the pmen bit (ppmcsr[8]) is set to 1. * not in d0 state. * the magic packet pattern matches, i.e., 6*ffh + 16* destination id. 34 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e * not in d0 state. * the destination address of the received wakeup frame matches. * no crc-32 error is detected in the wakeup frame. * the pmen bit (ppmcsr[8]) is set to 1. * the enable bit in the wakeup frame register block must be set. * the crc value calculated from the bytes in the pre-designated locations equals to the respectively stored crc-16 value. * if catenation must be met. enable bit wkfcaten is set, the condition in table 2. 5.3.3 link change link change wakeup event occurs when the following conditions are met: * not in d0 state. * the pmen bit (pmcsr[8]) is set to 1. * the cable is re-connected. the remote power-on (rpo) feature is a mechanism can be used to remotely power up a sleeping station. when the pc turned on, MX98715aec-e loads the net- work id from serial rom automatically. once the pc is turnned off, MX98715aec-e enters the rpo mode. MX98715aec-e monitors the network for receipt of a wakeup packet. if a magic packet or wake up frame is received, it asserts lanwake, signal to wake up the system. after main power is on, lanwake is deasserted by pci rstb signal. after the deassertion, MX98715aec-e can enter rpo mode again if the main power is switched off. driver sets filter 0 and filter 1 be contiguous and also sets filter 2 and filter 3 be contiguous by adjusting the offsets, then two 64-byte wake up frames are supported. another example is that if wkfcat<1:0>=11 and the driver sets filter 0,1,2,3 as contiguous, a 128-byte wake up frame is supported. wakeup frames event occurs when following conditions are met: 35 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 6. ac/dc characteristics 6.1 boot rom read timing trc bpa 15-0 toes tce bceb boeb (ce&oe is typical shorted) toh bpd 7:0 tac c toolz tcolz toh 6.2 ac characteristics symbol description minimum typical maximum units trc read cycle 8 - - pci cycle tce chip enable access time - - 7 pci cycle tacc address access time - - 7 pci cycle toes output enable access time - - 7 pci cycl toh output hold from address, ceb, or oeb 0 - - ns pci cycle range:66ns (16mhz)~25ns (40mhz) 36 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 6.3 absolute operation condition supply voltage (vcc) -0.5v to +7.0v dc input voltage (vin) 4.75v to 5.25v dc output voltage (vout) -0.5v to vcc + 0.5v storage temperature range (tstg) -55 c to +150 c operating temperature range 0 c to 70 c operating surface temperarure(25 c) 49 c(typ) power dissipation (pd) 750mw (typ.) lead temp. (tl) (soldering, 10 sec) 260 c esd rating (rzap = 1.5k, czap = 100pf) 1.0kv clamp diode current 20ma 6.4 dc characteristics symbol parameter conditions min max units ttl/pci input/output voh minimum high level output voltage ioh = -3ma 2.4 v vol maximum low level output voltage iol = +6ma 0.4 v vih minimum high level input voltage 2.0 v vil maximum low level input voltage 0.8 v iin input current vi = vcc or gnd - 1.0 + 1.0 ua ioz minimum tri-state output leakage current vout = vcc or gnd -10 +10 ua led output driver vlol led turn on output voltage iol = 16ma 0.4 v supply idd average supply current ckref =25mhz pciclk = 33mhz d0 (100mbps) 150 185 ma d1 (100mbps) 150 185 d2 (100mbps) 150 180 d3 (100mbps) 150 180 d0 (10mbps) 170 200 d1 (10mbps) 170 195 d2 (10mbps) 170 195 d3 (10mbps) 170 195 vdd average supply voltage 4.75v 5.25v v 37 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e 7.0 package information 128-pin plastic quad flat pack a e l a1 l1 e3 a e 38 1 64 65 102 103 128 39 i h d3 d zd b c d ze item millimeters inches a 14.00 .05 5.512 .002 b .20 [typ.] .08 [typ.] c 20.00 .05 7.87 .002 d 1.346 .530 e .50 [typ.] .20 [typ.] l1 1.60 .1 .63 .04 l .80 .1 .31 .04 ze .75 [typ.] .30 [typ.] e3 12.50 [typ.] 4.92 [typ.] e 17.20 .2 6.77 .08 zd .75 [typ.] .30 [typ.] d3 18.50 [typ.] 7.28 [typ.] d 23.20 .2 9.13 .08 a1 .25 .1 min. .01 .04 min. a 3.40 .1 max. 1.34 .04 max. note short lead short lead note: each lead centerline is located within .25 mm[.01 inch] of its true position [tp] at maximum material condi- tion. 38 p/n:pm0676 rev. 0.2, mar. 04, 2000 MX98715aec-e revision history revision description page date 0.1 modify non-volatile memory control register p23 dec/13/1999 modify flow control register p28 0.2 add & modify features p1 ma y/04/2000 add field 22,16 (csr20) p27 m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. 39 MX98715aec-e MX98715aec-e c9930 ta777001 37dex taiwan top side marking line 1 : MX98715a is mxic parts no. "e" : pqfp "c" : commercial grade "-e" : bonding option line 2 : assembly date code. line 3 : wafer lot no. line 4 : "37d" : revision code, "e" : bonding option "x" : no used line 5 : state |
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