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data sheet ics853s004aki may 27, 2017 1 ?2017 integrated device technology, inc. low skew, 1-to-4, differential-to-2.5v, 3.3v lvpecl fanout buffer ics853S004I general description the ics853S004I is a low skew, high performance 1-to-4, 2.5v/3.3v differential-to-lvpecl fanout bu ffer. guaranteed output and part-to-part skew characteristics make the ics853S004I ideal for those applications demanding well defined performance and repeatability. features ? four differential lvpecl outputs ? differential lvpecl clock input pair ? pclk, npclk pair can accept the following differential input levels: lvpecl, lvds, cml ? maximum output frequency: 2ghz ? output skew: 25ps (maximum) ? part-to-part skew: 100ps (maximum) ? propagation delay: 500ps (maximum) ? additive phase jitter, rms: 0.10ps (maximum) @156.25mhz (12khz - 20mhz) ? clock enable signal synchronized to eliminate runt clock pulses ? lvpecl mode operating voltage supply range: v cc = 2.375v to 3.8v, v ee = 0v ? -40c to 85c ambient operating temperature block diagram pin assignment ics853S004I 16-lead vfqfn top view
ics853s004aki may 27, 2017 2 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 q1, nq1 output differential ou tput pair. lvpecl interface levels. 3, 4 q2, nq2 output differential ou tput pair. lvpecl interface levels. 5, 6 q3, nq3 output differential ou tput pair. lvpecl interface levels. 7v ee power negative supply pin. 8 nc unused no connect. 9 pclk input pulldown non- inverting differentia l lvpecl clock input. 10 npclk input pullup/ pulldown inverting differential lvpecl clock input. v cc /2 default when left floating. 11 v bb output bias voltage. 12, 14 v cc power power supply pins. 13 nen input pulldown synchronizing clock enable. when low, clock outputs follow clock input. when high, qx outputs are forced low, nqx outputs are forced high. single-ended lvpecl in terface levels. 15, 16 q0, nq0 output differential ou tput pair. lvpecl interface levels. symbol parameter test conditio ns minimum typical maximum units r pulldown input pulldown resistor 37 k ? r vcc/2 pullup/pulldown resistors 37 k ?
ics853s004aki may 27, 2017 3 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer function tables table 3a. control input function table after nen switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in figure 1 . in the active mode, the state of t he outputs are a function of the pclk/n pclk input as described in table 3b. figure 1. nen timing diagram table 3b. clock input function table note 1: please refer to the application information section, wiring the differential input to accept single-ended levels. inputs outputs nen q[0:3] nq[0:3] 1 disabled; low disabled; high 0 enabled enabled inputs outputs input to output mode polarity pclk npclk q0:q3 nq0:nq3 0 1 low high differential to differential non-inverting 1 0 high low differential to differential non-inverting 0 biased; note 1 low high single-ende d to differential non-inverting 1 biased; note 1 high low single-ende d to differential non-inverting biased; note 1 0 high low single-ended to differential inverting biased; note 1 1 low high single-ended to differential inverting t pd t s t h v dd /2 v dd /2 v pp nen npclk pclk nq[0:3] q[0:3]
ics853s004aki may 27, 2017 4 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operat ion of product at these condit ions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 4.6v (lvpecl mode, v ee = 0v) inputs, v i -0.5v to v cc + 0.5v outputs, i o continuous current surge current 50ma 100ma v bb sink//source, i bb 0.5ma operating temperature range, t a -40 ? c to +85 ? c package thermal impedance, ? ja 74.7 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v cc positive supply voltage 2.375 3.3 3.8 v i ee power supply current 68 ma
ics853s004aki may 27, 2017 5 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer table 4b. dc characteristics, v cc = 3.3v; v ee = 0v, t a = -40c to 85c note: input and output par ameters vary 1:1 with v cc . v ee can vary +0.165v to -0.5v. note 1: outputs terminated with 50 ? to v cc ? 2v. note 2: single-ended input operation is limited. v cc ? 3v in lvpecl mode. note 3: common mode voltage is defined as v ih for the differential inputs. note 4: the v cmr and v pp levels should be such that the input low voltage never goes below v ee . table 4c. lvpecl dc characteristics, v cc = 2.5v; v ee = 0v, t a = -40c to 85c note: input and output par ameters vary 1:1 with v cc . v ee can vary +0.125v to -0.125v. note 1: outputs terminated with 50 ? to v cc ? 2v. note 2: common mode voltage is defined as v ih for the differential inputs. note 3: the v cmr and v pp levels should be such that the input low voltage never goes below v ee . symbol parameter -40c 25c 85c units min typ max min typ max min typ max v oh output high voltage; note 1 2.175 2. 275 2.50 2.165 2.295 2. 495 2.160 2.295 2.485 v v ol output low voltage; note 1 1.405 1.545 1.68 1.40 1.52 1.615 1.39 1.535 1.63 v v ih input high voltage nen 2.075 2.36 2.075 2.36 2.075 2.36 v v il input low voltage nen 1.43 1.765 1.43 1.765 1.43 1.765 v v bb output voltage reference; note 2 1.72 2.00 1.72 2.00 1.72 2.00 v v cmr input high voltage common mode range; note 3 1.2 3.3 1.2 3.3 1.2 3.3 v v pp peak-to-peak input voltage; note 4 150 800 1200 150 800 1200 150 800 1200 mv i ih input high current nen, pclk, npclk 150 150 150 a i il input low current nen, pclk -10 -10 -10 a npclk -150 -150 -150 a symbol parameter -40c 25c 85c units min typ max min typ max min typ max v oh output high voltage; note 1 1.375 1. 475 1.70 1.425 1.495 1.69 1.40 1.495 1.685 v v ol output low voltage; note 1 0.605 0.745 0.88 0.625 0.72 0.86 0.64 0.735 0.85 v v ih input high voltage nen 1.275 1.56 1.275 1.56 1.275 1.56 v v il input low voltage nen 0.63 0.965 0.63 0.965 0.63 0.965 v v cmr input high voltage common mode range; note 2, 3 1.2 2.5 1.2 2.5 1.2 2.5 v v pp peak-to-peak input voltage; note 4 150 800 1200 150 800 1200 150 800 1200 mv i ih input high current nen, pclk, npclk 150 150 150 a i il input low current nen, pclk -10 -10 -10 a npclk -150 -150 -150 a
ics853s004aki may 27, 2017 6 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer ac electrical characteristics table 5. ac characteristics, v cc = -3.8v to -2.375v or , v cc = 2.375v to 3.8v; v ee = 0v, t a = -40c to 85c note: all parameters are measured at f ? 1ghz, unless otherwise noted. note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. th e device will meet specifications after thermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the output differential cross points. note 3: defined as skew between outputs on different devices operating at the same su pply voltage, same frequency, same tempera ture and with equal load conditions. using the same type of inputs on ea ch device, the outputs are measur ed at the differential cross po ints. note 4: this parameter is defined in accordance with jedec standard 65. symbol parameter -40c 25c 80c units min typ max min typ max min typ max f out output frequency 2 2 2 ghz t pd propagation delay; note 1 250 350 450 300 400 500 300 400 500 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section (? = 156.25mhz,12khz - 20mhz) 0.06 0.10 0.07 0.10 0.07 0.10 ps t sk(o) output skew; note 2, 4 10 25 10 25 10 25 ps t sk(pp) part-to-part skew; note 3, 4 100 100 100 ps t r / t f output rise/fall time 20% to 80% 100 165 225 100 165 225 100 165 225 ps t s clock enable setup time 100 50 100 50 100 50 ps t h clock enable hold time 200 140 200 140 200 140 ps
ics853s004aki may 27, 2017 7 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer additive phase jitter the spectral purity in a band at a sp ecific offset from the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specifi ed, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the fr equency domain, we get a better understanding of its effects on the de sired application over the entire time record of the signal. it is ma thematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device m eets the noise floor of what is shown, but can actually be lowe r. the phase noise is dependent on the input source and measurement equipment. the source generator ?ifr2042 10k hz ? 5.4ghz low noise signal generator used as external input to an agilent 8133a 3ghz pulse generator?. additive phase jitter @ 156.25mhz 12khz to 20mhz = 0.07ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
ics853s004aki may 27, 2017 8 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer parameter measureme nt information lvpecl output load test circuit part-to-part skew output rise/fall time differential input level output skew propagation delay scope qx nqx v ee v cc 2v -1.8v to -0.375v t sk(pp) part 1 part 2 nqx qx nqy qy nq[0:3] q[0:3] v cc v ee v cmr cross points v pp npclk pclk nqx qx nqy qy t pd nq[0:3] q[0:3] npclk pclk
ics853s004aki may 27, 2017 9 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer applications information wiring the differential input to accept single ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bi as circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specific ations are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a di fferential input to accept single-ended levels
ics853s004aki may 27, 2017 10 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 3.3v lvpecl clock input interface the pclk /npclk accepts lvpecl, lvds, cml and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 3a to 3e show interface examples for the pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use t heir termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 3a. pclk/npclk input driven by a cml driver figure 3c. pclk/npclk input driven by a 3.3v lvpecl driver figure 3e. pclk/npclk input driven by a 3.3v lvds driver figure 3b. pclk/npclk input driven by a built-in pullup cml driver figure 3d. pclk/npclk input driven by a 3.3v lvpecl driver with ac couple pclk npclk lvpecl input cml 3.3v zo = 50 zo = 50 3.3v 3.3v r1 50 r2 50 r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 pclk npclk 3.3v 3.3v lvpecl lvpecl input pclk npclk vbb 3.3v lvpecl input r1 1k r2 1k 3.3v zo = 50 zo = 50 c1 c2 r5 100 lvds c3 0.1f 3.3v r1 100 cml built-in pullup pclk npclk 3.3v lvpecl input zo = 50 zo = 50 r1 50 r2 50 r5 100 - 200 r6 100 - 200 pclk vbb npclk 3.3v lvpecl 3.3v zo = 50 zo = 50 3.3v lvpec l input c1 c2
ics853s004aki may 27, 2017 11 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 2.5v lvpecl clock input interface the pclk /npclk accepts lvpecl, lvds, cml and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 4a to 4e show interface examples for the pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use th eir termination recommendation. please consult with the vendor of t he driver component to confirm the driver termination requirements. figure 4a. pclk/npclk input driven by a cml driver figure 4c. pclk/npclk input driven by a 2.5v lvpecl driver figure 4e. pclk/npclk input driven by a 2.5v lvds driver figure 4b.pclk/npclk input driven by a built-in pullup cml driver figure 4d. pclk/npclk input driven by a 2.5v lvpecl driver with ac couple pclk npclk lvpecl input cml 2.5v zo = 50 zo = 50 2.5v 2.5v r1 50 r2 50 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? pclk npclk vbb 2.5v lvpecl input r1 1k r2 1k 2.5v zo = 50 zo = 50 c1 c2 r5 100 lvds c3 0.1f 2.5v r1 100 cml built-in pullup pclk npclk 2.5v lvpecl input zo = 50 zo = 50 r2 50 r5 100 - 200 r6 100 - 200 pclk vbb npclk 2.5v lvpecl 2.5v zo = 50 zo = 50 2.5v lvpecl input c1 c2
ics853s004aki may 27, 2017 12 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer recommendations for unused output pins outputs: lvpecl outputs all unused lvpecl output pairs can be left fl oating. we recommend that there is no trace attached. bo th sides of the differential output pair should either be left floating or terminated. termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are low impedance follower outputs that generate ecl/lvpecl compatible ou tputs. therefor e, terminating resistors (dc current pa th to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 5a and 5b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommend ed that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 5a. 3.3v lvpecl output termination figure 5b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? inp ut 3.3v 3 .3v + _
ics853s004aki may 27, 2017 13 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer termination for 2.5v lvpecl outputs figure 6a and figure 6b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cc ? 2v. for v cc = 2.5v, the v cc ? 2v is very close to ground level. the r3 in figure 6b can be eliminated and the termination is shown in figure 6c. figure 6a. 2.5v lvpecl dr iver termination example figure 6c. 2.5v lvpecl dr iver termination example figure 6b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cc = 2.5v 2.5v 2.5v 50 50 r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 + ? 2.5v lvpecl driver v cc = 2.5v 2.5v 50 50 r1 50 r2 50 r3 18 + ?
ics853s004aki may 27, 2017 14 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) wit hin the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 7. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the out er edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from t he package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirement s. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further informati on, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 7. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics853s004aki may 27, 2017 15 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer power considerations this section provides information on power dissipa tion and junction temperature for the ics853S004I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics853S004I is the sum of t he core power plus the output power dissipated due to loading. the following is the power dissipation for v cc = 3.8v, which gives worst case results. note: please refer to section 3 for details on calculating output power dissipated due to loading. ? power (core) max = v cc_max * i ee_max = 3.8v * 68ma = 258.4mw ? power (outputs) max = 30.34mw/loaded output pair if all outputs are lo aded, the total power is 4 * 30.34mw = 123.36mw total power_ max (3.8v, with all outputs swit ching) = 258.4mw + 123.36mw = 379.76mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad dire ctly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (e xample calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 74.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.380w * 74.7c/w = 113.4c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depe nding on the number of loaded ou tputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 16 lead vfqfn, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 74.7c/w 65.3c/w 58.5c/w
ics853s004aki may 27, 2017 16 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 3. calculations and equations. the purpose of this section is to calculate the power dissipa tion for the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 8. figure 8. lvpecl driver circuit and termination t o calculate output power dissipated due to load ing, use the following equations which assume a 50 ? load, and a termination voltage of v cc ? 2v. ? for logic high, v out = v oh_max = v cc_max ? 0.815v (v cc_max ? v oh_max ) = 0.815v ? for logic low, v out = v ol_max = v cc_max ? 1.67v (v cc_max ? v ol_max ) = 1.67v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v oh_max ) = [(2v ? (v cc_max ? v oh_max ))/r l ] * (v cc_max ? v oh_max ) = [(2v ? 0.815v)/50 ? ] * 0.815v = 19.32mw pd_l = [(v ol_max ? (v cc_max ? 2v))/r l ] * (v cc_max ? v ol_max ) = [(2v ? (v cc_max ? v ol_max ))/r l] * (v cc_max ? v ol_max ) = [(2v ? 1.67v)/50 ? ] * 1.67v = 11.02mw total power dissipation per output pair = pd_h + pd_l = 30.34mw v out v cc v cc - 2v q1 rl 50
ics853s004aki may 27, 2017 17 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer reliability information table 7. ? ja vs. air flow table for a 16 lead vfqfn transistor count the transistor count for ics853S004I is: 407 ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 74.7c/w 65.3c/w 58.5c/w
ics853s004aki may 27, 2017 18 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer package outline drawings (sheet 1)
ics853s004aki may 27, 2017 19 ?2017 integrated device technology, inc. ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer package outline drawings (sheet 2)
ics853S004I data sheet low skew, 1-to-4, differe ntial-to-2.5v, 3.3v lvpecl/ecl fanout buffer 20 ?2017 integrated device technology, inc. disclaimer integrated device te chnology, inc. (idt) and its aff iliated companies (herein referred to as ?idt?) reserve the righ t to modify the products and/or specific ations described herein at any time, without notice, at idt?s sole discretion. performance specifications and operati ng parameters of the described products are det ermined in an independent state and are not guaranteed to perform the same way when installed in customer products. the informati on contained herein is provided without representation or warranty of any kind, whether express or implied, incl uding, but not limited to, the suitability of idt's products for any particular purpose, an implied warran ty of merchantab ility, or non-infringement of the intellectual p roperty rights of others. this documen t is presented only as a guide and does not convey any license under intellectual propert y rights of idt or any third parties. idt's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be rea- sonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other c ountries. other trademarks used herein are the property of idt or their respective third party owners. for datas heet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology, inc.. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com ordering information table 9. ordering information revision history sheet part/order number marking package shipping packaging temperature 853s004akilf 4ail ?lead-free? 16 lead vfqfn tray -40 ? c to 85 ? c 853s004akilft 4ail ?lead-free? 16 lead vfqfn tape & reel -40 ? c to 85 ? c rev table page description of change date a - - initial release. 8/5/2013 b - 18 updated the package outline drawings. 5/27/2017

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