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ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 1 ? copyright 2012?2015 xilinx, inc. xilinx, the xilinx logo, zynq, virtex, artix, kintex, spartan, ise, vivado and other designa ted brands included herein are trademarks of xilinx in the united states and other countries. amba, amba designer, arm, cortex-a9, coresight, cortex, primecell, arm powered, and a rm connected partner are trademarks of arm ltd. all other trademarks are the property of their respective owners. introduction the zynq?-7000 all programmable socs are available in -3, -2, -2li, -1, and -1lq speed grades, with -3 having the highest performance. the -2li devices operate at programmable logic (pl) v ccint /v ccbram = 0.95v and are screened for lower maximum static power. the speed specification of a -2li device is the same as that of a -2 device. the -1lq devices operate at the same voltage and speed as the -1q devices and are screened for lower power. zynq-7000 device dc and ac characteristics are specified in commercial, extended, industrial, and expanded (q-temp) temperature ranges. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). however, only selected speed grades and/or devices are available in the commercial, extended, or industrial temperature ranges. all supply voltage and junction temperature specifications are representative of worst-case conditions. the parameters included are common to popular designs and typical applications. the available device/package combinations are outlined in: ? zynq-7000 all programmable soc overview ( ds190 ) ? defense-grade zynq-7000q all programmable soc overview ( ds196 ) ? xa zynq-7000 all programmable soc overview ( ds188 ) this zynq-7000 ap soc data sheet, which covers the specifications for the xc7z030, xa7z030, xq7z030, xc7z035, xc7z045, xq7z045, xc7z100, and XQ7Z100 complements the zynq-7000 ap soc documentation suite available on the xilinx website at www.xilinx.com/zynq . dc characteristics zynq-7000 all programmable soc (z-7030, z-7035, z-7045, and z-7100) : dc and ac switching characteristics ds191 (v1.17) november 24, 2015 product specification ta bl e 1 : absolute maximum ratings (1) symbol description min max units processing system (ps) v ccpint ps internal logic supply voltage ?0.5 1.1 v v ccpaux ps auxiliary supply voltage ?0.5 2.0 v v ccpll ps pll supply ?0.5 2.0 v v cco_ddr ps ddr i/o supply ?0.5 2.0 v v cco_mio (2) ps mio i/o supply ?0.5 3.6 v v pref ps input reference voltage ?0.5 2.0 v v pin (2)(3)(4)(5) ps mio i/o input voltage ?0.40 v cco_mio +0.55 v ps ddr i/o input voltage ?0.55 v cco_ddr +0.55 v programmable logic (pl) v ccint pl internal supply voltage ?0.5 1.1 v v ccbram pl supply voltage for the block ram memories ?0.5 1.1 v v ccaux pl auxiliary supply voltage ?0.5 2.0 v v cco pl output drivers supply voltage for hr i/o banks ?0.5 3.6 v pl output drivers supply voltage for hp i/o banks ?0.5 2.0 v v ccaux_io (4) auxiliary supply voltage ?0.5 2.06 v s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 2 v ref input reference voltage ?0.5 2.0 v v in (3)(4)(5) i/o input voltage for hr i/o banks ?0.40 v cco +0.55 v i/o input voltage for hp i/o banks ?0.55 v cco +0.55 v i/o input voltage (when v cco = 3.3v) for v ref and differential i/o standards except tmds_33 (6) ?0.40 2.625 v v ccbatt key memory battery backup supply ?0.5 2.0 v gtx transceiver v mgtavcc analog supply voltage for the gtx transmitter and receiver circuits ?0.5 1.1 v v mgtavtt analog supply voltage for the gtx transmitter and receiver termination circuits ?0.5 1.32 v v mgtvccaux auxiliary analog quad pll (qpll) voltage supply for the gtx transceivers ?0.5 1.935 v v mgtrefclk gtx transceiver reference clock absolute input voltage ?0.5 1.32 v v mgtavttrcal analog supply voltage for the resistor ca libration circuit of the gtx transceiver column ?0.5 1.32 v v in receiver (rxp/rxn) and transmitter (txp /txn) absolute input voltage ?0.5 1.26 v i dcin-float dc input current for receiver input pins dc coupled rx termination = floating ? 14 ma i dcin-mgtavtt dc input current for receiver input pins dc coupled rx termination = v mgtavtt ?12ma i dcin-gnd dc input current for receiver input pins dc coupled rx termination = gnd ? 6.5 ma i dcout-float dc output current for transmitter pins dc coupled rx termination = floating ? 14 ma i dcout-mgtavtt dc output current for transmitter pins dc coupled rx termination = v mgtavtt ?12ma xadc v ccadc xadc supply relative to gndadc ?0.5 2.0 v v refp xadc reference input relative to gndadc ?0.5 2.0 v temperature t stg storage temperature (ambient) ?65 150 c t sol maximum soldering temperature for pb/sn component bodies (7) ? +220 c maximum soldering temperature for pb-free component bodies (7) ? +260 c t j maximum junction temperature (7) ? +125 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. applies to both mio supply banks v cco_mio0 and v cco_mio1 . 3. the lower absolute voltage specification always applies. 4. for i/o operation, refer to the 7 series fpgas selectio resources user guide ( ug471 ) or the zynq-7000 all programmable soc technical reference manual ( ug585 ). 5. the maximum limit applies to dc signals. for maximum undershoot and overshoot ac specifications, see ta b l e 4 and ta bl e 5 . 6. see ta bl e 1 2 for tmds_33 specifications. 7. for soldering guidelines and thermal considerations, see the zynq-7000 all programmable soc packaging and pinout specification ( ug865 ). ta bl e 1 : absolute maximum ratings (1) (cont?d) symbol description min max units s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 3 ta bl e 2 : recommended operating conditions (1)(2) symbol description min typ max units ps v ccpint (3) ps internal logic supply voltage 0.95 1.00 1.05 v v ccpaux ps auxiliary supply voltage 1.71 1.80 1.89 v v ccpll ps pll supply voltage 1.71 1.80 1.89 v v cco_ddr ps ddr supply voltage 1.14 ? 1.89 v v cco_mio (4) ps supply voltage for mio banks 1.71 ? 3.465 v v pin (5) ps ddr and mio i/o input voltage ?0.20 ? v cco_ddr + 0.20 v cco_mio +0.20 v pl v ccint (6) pl internal supply voltage 0.97 1.00 1.03 v pl -2li (0.95v) internal supply voltage 0.93 0.95 0.97 v v ccbram (6) pl block ram supply voltage 0.97 1.00 1.03 v pl -2li (0.95v) block ram supply voltage 0.93 0.95 0.97 v v ccaux pl auxiliary supply voltage 1.71 1.80 1.89 v v cco (7)(8) pl supply voltage for hr i/o banks 1.14 ? 3.465 v pl supply voltage for hp i/o banks 1.14 ? 1.89 v v ccaux_io (9) pl auxiliary supply voltage when set to 1.8v 1.71 1.80 1.89 v pl auxiliary supply voltage when set to 2.0v 1.94 2.00 2.06 v v in (5) i/o input voltage ?0.20 ? v cco +0.20 v i/o input voltage (when v cco =3.3v) for v ref and differential i/o standards except tmds_33 (10) ?0.20 ? 2.625 v i in (11) maximum current through any (ps or pl) pin in a powered or unpowered bank when forward biasing the clamp diode ?? 10 ma v ccbatt (12) battery voltage 1.0 ? 1.89 v gtx transceiver v mgtavcc (13) analog supply voltage for the gtx transceiver qpll frequency range 10.3125 ghz (14)(15) 0.97 1.0 1.08 v analog supply voltage for the gtx transceiver qpll frequency range > 10.3125 ghz 1.02 1.05 1.08 v mgtavtt (13) analog supply voltage for the gtx transmitter and receiver termination circuits 1.17 1.2 1.23 v v mgtvccaux (13) auxiliary analog qpll voltage supply for the transceivers 1.75 1.80 1.85 v v mgtavttrcal (13) analog supply voltage for the resistor calibration circuit of the gtx transceiver column 1.17 1.2 1.23 v xadc v ccadc xadc supply relative to gndadc 1.71 1.80 1.89 v v refp externally supplied reference voltage 1.20 1.25 1.30 v s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 4 temperature t j junction temperature operating range for commercial (c) temperature devices 0? 85 c junction temperature operating range for extended (e) temperature devices 0? 100 c junction temperature operating range for industrial (i) temperature devices ?40 ? 100 c junction temperature operating range for expanded (q) temperature devices ?40 ? 125 c notes: 1. all voltages are relative to ground. the pl and ps share a common ground. 2. for the design of the power distribution system consult the zynq-7000 all programmable soc pcb design guide ( ug933 ). 3. when the processor cores operate f cpu_6x4x_621_max at 1 ghz (-3e speed grade) or when the ddr interface operates at 1333 mb/s, the v ccpint minimum is 0.97v and the v ccpint maximum is 1.03v. 4. applies to both mio supply banks v cco_mio0 and v cco_mio1 . 5. the lower absolute voltage specification always applies. 6. v ccint and v ccbram should be connected to the same supply. 7. configuration data is retained even if v cco drops to 0v. 8. includes v cco of 1.2v, 1.5v, 1.8v, 2.5v, and 3.3v at 5%. 9. for more information, refer to the v ccaux_io section of the 7 series fpgas selectio resources user guide ( ug471 ) or the zynq-7000 all programmable soc technical reference manual ( ug585 ). 10. see ta bl e 1 2 for tmds_33 specifications. 11. a total of 200 ma per ps or pl bank should not be exceeded. 12. v ccbatt is required only when using bitstream encryption. if battery is not used, connect v ccbatt to either ground or v ccaux . 13. each voltage listed requires the filter circuit described in the 7 series fpgas gtx/gth tr ansceivers user guide ( ug476 ). 14. for data rates 10.3125 gb/s, v mgtavcc should be 1.0v 3% for lower power consumption. 15. for lower power consumption, v mgtavcc should be 1.0v 3% over the entire cpll frequency range. ta bl e 2 : recommended operating conditions (1)(2) (cont?d) symbol description min typ max units s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 5 ta bl e 3 : dc characteristics over recommended operating conditions symbol description min typ (1) max units v drint data retention v ccint voltage (below which configur ation data might be lost) 0.75 ? ? v v dri data retention v ccaux voltage (below which configuration data might be lost) 1.5 ? ? v i ref ps_ddr_vref 0/1, ps_mio_vref, and v ref leakage current per pin ? ? 15 a i l input or output leakage current per pin (sample-tested) ? ? 15 a c in (2) pl die input capacitance at the pad ? ? 8 pf c pin (2) ps die input capacitance at the pad ? ? 8 pf i rpu pad pull-up (when selected) @ v in =0v, v cco =3.3v 90 ? 330 a pad pull-up (when selected) @ v in =0v, v cco =2.5v 68 ? 250 a pad pull-up (when selected) @ v in =0v, v cco =1.8v 34 ? 220 a pad pull-up (when selected) @ v in =0v, v cco =1.5v 23 ? 150 a pad pull-up (when selected) @ v in =0v, v cco =1.2v 12 ? 120 a i rpd pad pull-down (when selected) @ v in =3.3v 68 ? 330 a pad pull-down (when selected) @ v in =1.8v 45 ? 180 a i ccadc analog supply current, analog circuits in powered up state ? ? 25 ma i batt (3) battery supply current ? ? 150 na r in_term (4) thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_40) 28 40 55 thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_50) 35 50 65 thevenin equivalent resistance of programmable input termination to v cco /2 (untuned_split_60) 44 60 83 n temperature diode ideality factor ? 1.010 ? ? r temperature diode series resistance ? 2 ? notes: 1. typical values are specified at nominal voltage, 25c. 2. this measurement represents the die capacitance at the pad, not including the package. 3. maximum value specified for worst case process at 25c. 4. termination resistance to a v cco /2 level. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 6 ta bl e 4 : v in maximum allowed ac voltage overshoot and undershoot for ps i/o and pl hr i/o banks (1)(2) ac voltage overshoot % of ui @?40c to 125c ac voltage undershoot % of ui @?40c to 125c v cco + 0.55 100 ?0.40 100 ?0.45 61.7 ?0.50 25.8 ?0.55 11.0 v cco + 0.60 46.6 ?0.60 4.77 v cco + 0.65 21.2 ?0.65 2.10 v cco + 0.70 9.75 ?0.70 0.94 v cco + 0.75 4.55 ?0.75 0.43 v cco + 0.80 2.15 ?0.80 0.20 v cco + 0.85 1.02 ?0.85 0.09 v cco + 0.90 0.49 ?0.90 0.04 v cco + 0.95 0.24 ?0.95 0.02 notes: 1. a total of 200 ma per bank should not be exceeded. 2. the peak voltage of the overshoot or undershoot, and the duration above v cco + 0.20v or below gnd ? 0.20v, must not exceed the values in this table. ta bl e 5 : v in maximum allowed ac voltage overshoot and undershoot for pl hp i/o banks (1)(2) ac voltage overshoot % of ui at ?40c to 125 c ac voltage undershoot % of ui at ?40c to 125c v cco + 0.55 100 ?0.55 100 v cco + 0.60 50.0 (3) ?0.60 50.0 (3) v cco + 0.65 50.0 (3) ?0.65 50.0 (3) v cco + 0.70 47.0 ?0.70 50.0 (3) v cco + 0.75 21.2 ?0.75 50.0 (3) v cco + 0.80 9.71 ?0.80 50.0 (3) v cco + 0.85 4.51 ?0.85 28.4 v cco + 0.90 2.12 ?0.90 12.7 v cco + 0.95 1.01 ?0.95 5.79 notes: 1. a total of 200 ma per bank should not be exceeded. 2. the peak voltage of the overshoot or undershoot, and the duration above v cco + 0.20v or below gnd ? 0.20v, must not exceed the values in this table. 3. for ui lasting less than 20 s. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 7 ta bl e 6 : typical quiescent supply current symbol description device speed grade units -3e -2e -2i -2li -1c -1i -1q -1lq i ccpintq ps quiescent v ccpint supply current xc7z030 122 122 122 79 122 122 n/a n/a ma xc7z035 122 122 122 79 122 122 n/a n/a ma xc7z045 122 122 122 79 122 122 n/a n/a ma xc7z100 n/a n/a 122 79 n/a 122 n/a n/a ma xa7z030 n/a n/a n/a n/a n/a 122 122 n/a ma xq7z030 n/a n/a 122 79 n/a 122 122 n/a ma xq7z045 n/a n/a 122 79 n/a 122 122 122 ma XQ7Z100 n/a n/a 122 79 n/a 122 n/a n/a ma i ccpauxq ps quiescent v ccpaux supply current xc7z030131313111313n/an/ama xc7z035131313111313n/an/ama xc7z045131313111313n/an/ama xc7z100 n/a n/a 13 11 n/a 13 n/a n/a ma xa7z030 n/a n/a n/a n/a n/a 13 13 n/a ma xq7z030 n/a n/a 13 11 n/a 13 13 n/a ma xq7z045 n/a n/a 13 11 n/a 13 13 13 ma XQ7Z100 n/a n/a 13 11 n/a 13 n/a n/a ma i ccddrq ps quiescent v cco_ddr supply current xc7z030444444n/an/ama xc7z035444444n/an/ama xc7z045444444n/an/ama xc7z100 n/a n/a 4 4 n/a 4 n/a n/a ma xa7z030 n/a n/a n/a n/a n/a 4 4 n/a ma xq7z030 n/a n/a 4 4 n/a 4 4 n/a ma xq7z045 n/a n/a 4 4 n/a 4 4 4 ma XQ7Z100 n/a n/a 4 4 n/a 4 n/a n/a ma i ccintq pl quiescent v ccint supply current xc7z030 246 246 246 141 246 246 n/a n/a ma xc7z035 611 611 611 351 611 611 n/a n/a ma xc7z045 611 611 611 351 611 611 n/a n/a ma xc7z100 n/a n/a 795 457 n/a 795 n/a n/a ma xa7z030 n/a n/a n/a n/a n/a 246 246 n/a ma xq7z030 n/a n/a 246 141 n/a 246 246 n/a ma xq7z045 n/a n/a 611 351 n/a 611 611 611 ma XQ7Z100 n/a n/a 795 457 n/a 795 n/a n/a ma s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 8 i ccauxq pl quiescent v ccaux supply current xc7z030565656505656n/an/ama xc7z035 131 131 131 117 131 131 n/a n/a ma xc7z045 131 131 131 117 131 131 n/a n/a ma xc7z100 n/a n/a 165 148 n/a 165 n/a n/a ma xa7z030 n/a n/a n/a n/a n/a 56 56 n/a ma xq7z030 n/a n/a 56 50 n/a 56 56 n/a ma xq7z045 n/a n/a 131 117 n/a 131 131 131 ma XQ7Z100 n/a n/a 165 148 n/a 165 n/a n/a ma i ccaux_ioq pl quiescent v ccaux_io supply current xc7z030222122n/an/ama xc7z035222122n/an/ama xc7z045222122n/an/ama xc7z100 n/a n/a 2 1 n/a 2 n/a n/a ma xa7z030 n/a n/a n/a n/a n/a 2 2 n/a ma xq7z030 n/a n/a 2 1 n/a 2 2 n/a ma xq7z045 n/a n/a 2 1 n/a 2 2 2 ma XQ7Z100 n/a n/a 2 1 n/a 2 n/a n/a ma i ccoq pl quiescent v cco supply current xc7z030444444n/an/ama xc7z035444444n/an/ama xc7z045444444n/an/ama xc7z100 n/a n/a 4 4 n/a 4 n/a n/a ma xa7z030 n/a n/a n/a n/a n/a 4 4 n/a ma xq7z030 n/a n/a 4 4 n/a 4 4 n/a ma xq7z045 n/a n/a 4 4 n/a 4 4 4 ma XQ7Z100 n/a n/a 4 4 n/a 4 n/a n/a ma i ccbramq pl quiescent v ccbram supply current xc7z030111111 6 1111n/an/ama xc7z035232323132323n/an/ama xc7z045232323132323n/an/ama xc7z100 n/a n/a 33 19 n/a 33 n/a n/a ma xa7z030 n/a n/a n/a n/a n/a 11 11 n/a ma xq7z030 n/a n/a 11 6 n/a 11 11 n/a ma xq7z045 n/a n/a 23 13 n/a 23 23 23 ma XQ7Z100 n/a n/a 33 19 n/a 33 n/a n/a ma notes: 1. typical values are specified at nominal voltage, 85c junction temperatures (t j ) with single-ended selectio resources. 2. typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 3. use the xilinx power estimator (xpe) spreadsheet tool (download at http://www.xilinx.com/power ) to estimate static power consumption for conditions other than those specified. ta bl e 6 : typical quiescent supply current (cont?d) symbol description device speed grade units -3e -2e -2i -2li -1c -1i -1q -1lq s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 9 ps power-on/off power supply sequencing the recommended power-on sequence is v ccpint , v ccpaux , and v ccpll together, then the ps v cco supplies (v cco_mio0 , v cco_mio1 , and v cco_ddr ) to achieve minimum current draw and ensure that the i/os are 3-stated at power-on. the ps_por_b input is required to be asserted to gnd during the power-on sequence until v ccpint , v ccpaux and v cco_mio0 have reached minimum operating levels to ensure ps efuse in tegrity. for additional information about ps_por_b timing requirements refer to resets . the recommended power-off sequence is the reverse of the power-on sequence. if v ccpaux , v ccpll , and the ps v cco supplies (v cco_mio0 , v cco_mio1 , and v cco_ddr ) have the same recommended voltage levels, then they can be powered by the same supply and ramped simult aneously. xilinx recommends powering v ccpll with the same supply as v ccpaux , with an optional ferrite bead filter. before v ccpint reaches 0.80v at least one of the four following conditions is required during the power-off stage: the ps_por_b input is asserted to gnd, the reference clock to the ps_clk input is disabled, v ccpaux is lower than 0.70v, or v cco_mio0 is lower than 0.90v. the co ndition must be held until v ccpint reaches 0.40v to ensure ps efuse integrity. for v cco_mio0 and v cco_mio1 voltages of 3.3v: ? the voltage difference between v cco_mio0 /v cco_mio1 and v ccpaux must not exceed 2.625v for longer than t vcco2vccaux for each power-on/off cycle to ma intain device reliability levels. ?the t vcco2vccaux time can be allocated in any percentage between the power-on and power-off ramps. pl power-on/off power supply sequencing the recommended power-on sequence for the pl is v ccint , v ccbram , v ccaux , v ccaux_io , and v cco to achieve minimum current draw and ensure that the i/os are 3-stated at power-on. the recommended power-off sequence is the reverse of the power-on sequence. if v ccint and v ccbram have the same recommended voltage levels then both can be powered by the same supply and ramped simultaneously. if v ccaux , v ccaux_io , and v cco have the same recommended voltage levels then they can be powered by the same supply and ramped simultaneously. for v cco voltages of 3.3v in hr i/o banks and configuration bank 0: ? the voltage difference between v cco and v ccaux must not exceed 2.625v for longer than t vcco2vccaux for each power-on/off cycle to maintain device reliability levels. ?the t vcco2vccaux time can be allocated in any percentage between the power-on and power-off ramps. the recommended power-on sequence to achieve minimu m current draw for the gtx transceivers is v ccint , v mgtavcc , v mgtavtt or v mgtavcc , v ccint , v mgtavtt . there is no recommended sequencing for v mgtvccaux . both v mgtavcc and v ccint can be ramped simultaneously. the recommended power-off sequence is the reverse of the power-on sequence to achieve minimum current draw. if these recommended sequences are not met, current drawn from v mgtavtt can be higher than specifications during power-up and power-down. ? when v mgtavtt is powered before v mgtavcc and v mgtavtt ?v mgtavcc > 150 mv and v mgtavcc < 0.7v, the v mgtavtt current draw can increase by 460 ma per transceiver during v mgtavcc ramp up. the duration of the current draw can be up to 0.3 x t mgtavcc (ramp time from gnd to 90% of v mgtavcc ). the reverse is true for power-down. ? when v mgtavtt is powered before v ccint and v mgtavtt ?v ccint > 150 mv and v ccint < 0.7v, the v mgtavtt current draw can increase by 50 ma per transceiver during v ccint ramp up. the duration of the current draw can be up to 0.3 x t vccint (ramp time from gnd to 90% of v ccint ). the reverse is true for power-down. there is no recommended sequence for supplies not shown. ps?pl power sequencing the ps and pl power supplies are fully independent. ps power supplies (v ccpint , v ccpaux , v ccpll , v cco_ddr , v cco_mio0 , and v cco_mio1 ) can be powered before or after any pl power supplies. the ps and pl power regions are isolated to prevent damage. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 10 power supply requirements ta bl e 7 shows the minimum current, in addition to i ccq , that is required by zynq-7000 devices for proper power-on and configuration. if the current minimums shown in ta bl e 6 and ta b l e 7 are met, the device powers on after all five supplies have passed through their power-on reset threshold voltages. the zynq-7000 device must not be configured until after v ccint is applied. once initialized and configured, use the xilin x power estimator (xpe) spreadsheet tool (download at www.xilinx.com/power ) to estimate current drain on these supplies. ta bl e 7 : power-on current for zynq-7000 devices device i ccpintmin i ccpauxmin i ccddrmin i ccintmin i ccauxmin i ccomin i ccaux_iomin i ccbrammin units xc7z030 i ccpintq + 70 ma i ccpauxq + 40 ma i ccddrq + 130 ma per bank i ccintq + 900 ma i ccauxq + 60 ma i ccoq + 90 ma per bank i ccoauxioq + 40 ma per bank i ccbramq + 90 ma ma xc7z035 i ccpintq + 70 ma i ccpauxq + 40 ma i ccddrq + 130 ma per bank i ccintq + 1400 ma i ccauxq + 60 ma i ccoq + 90 ma per bank i ccoauxioq + 40 ma per bank i ccbramq + 90 ma ma xc7z045 i ccpintq + 70 ma i ccpauxq + 40 ma i ccddrq + 130 ma per bank i ccintq + 1400 ma i ccauxq + 60 ma i ccoq + 90 ma per bank i ccoauxioq + 40 ma per bank i ccbramq + 90 ma ma xc7z100 i ccpintq + 70 ma i ccpauxq + 40 ma i ccddrq + 130 ma per bank i ccintq + 2200 ma i ccauxq + 60 ma i ccoq + 90 ma per bank i ccoauxioq + 40 ma per bank i ccbramq + 90 ma ma xa7z030 i ccpintq + 70 ma i ccpauxq + 40 ma i ccddrq + 130 ma per bank i ccintq + 900 ma i ccauxq + 60 ma i ccoq + 90 ma per bank i ccoauxioq + 40 ma per bank i ccbramq + 90 ma ma xq7z030 i ccpintq + 70 ma i ccpauxq + 40 ma i ccddrq + 130 ma per bank i ccintq + 900 ma i ccauxq + 60 ma i ccoq + 90 ma per bank i ccoauxioq + 40 ma per bank i ccbramq + 90 ma ma xq7z045 i ccpintq + 70 ma i ccpauxq + 40 ma i ccddrq + 130 ma per bank i ccintq + 1400 ma i ccauxq + 60 ma i ccoq + 90 ma per bank i ccoauxioq + 40 ma per bank i ccbramq + 90 ma ma XQ7Z100 i ccpintq + 70 ma i ccpauxq + 40 ma i ccddrq + 130 ma per bank i ccintq + 2200 ma i ccauxq + 60 ma i ccoq + 90 ma per bank i ccoauxioq + 40 ma per bank i ccbramq + 90 ma ma ta bl e 8 : power supply ramp time symbol description conditions min max units t vccpint ramp time from gnd to 90% of v ccpint 0.2 50 ms t vccpaux ramp time from gnd to 90% of v ccpaux 0.2 50 ms t vcco_ddr ramp time from gnd to 90% of v cco_ddr 0.2 50 ms t vcco_mio ramp time from gnd to 90% of v cco_mio 0.2 50 ms t vccint ramp time from gnd to 90% of v ccint 0.2 50 ms t vcco ramp time from gnd to 90% of v cco 0.2 50 ms t vccaux ramp time from gnd to 90% of v ccaux 0.2 50 ms t vccaux_io ramp time from gnd to 90% of v ccaux_io 0.2 50 ms t vccbram ramp time from gnd to 90% of v ccbram 0.2 50 ms t vcco2vccaux allowed time per power cycle for v cco ?v ccaux > 2.625v and v cco_mio ?v ccpaux >2.625v t j = 125c (1) ?300 ms t j = 100c (1) ?500 ms t j = 85c (1) ?800 ms t mgtavcc ramp time from gnd to 90% of v mgtavcc 0.2 50 ms t mgtavtt ramp time from gnd to 90% of v mgtavtt 0.2 50 ms s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 11 dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ps i/o levels t mgtvccaux ramp time from gnd to 90% of v mgtvccaux 0.2 50 ms notes: 1. based on 240,000 power cycles with nominal v cco of 3.3v or 36,500 power cycles with a worst case v cco of 3.465v. ta bl e 9 : ps dc input and output levels (1) bank i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma mio lvcmos18 ?0.300 35% v cco_mio 65% v cco_mio v cco_mio + 0.300 0.450 v cco_mio ? 0.450 8 ?8 mio lvcmos25 ?0.300 0.700 1.700 v cco_mio + 0.300 0.400 v cco_mio ? 0.400 8 ?8 mio lvcmos33 ?0.300 0.800 2.000 3.450 0.400 v cco_mio ? 0.400 8 ?8 mio hstl_i_18 ?0.300 v pref ? 0.100 v pref +0.100 v cco_mio + 0.300 0.400 v cco_mio ? 0.400 8 ?8 ddr sstl18_i ?0.300 v pref ? 0.125 v pref +0.125 v cco_ddr +0.300 v cco_ddr /2?0.470 v cco_ddr /2 + 0.470 8 ?8 ddr sstl15 ?0.300 v pref ? 0.100 v pref +0.100 v cco_ddr +0.300 v cco_ddr /2?0.175 v cco_ddr /2 + 0.175 13.0 ?13.0 ddr sstl135 ?0.300 v pref ? 0.090 v pref +0.090 v cco_ddr +0.300 v cco_ddr /2?0.150 v cco_ddr /2 + 0.150 13.0 ?13.0 ddr hsul_12 ?0.300 v pref ? 0.130 v pref +0.130 v cco_ddr + 0.300 20% v cco_ddr 80% v cco_ddr 0.1 ?0.1 notes: 1. tested according to relevant specifications. ta bl e 1 0 : ps complementary differential dc input and output levels bank i/o standard v icm (1) v id (2) v ol (3) v oh (4) i ol i oh v, min v,typ v, max v,min v, max v, max v, min ma, max ma, min ddr diff_hsul_12 0.300 0.600 0.850 0.100 ? 20% v cco 80% v cco 0.100 ?0.100 ddr diff_sstl135 0.300 0.675 1.000 0.100 ? (v cco_ddr /2) ? 0.150 (v cco_ddr /2) + 0.150 13.0 ?13.0 ddr diff_sstl15 0.300 0.750 1.125 0.100 ? (v cco_ddr /2) ? 0.175 (v cco_ddr /2) + 0.175 13.0 ?13.0 ddr diff_sstl18_i 0.300 0.900 1.425 0.100 ? (v cco_ddr /2) ? 0.470 (v cco_ddr /2) + 0.470 8.00 ?8.00 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q?q ). 3. v ol is the single-ended low-output voltage. 4. v oh is the single-ended high-output voltage. ta bl e 8 : power supply ramp time (cont?d) symbol description conditions min max units s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 12 pl i/o levels ta bl e 1 1 : selectio dc input and output levels (1)(2) i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma hstl_i ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 8 ?8 hstl_i_12 ?0.300 v ref ?0.080 v ref + 0.080 v cco + 0.300 25% v cco 75% v cco 6.3 ?6.3 hstl_i_18 ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 8 ?8 hstl_ii ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 16 ?16 hstl_ii_18 ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 0.400 v cco ? 0.400 16 ?16 hsul_12 ?0.300 v ref ?0.130 v ref + 0.130 v cco + 0.300 20% v cco 80% v cco 0.1 ?0.1 lvcmos12 ?0.300 35% v cco 65% v cco v cco + 0.300 0.400 v cco ? 0.400 note 3 note 3 lvcmos15, lvdci_15 ?0.300 35% v cco 65% v cco v cco + 0.300 25% v cco 75% v cco note 4 note 4 lvcmos18, lvdci_18 ?0.300 35% v cco 65% v cco v cco + 0.300 0.450 v cco ? 0.450 note 5 note 5 lvcmos25 ?0.300 0.700 1.700 v cco + 0.300 0.400 v cco ? 0.400 note 6 note 6 lvcmos33 ?0.300 0.800 2.000 3.450 0.400 v cco ? 0.400 note 6 note 6 lvttl ?0.300 0.800 2.000 3.450 0.400 2.400 note 7 note 7 mobile_ddr ?0.300 20% v cco 80% v cco v cco + 0.300 10% v cco 90% v cco 0.1 ?0.1 pci33_3 ?0.400 30% v cco 50% v cco v cco + 0.500 10% v cco 90% v cco 1.5 ?0.5 sstl12 ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 14.25 ?14.25 sstl135 ?0.300 v ref ?0.090 v ref + 0.090 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 13.0 ?13.0 sstl135_r ?0.300 v ref ?0.090 v ref + 0.090 v cco + 0.300 v cco /2?0.150 v cco /2 + 0.150 8.9 ?8.9 sstl15 ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 v cco /2?0.175 v cco /2 + 0.175 13.0 ?13.0 sstl15_r ?0.300 v ref ?0.100 v ref + 0.100 v cco + 0.300 v cco /2?0.175 v cco /2 + 0.175 8.9 ?8.9 sstl18_i ?0.300 v ref ?0.125 v ref + 0.125 v cco + 0.300 v cco /2?0.470 v cco /2 + 0.470 8 ?8 sstl18_ii ?0.300 v ref ?0.125 v ref + 0.125 v cco + 0.300 v cco /2?0.600 v cco /2 + 0.600 13.4 ?13.4 notes: 1. tested according to relevant specifications. 2. 3.3v and 2.5v standards are only supported in hr i/o banks. 3. supported drive strengths of 2, 4, 6, or 8 ma in hp i/o banks and 4, 8, or 12 ma in hr i/o banks. 4. supported drive strengths of 2, 4, 6, 8, 12, or 16 ma in hp i/o banks and 4, 8, 12, or 16 ma in hr i/o banks. 5. supported drive strengths of 2, 4, 6, 8, 12, or 16 ma in hp i/o banks and 4, 8, 12, 16, or 24 ma in hr i/o banks. 6. supported drive strengths of 4, 8, 12, or 16 ma 7. supported drive strengths of 4, 8, 12, 16, or 24 ma 8. for detailed interface specific dc voltage levels, see the 7 series fpgas selectio resources user guide ( ug471 ). s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 13 ta bl e 1 2 : differential selectio dc input and output levels i/o standard v icm (1) v id (2) v ocm (3) v od (4) v, min v, typ v, max v, min v, typ v, max v, min v, typ v, max v, min v, typ v, max blvds_25 0.300 1.200 1.425 0.100 ? ? ? 1.250 ? note 5 mini_lvds_25 0.300 1.200 v ccaux 0.200 0.400 0.600 1.000 1.20 0 1.400 0.300 0.450 0.600 ppds_25 0.200 0.900 v ccaux 0.100 0.250 0.400 0.500 0.95 0 1.400 0.100 0.250 0.400 rsds_25 0.300 0.900 1.500 0.100 0.350 0. 600 1.000 1.200 1.400 0.100 0.350 0.600 tmds_33 2.700 2.965 3.230 0.150 0.675 1.200 v cco ?0.405 v cco ?0.300 v cco ?0.190 0.400 0.600 0.800 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q ? q ). 3. v ocm is the output common mode voltage. 4. v od is the output differential voltage (q ? q ). 5. v od for blvds will vary significantly depending on topology and loading. 6. lvds_25 is specified in ta bl e 1 4 . 7. lvds is specified in ta bl e 1 5 . ta bl e 1 3 : complementary differential selectio dc input and output levels i/o standard v icm (1) v id (2) v ol (3) v oh (4) i ol i oh v, min v, typ v, max v, min v, max v, max v, min ma, max ma, min diff_hstl_i 0.300 0.750 1.125 0.100 ? 0.400 v cco ?0.400 8.00 ?8.00 diff_hstl_i_18 0.300 0.900 1.425 0.100 ? 0.400 v cco ?0.400 8.00 ?8.00 diff_hstl_ii 0.300 0.750 1.125 0.100 ? 0.400 v cco ?0.400 16.00 ?16.00 diff_hstl_ii_18 0.300 0.900 1.425 0.100 ? 0.400 v cco ?0.400 16.00 ?16.00 diff_hsul_12 0.300 0.600 0.850 0.100 ? 20% v cco 80% v cco 0.100 ?0.100 diff_mobile_ddr 0.300 0.900 1.425 0.100 ? 10% v cco 90% v cco 0.100 ?0.100 diff_sstl12 0.300 0.600 0.850 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 14.25 ?14.25 diff_sstl135 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 13.0 ?13.0 diff_sstl135_r 0.300 0.675 1.000 0.100 ? (v cco /2) ? 0.150 (v cco /2) + 0.150 8.9 ?8.9 diff_sstl15 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 13.0 ?13.0 diff_sstl15_r 0.300 0.750 1.125 0.100 ? (v cco /2) ? 0.175 (v cco /2) + 0.175 8.9 ?8.9 diff_sstl18_i 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.470 (v cco /2) + 0.470 8.00 ?8.00 diff_sstl18_ii 0.300 0.900 1.425 0.100 ? (v cco /2) ? 0.600 (v cco /2) + 0.600 13.4 ?13.4 notes: 1. v icm is the input common mode voltage. 2. v id is the input differential voltage (q ? q ). 3. v ol is the single-ended low-output voltage. 4. v oh is the single-ended high-output voltage. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 14 lvds dc specifications (lvds_25) the lvds_25 standard is available in the hr i/o banks. lvds dc specifications (lvds) the lvds standard is available in the hp i/o banks. ta bl e 1 4 : lvds_25 dc specifications (1) symbol dc parameter conditions min typ max units v cco supply voltage 2.375 2.500 2.625 v v oh output high voltage for q and q r t = 100 across q and q signals ? ? 1.675 v v ol output low voltage for q and q r t = 100 across q and q signals 0.700 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q =high r t = 100 across q and q signals 247 350 600 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.000 1.250 1.425 v v idiff differential input voltage (q ? q ), q = high (q ?q), q =high 100 350 600 mv v icm input common-mode voltage 0.300 1.200 1.500 v notes: 1. differential inputs for lvds_25 can be placed in banks with v cco levels that are different from the required level for outputs. consult the 7 series fpgas selectio resources user guide ( ug471 ) for more information. ta bl e 1 5 : lvds dc specifications (1) symbol dc parameter conditions min typ max units v cco supply voltage 1.710 1.800 1.890 v v oh output high voltage for q and q r t = 100 across q and q signals ? ? 1.675 v v ol output low voltage for q and q r t = 100 across q and q signals 0.825 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q =high r t = 100 across q and q signals 247 350 600 mv v ocm output common-mode voltage r t = 100 across q and q signals 1.000 1.250 1.425 v v idiff differential input voltage (q ? q ), q = high (q ?q), q =high common-mode input voltage = 1.25v 100 350 600 mv v icm input common-mode voltage differential input voltage = 350 mv 0.300 1.200 1.425 v notes: 1. differential inputs for lvds can be placed in banks with v cco levels that are different from the required level for outputs. consult the 7series fpgas selectio resources user guide ( ug471 ) for more information. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 15 ac switching characteristics all values represented in this data sheet are based on th e speed specifications in the ise? design suite 14.7 and vivado? design suite 2015.4 as outlined in ta bl e 1 6 . switching characteristics are specified on a per-speed-grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance product specification these specifications are based on simulati ons only and are typically available soon after device design specifications are frozen. although speed grades with this designation are cons idered relatively stable and conservative, some under- reporting might still occur. preliminary product specification these specifications ar e based on complete es (engineer ing sample) silicon characterizati on. devices and speed grades with this designation are intended to give a better indication of the expec ted performance of production silicon. the probability of under-repo rting delays is greatly reduced as compared to advance data. production product specification these specifications ar e released once enough produc tion silicon of a particular de vice family member has been characterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal not ification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. testing of ac switching characteristics internal timing parameters are derived from measuring internal test patterns. all ac switching characteristics are representative of worst-case supply voltage and junction temperature conditions. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. unless otherwise noted, values apply to all zynq-7000 devices. speed grade designations since individual family members are produced at different ti mes, the migration from one category to another depends completely on the status of the fabrication process for each device. ta bl e 1 7 correlates the current status of each zynq-7000 device on a per speed grade basis. ta bl e 1 6 : zynq-7000 all programmable soc speed specification version by device ise 14.7 vivado 2015.4 device 1.08 1.11 xc7z030 and xc7z045 n/a 1.11 xc7z035 and xc7z100 n/a 1.09 xa7z030 1.06 1.10 xq7z030 and xq7z045 n/a 1.10 XQ7Z100 ta bl e 1 7 : zynq-7000 device speed grade designations device speed grade designations advance preliminary production xc7z030 -3, -2, -2li, -1 xc7z035 -3, -2, -2li, -1 xc7z045 -3, -2, -2li, -1 xc7z100 -2, -2li, -1 xa7z030 -1i, -1q s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 16 production silicon and software status in some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (advance, preliminary, production). any labeling discrepancies are corrected in subsequent speed specification releases. ta bl e 1 8 lists the production released zynq-7000 device, speed grade, and the minimum corresponding supported speed specification version and software revisions. the software and speed specifications listed are the minimum releases required for production. all subsequent releases of software and speed specifications are valid. selecting the correct speed grade and voltage in the vivado tools it is important to select the correct device speed grade and voltage in the vivado tools for the device that you are selecting. to select the -3, -2, or -1 (pl 1.0v) speed s pecifications in the vivado tools, select the zynq-7000 , xa zynq-7000 , or defense grade zynq-7000 sub-family, and then select the part name that is the device name followed by the package name followed by the speed grade. for example, select the xc7z030fbg676-3 part name for the xc7z030 device in the fbg676 package and -3 speed grade. to select the -2li (pl 0.95v) speed specifications in the vivado tools, select the zynq-7000 sub-family and then select the part name that is the device name followed by an i followed by the package name followed by the speed grade. for example, select the xc7z030ifbg676-2l part name for the xc7z030 device in the fbg676 package and -2li (pl 0.95v) speed grade. the -2li (pl 0.95v) speed specificati ons are not supported in the ise tools. a similar part naming convention applies to the speed specifications selection in the ise tools for supported devices. see ta bl e 1 8 for the subset of zynq-7000 devices supported in the ise tools. xq7z030 -2i, -2li, -1i, -1q xq7z045 -2i, -2li, -1i, -1q, -1lq XQ7Z100 -2i, -2li, -1i ta bl e 1 8 : zynq-7000 device production software and speed specification release device speed grade designations -3e -2e -2i -2li -1c -1i -1q -1lq xc7z030 ise tools 14.5 v1.06 and vivado tools 2013.1 v1.06 vivado tools 2014.4 v1.11 ise tools 14.5 v1.06 and vivado tools 2013.1 v1.06 n/a n/a xc7z035 vivado tools 2014.4 v1.11 n/a n/a xc7z045 ise tools 14.5 v1.06 and vivado tools 2013.1 v1.06 vivado tools 2014.4 v1.11 ise tools 14.5 v1.06 and vivado tools 2013.1 v1.06 n/a n/a xc7z100 n/a n/a vivado tools 2013.2 v1.07 vivado tools 2014.4 v1.11 n/a vivado tools 2013.2 v1.07 n/a n/a xa7z030 n/a n/a n/a n/a n/a vivado tools 2014.2 v1.08 n/a xq7z030 n/a n/a ise tools 14.7 v1.06 and vivado tools 2013.3 v1.06 vivado tools 2015.4 v1.10 n/a ise tools 14.7 v1.06 and vivado tools 2013.3 v1.06 n/a xq7z045 n/a n/a n/a vivado tools 2015.2 v1.09 XQ7Z100 n/a n/a vivado tools 2015.4 v1.10 n/a vivado tools 2015.2 v1.09 n/a n/a ta bl e 1 7 : zynq-7000 device speed grade designations (cont?d) device speed grade designations advance preliminary production s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 17 ps performance characteristics for further design requirement details, refer to the zynq-7000 all programmable soc technical reference manual ( ug585 ). ta bl e 1 9 : cpu clock domains performance symbol clock ratio description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq f cpu_6x4x_621_max (1)(2) 6:2:1 maximum cpu clock frequency 1000 800 667 667 mhz f cpu_3x2x_621_max maximum cpu_3x clock frequency 500 400 333 333 mhz f cpu_2x_621_max maximum cpu_2x clock frequency 333 266 222 222 mhz f cpu_1x_621_max maximum cpu_1x clock frequency 167 133 111 111 mhz f cpu_6x4x_421_max (1) 4:2:1 maximum cpu clock frequency 710 600 533 533 mhz f cpu_3x2x_421_max maximum cpu_3x clock frequency 355 300 267 267 mhz f cpu_2x_421_max maximum cpu_2x clock frequency 355 300 267 267 mhz f cpu_1x_421_max maximum cpu_1x clock frequency 178 150 133 133 mhz notes: 1. the maximum frequency during bootrom execution is 500 mhz across all speed specifications. 2. when the processor cores operate f cpu_6x4x_621_max at 1 ghz (-3e speed grade), the v ccpint minimum is 0.97v and the v ccpint maximum is 1.03v. ta bl e 2 0 : ps ddr clock domains performance (1) symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq f ddr3_max maximum ddr3 interface performance 1333 (2) 1066 1066 1066 mb/s f ddr3l_max maximum ddr3l interface performance 1066 1066 1066 1066 mb/s f ddr2_max maximum ddr2 interface performance 800 800 800 800 mb/s f lpddr2_max maximum lpddr2 interface performance 800 800 800 800 mb/s f ddrclk_2xmax maximum ddr_2x clock frequency 444 408 355 355 mhz notes: 1. all performance numbers apply to both internal and external v ref configurations. 2. when a ddr interface operates at 1333 mb/s, the v ccpint minimum is 0.97v and the v ccpint maximum is 1.03v. ta bl e 2 1 : ps-pl interface performance symbol description min max units f emiogemclk emio gigabit ethernet controller maximum frequency ? 125 mhz f emiosdclk emio sd controller maximum frequency ? 25 mhz f emiospiclk emio spi controller maximum frequency ? 25 mhz f emiojtagclk emio jtag controller maximum frequency ? 20 mhz f emiotraceclk emio trace controller maximum frequency ? 125 mhz f ftmclk fabric trace monitor maximum frequency ? 125 mhz f emiodmaclk dma maximum frequency ? 100 mhz f axi_max maximum axi interface performance ? 250 mhz s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 18 ps switching characteristics clocks resets the ps_por_b deassertion must meet the following requirements to avoid coinciding with the secure lockdown window. figure 1 shows the timing relationship between ps_por_b and the last power supply ramp (v ccint , v ccbram , v ccaux , or v cco in bank 0). t slw minimum and maximum parameters define the beginning and end, respectively, of the secure lockdown window relative to the last pl power supply reaching 250 mv. the ps_por_b must not be deasserted within the secure lockdown window. ta bl e 2 2 : system reference clock input requirements symbol description min typ max units t jtpsclk ps_clk rms clock jitter tolerance ? ? 0.5 % t dcpsclk ps_clk duty cycle 40 ? 60 % t rfpsclk ps_clk rise and fall time ? ? 6 ns f psclk ps_clk frequency 30 ? 60 mhz ta bl e 2 3 : ps pll switching characteristics symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq t lock_pspll pll maximum lock time 60 60 60 60 s f pspll_max pll maximum output frequency 2000 1800 1600 1600 mhz f pspll_min pll minimum output frequency 780 780 780 780 mhz ta bl e 2 4 : ps reset assertion timing requirements symbol description min typ max units t pspor required ps_por_b assertion time (1) 100 ? ? s t psrst required ps_srst_b assertion time 3 ? ? ps_clk clock cycles notes: 1. ps_por_b needs to be asserted low until ps supply voltages reach minimum levels. x-ref target - figure 1 figure 1: ps_por_b and power supply ramp timing requirements p s _por_b l as t r a mping pl su pply s ec u re lockdown window do not de ass ert p s _por_b t s lw(min) t s lw(m a x) 250 mv d s 191_21_022015 s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 19 ps configuration ddr memory interfaces ta bl e 2 5 : ps reset/power supply timing requirements symbol description ps_clk frequency (mhz) min max units t slw (1) 128 kb crc efuse disabled and pll enabled. default configuration 30 12 39 ms 33.33 12 40 ms 60 13 40 ms 128 kb crc efuse disabled and pll in bypass. 30 ?32 13 ms 33.33 ?27 13 ms 60 ?9 25 ms 128 kb crc efuse enabled and pll enabled. (2) 30 ?19 9 ms 33.33 ?16 12 ms 60 ?3 25 ms 128 kb crc efuse enabled and pll in bypass. (2) 30 ?830 ?788 ms 33.33 ?746 ?705 ms 60 ?408 ?374 ms notes: 1. valid for power supply ramp times of less than 6 ms. for ramp times longer than 6 ms, see the bootrom performance section of th e zynq- 7000 all programmable soc technical reference manual ( ug585 ). 2. if any ps and pl power supplies are tied together , observe the ps_por_b assertion time requirement (t pspor ) in ta b l e 2 4 and its accompanying note. ta bl e 2 6 : processor configuration access port switching characteristics symbol description min typ max units f pcapck maximum processor configuration access port (pcap) frequency ? ? 100 mhz ta bl e 2 7 : ddr3 interface switching ch aracteristics (1333 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 450 ? ps t dqds (3) output dq to dqs skew 95 ? ps t dqdh (4) output dqs to dq skew 222 ? ps t dqss output clock to dqs skew ?0.11 0.08 t ck t cack (5) command/address output setup time with respect to clk 465 ? ps t ckca (6) command/address output hold time with respect to clk 528 ? ps notes: 1. recommended v cco_ddr =1.5v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 20 ta bl e 2 8 : ddr3 interface switching ch aracteristics (1066 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 450 ? ps t dqds (3) output dq to dqs skew 100 ? ps t dqdh (4) output dqs to dq skew 350 ? ps t dqss output clock to dqs skew ?0.10 0.10 t ck t cack (5) command/address output setup time with respect to clk 560 ? ps t ckca (6) command/address output hold time with respect to clk 658 ? ps notes: 1. recommended v cco_ddr =1.5v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. ta bl e 2 9 : ddr3l interface switching ch aracteristics (1066 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 450 ? ps t dqds (3) output dq to dqs skew 189 ? ps t dqdh (4) output dqs to dq skew 267 ? ps t dqss output clock to dqs skew ?0.13 0.04 t ck t cack (5) command/address output setup time with respect to clk 410 ? ps t ckca (6) command/address output hold time with respect to clk 629 ? ps notes: 1. recommended v cco_ddr = 1.35v 5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. ta bl e 3 0 : ddr3l interface switching ch aracteristics (800 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 500 ? ps t dqds (3) output dq to dqs skew 321 ? ps t dqdh (4) output dqs to dq skew 380 ? ps t dqss output clock to dqs skew ?0.12 0.04 t ck t cack (5) command/address output setup time with respect to clk 636 ? ps s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 21 t ckca (6) command/address output hold time with respect to clk 853 ? ps notes: 1. recommended v cco_ddr = 1.35v 5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. ta bl e 3 1 : lpddr2 interface switching characteristics (800 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 500 ? ps t dqds (3) output dq to dqs skew 111 ? ps t dqdh (4) output dqs to dq skew 318 ? ps t dqss output clock to dqs skew 0.91 1.10 t ck t cack (5) command/address output setup time with respect to clk 132 ? ps t ckca (6) command/address output hold time with respect to clk 363 ? ps notes: 1. recommended v cco_ddr =1.2v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. ta bl e 3 2 : lpddr2 interface switching characteristics (400 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 500 ? ps t dqds (3) output dq to dqs skew 561 ? ps t dqdh (4) output dqs to dq skew 852 ? ps t dqss output clock to dqs skew 0.91 1.08 t ck t cack (5) command/address output setup time with respect to clk 617 ? ps t ckca (6) command/address output hold time with respect to clk 918 ? ps notes: 1. recommended v cco_ddr =1.2v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. ta bl e 3 0 : ddr3l interface switching ch aracteristics (800 mb/s) (1) (cont?d) symbol description min max units s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 22 ta bl e 3 3 : ddr2 interface switching ch aracteristic s (800 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 500 ? ps t dqds (3) output dq to dqs skew 147 ? ps t dqdh (4) output dqs to dq skew 376 ? ps t dqss output clock to dqs skew ?0.07 0.08 t ck t cack (5) command/address output setup time with respect to clk 732 ? ps t ckca (6) command/address output hold time with respect to clk 938 ? ps notes: 1. recommended v cco_ddr =1.8v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. ta bl e 3 4 : ddr2 interface switching ch aracteristic s (400 mb/s) (1) symbol description min max units t dqvalid (2) input data valid window 500 ? ps t dqds (3) output dq to dqs skew 385 ? ps t dqdh (4) output dqs to dq skew 662 ? ps t dqss output clock to dqs skew ?0.11 0.06 t ck t cack (5) command/address output setup time with respect to clk 1760 ? ps t ckca (6) command/address output hold time with respect to clk 1739 ? ps notes: 1. recommended v cco_ddr =1.8v5%. 2. measurement is taken from v ref to v ref . 3. measurement is taken from either the rising edge of dq that crosses v ih (ac) or the falling edge of dq that crosses v il (ac) to v ref of dqs. 4. measurement is taken from either the rising edge of dq that crosses v il (dc) or the falling edge of dq that crosses v ih (dc) to v ref of dqs. 5. measurement is taken from either the rising edge of cmd/addr that crosses v ih (ac) or the falling edge of cmd/addr that crosses v il (ac) to v ref of clk. 6. measurement is taken from either the rising edge of cmd/addr that crosses v il (dc) or the falling edge of cmd/addr that crosses v ih (dc) to v ref of clk. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 23 x-ref target - figure 2 figure 2: ddr output timing diagram x-ref target - figure 3 figure 3: ddr input timing diagram write nop nop nop nop b a nk, col n d0 d1 d 3 t dqdh t dqd s t dqdh t dqd s t dq ss t ckca t cack t ckca t cack d s 191_01_052714 clk clk comm a nd addre ss dq s dq s dq d2 d0 d1 d2 d 3 t dqvalid clk clk dq s dq s dq d s 191_02_052714 s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 24 static memory controller ta bl e 3 5 : smc interface delay characteristics (1)(2) symbol description min max units t nanddout nand_io output delay from last register to pad 4.12 6.45 ns t nandale nand_ale output delay from last register to pad 5.08 6.33 ns t nandcle nand_cle output delay from last register to pad 4.87 6.40 ns t nandwe nand_we_b output delay from last register to pad 4.69 5.89 ns t nandre nand_re_b output delay from last register to pad 5.12 6.44 ns t nandce nand_ce_b output delay from last register to pad 4.68 5.89 ns t nanddin nand_io setup time and input delay from pad to first register 1.48 3.09 ns t nandbusy nand_busy setup time and input delay from pad to first register 2.48 3.33 ns t srama sram_a output delay from last register to pad 3.94 5.73 ns t sramdout sram_dq output delay from last register to pad 4.66 6.45 ns t sramce sram_ce output delay from last register to pad 4.57 5.95 ns t sramoe sram_oe_b output delay from la st register to pad 4.79 6.13 ns t srambls sram_bls_b output delay from last register to pad 5.25 6.74 ns t sramwe sram_we_b output delay from last register to pad 5.12 6.48 ns t sramdin sram_dq setup time and input delay from pad to first register 1.93 3.05 ns t sramwait sram_wait setup time and input delay from pad to first register 2.26 3.15 ns f smc_ref_clk smc reference clock frequency ? 100 mhz notes: 1. all parameters do not include the package flight time and register controlled delays. 2. refer to the arm? primecell? static memo ry controller (pl350 series) technical reference manual for more smc timing details. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 25 quad-spi interfaces ta bl e 3 6 : quad-spi interface switching characteristics symbol description load conditions min max units feedback clock enabled t dcqspiclk1 quad-spi clock duty cycle all (1)(2) 44 56 % t qspicko1 data and slave select output delay 15 pf (1) ?0.10 (3) 2.30 ns 30 pf (2) ?1.00 3.80 t qspidck1 input data setup time 15 pf (1) 2.00 ? ns 30 pf (2) 3.30 ? t qspickd1 input data hold time 15 pf (1) 1.30 ? ns 30 pf (2) 1.50 ? t qspissclk1 slave select asserted to next clock edge all (1)(2) 1?f qspi_ref_clk cycle t qspiclkss1 clock edge to slave select deasserted all (1)(2) 1?f qspi_ref_clk cycle f qspiclk1 quad-spi device clock frequency 15 pf (1) ? 100 (4) mhz 30 pf (2) ?70 (4) feedback clock disabled t dcqspiclk2 quad-spi clock duty cycle all (1)(2) 44 56 % t qspicko2 data and slave select output delay 15 pf (1) ?0.10 3.80 ns 30 pf (2) ?1.00 3.80 ns t qspidck2 input data setup time all (1)(2) 6?ns t qspickd2 input data hold time all (1)(2) 12.5 ? ns t qspissclk2 slave select asserted to next clock edge all (1)(2) 1?f qspi_ref_clk cycle t qspiclkss2 clock edge to slave select deasserted all (1)(2) 1?f qspi_ref_clk cycle f qspiclk2 quad-spi device clock frequency all (1)(2) ?40mhz feedback clock enabled or disabled f qspi_ref_clk quad-spi reference clock frequency all (1)(2) ?200mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads, feedback clock pin has no load. quad-spi single sl ave select 4-bit i/o mode. 2. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 30 pf loads in 4-bit stacked i/o configuration, feedback clock pin has no load. quad-spi single slave select 4-bit i/o mode. 3. the t qspicko1 is an effective value. use it to compute the available memory device input setup and hold timing budgets based on the given device clock-out duty-cycle limits. 4. requires appropriate component selection/board design. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 26 x-ref target - figure 4 figure 4: quad-spi interface (feedback clock enabled) timing diagram x-ref target - figure 5 figure 5: quad-spi interface (feedback clock disabled) timing diagram q s pi{1,0}_ ss _b q s pi_ s clk_out cpol = 0 q s pi{1,0}_io_[ 3 ,0] q s pi_ s clk_out cpol = 1 d s 191_0 3 _110615 t q s picko1 t q s pi ss clk1 t q s pi ss clk1 t q s piclk ss 1 t q s piclk ss 1 t q s pidck1 t q s pickd1 out1 out0 inn-2 inn-1 inn out0 out1 inn-1 q s pi{1,0}_ ss _b q s pi_ s clk_out (cpol = 0) q s pi_ s clk_out (cpol = 1) q s pi{0,1}_io_[ 3 :0] t q s pickd2 t q s pidck2 t q s picko2 t q s piclk ss 2 t q s pi ss clk2 t q s piclk ss 2 t q s pi ss clk2 inn d s 191_04_110615 s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 27 ulpi interfaces ta bl e 3 7 : ulpi interface clock receiving mode switching characteristics (1)(2) symbol description min typ max units t ulpidck input setup to ulpi clock, all inputs 3.00 ? ? ns t ulpickd input hold to ulpi clock, all inputs 1.00 ? ? ns t ulpicko ulpi clock to output valid, all outputs 1.70 ? 8.86 ns f ulpiclk ulpi device clock frequency ? 60 ? mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads, 60 mhz device clock frequency. 2. all timing values assume an ideal external input clock. actual design system timing budgets should account for additional ext ernal clock jitter. x-ref target - figure 6 figure 6: ulpi interface timing diagram t ulpicko t ulpicko t ulpickd t ulpidck t ulpickd t ulpidck u s b{0,1}_ulpi_clk u s b{0,1}_ulpi_data[7:0] (inp u t) u s b{0,1}_ulpi_dir, u s b{0,1}_ulpi_nxt u s b{0,1}_ulpi_ s tp u s b{0,1}_ulpi_data[7:0] (o u tp u t) d s 191_05_02201 3 s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 28 rgmii and mdio interfaces ta bl e 3 8 : rgmii and mdio interface switching characteristics (1)(2)(3) symbol description min typ max units t dcgetxclk transmit clock duty cycle 45 ? 55 % t gemtxcko rgmii_tx_d[3:0], rgmii_tx_ctl output clock to out time ?0.50 ? 0.50 ns t gemrxdck rgmii_rx_d[3:0], rgmii_rx_ctl input setup time 0.80 ? ? ns t gemrxckd rgmii_rx_d[3:0], rgmii_rx_ctl input hold time 0.80 ? ? ns t mdioclk mdc output clock period 400 ? ? ns t mdiockh mdc clock high time 160 ? ? ns t mdiockl mdc clock low time 160 ? ? ns t mdiodck mdio input data setup time 80 ? ? ns t mdiockd mdio input data hold time 0 ? ? ns t mdiocko mdio data output delay ?20 ? 170 ns f getxclk rgmii_tx_clk transmit clock frequency ? 125 ? mhz f gerxclk rgmii_rx_clk receive clock frequency ? 125 ? mhz f enet_ref_clk ethernet reference clock frequency ? 125 ? mhz notes: 1. test conditions: lvcmos25, fast slew rate, 8 ma drive strength, 15 pf loads. values in this table are specified during 1000 mb/s operation. 2. lvcmos25 slow slew rate and lvcmos33 are not supported. 3. all timing values assume an ideal external input clock. actual design system timing budgets should account for additional ext ernal clock jitter. x-ref target - figure 7 figure 7: rgmii interface timing diagram rgmii_tx_clk mdio_clk rgmii_rx_clk t gemtxcko t mdiockh t mdioclk t mdiockl t gemrxckd rgmii_tx_d[ 3 :0] rgmii_tx_ctl rgmii_rx_d[ 3 :0] rgmii_rx_ctl t gemrxdck t mdiockd mdio_io (inp u t) t mdiodck d s 191 _06_02201 3 mdio_io (o u tp u t) t mdiocko s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 29 sd/sdio interfaces ta bl e 3 9 : sd/sdio interface high speed mode switching characteristics (1) symbol description min typ max units t dcsdhsclk sd device clock duty cycle ? 50 ? % t sdhscko clock to output delay, all outputs 2.00 ? 12.00 ns t sdhsdck input setup time, all inputs 3.00 ? ? ns t sdhsckd input hold time, all inputs 1.05 ? ? ns f sd_ref_clk sd reference clock frequency ? ? 125 mhz f sdhsclk high speed mode sd device clock frequency 0 ? 50 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 8 figure 8: sd/sdio interface high speed mode timing diagram ta bl e 4 0 : sd/sdio interface switching characteristics (1) symbol description min typ max units t dcsdsclk sd device clock duty cycle ? 50 ? % t sdscko clock to output delay, all outputs 2.00 ? 12.00 ns t sdsdck input setup time, all inputs 4.00 ? ? ns t sdsckd input hold time, all inputs 3.00 ? ? ns f sd_ref_clk sd reference clock frequency ? ? 125 mhz f sdidclk clock frequency in identification mode ? ? 400 khz f sdsclk standard mode sd device clock frequency 0 ? 25 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 9 figure 9: sd/sdio interface standard mode timing diagram t s dh s cko t s dh s ckd t s dh s dck s d{0,1}_clk s d{0,1}_data[ 3 :0], s d{0,1}_cmd (inp u t) s d{0,1}_data[ 3 :0], s d{0,1}_cmd (o u tp u t) d s 191 _07_02201 3 d s 191_10 8 _0 3 011 3 t s d s cko t s d s ckd t s d s dck s d{0,1}_clk s d{0,1}_data[ 3 :0], s d{0,1}_cmd (inp u t) s d{0,1}_data[ 3 :0], s d{0,1}_cmd (o u tp u t) s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 30 i2c interfaces ta bl e 4 1 : i2c fast mode interface switching characteristics (1) symbol description min typ max units t dci2cfclk i2c { 0,1}scl duty cycle ? 50 ? % t i2cfcko i2c { 0,1}sdao clock to out delay ? ? 900 ns t i2cfdck i2c { 0,1}sdai setup time 100 ? ? ns f i2cfclk i2c { 0,1}scl clock frequency ? ? 400 khz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 10 figure 10: i2c fast mode interface timing diagram ta bl e 4 2 : i2c standard mode interface switching characteristics (1) symbol description min typ max units t dci2csclk i2c { 0,1}scl duty cycle ? 50 ? % t i2cscko i2c { 0,1}sdao clock to out delay ? ? 3450 ns t i2csdck i2c { 0,1}sdai setup time 250 ? ? ns f i2csclk i2c { 0,1}scl clock frequency ? ? 100 khz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 11 figure 11: i2c standard mode interface timing diagram t i2cfcko t i2cfdck d s 191 _0 8 _02201 3 i2c{0,1} s cl i2c{0,1} s dai i2c{0,1} s dao t i2c s cko t i2c s dck d s 191 _09_02201 3 i2c{0,1} s cl i2c{0,1} s dai i2c{0,1} s dao s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 31 spi interfaces ta bl e 4 3 : spi master mode interface switching characteristics (1) symbol description min typ max units t dcmspiclk spi master mode clock duty cycle ? 50 ? % t mspidck input setup time for spi { 0,1}_miso 2.00 ? ? ns t mspickd input hold time for spi { 0,1}_miso 8.20 ? ? ns t mspicko output delay for spi { 0,1}_mosi and spi { 0,1}_ss ?3.10 ? 3.90 ns t mspissclk slave select asserted to first active clock edge 1 ? ? f spi_ref_clk cycles t mspiclkss last active clock edge to slave select deasserted 0.5 ? ? f spi_ref_clk cycles f mspiclk spi master mode device clock frequency ? ? 50.00 mhz f spi_ref_clk spi reference clock frequency ? ? 200.00 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. x-ref target - figure 12 figure 12: spi master (cpha = 0) interface timing diagram x-ref target - figure 13 figure 13: spi master (cpha = 1) interface timing diagram dn dn?1 dn?2 dn? 3 d0 dn dn?1 dn?2 t m s pickd t m s pidck t m s picko t m s piclk ss t m s pi ss clk s pi{0,1}_ ss s pi{0,1}_clk (cpol=0) s pi{0,1}_clk (cpol=1) s pi{0,1}_mo s i s pi{0,1}_mi s o d s 191 _10_02201 3 dn dn?1 dn?2 dn? 3 d0 dn dn?1 dn?2 dn? 3 d0 t m s pickd t m s pidck t m s picko t m s piclk ss t m s pi ss clk s pi{0,1}_ ss s pi{0,1}_clk (cpol=0) s pi{0,1}_clk (cpol=1) s pi{0,1}_mo s i s pi{0,1}_mi s o d s 191_11_02201 3 s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 32 ta bl e 4 4 : spi slave mode interface switching characteristics (1)(2) symbol description min max units t sspidck input setup time for spi { 0,1}_mosi and spi { 0,1}_ss 1 ? f spi_ref_clk cycles t sspickd input hold time for spi { 0,1}_mosi and spi { 0,1}_ss 1 ? f spi_ref_clk cycles t sspicko output delay for spi { 0,1}_miso 0 2.6 f spi_ref_clk cycles t sspissclk slave select asserted to first active clock edge 1 ? f spi_ref_clk cycles t sspiclkss last active clock edge to slave select deasserted 1 ? f spi_ref_clk cycles f sspiclk spi slave mode device clock frequency ? 25 mhz f spi_ref_clk spi reference clock frequency ? 200 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. 2. all timing values assume an ideal external input clock. actual design system timing budgets should account for additional ext ernal clock jitter. x-ref target - figure 14 figure 14: spi slave (cpha = 0) interface timing diagram x-ref target - figure 15 figure 15: spi slave (cpha = 1) interface timing diagram dn dn?1 dn?2 dn? 3 d0 dn dn?1 dn?2 dn? 3 d0 t ss picko t ss pickd t ss pidck t ss piclk ss t ss pi ss clk s pi{0,1}_ ss s pi{0,1}_clk (cpol=0) s pi{0,1}_clk (cpol=1) s pi{0,1}_mo s i s pi{0,1}_mi s o d s 191_12_02201 3 dn dn?1 dn?2 dn? 3 d0 dn dn?1 dn?2 dn? 3 d0 t ss picko t ss pickd t ss pidck t ss piclk ss t ss pi ss clk s pi{0,1}_ ss s pi{0,1}_clk (cpol=0) s pi{0,1}_clk (cpol=1) s pi{0,1}_mo s i s pi{0,1}_mi s o d s 191 _1 3 _02101 3 s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 33 can interfaces pjtag interfaces uart interfaces ta bl e 4 5 : can interface switchin g characteristics (1) symbol description min max units t pwcanrx minimum receive pulse width 1 ? s t pwcantx minimum transmit pulse width 1 ? s f can_ref_clk internally sourced can reference clock frequency ? 100 mhz externally sourced can reference clock frequency ? 40 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. ta bl e 4 6 : pjtag interface (1)(2) symbol description min max units t pjtagdck pjtag input setup time 2.4 ? ns t pjtagckd pjtag input hold time 2.0 ? ns t pjtagcko pjtag clock to out delay ? 12.5 ns t pjtagclk pjtag clock frequency ? 20 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. 2. all timing values assume an ideal external input clock. actual design system timing budgets should account for additional ext ernal clock jitter. x-ref target - figure 16 figure 16: pjtag interface timing diagram ta bl e 4 7 : uart interface switching characteristics (1) symbol description min max units baud txmax maximum transmit baud rate ? 1 mb/s baud rxmax maximum receive baud rate ? 1 mb/s f uart_ref_clk uart reference clock frequency ? 100 mhz notes: 1. test conditions: lvcmos33, slow slew rate, 8 ma drive strength, 15 pf loads. pjtagclk pjtagtm s , pjtagtdi pjtagtdo t pjtagdck t pjtagckd t pjtagcko d s 191 _14_02201 3 s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 34 gpio interfaces trace interface triple timer counter interface watchdog timer ta bl e 4 8 : gpio banks switching characteristics (1) symbol description min max units t pwgpioh input high pulse width 10 x 1/cpu1x ? s t pwgpiol input low pulse width 10 x 1/cpu1x ? s notes: 1. pulse width requirement for interrupt. x-ref target - figure 17 figure 17: gpio interface timing diagram ta bl e 4 9 : trace interface switching characteristics (1) symbol description min max units t tcecko trace clock to output de lay, all outputs ?1.4 1.5 ns t dctceclk trace clock duty cycle 40 60 % f tceclk trace clock frequency ? 80 mhz notes: 1. test conditions: lvcmos25, fast slew rate, 8 ma drive strength, 15 pf loads. ta bl e 5 0 : triple timer counter interface switching characteristics (1) symbol description min max units t pwttcoclk triple timer counter output clock pulse width 2 x 1/cpu1x ? ns f ttcoclk triple timer counter output clock frequency ? cpu1x/4 mhz t ttciclkh triple timer counter input clock high pulse width 1.5 x 1/cpu1x ? ns t ttciclkl triple timer counter input clock low pulse width 1.5 x 1/cpu1x ? ns f ttciclk triple timer counter input clock frequency ? cpu1x/3 mhz notes: 1. all timing values assume an ideal external input clock. actual design system timing budgets should account for additional ext ernal clock jitter. ta bl e 5 1 : watchdog timer switching characteristics symbol descripti on min max units f wdtclk (1) watchdog timer input clock frequency ? 10 mhz notes: 1. applies to external input clock through mio pin only. t pwgpiol t pwgpioh gpio d s 191 _15_02201 3 s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 35 pl performance characteristics this section provides the performance characteristics of so me common functions and designs implemented in the pl. the numbers reported here are worst-case values; they have all been fully characterized. these values are subject to the same guidelines as the ac switching characteristics, page 15 . in each table, the i/o bank type is either high performance (hp) or high range (hr). ta bl e 5 3 provides the maximum data rates for applicable memo ry standards using the zynq-7000 ap soc memory phy. the final performance of the memory interface is determined through a complete design implemented in the vivado or ise design suite, following guidelines in the zynq-7000 ap soc and 7 series devices memory interface solutions user guide ( ug586 ). ta bl e 5 2 : pl networking applications interface performances description i/o bank type speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq sdr lvds transmitter (using oserdes; data_width = 4 to 8) hr 710 710 625 625 mb/s hp 710 710 625 625 mb/s ddr lvds transmitter (using oserdes; data_width = 4 to 14) hr 1250 1250 950 950 mb/s hp 1600 1400 1250 1250 mb/s sdr lvds receiver (sfi-4.1) (1) hr 710 710 625 625 mb/s hp 710 710 625 625 mb/s ddr lvds receiver (spi-4.2) (1) hr 1250 1250 950 950 mb/s hp 1600 1400 1250 1250 mb/s notes: 1. lvds receivers are typically bounded with certain applications where specific dynamic phase-alignment (dpa) algorithms domina te deterministic performance. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 36 ta bl e 5 3 : maximum physical interface (phy) rate for memory interfaces ip available with the memory interface generator (ff and rf packages) (1)(2) memory standard i/o bank type v ccaux_io speed grade units -3e -2e/-2i -2li -1c/-1i -1q/-1lq 4:1 memory controllers ddr3 hp 2.0v 1866 (3) 1866 (3) 1600 1600 1066 mb/s hp 1.8v 1600 1333 1333 1066 800 mb/s hr n/a 1066 1066 1066 800 800 mb/s ddr3l hp 2.0v 1600 1600 1600 1333 1066 mb/s hp 1.8v 1333 1066 1066 800 800 mb/s hr n/a 800 800 800 667 n/a mb/s ddr2 hp 2.0v 800 800 800 800 667 mb/s hp 1.8v 800 800 800 800 667 mb/s hr n/a 800 800 800 800 533 mb/s rldram iii hp 2.0v 800 667 667 667 550 mhz hp 1.8v 550 500 500 450 400 mhz hr n/a n/a 2:1 memory controllers ddr3 hp 2.0v 1066 1066 1066 800 667 mb/s hp 1.8v mb/s hr n/a mb/s ddr3l hp 2.0v 1066 1066 1066 800 667 mb/s hp 1.8v mb/s hr n/a 800 800 800 667 n/a mb/s ddr2 hp 2.0v 800 800 800 800 667 mb/s hp 1.8v 667 hr n/a 533 qdr ii+ (4) hp 2.0v 550 500 500 450 300 mhz hp 1.8v hr n/a 500 450 450 400 300 mhz rldram ii hp 2.0v 533 500 500 450 400 mhz hp 1.8v hr n/a lpddr2 hp 2.0v 667 667 667 667 533 mb/s hp 1.8v mb/s hr n/a mb/s notes: 1. v ref tracking is required. for more information, see the zynq-7000 ap soc and 7 series devices memory interface solutions user guide ( ug586 ). 2. when using the internal v ref , the maximum data rate is 800 mb/s (400 mhz). 3. for designs using 1866 mb/s components, contact xilinx technical support . 4. the maximum qdrii+ performance specifications are for burst-l ength 4 (bl = 4) implementations. burst length 2 (bl = 2) implementa tions are limited to 333 mhz for all speed grades and i/o bank types. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 37 ta bl e 5 4 : maximum physical interface (phy) rate for memory interfaces ip available with the memory interface generator (fb, rb, and sb packages) (1)(2) memory standard i/o bank type v ccaux_io (3) speed grade units -3e -2e/-2i/-2li -1c/-1i -1q 4:1 memory controllers ddr3 hp n/a 1333 1066 800 800 mb/s hr n/a 1066 800 800 800 mb/s ddr3l hp n/a 1066 800 667 667 mb/s hr n/a 800 800 667 n/a mb/s ddr2 hp n/a 800 800 800 667 mb/s hr n/a 800 667 667 533 mb/s rldram iii hp n/a 550 500 450 350 mhz hr n/a n/a 2:1 memory controllers ddr3 hp n/a 1066 1066 800 667 mb/s hr n/a 1066 800 800 667 mb/s ddr3l hp n/a 1066 800 667 667 mb/s hr n/a 800 800 667 n/a mb/s ddr2 hp n/a 800 800 800 667 mb/s hr n/a 800 667 667 533 mb/s qdr ii+ (4) hp n/a 550 500 450 300 mhz hr n/a 450 400 350 300 mhz rldram ii hp n/a 533 500 450 400 mhz hr n/a lpddr2 hp n/a 667 667 667 400 mb/s hr n/a 667 667 533 400 mb/s notes: 1. v ref tracking is required. for more information, see the zynq-7000 ap soc and 7 series devices memory interface solutions user guide ( ug586 ). 2. when using the internal v ref , the maximum data rate is 800 mb/s (400 mhz). 3. fb, rb, and sb packages do not have separate v ccaux_io supply pins to adjust the pre-driver voltage of the hp i/o banks. 4. the maximum qdrii+ performance specifications are for burst-l ength 4 (bl = 4) implementations. burst length 2 (bl = 2) implementa tions are limited to 333 mhz for all speed grades and i/o bank types. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 38 pl switching characteristics iob pad input/output/3-state ta bl e 5 5 (high-range iob (hr)) and ta b l e 5 6 (high-performance iob (hp)) summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. ?t iopi is described as the delay from iob pad through the input buffer to the i-pin of an iob pad. the delay varies depending on the capability of the selectio input buffer. ?t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the capability of the selectio output buffer. ?t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depending on th e selectio capability of th e output buffer. in hp i/o banks, the internal dci termination turn-on time is always faster than t iotp when the dcitermdisable pin is used. in hr i/o banks, the in_term termination turn-on time is always faster than t iotp when the intermdisable pin is used. ta bl e 5 5 : iob high range (hr) switching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq lvttl_s4 1.31 1.42 1.64 1.64 3.77 3.90 4.00 4.00 3.52 3.67 3.86 3.86 ns lvttl_s8 1.31 1.42 1.64 1.64 3.50 3.64 3.73 3.73 3.26 3.40 3.60 3.60 ns lvttl_s12 1.31 1.42 1.64 1.64 3.49 3.62 3.72 3.72 3.24 3.39 3.58 3.58 ns lvttl_s16 1.31 1.42 1.64 1.64 3.03 3.17 3.26 3.26 2.79 2.93 3.13 3.13 ns lvttl_s24 1.31 1.42 1.64 1.64 3.25 3.39 3.48 3.48 3.01 3.15 3.35 3.35 ns lvttl_f4 1.31 1.42 1.64 1.64 3.22 3.36 3.45 3.45 2.98 3.12 3.32 3.32 ns lvttl_f8 1.31 1.42 1.64 1.64 2.71 2.84 2.93 2.93 2.46 2.61 2.80 2.80 ns lvttl_f12 1.31 1.42 1.64 1.64 2.69 2.82 2.92 2.92 2.44 2.59 2.79 2.79 ns lvttl_f16 1.31 1.42 1.64 1.64 2.57 2.85 3.15 3.15 2.33 2.61 3.02 3.02 ns lvttl_f24 1.31 1.42 1.64 1.64 2.41 2.64 2.89 3.04 2.16 2.41 2.76 2.91 ns lvds_25 0.64 0.68 0.80 0. 87 1.36 1.47 1.55 1.55 1.11 1.24 1.41 1.41 ns mini_lvds_25 0.68 0.70 0. 79 0.87 1.36 1.47 1.55 1.55 1.11 1.24 1.41 1.41 ns blvds_25 0.65 0.69 0.80 0.85 1.83 2.02 2.20 2.57 1.59 1.79 2.07 2.44 ns rsds_25 0.63 0.68 0.79 0.87 1.36 1.48 1.55 1.55 1.11 1.24 1.41 1.41 ns ppds_25 0.65 0.69 0.80 0. 87 1.36 1.49 1.58 1.58 1.11 1.25 1.45 1.45 ns tmds_33 0.72 0.76 0.86 0 .90 1.43 1.54 1.60 1.60 1.18 1.31 1.47 1.47 ns pci33_3 1.28 1.41 1.65 1.65 2.71 3.08 3.52 3.52 2.46 2.84 3.39 3.39 ns hsul_12_s 0.63 0.64 0.71 0.85 1.77 1.90 2.00 2.00 1.52 1.67 1.86 1.86 ns hsul_12_f 0.63 0.64 0.71 0.85 1.26 1.40 1.50 1.50 1.01 1.16 1.37 1.37 ns diff_hsul_12_s 0.58 0.61 0. 70 0.84 1.55 1.68 1.78 1.78 1.30 1.45 1.65 1.65 ns diff_hsul_12_f 0.58 0.61 0. 70 0.84 1.16 1.28 1.35 1.35 0.92 1.04 1.21 1.21 ns mobile_ddr_s 0.64 0.66 0.74 0.74 2.58 2.91 3.31 3.31 2.33 2.68 3.17 3.17 ns mobile_ddr_f 0.64 0.66 0.74 0.74 1.91 2.13 2.36 2.36 1.66 1.89 2.23 2.23 ns diff_mobile_ddr_s 0.63 0.66 0.75 0.75 2.51 2.84 3.24 3.24 2.26 2.61 3.10 3.10 ns diff_mobile_ddr_f 0.63 0.66 0.75 0.75 1.89 2.11 2.34 2.34 1.64 1.88 2.21 2.21 ns hstl_i_s 0.61 0.64 0.73 0.84 1.55 1.69 1.80 1.80 1.30 1.46 1.67 1.67 ns s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 39 hstl_ii_s 0.61 0.64 0.73 0.84 1.21 1.34 1.43 1.61 0.96 1.11 1.30 1.47 ns hstl_i_18_s 0.64 0.67 0.76 0.85 1.28 1.39 1.45 1.45 1.04 1.16 1.31 1.32 ns hstl_ii_18_s 0.64 0.67 0.76 0.85 1.18 1.31 1.40 1.57 0.93 1.08 1.27 1.44 ns diff_hstl_i_s 0.63 0.67 0. 77 0.84 1.42 1.54 1.61 1.78 1.17 1.31 1.48 1.65 ns diff_hstl_ii_s 0.63 0.67 0.77 0.84 1.15 1.24 1.27 1.61 0.91 1.01 1.14 1.47 ns diff_hstl_i_18_s 0.65 0.69 0. 78 0.84 1.27 1.38 1.43 1.45 1.03 1.14 1.30 1.32 ns diff_hstl_ii_18_s 0.65 0.69 0.78 0.85 1.14 1.23 1.26 1.57 0.90 1.00 1.13 1.44 ns hstl_i_f 0.61 0.64 0.73 0.84 1.10 1.19 1.23 1.31 0.85 0.96 1.10 1.18 ns hstl_ii_f 0.61 0.64 0.73 0.84 1.05 1.18 1.28 1.31 0.80 0.95 1.15 1.18 ns hstl_i_18_f 0.64 0.67 0.76 0.85 1.05 1.18 1.28 1.36 0.80 0.95 1.15 1.22 ns hstl_ii_18_f 0.64 0.67 0.76 0.85 1.03 1.14 1.23 1.32 0.78 0.90 1.10 1.19 ns diff_hstl_i_f 0.63 0.67 0. 77 0.84 1.09 1.18 1.22 1.31 0.84 0.95 1.09 1.18 ns diff_hstl_ii_f 0.63 0.67 0.77 0.84 1.02 1.11 1.14 1.31 0.77 0.88 1.01 1.18 ns diff_hstl_i_18_f 0.65 0.69 0. 78 0.84 1.08 1.17 1.21 1.36 0.83 0.94 1.07 1.22 ns diff_hstl_ii_18_f 0.65 0.69 0.78 0.85 1.01 1.10 1.13 1.32 0.76 0.87 1.00 1.19 ns lvcmos33_s4 1.31 1.40 1.60 1.60 3.77 3.90 4.00 4.00 3.52 3.67 3.86 3.86 ns lvcmos33_s8 1.31 1.40 1.60 1.60 3.49 3.62 3.72 3.72 3.24 3.39 3.58 3.58 ns lvcmos33_s12 1.31 1.40 1. 60 1.60 3.05 3.18 3.28 3.28 2.80 2.95 3.15 3.15 ns lvcmos33_s16 1.31 1.40 1. 60 1.60 3.06 3.43 3.88 3.88 2.81 3.20 3.75 3.75 ns lvcmos33_f4 1.31 1.40 1.60 1.60 3.22 3.36 3.45 3.45 2.98 3.12 3.32 3.32 ns lvcmos33_f8 1.31 1.40 1.60 1.60 2.71 2.84 2.93 2.93 2.46 2.61 2.80 2.80 ns lvcmos33_f12 1.31 1.40 1. 60 1.60 2.57 2.85 3.15 3.15 2.33 2.61 3.02 3.02 ns lvcmos33_f16 1.31 1.40 1. 60 1.60 2.44 2.69 2.96 2.96 2.19 2.45 2.82 2.82 ns lvcmos25_s4 1.08 1.16 1.32 1.35 3.08 3.22 3.31 3.31 2.84 2.98 3.18 3.18 ns lvcmos25_s8 1.08 1.16 1.32 1.35 2.85 2.98 3.07 3.08 2.60 2.75 2.94 2.94 ns lvcmos25_s12 1.08 1.16 1. 32 1.35 2.44 2.57 2.67 2.67 2.19 2.34 2.54 2.54 ns lvcmos25_s16 1.08 1.16 1. 32 1.35 2.79 2.92 3.01 3.01 2.54 2.68 2.88 2.88 ns lvcmos25_f4 1.08 1.16 1.32 1.35 2.71 2.84 2.93 2.93 2.46 2.61 2.80 2.80 ns lvcmos25_f8 1.08 1.16 1.32 1.35 2.14 2.28 2.37 2.37 1.90 2.04 2.24 2.24 ns lvcmos25_f12 1.08 1.16 1. 32 1.35 2.15 2.29 2.52 2.52 1.91 2.05 2.38 2.38 ns lvcmos25_f16 1.08 1.16 1. 32 1.35 1.92 2.17 2.45 2.45 1.67 1.94 2.32 2.32 ns lvcmos18_s4 0.64 0.66 0.74 0.95 1.55 1.68 1.78 1.78 1.30 1.45 1.65 1.65 ns lvcmos18_s8 0.64 0.66 0.74 0.95 2.14 2.28 2.37 2.37 1.90 2.04 2.24 2.24 ns lvcmos18_s12 0.64 0.66 0. 74 0.95 2.14 2.28 2.37 2.37 1.90 2.04 2.24 2.24 ns lvcmos18_s16 0.64 0.66 0. 74 0.95 1.49 1.62 1.72 1.72 1.24 1.39 1.58 1.58 ns lvcmos18_s24 0.64 0.66 0. 74 0.95 1.74 1.92 2.08 2.22 1.50 1.69 1.95 2.08 ns ta bl e 5 5 : iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 40 lvcmos18_f4 0.64 0.66 0.74 0.95 1.38 1.51 1.61 1.64 1.13 1.28 1.47 1.50 ns lvcmos18_f8 0.64 0.66 0.74 0.95 1.64 1.78 1.87 1.87 1.40 1.54 1.74 1.74 ns lvcmos18_f12 0.64 0.66 0. 74 0.95 1.64 1.78 1.87 1.87 1.40 1.54 1.74 1.74 ns lvcmos18_f16 0.64 0.66 0. 74 0.95 1.52 1.68 1.81 1.81 1.28 1.45 1.68 1.68 ns lvcmos18_f24 0.64 0.66 0. 74 0.95 1.34 1.46 1.55 2.09 1.09 1.23 1.42 1.96 ns lvcmos15_s4 0.66 0.69 0.81 0.93 1.86 2.00 2.09 2.09 1.62 1.76 1.96 1.96 ns lvcmos15_s8 0.66 0.69 0.81 0.93 2.05 2.18 2.28 2.28 1.80 1.95 2.14 2.15 ns lvcmos15_s12 0.66 0.69 0. 81 0.93 1.83 2.03 2.23 2.23 1.59 1.80 2.10 2.10 ns lvcmos15_s16 0.66 0.69 0. 81 0.93 1.76 1.95 2.13 2.13 1.52 1.72 1.99 1.99 ns lvcmos15_f4 0.66 0.69 0.81 0.93 1.63 1.76 1.86 1.86 1.38 1.53 1.72 1.72 ns lvcmos15_f8 0.66 0.69 0.81 0.93 1.79 1.99 2.18 2.18 1.55 1.76 2.05 2.05 ns lvcmos15_f12 0.66 0.69 0. 81 0.93 1.40 1.54 1.65 1.65 1.15 1.31 1.52 1.52 ns lvcmos15_f16 0.66 0.69 0. 81 0.93 1.37 1.51 1.61 1.89 1.13 1.27 1.48 1.75 ns lvcmos12_s4 0.88 0.91 1.00 1.17 2.53 2.67 2.76 2.76 2.29 2.43 2.63 2.63 ns lvcmos12_s8 0.88 0.91 1.00 1.17 2.05 2.18 2.28 2.28 1.80 1.95 2.14 2.15 ns lvcmos12_s12 0.88 0.91 1. 00 1.17 1.75 1.89 1.98 1.98 1.51 1.65 1.85 1.85 ns lvcmos12_f4 0.88 0.91 1.00 1.17 1.94 2.07 2.17 2.17 1.69 1.84 2.04 2.04 ns lvcmos12_f8 0.88 0.91 1.00 1.17 1.50 1.64 1.73 1.73 1.26 1.40 1.60 1.60 ns lvcmos12_f12 0.88 0.91 1. 00 1.17 1.54 1.71 1.87 1.87 1.29 1.48 1.74 1.74 ns sstl135_s 0.61 0.64 0.73 0.85 1.27 1.40 1.50 1.53 1.02 1.17 1.36 1.40 ns sstl15_s 0.61 0.64 0.73 0.73 1.24 1.37 1.47 1.53 0.99 1.14 1.33 1.40 ns sstl18_i_s 0.64 0.67 0.76 0.84 1.59 1.74 1.85 1.85 1.34 1.50 1.72 1.72 ns sstl18_ii_s 0.64 0.67 0.76 0.85 1.27 1.40 1.50 1.50 1.02 1.17 1.36 1.36 ns diff_sstl135_s 0.59 0.61 0. 73 0.85 1.27 1.40 1.50 1.53 1.02 1.17 1.36 1.40 ns diff_sstl15_s 0.63 0.67 0.77 0.85 1.24 1.37 1.47 1.53 0.99 1.14 1.33 1.40 ns diff_sstl18_i_s 0.65 0.69 0.78 0.85 1.50 1.63 1.72 1.82 1.26 1.40 1.59 1.69 ns diff_sstl18_ii_s 0.65 0.69 0. 78 0.85 1.13 1.22 1.25 1.50 0.88 0.99 1.12 1.36 ns sstl135_f 0.61 0.64 0.73 0.85 1.04 1.17 1.26 1.31 0.79 0.93 1.13 1.18 ns sstl15_f 0.61 0.64 0.73 0.73 1.04 1.17 1.26 1.26 0.79 0.93 1.13 1.13 ns sstl18_i_f 0.64 0.67 0.76 0.84 1.12 1.22 1.26 1.34 0.88 0.99 1.13 1.21 ns sstl18_ii_f 0.64 0.67 0.76 0.85 1.05 1.18 1.28 1.32 0.80 0.95 1.15 1.19 ns diff_sstl135_f 0.59 0.61 0. 73 0.85 1.04 1.17 1.26 1.31 0.79 0.93 1.13 1.18 ns diff_sstl15_f 0.63 0.67 0.77 0.85 1.04 1.17 1.26 1.26 0.79 0.93 1.13 1.13 ns diff_sstl18_i_f 0.65 0.69 0.78 0.85 1.10 1.19 1.23 1.34 0.85 0.96 1.10 1.21 ns diff_sstl18_ii_f 0.65 0.69 0. 78 0.85 1.02 1.10 1.14 1.32 0.77 0.87 1.00 1.19 ns ta bl e 5 5 : iob high range (hr) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 41 ta bl e 5 6 : iob high performance (hp) switching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq lvds 0.75 0.79 0.92 0. 96 1.05 1.17 1.24 1.26 0.88 1.01 1.08 1.10 ns hsul_12_s 0.69 0.72 0.82 0.98 1.65 1.84 2.05 2.05 1.48 1.68 1.89 1.89 ns hsul_12_f 0.69 0.72 0.82 0.98 1.39 1.54 1.68 1.68 1.22 1.38 1.52 1.52 ns diff_hsul_12_s 0.69 0.72 0.82 0.98 1.65 1.84 2.05 2. 05 1.48 1.68 1.89 1.89 ns diff_hsul_12_f 0.69 0.72 0.82 0.98 1.39 1.54 1.68 1. 68 1.22 1.38 1.52 1.52 ns diff_hsul_12_dci_s 0.69 0. 72 0.82 0.82 1.78 1.91 2.05 2.05 1.61 1.76 1.89 1.89 ns diff_hsul_12_dci_f 0.69 0. 72 0.82 0.82 1.56 1.67 1.76 1.76 1.39 1.51 1.60 1.60 ns hstl_i_s 0.68 0.72 0.82 0.90 1.15 1.28 1.38 1.38 0.98 1.12 1.22 1.22 ns hstl_ii_s 0.68 0.72 0.82 0.90 1.05 1 .17 1.26 1.27 0.88 1.01 1.10 1.11 ns hstl_i_18_s 0.70 0.72 0. 82 0.95 1.12 1.24 1.34 1. 34 0.95 1.08 1.18 1.18 ns hstl_ii_18_s 0.70 0.72 0.82 0.90 1.06 1.18 1.26 1.27 0.89 1.02 1.10 1.11 ns hstl_i_12_s 0.68 0.72 0. 82 0.96 1.14 1.27 1.37 1. 37 0.97 1.11 1.21 1.21 ns hstl_i_dci_s 0.68 0.72 0. 82 0.90 1.11 1.23 1.33 1. 33 0.94 1.07 1.17 1.17 ns hstl_ii_dci_s 0.68 0.72 0. 82 0.85 1.05 1.17 1.26 1. 26 0.88 1.01 1.10 1.10 ns hstl_ii_t_dci_s 0.70 0.72 0.82 0.82 1.15 1.28 1.38 1. 38 0.98 1.12 1.22 1.22 ns hstl_i_dci_18_s 0.70 0.72 0.82 0.90 1.11 1.23 1.33 1. 33 0.94 1.07 1.17 1.17 ns hstl_ii_dci_18_s 0.70 0.72 0.82 0.82 1.05 1.16 1.24 1. 24 0.88 1.00 1.08 1.08 ns hstl_ii _t_dci_18_s 0.70 0. 72 0.82 0.84 1.11 1.23 1.33 1.34 0.94 1.07 1.17 1.18 ns diff_hstl_i_s 0.75 0.79 0.92 1.02 1.15 1.28 1.38 1.38 0.98 1.12 1.22 1.22 ns diff_hstl_ii_s 0.75 0.79 0.92 1.02 1.0 5 1.17 1.26 1.32 0.88 1.01 1.10 1.16 ns diff_hstl_i_dci_s 0.75 0. 79 0.92 0.92 1.15 1.28 1.38 1.38 0.98 1.12 1.22 1.22 ns diff_hstl_ii_dci_s 0.75 0. 79 0.92 0.92 1.05 1.17 1.26 1.26 0.88 1.01 1.10 1.10 ns diff_hstl_i_18_s 0. 75 0.79 0.92 0.98 1.12 1.24 1. 34 1.34 0.95 1.08 1.18 1.18 ns diff_hstl_ii_18_s 0.75 0. 79 0.92 0.99 1.06 1.18 1.26 1.32 0.89 1.02 1.10 1.16 ns diff_hstl_i_dci_18_s 0.75 0. 79 0.92 0.92 1.11 1.23 1.33 1.33 0.94 1.07 1.17 1.17 ns diff_hstl_ii_dci_18_s 0.75 0. 79 0.92 0.93 1.05 1.16 1.24 1.26 0.88 1.00 1.08 1.10 ns diff_hstl_ii _t_dci_18_s 0.75 0.79 0.92 0.9 2 1.11 1.23 1.33 1.33 0.94 1.07 1.17 1.17 ns hstl_i_f 0.68 0.72 0.82 0.90 1.02 1.14 1.22 1.22 0.85 0.98 1.06 1.06 ns hstl_ii_f 0.68 0.72 0.82 0.90 0.97 1 .08 1.15 1.15 0.80 0.92 0.99 0.99 ns hstl_i_18_f 0.70 0.72 0. 82 0.95 1.04 1.16 1.24 1. 24 0.87 1.00 1.08 1.08 ns hstl_ii_18_f 0.70 0.72 0.82 0.90 0.98 1.09 1.16 1.20 0.81 0.94 1.00 1.03 ns hstl_i_12_f 0.68 0.72 0. 82 0.96 1.02 1.13 1.21 1. 21 0.85 0.97 1.05 1.05 ns hstl_i_dci_f 0.68 0.72 0. 82 0.90 1.04 1.16 1.24 1. 24 0.87 1.00 1.08 1.08 ns hstl_ii_dci_f 0.68 0.72 0. 82 0.85 0.97 1.08 1.15 1. 15 0.80 0.92 0.99 0.99 ns hstl_ii_t_dci_f 0.70 0.72 0.82 0.82 1.02 1.14 1.22 1. 22 0.85 0.98 1.06 1.06 ns hstl_i_dci_18_f 0.70 0.72 0.82 0.90 1.04 1.16 1.24 1. 24 0.87 1.00 1.08 1.08 ns hstl_ii_dci_18_f 0.70 0.72 0.82 0.82 0.98 1.09 1.16 1. 16 0.81 0.93 1.00 1.00 ns hstl_ii _t_dci_18_f 0.70 0. 72 0.82 0.84 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 42 diff_hstl_i_f 0.75 0.79 0.92 1.02 1.02 1.14 1.22 1.22 0.85 0.98 1.06 1.06 ns diff_hstl_ii_f 0.75 0.79 0.92 1.02 0.9 7 1.08 1.15 1.20 0.80 0.92 0.99 1.03 ns diff_hstl_i_dci_f 0.75 0. 79 0.92 0.92 1.02 1.14 1.22 1.22 0.85 0.98 1.06 1.06 ns diff_hstl_ii_dci_f 0.75 0. 79 0.92 0.92 0.97 1.08 1.15 1.15 0.80 0.92 0.99 0.99 ns diff_hstl_i_18_f 0. 75 0.79 0.92 0.98 1.04 1.16 1. 24 1.24 0.87 1.00 1.08 1.08 ns diff_hstl_ii_18_f 0.75 0. 79 0.92 0.99 0.98 1.09 1.16 1.24 0.81 0.94 1.00 1.08 ns diff_hstl_i_dci_18_f 0.75 0. 79 0.92 0.92 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns diff_hstl_ii_dci_18_f 0.75 0. 79 0.92 0.93 0.98 1.09 1.16 1.18 0.81 0.93 1.00 1.02 ns diff_hstl_ii _t_dci_18_f 0.75 0.79 0.92 0.9 2 1.04 1.16 1.24 1.24 0.87 1.00 1.08 1.08 ns lvcmos18_s2 0.47 0.50 0.60 0.90 3.95 4 .28 4.85 4.85 3.78 4.13 4.69 4.69 ns lvcmos18_s4 0.47 0.50 0.60 0.90 2.67 2 .98 3.43 3.43 2.50 2.82 3.27 3.27 ns lvcmos18_s6 0.47 0.50 0.60 0.90 2.14 2 .38 2.72 2.72 1.97 2.22 2.56 2.56 ns lvcmos18_s8 0.47 0.50 0.60 0.90 1.98 2 .21 2.52 2.52 1.81 2.05 2.36 2.36 ns lvcmos18_s12 0.47 0.50 0. 60 0.90 1.70 1.91 2.17 2. 17 1.53 1.75 2.01 2.01 ns lvcmos18_s16 0.47 0.50 0. 60 0.90 1.57 1.75 1.97 1. 97 1.40 1.59 1.81 1.81 ns lvcmos18_f2 0.47 0.50 0.60 0.90 3.50 3 .87 4.48 4.48 3.33 3.71 4.32 4.32 ns lvcmos18_f4 0.47 0.50 0.60 0.90 2.23 2 .50 2.87 2.87 2.06 2.34 2.71 2.71 ns lvcmos18_f6 0.47 0.50 0.60 0.90 1.80 2 .00 2.26 2.26 1.63 1.84 2.09 2.09 ns lvcmos18_f8 0.47 0.50 0.60 0.90 1.46 1 .72 2.04 2.04 1.29 1.56 1.88 1.88 ns lvcmos18_f12 0.47 0.50 0. 60 0.90 1.26 1.40 1.53 1. 53 1.09 1.24 1.37 1.37 ns lvcmos18_f16 0.47 0.50 0. 60 0.90 1.19 1.33 1.44 1. 66 1.02 1.17 1.28 1.50 ns lvcmos15_s2 0.59 0.62 0.73 0.88 3.55 3 .89 4.45 4.45 3.38 3.73 4.29 4.29 ns lvcmos15_s4 0.59 0.62 0.73 0.88 2.45 2 .70 3.06 3.06 2.28 2.54 2.90 2.90 ns lvcmos15_s6 0.59 0.62 0.73 0.88 2.24 2 .51 2.88 2.88 2.07 2.35 2.72 2.72 ns lvcmos15_s8 0.59 0.62 0.73 0.88 1.91 2 .16 2.49 2.49 1.74 2.00 2.32 2.32 ns lvcmos15_s12 0.59 0.62 0. 73 0.88 1.77 1.98 2.23 2. 23 1.60 1.82 2.07 2.07 ns lvcmos15_s16 0.59 0.62 0. 73 0.88 1.62 1.81 2.02 2. 02 1.45 1.65 1.86 1.86 ns lvcmos15_f2 0.59 0.62 0.73 0.88 3.38 3 .69 4.18 4.18 3.21 3.53 4.02 4.02 ns lvcmos15_f4 0.59 0.62 0.73 0.88 2.04 2 .21 2.44 2.44 1.87 2.06 2.27 2.27 ns lvcmos15_f6 0.59 0.62 0.73 0.88 1.47 1 .74 2.09 2.09 1.30 1.58 1.93 1.93 ns lvcmos15_f8 0.59 0.62 0.73 0.88 1.31 1 .46 1.61 1.61 1.14 1.30 1.45 1.45 ns lvcmos15_f12 0.59 0.62 0. 73 0.88 1.21 1.34 1.45 1. 45 1.04 1.18 1.29 1.29 ns lvcmos15_f16 0.59 0.62 0. 73 0.88 1.18 1.31 1.41 1. 68 1.01 1.15 1.25 1.52 ns lvcmos12_s2 0.64 0.67 0.78 1.04 3.38 3 .80 4.48 4.48 3.21 3.64 4.31 4.31 ns lvcmos12_s4 0.64 0.67 0.78 1.04 2.62 2 .94 3.43 3.43 2.45 2.78 3.27 3.27 ns lvcmos12_s6 0.64 0.67 0.78 1.04 2.05 2 .33 2.72 2.72 1.88 2.17 2.56 2.56 ns lvcmos12_s8 0.64 0.67 0.78 1.04 1.94 2 .18 2.51 2.51 1.77 2.02 2.34 2.34 ns ta bl e 5 6 : iob high performance (hp) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 43 lvcmos12_f2 0.64 0.67 0.78 1.04 2.84 3 .15 3.62 3.62 2.67 2.99 3.46 3.46 ns lvcmos12_f4 0.64 0.67 0.78 1.04 1.97 2 .18 2.44 2.44 1.80 2.02 2.28 2.28 ns lvcmos12_f6 0.64 0.67 0.78 1.04 1.33 1 .51 1.70 1.70 1.16 1.35 1.54 1.54 ns lvcmos12_f8 0.64 0.67 0.78 1.04 1.27 1 .42 1.55 1.55 1.10 1.26 1.39 1.39 ns lvdci_18 0.47 0.50 0.60 0. 87 1.99 2.15 2.35 2.35 1.82 1.99 2.19 2.19 ns lvdci_15 0.59 0.62 0.73 0. 92 1.98 2.23 2.58 2.58 1.81 2.07 2.41 2.41 ns lvdci_dv2_18 0.47 0.50 0.60 0.88 1.99 2.15 2.34 2.34 1.82 1.99 2.18 2.18 ns lvdci_dv2_15 0.59 0.62 0.73 0.88 1.98 2.23 2.58 2.58 1.81 2.07 2.41 2.41 ns hslvdci_18 0.68 0.72 0.82 0.90 1.99 2.15 2.35 2.35 1.82 1.99 2.19 2.19 ns hslvdci_15 0.68 0.72 0.82 0.93 1.98 2.23 2.58 2.58 1.81 2.07 2.41 2.41 ns sstl18_i_s 0.68 0.72 0.82 0.95 1.02 1 .15 1.24 1.24 0.85 0.99 1.08 1.08 ns sstl18_ii_s 0.68 0.72 0. 82 1.01 1.17 1.29 1.37 1. 38 1.00 1.13 1.21 1.22 ns sstl18_i_dci_s 0.68 0.72 0.82 0.87 0.92 1.06 1.17 1.18 0.75 0.90 1.01 1.02 ns sstl18_ii_dci_s 0.68 0.72 0.82 0.82 0.88 0.98 1.08 1. 12 0.71 0.83 0.92 0.96 ns sstl18_ii_t_dci_s 0.68 0. 72 0.82 0.98 0.92 1.06 1.17 1.18 0.75 0.90 1.01 1.02 ns sstl15_s 0.68 0.72 0.82 0.82 0.94 1.0 6 1.15 1.16 0.77 0.91 0.99 1.00 ns sstl15_dci_s 0.68 0.72 0. 82 0.90 0.94 1.06 1.15 1. 16 0.77 0.90 0.99 1.00 ns sstl15_t_dci_s 0.68 0.72 0.82 0.87 0.9 4 1.06 1.15 1.15 0.77 0.90 0.99 0.99 ns sstl135_s 0.69 0.72 0.82 0.93 0.97 1. 10 1.19 1.20 0.80 0.94 1.03 1.03 ns sstl135_dci_s 0.69 0.72 0. 82 0.85 0.97 1.09 1.19 1. 20 0.80 0.93 1.03 1.03 ns sstl135_t_dci_s 0.69 0.72 0.82 0.93 0. 97 1.09 1.19 1.20 0.80 0.93 1.03 1.03 ns sstl12_s 0.69 0.72 0.82 1.02 0.96 1.0 9 1.18 1.18 0.79 0.93 1.02 1.02 ns sstl12_dci_s 0.69 0.72 0. 82 0.90 1.03 1.17 1.27 1. 27 0.86 1.01 1.11 1.11 ns sstl12_t_dci_s 0.69 0.72 0.82 0.88 1.0 3 1.17 1.27 1.27 0.86 1.01 1.11 1.11 ns diff_sstl18_i_s 0.75 0.79 0.92 0.99 1.02 1.15 1.24 1.29 0.85 0.99 1.08 1.13 ns diff_sstl18_ii_s 0. 75 0.79 0.92 0.93 1.17 1.29 1. 37 1.40 1.00 1.13 1.21 1.24 ns diff_sstl18_i_dci_s 0.75 0. 79 0.92 0.92 0.92 1.06 1.17 1.24 0.75 0.90 1.01 1.08 ns diff_sstl18_ii_dci_s 0.75 0. 79 0.92 0.96 0.88 0.98 1.08 1.18 0.71 0.83 0.92 1.02 ns diff_sstl18_ii_t_dci _s 0.75 0.79 0.92 0.92 0.92 1.06 1.17 1.24 0.75 0.90 1.01 1.08 ns diff_sstl15_s 0.68 0.72 0.82 0.99 0.94 1.06 1.15 1.16 0.77 0.91 0.99 1.00 ns diff_sstl15_dci_s 0. 68 0.72 0.82 0.96 0.94 1.06 1. 15 1.16 0.77 0.90 0.99 1.00 ns diff_sstl15_t_dci_s 0.68 0. 72 0.82 0.88 0.94 1.06 1.15 1.23 0.77 0.90 0.99 1.07 ns diff_sstl135_s 0.69 0.72 0. 82 1.09 0.97 1.10 1.19 1. 20 0.80 0.94 1.03 1.03 ns diff_sstl135_dci_s 0.69 0. 72 0.82 0.90 0.97 1.09 1.19 1.20 0.80 0.93 1.03 1.03 ns diff_sstl135_t_dci_s 0.69 0.72 0.82 0.84 0. 97 1.09 1.19 1.27 0.80 0.93 1.03 1.11 ns diff_sstl12_s 0.69 0.72 0.82 0.96 0.96 1.09 1.18 1.18 0.79 0.93 1.02 1.02 ns diff_sstl12_dci_s 0. 69 0.72 0.82 0.87 1.03 1.17 1. 27 1.27 0.86 1.01 1.11 1.11 ns diff_sstl12_t_dci_s 0.69 0. 72 0.82 0.96 1.03 1.17 1.27 1.27 0.86 1.01 1.11 1.11 ns ta bl e 5 6 : iob high performance (hp) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 44 sstl18_i_f 0.68 0.72 0.82 0.95 0.94 1 .06 1.15 1.15 0.77 0.91 0.99 0.99 ns sstl18_ii_f 0.68 0.72 0. 82 1.01 0.97 1.09 1.16 1. 21 0.80 0.93 1.00 1.05 ns sstl18_i_dci_f 0.68 0.72 0.82 0.87 0.89 1.02 1.10 1.15 0.72 0.86 0.94 0.99 ns sstl18_ii_dci_f 0.68 0.72 0.82 0.82 0.89 1.02 1.10 1. 10 0.72 0.86 0.94 0.94 ns sstl18_ii_t_dci_f 0.68 0. 72 0.82 0.98 0.89 1.02 1.10 1.15 0.72 0.86 0.94 0.99 ns sstl15_f 0.68 0.72 0.82 0.82 0.89 1.0 1 1.09 1.09 0.72 0.85 0.93 0.93 ns sstl15_dci_f 0.68 0.72 0. 82 0.90 0.89 1.01 1.09 1. 12 0.72 0.85 0.93 0.96 ns sstl15_t_dci_f 0.68 0.72 0.82 0.87 0.8 9 1.01 1.09 1.12 0.72 0.85 0.93 0.96 ns sstl135_f 0.69 0.72 0.82 0.93 0.88 1. 00 1.08 1.12 0.71 0.85 0.92 0.96 ns sstl135_dci_f 0.69 0.72 0. 82 0.85 0.89 1.00 1.08 1. 12 0.72 0.85 0.92 0.96 ns sstl135_t_dci_f 0.69 0.72 0.82 0.93 0. 89 1.00 1.08 1.12 0.72 0.85 0.92 0.96 ns sstl12_f 0.69 0.72 0.82 1.02 0.88 1.0 0 1.08 1.12 0.71 0.84 0.92 0.96 ns sstl12_dci_f 0.69 0.72 0. 82 0.90 0.91 1.03 1.11 1. 11 0.74 0.88 0.95 0.95 ns sstl12_t_dci_f 0.69 0.72 0.82 0.88 0.9 1 1.03 1.11 1.12 0.74 0.88 0.95 0.96 ns diff_sstl18_i_f 0.75 0.79 0.92 0.99 0.94 1.06 1.15 1.23 0.77 0.91 0.99 1.07 ns diff_sstl18_ii_f 0. 75 0.79 0.92 0.93 0.97 1.09 1. 16 1.24 0.80 0.93 1.00 1.08 ns diff_sstl18_i_dci_f 0.75 0. 79 0.92 0.92 0.89 1.02 1.10 1.23 0.72 0.86 0.94 1.07 ns diff_sstl18_ii_dci_f 0.75 0. 79 0.92 0.96 0.89 1.02 1.10 1.16 0.72 0.86 0.94 1.00 ns diff_sstl18_ii_t_dci _f 0.75 0.79 0.92 0.92 0.89 1.02 1.10 1.24 0.72 0.86 0.94 1.08 ns diff_sstl15_f 0.68 0.72 0.82 0.99 0.89 1.01 1.09 1.09 0.72 0.85 0.93 0.93 ns diff_sstl15_dci_f 0. 68 0.72 0.82 0.96 0.89 1.01 1. 09 1.12 0.72 0.85 0.93 0.96 ns diff_sstl15_t_dci_f 0.68 0. 72 0.82 0.88 0.89 1.01 1.09 1.20 0.72 0.85 0.93 1.03 ns diff_sstl135_f 0.69 0.72 0. 82 1.09 0.88 1.00 1.08 1. 12 0.71 0.85 0.92 0.96 ns diff_sstl135_dci_f 0.69 0. 72 0.82 0.90 0.89 1.00 1.08 1.12 0.72 0.85 0.92 0.96 ns diff_sstl135_t_dci_f 0.69 0.72 0.82 0.84 0. 89 1.00 1.08 1.20 0.72 0.85 0.92 1.03 ns diff_sstl12_f 0.69 0.72 0.82 0.96 0.88 1.00 1.08 1.12 0.71 0.84 0.92 0.96 ns diff_sstl12_dci_f 0. 69 0.72 0.82 0.87 0.91 1.03 1. 11 1.11 0.74 0.88 0.95 0.95 ns diff_sstl12_t_dci_f 0.69 0. 72 0.82 0.96 0.91 1.03 1.11 1.18 0.74 0.88 0.95 1.02 ns ta bl e 5 6 : iob high performance (hp) switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 45 ta bl e 5 7 specifies the values of t iotphz and t ioibufdisable . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). t ioibufdisable is described as the iob delay from ibufdisable to o outp ut. in hp i/o banks, the internal dci te rmination turn-off time is always faster than t iotphz when the dcitermdisable pin is used . in hr i/o banks, the internal in_term termination turn-off time is always faster than t iotphz when the intermdisable pin is used. ta bl e 5 7 : iob 3-state output switching characteristics symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq t iotphz t input to pad high-impedance 0.76 0.86 0.99 0.99 ns t ioibufdisable_hr ibuf turn-on time from ib ufdisable to o output for hr i/o banks 1.72 1.89 2.14 2.14 ns t ioibufdisable_hp ibuf turn-on time from ibufdisable to o output for hp i/o banks 1.31 1.46 1.76 1.76 ns s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 46 i/o standard adjustment measurement methodology input delay measurements ta bl e 5 8 shows the test setup parameters used for measuring input delay. ta bl e 5 8 : input delay measurement methodology description i /o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(6) v ref (1)(3)(5) lvcmos, 1.2v lvcmos12 0.1 1.1 0.6 ? lvcmos, 1.5v lvcmos15 0.1 1.4 0.75 ? lvcmos, 1.8v lvcmos18 0.1 1.7 0.9 ? lvcmos, 2.5v lvcmos25 0.1 2.4 1.25 ? lvcmos, 3.3v lvcmos33 0.1 3.2 1.75 ? lvttl, 3.3v lvttl 0.1 3.2 1.75 ? mobile_ddr, 1.8v mobile_ddr 0.1 1.7 0.9 ? pci33, 3.3v pci33_3 0.1 3.2 1.32 ? hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 v ref ?0.5 v ref +0.5 v ref 0.60 hstl, class i & ii, 1.5v hstl_i, hstl_ii v ref ?0.65 v ref +0.65 v ref 0.75 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.8 v ref +0.8 v ref 0.90 hsul (high-speed unterminated logic), 1.2v hsul_12 v ref ?0.5 v ref +0.5 v ref 0.60 sstl (stub terminated transceiver logic), 1.2v sstl12 v ref ?0.5 v ref +0.5 v ref 0.60 sstl, 1.35v sstl135, sstl135_r v ref ? 0.575 v ref + 0.575 v ref 0.675 sstl, 1.5v sstl15, sstl15_r v ref ?0.65 v ref +0.65 v ref 0.75 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.8 v ref +0.8 v ref 0.90 diff_mobile_ddr, 1.8v diff_mo bile_ddr 0.9 ? 0.125 0.9 + 0.125 0 (6) ? diff_hstl, class i, 1.2v di ff_hstl_i_12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_hstl, class i & ii,1.5v diff_hstl_i, diff_hstl_ii 0.75 ? 0.125 0.75 + 0.125 0 (6) ? diff_hstl, class i & ii, 1.8v diff_hstl_i_18, diff_hstl_ii_18 0.9 ? 0.125 0.9 + 0.125 0 (6) ? diff_hsul, 1.2v diff_hsul _12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_sstl, 1.2v diff_sst l12 0.6 ? 0.125 0.6 + 0.125 0 (6) ? diff_sstl135/dif f_sstl135_r, 1.35v diff_sstl135, diff_sstl135_r 0.675 ? 0.125 0.675 + 0.125 0 (6) ? diff_sstl15/diff _sstl15_r, 1.5v diff_sstl15, diff_sstl15_r 0.75 ? 0.125 0.75 + 0.125 0 (6) ? diff_sstl18_i/di ff_sstl18_ii, 1.8v diff_sstl18_i, diff_sstl18_ii 0.9 ? 0.125 0.9 + 0.125 0 (6) ? lvds (low-voltage differential si gnaling), 1.8v lvds 0.9 ? 0.125 0.9 + 0.125 0 (6) ? lvds_25, 2.5v lvds_25 1.2 ? 0.125 1.2 + 0.125 0 (6) ? blvds_25, 2.5v blvds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? mini_lvds_25, 2.5v mini_lvd s_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? ppds_25 ppds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? rsds_25 rsds_25 1.25 ? 0.125 1.25 + 0.125 0 (6) ? s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 47 output delay measurements output delays are measured with short output traces. standard termination was used for all testing. the propagation delay of the trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 18 and figure 19 . parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagation delay in any given application c an be obtained through ibis simulation, using this method: 1. simulate the output driver of choice into the generalized test setup using values from ta bl e 5 9 . 2. record the time to v meas . 3. simulate the output driver of choice into the actual pcb trace and load using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . tmds_33 tmds_33 3 ? 0.125 3 + 0.125 0 (6) ? notes: 1. the input delay measurement methodology parameters for lvdci are the same for lvcmos standards of the same voltage. input del ay measurement methodology parameters for hslvdci are the same as for hstl_ii standards of the same voltage. parameters for all ot her dci standards are the same for the corresponding non-dci standards. 2. input waveform switches between v l and v h . 3. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 4. input voltage level from which measurement starts. 5. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 18 . 6. the value given is the differential input voltage. x-ref target - figure 18 figure 18: single-ended test setup x-ref target - figure 19 figure 19: differential test setup ta bl e 5 8 : input delay measurement methodology (cont?d) description i /o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(6) v ref (1)(3)(5) v ref r ref v mea s (volt a ge level when t a king del a y me asu rement) c ref (pro b e c a p a cit a nce) o u tp u t d s 191_19_060415 r ref v mea s + ? c ref o u tp u t d s 191_20_060415 s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 48 5. compare the results of step 2 and step 4 . the increase or decrease in delay yields the actual propagation delay of the pcb trace. ta bl e 5 9 : output delay measurement methodology description i/o standard attribute r ref ( ) c ref (1) (pf) v meas (v) v ref (v) lvcmos, 1.2v lvcmos12 1m 0 0.6 0 lvcmos/lvdci/hslvdci, 1.5v lvcmos15, lvdci_15, hslvdci_15 1m 0 0.75 0 lvcmos/lvdci/hslvdci, 1.8v lvcmos 18, lvdci_15, hslvdci_18 1m 0 0.9 0 lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 3.3v lvcmos33 1m 0 1.65 0 lvttl, 3.3v lvttl 1m 0 1.65 0 pci33, 3.3v pci33_3 25 10 1.65 0 hstl (high-speed transceiver logic), class i, 1.2v hstl_i_12 50 0 v ref 0.6 hstl, class i, 1.5v hstl_i 50 0 v ref 0.75 hstl, class ii, 1.5v hstl_ii 25 0 v ref 0.75 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hsul (high-speed unterminated logic), 1.2v hsul_12 50 0 v ref 0.6 sstl12, 1.2v sstl12 50 0 v ref 0.6 sstl135/sstl135_r, 1.35v sstl135, sstl135_r 50 0 v ref 0.675 sstl15/sstl15_r, 1.5v sstl15, sstl15_r 50 0 v ref 0.75 sstl (stub series terminated logic), class i & class ii, 1.8v sstl18_i, sstl18_ii 50 0 v ref 0.9 diff_mobile_ddr, 1.8v diff_mobile_ddr 50 0 v ref 0.9 diff_hstl, class i, 1.2v diff_hstl_i_12 50 0 v ref 0.6 diff_hstl, class i & ii, 1.5v diff_hstl_i, diff_hstl_ii 50 0 v ref 0.75 diff_hstl, class i & ii, 1.8v diff _hstl_i_18, diff_hstl_ii_18 50 0 v ref 0.9 diff_hsul_12, 1.2v diff_hsul_12 50 0 v ref 0.6 diff_sstl12, 1.2v diff_sstl12 50 0 v ref 0.6 diff_sstl135/diff_sst l135_r, 1.35v diff_sstl135, diff_sstl135_r 50 0 v ref 0.675 diff_sstl15/diff_ sstl15_r, 1.5v diff_sstl1 5, diff_sstl15_r 50 0 v ref 0.75 diff_sstl18, class i & ii, 1.8v di ff_sstl18_i, diff_sstl18_ii 50 0 v ref 0.9 lvds (low-voltage differential signaling), 1.8v lvds 100 0 0 (2) 0 lvds, 2.5v lvds_25 100 0 0 (2) 0 blvds (bus lvds), 2.5v blvds_25 100 0 0 (2) 0 mini lvds, 2.5v mini_lvds_25 100 0 0 (2) 0 ppds_25 ppds_25 100 0 0 (2) 0 rsds_25 rsds_25 100 0 0 (2) 0 tmds_33 tmds_33 50 0 0 (2) 3.3 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. the value given is the differential output voltage. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 49 input/output logic switching characteristics ta bl e 6 0 : ilogic switching characteristics symbol description speed grade units -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq setup/hold t ice1ck /t ickce1 ce1 pin setup/hold with respect to cl k 0.42/0.00 0.48/0.00 0.67/0.00 0.67/0.00 ns t isrck /t icksr sr pin setup/hold with respect to clk 0.53/0.01 0.61/0.01 0.99/0.01 0.99/0.01 ns t idocke2 /t iockde2 d pin setup/hold with respect to clk without delay (hp i/o banks only) 0.01/0.27 0.01/0.29 0. 01/0.34 0.01/0.34 ns t idockde2 /t iockdde2 ddly pin setup/hold with respect to clk (using idelay) (hp i/o banks only) 0.01/0.27 0.02/0.29 0. 02/0.34 0.02/0.34 ns t idocke3 /t iockde3 d pin setup/hold with respect to clk without delay (hr i/o banks only) 0.01/0.27 0.01/0.29 0. 01/0.34 0.01/0.34 ns t idockde3 /t iockdde3 ddly pin setup/hold with respect to clk (using idelay) (hr i/o banks only) 0.01/0.27 0.02/0.29 0. 02/0.34 0.02/0.34 ns combinatorial t idie2 d pin to o pin propagation delay, no delay (hp i/o banks only) 0.09 0.10 0.12 0.12 ns t idide2 ddly pin to o pin propagation delay (using idelay) (hp i/o banks only) 0.10 0.11 0.13 0.13 ns t idie3 d pin to o pin propagation delay, no delay (hr i/o banks only) 0.09 0.10 0.12 0.12 ns t idide3 ddly pin to o pin propagation delay (using idelay) (hr i/o banks only) 0.10 0.11 0.13 0.13 ns sequential delays t idloe2 d pin to q1 pin using flip-flop as a latch without delay (hp i/o banks only) 0.36 0.39 0.45 0.45 ns t idlode2 ddly pin to q1 pin using flip-flop as a latch (using idelay) (hp i/o banks only) 0.36 0.39 0.45 0.45 ns t idloe3 d pin to q1 pin using flip-flop as a latch without delay (hr i/o banks only) 0.36 0.39 0.45 0.45 ns t idlode3 ddly pin to q1 pin using flip-flop as a latch (using idelay) (hr i/o banks only) 0.36 0.39 0.45 0.45 ns t ickq clk to q outputs 0.47 0.50 0.58 0.58 ns t rq_ilogice2 sr pin to oq/tq out (hp i/o banks only) 0.84 0.94 1.16 1.16 ns t gsrq_ilogice2 global set/reset to q outputs (hp i/o banks only) 7.60 7.60 10.51 10.51 ns t rq_ilogice3 sr pin to oq/tq out (hr i/o banks only) 0.84 0.94 1.16 1.16 ns t gsrq_ilogice3 global set/reset to q outputs (hr i/o banks only) 7.60 7.60 10.51 10.51 ns set/reset t rpw_ilogice2 minimum pulse width, sr inputs (hp i/o banks only) 0.54 0.63 0.63 0.63 ns, min t rpw_ilogice3 minimum pulse width, sr inputs (hr i/o banks only) 0.54 0.63 0.63 0.63 ns, min s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 50 ta bl e 6 1 : ologic switching characteristics symbol description speed grade units -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq setup/hold t odck /t ockd d1/d2 pins setup/hold with respect to cl k 0.45/?0.13 0.50/?0.13 0.58/?0.13 0.58/?0.13 ns t ooceck /t ockoce oce pin setup/hold with respect to cl k 0.28/0.03 0.29/0.03 0. 45/0.03 0.45/0.03 ns t osrck /t ocksr sr pin setup/hold with respect to cl k 0.32/0.18 0.38/0.18 0. 70/0.18 0.70/0.18 ns t otck /t ockt t1/t2 pins setup/hold with respect to clk 0 .49/?0.16 0.56/?0.16 0.68/?0.16 0.68/?0.13 ns t otceck /t ocktce tce pin setup/hold with respect to cl k 0.28/0.01 0.30/0.01 0. 45/0.01 0.45/0.06 ns combinatorial t odq d1 to oq out or t1 to tq out 0.73 0.81 0.97 0.97 ns sequential delays t ockq clk to oq/tq out 0.41 0.43 0.49 0.49 ns t rq_ologice2 sr pin to oq/tq out (hp i/o banks only) 0.63 0.70 0.83 0.83 ns t gsrq_ologice2 global set/reset to q outputs (hp i/o banks only) 7.60 7.60 10.51 10.51 ns t rq_ologice3 sr pin to oq/tq out (hr i/o banks only) 0.63 0.70 0.83 0.83 ns t gsrq_ologice3 global set/reset to q outputs (hr i/o banks only) 7.60 7.60 10.51 10.51 ns set/reset t rpw_ologice2 minimum pulse width, sr inputs (hp i/o banks only) 0.54 0.54 0.63 0.63 ns, min t rpw_ologice3 minimum pulse width, sr inputs (hr i/o banks only) 0.54 0.54 0.63 0.63 ns, min s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 51 input serializer/deserializer switching characteristics output serializer/deserializ er switching characteristics ta bl e 6 2 : iserdes switching characteristics symbol description speed grade units -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to clkd iv 0.01/0.12 0.02/0.13 0.02/0.15 0.02/0.15 ns t iscck_ce / t isckc_ce (2) ce pin setup/hold with respect to clk (for ce1) 0.39/?0.02 0.44/?0. 02 0.63/?0.02 0.63/?0.02 ns t iscck_ce2 / t isckc_ce2 (2) ce pin setup/hold with respect to clkdiv (for ce2) ?0.12/0.29 ?0.12/0.31 ?0.12/0.35 ?0.12/0.35 ns setup/hold for data lines t isdck_d /t isckd_d d pin setup/hold with respect to clk ?0. 02/0.11 ?0.02/0.12 ?0.02/0.15 ?0.02/0.15 ns t isdck_ddly /t isckd_ddly ddly pin setup/hold with respect to clk (using idelay) (1) ?0.02/0.11 ?0.02/0.12 ?0.02/0.15 ?0.02/0.15 ns t isdck_d_ddr /t isckd_d_ddr d pin setup/hold with respect to clk at ddr mode ?0.02/0.11 ?0.02/0.12 ?0.02/0.15 ?0.02/0.15 ns t isdck_ddly_ddr / t isckd_ddly_ddr d pin setup/hold with respect to clk at ddr mode (using idelay) (1) 0.11/0.11 0.12/0.12 0. 15/0.15 0.15/0.15 ns sequential delays t iscko_q clkdiv to out at q pin 0.46 0.47 0.58 0.58 ns propagation delays t isdo_do d input to do output pin 0.09 0.10 0.12 0.12 ns notes: 1. recorded at 0 tap value. 2. t iscck_ce2 and t isckc_ce2 are reported as t iscck_ce /t isckc_ce in the timing report. ta bl e 6 3 : oserdes switching characteristics symbol description speed grade units -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq setup/hold t osdck_d /t osckd_d d input setup/hold with respect to clkd iv 0.37/0.02 0.40/0.02 0.55/0.02 0.55/0.02 ns t osdck_t /t osckd_t (1) t input setup/hold with respect to clk 0 .49/?0.15 0.56/?0.15 0 .68/?0.15 0.68/?0.15 ns t osdck_t2 /t osckd_t2 (1) t input setup/hold with respect to clkd iv 0.27/?0.15 0.30/?0.15 0 .34/?0.15 0.34/?0.15 ns t oscck_oce /t osckc_oce oce input setup/hold with respect to cl k 0.28/0.03 0.29/0.03 0. 45/0.03 0.45/0.03 ns t oscck_s sr (reset) input setup with respect to clkdiv 0.41 0.46 0.75 0.75 ns t oscck_tce /t osckc_tce tce input setup/hold with respect to cl k 0.28/0.01 0.30/0.01 0. 45/0.01 0.45/0.01 ns sequential delays t oscko_oq clock to out from clk to oq 0.35 0.37 0.42 0.42 ns t oscko_tq clock to out from clk to tq 0.41 0.43 0.49 0.49 ns combinatorial t osdo_ttq t input to tq out 0.73 0.81 0.97 0.97 ns notes: 1. t osdck_t2 and t osckd_t2 are reported as t osdck_t /t osckd_t in the timing report. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 52 input/output delay swit ching characteristics ta bl e 6 4 : input/output delay switching characteristics symbol description speed grade units -3e -2e/-2i/ -2li -1c/-1i -1q/ -1lq idelayctrl t dlycco_rdy reset to ready for idelayctrl 3.22 3.22 3.22 3.22 s f idelayctrl_ref attribute refclk frequency = 200.0 (1) 200 200 200 200 mhz attribute refclk frequency = 300.0 (1) 300 300 n/a n/a mhz attribute refclk frequency = 400.0 (1) 400 400 n/a n/a mhz idelayctrl_ref_preci sion refclk precision 10 10 10 10 mhz t idelayctrl_rpw minimum reset pulse width 52.00 52.00 52.00 52.00 ns idelay/odelay t idelayresolution idelay/odelay chain delay resolution 1/(32 x 2 x f ref )ps t idelaypat_jit and t odelaypat_jit pattern dependent period jitter in delay chain for clock pattern. (2) 0000ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23) (3) 5 5 5 5 ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23) (4) 9 9 9 9 ps per tap t idelay_clk_max / t odelay_clk_max maximum frequency of clk input to idelay/odelay 800 800 710 710 mhz t idcck_ce / t idckc_ce ce pin setup/hold with respect to c for idelay 0.11/0.10 0.14/0. 12 0.18/0.14 0.18/0.14 ns t odcck_ce / t odckc_ce ce pin setup/hold with respect to c for odelay 0.14/0.03 0.16/0. 04 0.19/0.05 0.19/0.05 ns t idcck_inc / t idckc_inc inc pin setup/hold with respect to c for id elay 0.10/0.14 0.12/0.16 0.14/0.20 0.14/0.20 ns t odcck_inc / t odckc_inc inc pin setup/hold with respect to c for od elay 0.10/0.07 0.12/0.08 0.13/0.09 0.13/0.09 ns t idcck_rst / t idckc_rst rst pin setup/hold with respect to c for id elay 0.13/0.08 0.14/0.10 0.16/0.12 0.16/0.12 ns t odcck_rst / t odckc_rst rst pin setup/hold with respect to c for odelay 0.16/0.04 0.19/0. 06 0.24/0.08 0.24/0.08 ns t iddo_idatain propagation delay through idelay note 5 note 5 note 5 note 5 ps t oddo_odatain propagation delay through odelay note 5 note 5 note 5 note 5 ps notes: 1. average tap delay at 200 mhz = 78 ps, at 300 mhz = 52 ps, and at 400 mhz = 39 ps. 2. when high_performance mode is set to true or false. 3. when high_performance mode is set to true. 4. when high_performance mode is set to false. 5. delay depends on idelay/odelay tap setting. see the timing report for actual values. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 53 ta bl e 6 5 : io_fifo switching characteristics symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq io_fifo clock to out delays t offcko_do rdclk to q outputs 0.51 0.56 0.63 0.63 ns t cko_flags clock to io_fifo flags 0.59 0.62 0.81 0.81 ns setup/hold t cck_d /t ckc_d d inputs to wrclk 0.43/?0.01 0.4 7/?0.01 0.53/?0.01 0.53/0.09 ns t iffcck_wren /t iffckc_wren wren to wrclk 0.39/?0.01 0.4 3/?0.01 0.50/?0.01 0.50/?0.01 ns t offcck_rden /t offckc_rden rden to rdclk 0.49/0.01 0.53 /0.02 0.61/0.02 0.61/0.02 ns minimum pulse width t pwh_io_fifo reset, rdclk, wrclk 0.81 0.92 1.08 1.08 ns t pwl_io_fifo reset, rdclk, wrclk 0.81 0.92 1.08 1.08 ns maximum frequency f max rdclk and wrclk 533.05 470.37 400.00 400.00 mhz s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 54 clb switching characteristics ta bl e 6 6 : clb switching characteristics symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq combinatorial delays t ilo an ? dn lut address to a 0.05 0.05 0.06 0.06 ns, max t ilo_2 an ? dn lut address to amux/cmux 0.15 0.16 0.19 0.19 ns, max t ilo_3 an ? dn lut address to bmux_a 0.24 0.25 0.30 0.30 ns, max t ito an ? dn inputs to a ? d q outputs 0.58 0.61 0.74 0.74 ns, max t axa ax inputs to amux output 0.38 0.40 0.49 0.49 ns, max t axb ax inputs to bmux output 0.40 0.42 0.52 0.52 ns, max t axc ax inputs to cmux output 0.39 0.41 0.50 0.50 ns, max t axd ax inputs to dmux output 0.43 0.44 0.52 0.52 ns, max t bxb bx inputs to bmux output 0.31 0.33 0.40 0.40 ns, max t bxd bx inputs to dmux output 0.38 0.39 0.47 0.47 ns, max t cxc cx inputs to cmux output 0.27 0.28 0.34 0.34 ns, max t cxd cx inputs to dmux output 0.33 0.34 0.41 0.41 ns, max t dxd dx inputs to dmux output 0.32 0.33 0.40 0.40 ns, max sequential delays t cko clock to aq ? dq outputs 0.26 0.27 0.32 0.32 ns, max t shcko clock to amux ? dmux outputs 0.32 0.32 0.39 0.39 ns, max setup and hold times of clb fl ip-flops before/after clock clk t as /t ah a n ?d n input to clk on a ? d flip-flops 0.01/0. 12 0.02/0.13 0.03/0.18 0.03/0.24 ns, min t dick /t ckdi a x ?d x input to clk on a ? d flip-flops 0.04/ 0.14 0.04/0.14 0.05/0.20 0.05/0.26 ns, min a x ?d x input through muxs and/or carry logic to clk on a ? d flip-flops 0.36/0.10 0.37/0.11 0.46/ 0.16 0.46/0.22 ns, min t ceck_clb /t ckce_clb ce input to clk on a ? d flip-flops 0.19/ 0.05 0.20/0.05 0.25/0.05 0.25/0.11 ns, min t srck /t cksr sr input to clk on a ? d flip-flops 0.30/ 0.05 0.31/0.07 0.37/0.09 0.37/0.22 ns, min set/reset t srmin sr input minimum pulse width 0.52 0.78 1.04 1.04 ns, min t rq delay from sr input to aq ? dq flip-flops 0.38 0.38 0.46 0.46 ns, max t ceo delay from ce input to aq ? dq flip-flops 0.34 0.35 0.43 0.43 ns, max f tog toggle frequency (for export control) 1818 1818 1818 1818 mhz s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 55 clb distributed ram switching characteristics (slicem only) clb shift register switching characteristics (slicem only) ta bl e 6 7 : clb distributed ram swit ching characteristics symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq sequential delays t shcko (1) clock to a ? b outputs 0.68 0.70 0.85 0.85 ns, max t shcko_1 clock to amux ? bmux outputs 0.91 0.95 1.15 1.15 ns, max setup and hold times before/after clock clk t ds_lram /t dh_lram a ? d inputs to clk 0.45/0.23 0.45 /0.24 0.54/0.27 0.54/0.28 ns, min t as_lram /t ah_lram address an inputs to clock 0.13/0.50 0.14/0.50 0.17/0.58 0.17/0.61 ns, min address an inputs through muxs and/or carry logic to clock 0.40/0.16 0.42/0.17 0.52/ 0.23 0.52/0.29 ns, min t ws_lram /t wh_lram we input to clock 0.29/0.09 0.30 /0.09 0.36/0.09 0.36/0.11 ns, min t ceck_lram /t ckce_lram ce input to clk 0.29/0.09 0.30 /0.09 0.37/0.09 0.37/0.11 ns, min clock clk t mpw_lram minimum pulse width 0.68 0.77 0.91 0.91 ns, min t mcp minimum clock period 1.35 1.54 1.82 1.82 ns, min notes: 1. t shcko also represents the clk to xmux output. refer to the timing report for the clk to xmux path. ta bl e 6 8 : clb shift register switching characteristics symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq sequential delays t reg clock to a ? d outputs 0.96 0.98 1.20 1.20 ns, max t reg_mux clock to amux ? dmux output 1.19 1.23 1.50 1.50 ns, max t reg_m31 clock to dmux output via m31 output 0.89 0.91 1.10 1.10 ns, max setup and hold times before/after clock clk t ws_shfreg /t wh_shfreg we input 0.26/0.09 0.27/0.09 0 .33/0.09 0.33/0.11 ns, min t ceck_shfreg /t ckce_shfreg ce input to clk 0.27/0.09 0.28/0 .09 0.33/0.09 0.33/0.11 ns, min t ds_shfreg /t dh_shfreg a ? d inputs to clk 0.28/0.26 0.28/0.26 0.33/0.30 0.33/0.36 ns, min clock clk t mpw_shfreg minimum pulse width 0.55 0.65 0.78 0.78 ns, min s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 56 block ram and fifo switching characteristics ta bl e 6 9 : block ram and fifo switching characteristics symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq block ram and fifo clock-to-out delays t rcko_do and t rcko_do_reg (1) clock clk to dout outp ut (without output register) (2)(3) 1.57 1.80 2.08 2.08 ns, max clock clk to dout output (with output register) (4)(5) 0.54 0.63 0.75 0.75 ns, max t rcko_do_ecc and t rcko_do_ecc_reg clock clk to dout output with ecc (without output register) (2)(3) 2.35 2.58 3.26 3.26 ns, max clock clk to dout output with ecc (with output register) (4)(5) 0.62 0.69 0.80 0.80 ns, max t rcko_do_cascout and t rcko_do_cascout_reg clock clk to dout output with cascade (without output register) (2) 2.21 2.45 2.80 2.80 ns, max clock clk to dout output with cascade (with output register) (4) 0.98 1.08 1.24 1.24 ns, max t rcko_flags clock clk to fifo flags outputs (6) 0.65 0.74 0.89 0.89 ns, max t rcko_pointers clock clk to fifo pointers outputs (7) 0.79 0.87 0.98 0.98 ns, max t rcko_parity_ecc clock clk to eccparity in ecc encode only mode 0.66 0.72 0.80 0.80 ns, max t rcko_sdbit_ecc and t rcko_sdbit_ecc_reg clock clk to biterr (without output register) 2.17 2.38 3.01 3.01 ns, max clock clk to biterr (with output register) 0.57 0.65 0.76 0.76 ns, max t rcko_rdaddr_ecc and t rcko_rdaddr_ecc_reg clock clk to rdaddr output with ecc (without output register) 0.64 0.74 0.90 0.90 ns, max clock clk to rdaddr output with ecc (with output register) 0.71 0.79 0.92 0.92 ns, max setup and hold times before/after clock clk t rcck_addra /t rckc_addra addr inputs (8) 0.38/0.27 0.42/0.28 0.48/ 0.31 0.48/0.38 ns, min t rdck_di_wf_nc / t rckd_di_wf_nc data input setup/hold time when block ram is configured in write_first or no_change mode (9) 0.49/0.51 0.55/0.53 0.63/ 0.57 0.63/0.57 ns, min t rdck_di_rf /t rckd_di_rf data input setup/hold time when block ram is configured in read_first mode (9) 0.17/0.25 0.19/0.29 0.21/ 0.35 0.21/0.35 ns, min t rdck_di_ecc /t rckd_di_ecc din inputs with block ram ecc in standard mode (9) 0.42/0.37 0.47/0.39 0.53/ 0.43 0.53/0.58 ns, min t rdck_di_eccw / t rckd_di_eccw din inputs with block ram ecc encode only (9) 0.79/0.37 0.87/0.39 0.99/ 0.43 0.99/0.58 ns, min t rdck_di_ecc_fifo / t rckd_di_ecc_fifo din inputs with fifo ecc in standard mode (9) 0.89/0.47 0.98/0.50 1.12/ 0.54 1.12/0.69 ns, min t rcck_injectbiterr / t rckc_injectbiterr inject single/double bit error in ecc mode 0.49/0.30 0.55/0.31 0.63/ 0.34 0.63/0.43 ns, min t rcck_en /t rckc_en block ram enable (en) input 0.30/0.1 7 0.33/0.18 0.38/0.20 0.38/0.32 ns, min t rcck_regce /t rckc_regce ce input of output register 0.21/0.1 3 0.25/0.13 0.31/0.14 0.31/0.19 ns, min t rcck_rstreg /t rckc_rstreg synchronous rstreg input 0.25/0.06 0 .27/0.06 0.29/0.06 0.29/0.14 ns, min t rcck_rstram /t rckc_rstram synchronous rstram input 0.27/0.35 0.29/0.37 0.31/0.39 0.31/0.39 ns, min t rcck_wea /t rckc_wea write enable (we) input (block ram only) 0.38/0.15 0.41/0.16 0.46/0.17 0.46/0.29 ns, min s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 57 t rcck_wren /t rckc_wren wren fifo inputs 0.39/0.25 0.39/ 0.30 0.40/0.37 0.40/0.49 ns, min t rcck_rden /t rckc_rden rden fifo inputs 0.36/0.26 0.36/ 0.30 0.37/0.37 0.37/0.49 ns, min reset delays t rco_flags reset rst to fifo flags/pointers (10) 0.76 0.83 0.93 0.93 ns, max t rrec_rst /t rrem_rst fifo reset recovery and removal timing (11) 1.59/?0.68 1.76/?0.6 8 2.01/?0.68 2.01/?0.68 ns, max maximum frequency f max_bram_wf_nc block ram (write first and no change modes) when not in sdp rf mode 601.32 543.77 458.09 458.09 mhz f max_bram_rf_performance block ram (read first, performance mode) when in sdp rf mode but no address overlap between port a and port b 601.32 543.77 458.09 458.09 mhz f max_bram_rf_delayed_write block ram (read first, delayed_write mode) when in sdp rf mode and there is possibility of overlap between port a and port b addresses 528.26 477.33 400.80 400.80 mhz f max_cas_wf_nc block ram cascade (write first, no change mode) when cascade but not in rf mode 551.27 493.93 408.00 408.00 mhz f max_cas_rf_performance block ram cascade (read first, performance mode) when in cascade with rf mode and no possibility of address overlap/one port is disabled 551.27 493.93 408.00 408.00 mhz f max_cas_rf_delayed_write when in cascade rf mode and there is a possibility of address overlap between port a and port b 478.24 427.35 350.88 350.88 mhz f max_fifo fifo in all modes without ecc 601.32 543.77 458.09 458.09 mhz f max_ecc block ram and fifo in ecc configuration 484.26 430.85 351.12 351.12 mhz notes: 1. the timing report shows all of these parameters as t rcko_do . 2. t rcko_dor includes t rcko_dow , t rcko_dopr , and t rcko_dopw as well as the b port equivalent timing parameters. 3. these parameters also apply to synchronous fifo with do_reg = 0. 4. t rcko_do includes t rcko_dop as well as the b port equivalent timing parameters. 5. these parameters also apply to multirate (asynchronous) and synchronous fifo with do_reg = 1. 6. t rcko_flags includes the following parameters: t rcko_aempty , t rcko_afull , t rcko_empty , t rcko_full , t rcko_rderr , t rcko_wrerr. 7. t rcko_pointers includes both t rcko_rdcount and t rcko_wrcount. 8. the addr setup and hold must be met when en is asserted (even when we is deasserted) . otherwise, block ram data corruption is possible. 9. these parameters include both a and b inputs as well as the parity inputs of a and b. 10. t rco_flags includes the following flags: aempty, afull, em pty, full, rderr, wrerr, rdcount, and wrcount. 11. rden and wren must be held low prior to and during reset. the fifo reset must be asserted for at least five positive clock e dges of the slowest clock (wrclk or rdclk). ta bl e 6 9 : block ram and fifo switching characteristics (cont?d) symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 58 dsp48e1 switching characteristics ta bl e 7 0 : dsp48e1 switching characteristics symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq setup and hold times of data/control pins to the input register clock t dspdck_a_areg / t dspckd_a_areg a input to a register clk 0.24/0.12 0.27/0.14 0.31/0.16 0.33/0.18 ns t dspdck_b_breg /t dspckd_b_breg b input to b register clk 0.28/0.13 0.32/0.14 0.39/0.15 0.41/0.18 ns t dspdck_c_creg /t dspckd_c_creg c input to c register clk 0.15/0. 15 0.17/0.17 0.20/0.20 0.20/0.22 ns t dspdck_d_dreg /t dspckd_d_dreg d input to d register clk 0.21/0. 19 0.27/0.22 0.35/0.26 0.35/0.27 ns t dspdck_acin_areg /t dspckd_acin_areg acin input to a register clk 0.21/0.12 0.24/0.14 0.27/0.16 0.30/0.16 ns t dspdck_bcin_breg /t dspckd_bcin_breg bcin input to b register clk 0.22/ 0.13 0.25/0.14 0.30/0.15 0.32/0.15 ns setup and hold times of data pins to the pipeline register clock t dspdck_ { a, b} _mreg_mult / t dspckd_ { a, b}_mreg_mult { a, b} input to m register clk using multiplier 2.04/?0.01 2.34/?0.01 2.7 9/?0.01 2.79/?0.01 ns t dspdck_ { a, d}_adreg / t dspckd_ { a, d}_adreg { a, d} input to ad register clk 1. 09/?0.02 1.25/?0.02 1.49/ ?0.02 1.49/?0.02 ns setup and hold times of data/control pins to the output register clock t dspdck_ { a, b}_preg_mult / t dspckd_ { a, b}_preg_mult { a, b} input to p register clk using multiplier 3.41/?0.24 3.90/?0.24 4.6 4/?0.24 4.64/?0.24 ns t dspdck_d_preg_mult / t dspckd_d_preg_mult d input to p register clk using multiplier 3.33/?0.62 3.81/?0.62 4.5 3/?0.62 4.53/?0.62 ns t dspdck_ { a, b}_preg / t dspckd_ { a, b}_preg a or b input to p register clk not using multiplier 1.47/?0.24 1.68/?0.24 2.0 0/?0.24 2.00/?0.24 ns t dspdck_c_preg / t dspckd_c_preg c input to p register clk not using multiplier 1.30/?0.22 1.49/?0.22 1.7 8/?0.22 1.78/?0.22 ns t dspdck_pcin_preg / t dspckd_pcin_preg pcin input to p register clk 1.12/?0. 13 1.28/?0.13 1.52/?0.13 1.52/?0.13 ns setup and hold times of the ce pins t dspdck_ { cea, ceb}_ { areg, breg} / t dspckd_ { cea, ceb}_ { areg, breg} { cea; ceb} input to { a; b} register clk 0.30/0.05 0.36/0.06 0.44/0.09 0.44/0.09 ns t dspdck_cec_creg / t dspckd_cec_creg cec input to c register clk 0.24/0. 08 0.29/0.09 0.36/0.11 0.36/0.11 ns t dspdck_ced_dreg / t dspckd_ced_dreg ced input to d register clk 0.31/?0. 02 0.36/?0.02 0.44/?0.02 0.44/0.02 ns t dspdck_cem_mreg / t dspckd_cem_mreg cem input to m register clk 0.26/0.15 0.29/0.17 0.33/0.20 0.33/0.20 ns t dspdck_cep_preg / t dspckd_cep_preg cep input to p register clk 0.31/0.01 0.36/0.01 0.45/0.01 0.45/0.01 ns setup and hold times of the rst pins t dspdck_ { rsta, rstb}_ { areg, breg} / t dspckd_ { rsta, rstb}_ { areg, breg} { rsta, rstb} input to { a, b} register clk 0.34/0.10 0.39/0.11 0.47/0.13 0.47/0.14 ns t dspdck_rstc_creg / t dspckd_r stc_creg rstc input to c register clk 0.06/0.22 0.07/0.24 0.08/0.26 0.08/0.26 ns t dspdck_rstd_dreg / t dspckd_r std_dreg rstd input to d register clk 0.37/0.06 0.42/0.06 0.50/0.07 0.50/0.07 ns t dspdck_rstm_mreg / t dspckd_rstm_mreg rstm input to m register clk 0.18/ 0.18 0.20/0.21 0.23/0.24 0.23/0.24 ns t dspdck_rstp_preg / t dspckd_rstp_preg rstp input to p register clk 0.24/ 0.01 0.26/0.01 0.30/0.01 0.30/0.11 ns combinatorial delays from input pins to output pins t dspdo_a_carryout_mult a input to carryout output using multiplier 3.21 3.69 4.39 4.39 ns t dspdo_d_p_mult d input to p output using multiplier 3.15 3.61 4.30 4.30 ns s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 59 t dspdo_a_p a input to p output not using multiplier 1.30 1.48 1.76 1.76 ns t dspdo_c_p c input to p output 1.13 1.30 1.55 1.55 ns combinatorial delays from input pins to cascading output pins t dspdo_ { a; b}_ { acout; bcout} { a, b} input to { acout, bcout} output 0.47 0.53 0.63 0.63 ns t dspdo_ { a, b}_carrycascout_mult { a, b} input to carrycascout output using multiplier 3.44 3.94 4.69 4.69 ns t dspdo_d_carrycascout_mult d input to carrycascout output using multiplier 3.36 3.85 4.58 4.58 ns t dspdo_ { a, b}_carrycascout { a, b} input to carrycascout output not using multiplier 1.50 1.72 2.04 2.04 ns t dspdo_c_carrycascout c input to carrycascout output 1.34 1.53 1.83 1.83 ns combinatorial delays from cascading input pins to all output pins t dspdo_acin_p_mult acin input to p output using multiplier 3.09 3.55 4.24 4.24 ns t dspdo_acin_p acin input to p output not using multiplier 1.16 1.33 1.59 1.59 ns t dspdo_acin_acout acin input to acout output 0.32 0.37 0.45 0.45 ns t dspdo_acin_carrycascout_mult acin input to carrycascout output using multiplier 3.30 3.79 4.52 4.52 ns t dspdo_acin_carrycascout acin input to carrycascout output not using multiplier 1.37 1.57 1.87 1.87 ns t dspdo_pcin_p pcin input to p output 0.94 1.08 1.29 1.29 ns t dspdo_pcin_c arrycascout pcin input to carrycascout output 1.15 1.32 1.57 1.57 ns clock to outs from output re gister clock to output pins t dspcko_p_preg clk preg to p output 0.33 0.35 0.39 0.39 ns t dspcko_carrycascout_preg clk preg to carrycascout output 0.44 0.50 0.59 0.59 ns clock to outs from pipeline register clock to output pins t dspcko_p_mreg clk mreg to p output 1.42 1.64 1.96 1.96 ns t dspcko_carrycascout_mreg clk mreg to carrycascout output 1.63 1.87 2.24 2.24 ns t dspcko_p_adreg_mult clk adreg to p output using multiplier 2.30 2.63 3.13 3.13 ns t dspcko_carrycascout_adreg_mult clk adreg to carrycascout output using multiplier 2.51 2.87 3.41 3.41 ns ta bl e 7 0 : dsp48e1 switching characteristics (cont?d) symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 60 clock to outs from input re gister clock to output pins t dspcko_p_areg_mult clk areg to p output using multiplier 3.34 3.83 4.55 4.55 ns t dspcko_p_breg clk breg to p output not using multiplier 1.39 1.59 1.88 1.88 ns t dspcko_p_creg clk creg to p output not using multiplier 1.43 1.64 1.95 1.95 ns t dspcko_p_dreg_mult clk dreg to p output using multiplier 3.32 3.80 4.51 4.51 ns clock to outs from input register clock to cascadi ng output pins t dspcko_ { acout; bcout}_ { areg; breg} clk (acout, bcout) to { a,b} register output 0.55 0.62 0.74 0.74 ns t dspcko_carrycascout_ { areg, breg}_mult clk (areg, breg) to carrycascout output using multiplier 3.55 4.06 4.84 4.84 ns t dspcko_carrycascout_breg clk breg to carrycascout output not using multiplier 1.60 1.82 2.16 2.16 ns t dspcko_carrycascout_dreg_mult clk dreg to carrycascout output using multiplier 3.52 4.03 4.79 4.79 ns t dspcko_carrycascout_creg clk creg to carrycascout output 1.64 1.88 2.23 2.23 ns maximum frequency f max with all registers used 741.84 650.20 547.95 547.95 mhz f max_patdet with pattern detector 627.35 549.75 463.61 463.61 mhz f max_mult_nomreg two register multiply without mreg 412.20 360.75 303.77 303.77 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect 374.25 327.65 276.01 276.01 mhz f max_preadd_mult_noadreg without adreg 468.82 408.66 342.70 342.70 mhz f max_preadd_mult_noadreg_patdet without adreg with pattern detect 468.82 408.66 342.70 342.70 mhz f max_nopipelinereg without pipeline registers (mreg, adreg) 306.84 267.81 225.02 225.02 mhz f max_nopipelinereg_patdet without pipeline registers (mreg, adreg) with pattern detect 285.23 249.13 209.38 209.38 mhz ta bl e 7 0 : dsp48e1 switching characteristics (cont?d) symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 61 clock buffers and networks ta bl e 7 1 : global clock switching characte ristics (incl uding bufgctrl) symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq t bccck_ce /t bcckc_ce (1) ce pins setup/hold 0.12/0.30 0.14/0.38 0.26/0. 38 0.26/0.92 ns t bccck_s /t bcckc_s (1) s pins setup/hold 0.12/0.30 0. 14/0.38 0.26/0.38 0.26/0.92 ns t bccko_o (2) bufgctrl delay from i0/i1 to o 0.08 0.10 0.12 0.12 ns maximum frequency f max_bufg global clock tree (bufg) 741.00 710.00 625.00 625.00 mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of the global clock when switching between clocks. these parameters do not apply to the bufgmux primitive that assures glitch-free operation. the other global clock setup and hold time s are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switchin g between clocks. 2. t bgcko_o (bufg delay from i0 to o) values are the same as t bccko_o values. ta bl e 7 2 : input/output clock switching characteristics (bufio) symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq t biocko_o clock to out delay from i to o 1.04 1.14 1.32 1.32 ns maximum frequency f max_bufio i/o clock tree (bufio) 800.00 800.00 710.00 710.00 mhz ta bl e 7 3 : regional clock buffer switching characteristics (bufr) symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq t brcko_o clock to out delay from i to o 0.60 0.65 0.77 0.77 ns t brcko_o_byp clock to out delay from i to o with divide bypass attribute set 0.30 0.32 0.38 0.38 ns t brdo_o propagation delay from cl r to o 0.71 0.75 0.96 0.96 ns maximum frequency f max_bufr (1) regional clock tree (bufr) 600.00 540.00 450.00 450.00 mhz notes: 1. the maximum input frequency to the bufr and bufmr is the bufio f max frequency. ta bl e 7 4 : horizontal clock buffer switching characteristics (bufh) symbol description speed grade units -3e -2e/-2i-2li -1c/-1i -1q/-1lq t bhcko_o bufh delay from i to o 0.10 0.11 0.13 0.13 ns t bhcck_ce /t bhckc_ce ce pin setup and hold 0.20/0.1 6 0.23/0.20 0.38/0.21 0.38/0.79 ns maximum frequency f max_bufh horizontal clock buffer (bufh) 741.00 710.00 625.00 625.00 mhz s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 62 mmcm switching characteristics ta bl e 7 5 : duty-cycle distortion and clock-tree skew symbol description device speed grade units -3e -2e -2i -2li -1c -1i -1q -1lq t dcd_clk global clock tree duty-cycle distortion (1) all 0.20 0.20 0.20 0.20 0.20 0.20 0.20 0.20 ns t ckskew global clock tree skew (2) xc7z030 0.29 0.36 0.36 0.36 0.37 0.37 n/a n/a ns xc7z035 0.43 0.54 0.54 0.54 0.57 0.57 n/a n/a ns xc7z045 0.43 0.54 0.54 0.54 0.57 0.57 n/a n/a ns xc7z100 n/a n/a 0.54 0.54 n/a 0.56 n/a n/a ns xa7z030 n/a n/a n/a n/a n/a 0.37 0.37 n/a ns xq7z030 n/a n/a 0.36 0.36 n/a 0.37 0.37 n/a ns xq7z045 n/a n/a 0.54 0.54 n/a 0.57 0.57 0.57 ns XQ7Z100 n/a n/a 0.54 0.54 n/a 0.56 n/a n/a ns t dcd_bufio i/o clock tree duty-cycle distortion all 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 ns t bufioskew i/o clock tree skew across one clock region all 0.02 0.02 0.02 0.02 0.02 0.02 0.02 0.02 ns t dcd_bufr regional clock tree duty-cycle distortion all 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.15 ns notes: 1. these parameters represent the worst-case duty-cycle distortion observable at the pins of the device using lvds output buffer s. for cases where other i/o standar ds are used, ibis can be used to calculate any additional duty-cycle distortion that might be caused by asymmetrical rise/fall times. 2. the t ckskew value represents the worst-case clock-tree skew observable between sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and f ed by the same or adjacent clock-tree branches. use the xilinx timing analyzer tools to evaluate application specific clock skew. ta bl e 7 6 : mmcm specification symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq mmcm_f inmax maximum input clock frequency 1066.00 933.00 800.00 800.00 mhz mmcm_f inmin minimum input clock freq uency 10.00 10.00 10.00 10.00 mhz mmcm_f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max mmcm_f induty allowable input duty cycle: 10?49 mhz 25.00 25.00 25.00 25.00 % allowable input duty cycle: 50?199 mhz 30.00 30. 00 30.00 30.00 % allowable input duty cycle: 200?399 mhz 35.00 35.00 35.00 35.00 % allowable input duty cycle: 400?499 mhz 40.00 40.00 40.00 40.00 % allowable input duty cycle: >500 mhz 45.00 45.00 45.00 45.00 % mmcm_f min_psclk minimum dynamic phase-shift clock frequency 0.01 0.01 0.01 0.01 mhz mmcm_f max_psclk maximum dynamic phase-shift clock frequency 550.00 500.00 450.00 450.00 mhz mmcm_f vcomin minimum mmcm vco frequency 600.00 600.00 600.00 600.00 mhz mmcm_f vcomax maximum mmcm vco frequency 1600.00 1440.00 1200.00 1200.00 mhz mmcm_f bandwidth low mmcm bandwidth at typical (1) 1.00 1.00 1.00 1.00 mhz high mmcm bandwidth at typical (1) 4.00 4.00 4.00 4.00 mhz mmcm_t statphaoffset static phase offset of the mmcm outputs (2) 0.12 0.12 0.12 0.12 ns s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 63 mmcm_t outjitter mmcm output jitter note 3 mmcm_t outduty mmcm output clock duty-cycle precision (4) 0.20 0.20 0.20 0.20 ns mmcm_t lockmax mmcm maximum lock time 100.00 100.00 100.00 100.00 s mmcm_f outmax mmcm maximum output frequenc y 1066.00 933.00 800.00 800.00 mhz mmcm_f outmin mmcm minimum output frequency (5)(6) 4.69 4.69 4.69 4.69 mhz mmcm_t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max mmcm_rst minpulse minimum reset pulse width 5.00 5.00 5.00 5.00 ns mmcm_f pfdmax maximum frequency at the phase frequency detector 550.00 500.00 450.00 450.00 mhz mmcm_f pfdmin minimum frequency at the phase frequency detector 10.00 10.00 10.00 10.00 mhz mmcm_t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle mmcm switching characteristics setup and hold t mmcmdck_psen / t mmcmckd_psen setup and hold of phase-shift enab le 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00 ns t mmcmdck_psincdec / t mmcmckd_psincdec setup and hold of phase-shift increment/decrement 1.04/0.00 1.04/0.00 1. 04/0.00 1.04/0.00 ns t mmcmcko_psdone phase shift clock-to-out of psdone 0.59 0.68 0.81 0.81 ns dynamic reconfiguration port (drp) for mmcm before and after dclk t mmcmdck_daddr / t mmcmckd_daddr daadr setup/hold 1.25/ 0.15 1.40/0.15 1.63/0. 15 1.63/0.15 ns, min t mmcmdck_di / t mmcmckd_di di setup/hold 1.25/0.15 1.40/0. 15 1.63/0.15 1.63/0.15 ns, min t mmcmdck_den / t mmcmckd_den den setup/hold 1.76/ 0.00 1.97/0.00 2.29/0. 00 2.29/0.00 ns, min t mmcmdck_dwe / t mmcmckd_dwe dwe setup/hold 1.25/ 0.15 1.40/0.15 1.63/0. 15 1.63/0.15 ns, min t mmcmcko_drdy clk to out of drdy 0.65 0.72 0.99 0.99 ns, max f dck dclk frequency 200.00 200.00 200.00 200.00 mhz, max notes: 1. the mmcm does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequen cies. 2. the static offset is measured between any mmcm outputs with identical phase. 3. values for this parameter are available in the clocking wizard. see http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm . 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. 6. when clkout4_cascade = true, mmcm_f outmin is 0.036 mhz. ta bl e 7 6 : mmcm specification (cont?d) symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 64 pll switching characteristics ta bl e 7 7 : pll specification symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq pll_f inmax maximum input clock frequency 1066.00 933.00 800.00 800.00 mhz pll_f inmin minimum input clock frequency 19.00 19.00 19.00 19.00 mhz pll_f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max pll_f induty allowable input duty cycle: 19?49 mhz 25.00 25.00 25.00 25.00 % allowable input duty cycle: 50 ?199 mhz 30.00 30.00 30.00 30.00 % allowable input duty cycle: 2 00?399 mhz 35.00 35.00 35.00 35.00 % allowable input duty cycle: 4 00?499 mhz 40.00 40.00 40.00 40.00 % allowable input duty cycle: >500 mhz 45.00 45.00 45.00 45.00 % pll_f vcomin minimum pll vco frequency 800.00 800.00 800.00 800.00 mhz pll_f vcomax maximum pll vco frequency 2133.00 1866.00 1600.00 1600.00 mhz pll_f bandwidth low pll bandwidth at typical (1) 1.00 1.00 1.00 1.00 mhz high pll bandwidth at typical (1) 4.00 4.00 4.00 4.00 mhz pll_t statphaoffset static phase offset of the pll outputs (2) 0.12 0.12 0.12 0.12 ns pll_t outjitter pll output jitter (3) note 1 pll_t outduty pll output clock duty-cycle precision (4) 0.20 0.20 0.20 0.20 ns pll_t lockmax pll maximum lock time 100.00 100.00 100.00 100.00 s pll_f outmax pll maximum output frequency 1066.00 933.00 800.00 800.00 mhz pll_f outmin pll minimum output frequency (5) 6.25 6.25 6.25 6.25 mhz pll_t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max pll_rst minpulse minimum reset pulse width 5.00 5.00 5.00 5.00 ns pll_f pfdmax maximum frequency at the phase frequency detector 550.00 500.00 450.00 450.00 mhz pll_f pfdmin minimum frequency at the phase frequen cy detector 19.00 19.00 19.00 19.00 mhz pll_t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle dynamic reconfiguration port (drp) for pll before and after dclk t pllcck_daddr / t pllckc_daddr setup and hold of d address 1.25/0.15 1.40/0.15 1.63/0.15 1.63/0.15 ns, min t pllcck_di / t pllckc_di setup and hold of d input 1.25/0.15 1. 40/0.15 1.63/0.15 1.63/0.15 ns, min t pllcck_den / t pllckc_den setup and hold of d enable 1.76/0.00 1.97/0.00 2.29/0.00 2.29/0.00 ns, min t pllcck_dwe / t pllckc_dwe setup and hold of d write enable 1.25/0. 15 1.40/0.15 1.63/0.15 1.63/0.15 ns, min t pllcko_drdy clk to out of drdy 0.65 0.72 0.99 0.99 ns, max f dck dclk frequency 200.00 200.00 200.00 200.00 mhz, max notes: 1. the pll does not filter typical spread-spectrum input cloc ks because they are usually far below the bandwidth filter frequenc ies. 2. the static offset is measured between any pll outputs with identical phase. 3. values for this parameter are available in the clocking wizard. see http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm . 4. includes global clock buffer. 5. calculated as f vco /128 assuming output duty cycle is 50%. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 65 device pin-to-pin outp ut paramete r guidelines ta bl e 7 8 : clock-capable clock input to output delay without mmcm/pll (near clock region) symbol description device speed grade units -3e -2e -2i -2li -1c -1i -1q -1lq sstl15 clock-capable clock input to output dela y using output flip-flops, fast slew rate, without mmcm/pll. t ickof clock-capable clock input and outff at pins/banks closest to the bufgs without mmcm/pll (near clock region) xc7z030 5.32 5.85 5.85 5.85 6.55 6.55 n/a n/a ns xc7z035 5.27 5.78 5.78 5.78 6.48 6.48 n/a n/a ns xc7z045 5.27 5.78 5.78 5.78 6.48 6.48 n/a n/a ns xc7z100 n/a n/a 5.91 5.91 n/a 6.62 n/a n/a ns xa7z030 n/a n/a n/a n/a n/a 6.55 6.55 n/a ns xq7z030 n/a n/a 5.85 5.85 n/a 6.55 6.55 n/a ns xq7z045 n/a n/a 5.78 5.78 n/a 6.48 6.48 6.48 ns XQ7Z100 n/a n/a 5.91 5. 91 n/a 6.62 n/a n/a ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. refer to the die level bank numbering overview section of zynq-7000 all programmable soc packaging and pinout specification (ug865). ta bl e 7 9 : clock-capable clock input to output de lay without mmcm/pll (far clock region) symbol description device speed grade units -3e -2e -2i -2li -1c -1i -1q -1lq sstl15 clock-capable clock input to output dela y using output flip-flops, fast slew rate, without mmcm/pll. t ickoffar clock-capable clock input and outff at pins/banks farthest from the bufgs without mmcm/pll (far clock region) xc7z030 5.32 5.85 5.85 5. 85 6.55 6.55 n/a n/a ns xc7z035 5.88 6.46 6.46 6. 46 7.23 7.23 n/a n/a ns xc7z045 5.88 6.46 6.46 6. 46 7.23 7.23 n/a n/a ns xc7z100 n/a n/a 6.59 6.59 n/a 7.37 n/a n/a ns xa7z030 n/a n/a n/a n/a n/a 6.55 6.55 n/a ns xq7z030 n/a n/a 5.85 5.85 n/a 6.55 6.55 n/a ns xq7z045 n/a n/a 6.46 6.46 n/a 7.23 7.23 7.23 ns XQ7Z100 n/a n/a 6.59 6.59 n/a 7.37 n/a n/a ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. refer to the die level bank numbering overview section of zynq-7000 all programmable soc packaging and pinout specification (ug865). s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 66 ta bl e 8 0 : clock-capable clock input to output delay with mmcm symbol description device speed grade units -3e -2e -2i -2li -1c -1i -1q -1lq sstl15 clock-capable clock input to output dela y using output flip-flops, fast slew rate, with mmcm. t ickofmmcmcc clock-capable clock input and outff with mmcm xc7z030 0.92 0.92 0.92 0.92 0.92 0.92 n/a n/a ns xc7z035 0.97 0.97 0.97 0.97 0.97 0.97 n/a n/a ns xc7z045 0.97 0.97 0.97 0.97 0.97 0.97 n/a n/a ns xc7z100 n/a n/a 0.96 0.96 n/a 0.96 n/a n/a ns xa7z030 n/a n/a n/a n/a n/a 0.92 0.92 n/a ns xq7z030 n/a n/a 0.92 0.92 n/a 0.92 0.92 n/a ns xq7z045 n/a n/a 0.97 0.97 n/a 0.97 0.97 0.97 ns XQ7Z100 n/a n/a 0.96 0.96 n/a 0.96 n/a n/a ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. mmcm output jitter is already included in the timing calculation. ta bl e 8 1 : clock-capable clock input to output delay with pll symbol description device speed grade units -3e -2e -2i -2li -1c -1i -1q -1lq sstl15 clock-capable clock input to output dela y using output flip-flops, fast slew rate, with pll. t ickofpllcc clock-capable clock input and outff with pll xc7z030 0.81 0.81 0.81 0.81 0.81 0.81 n/a n/a ns xc7z035 0.86 0.86 0.86 0.86 0.86 0.86 n/a n/a ns xc7z045 0.86 0.86 0.86 0.86 0.86 0.86 n/a n/a ns xc7z100 n/a n/a 0.85 0.85 n/a 0.85 n/a n/a ns xa7z030 n/a n/a n/a n/a n/a 0.81 0.81 n/a ns xq7z030 n/a n/a 0.81 0.81 n/a 0.81 0.81 n/a ns xq7z045 n/a n/a 0.86 0.86 n/a 0.86 0.86 0.86 ns XQ7Z100 n/a n/a 0.85 0.85 n/a 0.85 n/a n/a ns notes: 1. this table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. pll output jitter is already included in the timing calculation. ta bl e 8 2 : pin-to-pin, clock-to-out using bufio symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq t ickofcs clock-to-out of i/o clock for hr i/o banks 4.93 5.52 6.20 6.20 ns clock-to-out of i/o clock for hp i/o banks 4.85 5.44 6.11 6.11 ns s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 67 device pin-to-pin input parameter guidelines ta bl e 8 3 : global clock input setup and hold without mmcm/pll with zhold_delay on hr i/o banks symbol description device speed grade units -3e -2e -2i -2li -1c -1i -1q -1lq input setup and hold time relative to global clock input signal for sstl15 standard. (1) t psfd / t phfd full delay (legacy delay or default delay) global clock input and iff (2) without mmcm/pll with zhold_delay on hr i/o banks xc7z030 3.04/ ?0.34 3.16/ ?0.34 3.16/ ?0.34 3.16/ ?0.34 3.40/ ?0.34 3.40/ ?0.34 n/a n/a ns xc7z035 3.50/ ?0.47 3.67/ ?0.47 3.67/ ?0.47 3.67/ ?0.47 3.97/ ?0.47 3.97/ ?0.47 n/a n/a ns xc7z045 3.50/ ?0.47 3.67/ ?0.47 3.67/ ?0.47 3.67/ ?0.47 3.97/ ?0.47 3.97/ ?0.47 n/a n/a ns xc7z100 n/a n/a 3.81/ ?0.52 3.81/ ?0.52 n/a 4.13/ ?0.52 n/a n/a ns xa7z030 n/a n/a n/a n/a n/a 3.40/ ?0.34 3.40/ ?0.34 n/a ns xq7z030 n/a n/a 3.16/ ?0.34 3.16/ ?0.34 n/a 3.40/ ?0.34 3.40/ ?0.34 n/a ns xq7z045 n/a n/a 3.67/ ?0.47 3.67/ ?0.47 n/a 3.97/ ?0.47 3.97/ ?0.47 3.97/ ?0.47 ns XQ7Z100 n/a n/a 3.81 ?0.52 3.81 ?0.52 n/a 4.13/ ?0.52 n/a n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the gl obal clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 68 ta bl e 8 4 : clock-capable clock input setup and hold with mmcm symbol description device speed grade units -3e -2e -2i -2li -1c -1i -1q -1lq input setup and hold time relative to global clock input signal for sstl15 standard. (1) t psmmcmcc / t phmmcmcc no delay clock- capable clock input and iff (2) with mmcm xc7z030 2.41/ ?0.23 2.68/ ?0.23 2.68/ ?0.23 2.68/ ?0.23 2.95/ ?0.23 2.95/ ?0.23 n/a n/a ns xc7z035 2.73/ ?0.09 3.00/ ?0.09 3.00/ ?0.09 3.00/ ?0.09 3.32/ ?0.09 3.32/ ?0.09 n/a n/a ns xc7z045 2.73/ ?0.09 3.00/ ?0.09 3.00/ ?0.09 3.00/ ?0.09 3.32/ ?0.09 3.32/ ?0.09 n/a n/a ns xc7z100 n/a n/a 3.00/ ?0.10 3.00/ ?0.09 n/a 3.32/ ?0.10 n/a n/a ns xa7z030 n/a n/a n/a n/a n/a 2.95/ ?0.23 2.95/ ?0.23 n/a ns xq7z030 n/a n/a 2.68/ ?0.23 2.68/ ?0.23 n/a 2.95/ ?0.23 2.95/ ?0.23 n/a ns xq7z045 n/a n/a 3.00/ ?0.09 3.00/ ?0.09 n/a 3.32/ ?0.09 3.32/ ?0.09 3.32/ ?0.09 ns XQ7Z100 n/a n/a 3.00/ ?0.10 3.00/ ?0.09 n/a 3.32/ ?0.10 n/a n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the gl obal clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 69 ta bl e 8 5 : clock-capable clock input setup and hold with pll symbol description device speed grade units -3e -2e -2i -2li -1c -1i -1q -1lq input setup and hold time relative to clock-capable clock input signal for sstl15 standard. (1) t pspllcc / t phpllcc no delay clock- capable clock input and iff (2) with pll xc7z030 2.71/ ?0.34 3.02/ ?0.34 3.02/ ?0.34 3.02/ ?0.34 3.29/ ?0.34 3.29/ ?0.34 n/a n/a ns xc7z035 2.91/ ?0.20 3.24/ ?0.20 3.24/ ?0.20 3.24/ ?0.20 3.53/ ?0.20 3.53/ ?0.20 n/a n/a ns xc7z045 2.91/ ?0.20 3.24/ ?0.20 3.24/ ?0.20 3.24/ ?0.20 3.53/ ?0.20 3.53/ ?0.20 n/a n/a ns xc7z100 n/a n/a 3.24/ ?0.21 3.24/ ?0.21 n/a 3.53/ ?0.21 n/a n/a ns xa7z030 n/a n/a n/a n/a n/a 3.29/ ?0.34 3.29/ ?0.34 n/a ns xq7z030 n/a n/a 3.02/ ?0.34 3.02/ ?0.34 n/a 3.29/ ?0.34 3.29/ ?0.34 n/a ns xq7z045 n/a n/a 3.24/ ?0.20 3.24/ ?0.20 n/a 3.53/ ?0.20 3.53/ ?0.20 3.53/ ?0.20 ns XQ7Z100 n/a n/a 3.24/ ?0.21 3.24/ ?0.21 n/a 3.53/ ?0.21 n/a n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards. ta bl e 8 6 : data input setup and hold times relative to a forwarded clock input pin using bufio symbol description speed grade units -3e -2e/-2i-2li -1c/-1i -1q/-1lq input setup and hold time relative to a forwar ded clock input pin using bufio for sstl15 standard. t pscs /t phcs setup/hold of i/o clock for hr i/o banks ?0 .36/1.36 ?0.36/1.50 ?0. 36/1.70 ?0.36/1.70 ns setup/hold of i/o clock for hp i/o banks ? 0.34/1.39 ?0.34/1.53 ?0. 34/1.73 ?0.34/1.73 ns ta bl e 8 7 : sample window symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq t samp sampling error at receiver pins (1) 0.51 0.56 0.61 0.61 ns t samp_bufio sampling error at receiver pins using bufio (2) 0.30 0.35 0.40 0.40 ns notes: 1. this parameter indicates the total sampling error of the pl ddr input registers, measured across voltage, temperature, and pr ocess. the characterization methodology uses the mmcm to capture the ddr in put registers? edges of operation. these measurements include: - clk0 mmcm jitter - mmcm accuracy (phase offset) - mmcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of the pl ddr input registers, measured across voltage, temperature, and pr ocess. the characterization methodology uses the bufio clock network and idelay to capture the ddr input registers? edges of operation. th ese measurements do not include package or clock tree skew. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 70 additional package parameter guidelines the parameters in this section provide the necessary values for calculating timing budgets for pl clock transmitter and receiver data-valid windows. ta bl e 8 8 : package skew symbol description device package value units t pkgskew package skew (1) xc7z030 sbg485/sbv485 113 ps fbg484/fbv484 113 ps fbg676/fbv676 113 ps ffg676/ffv676 136 ps xc7z035 fbg676/fbv676 159 ps ffg676/ffv676 158 ps ffg900/ffv900 191 ps xc7z045 fbg676/fbv676 159 ps ffg676/ffv676 158 ps ffg900/ffv900 191 ps xc7z100 ffg900/ffv900 161 ps ffg1156/ffv1156 165 ps xa7z030 fbg484/fbv484 113 ps xq7z030 rb484 113 ps rf676 136 ps xq7z045 rf676/rfg676 158 ps rf900 191 ps XQ7Z100 rf900 161 ps rf1156 165 ps notes: 1. these values represent the worst-case skew between any two selectio resources in the package: shortest delay to longest delay from die pad to ball. 2. package delay information is available for these device/package combinations. this information can be used to deskew the pack age. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 71 gtx transceiver specifications gtx transceiver dc input and output levels ta bl e 8 9 summarizes the dc specifications of the gtx transceivers in zynq-7000 devices. consult the 7series fpgas gtx/gth transceivers user guide ( ug476 ) for further details. note: in figure 21 , differential peak-to-peak voltage = si ngle-ended peak-to-peak voltage x 2. ta bl e 9 0 summarizes the dc specifications of the cl ock input of the gtx transceiver. consult the 7 series fpgas gtx/gth transceivers user guide ( ug476 ) for further details. ta bl e 8 9 : gtx transceiver dc specifications symbol dc parameter conditions min typ max units dv ppout differential peak-t o-peak output voltage (1) transmitter output swing is set to maximum setting 1000 ? ? mv v cmoutdc dc common mode output voltage. equation based v mgtavtt ?dv ppout /4 mv r out differential output resistance ? 100 ? t oskew transmitter output pair (txp and txn) intra-pair skew ? 2 12 ps dv ppin differential peak-to-peak input voltage (external ac coupled) >10.3125 gb/s 150 ? 1250 mv 6.6 gb/s to 10.3125 gb/s 150 ? 1250 mv 6.6 gb/s 150 ? 2000 mv v in single-ended input voltage (2) dc coupled v mgtavtt =1.2v ?200 ? v mgtavtt mv v cmin common mode input voltage dc coupled v mgtavtt = 1.2v ? 2/3 v mgtavtt ?mv r in differential input resistance ? 100 ? c ext recommended external ac coupling capacitor (3) ? 100 ? nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in the 7 series fpgas gtx/gth transceivers user guide ( ug476 ) and can result in values lower than reported in this table. 2. voltage measured at the pin referenced to ground. 3. other values can be used as appropriate to conform to specific protocols and standards. x-ref target - figure 20 figure 20: single-ended peak-to-peak voltage x-ref target - figure 21 figure 21: differential peak-to-peak voltage 0 +v p n d s 191_16_ 090514 s ingle-ended pe a k-to-pe a k volt a ge 0 +v ?v p?n d s 191_17_ 090514 differenti a l pe a k-to-pe a k volt a ge s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 72 gtx transceiver switching characteristics consult the 7 series fpgas gtx/gth transceivers user guide ( ug476 ) for further information. performance specifications are divided between ta bl e 9 1 and ta b l e 9 2 . ta bl e 9 0 : gtx transceiver clock dc input level specification symbol dc parameter min typ max units v idiff differential peak-to-peak input voltage 250 ? 2000 mv r in differential input resistance ? 100 ? c ext required external ac coupling capacitor ? 100 ? nf ta bl e 9 1 : gtx transceiver performance for xc7z030, xa7z030, xc7z035, xc7z045, and xc7z100 devices by package symbol description output divider speed grade units -3e -2e/-2i/-2li -1c/1i (1) package type ff fb/sb ff fb/sb ff fb/sb f gtxmax (2) maximum gtx transceiver data rate 12.5 6.6 10.3125 6.6 8.0 6.6 gb/s f gtxmin (2) minimum gtx transceiver data rate 0.500 0.500 0.500 0.500 0.500 0.500 gb/s f gtxcrange cpll line rate range 1 3.2?6.6 gb/s 2 1.6?3.3 gb/s 4 0.8?1.65 gb/s 8 0.5?0.825 gb/s 16 n/a gb/s f gtxqrange1 qpll line rate range 1 1 5.93?8.0 5.93?6.6 5.93?8.0 5.93? 6.6 5.93?8.0 5.93?6.6 gb/s 2 2.965?4.0 2.965?4.0 2.965?4.0 gb/s 4 1.4825?2.0 1.4825?2.0 1.4825?2.0 gb/s 8 0.74125?1.0 0.74125?1.0 0.74125?1.0 gb/s 16 n/a n/a n/a gb/s f gtxqrange2 qpll line rate range 2 (3) 1 9.8? 12.5 n/a 9.8? 10.3125 n/a n/a gb/s 2 4.9?6.25 4.9?5.15625 n/a gb/s 4 2.45?3.125 2.45?2.578125 n/a gb/s 8 1.225?1.5625 1.225?1.2890625 n/a gb/s 16 0.6125?0.78125 0.61 25?0.64453125 n/a gb/s f gcpllrange gtx transceiver cpll frequency range 1.6?3.3 1.6?3.3 1.6?3.3 ghz f gqpllrange1 gtx transceiver qpll frequency range 1 5.93?8.0 5.93?8.0 5.93?8.0 ghz f gqpllrange2 gtx transceiver qpll frequency range 2 9.8?12.5 9.8?10.3125 n/a ghz notes: 1. the -1 speed grade requires a 4-byte internal data width for operation above 5.0 gb/s. 2. data rates between 8.0 gb/s and 9.8 gb/s are not available. 3. for qpll line rate range 2, the maximum line rate with the divider n set to 66 is 10.3125gb/s. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 73 ta bl e 9 2 : gtx transceiver performance for the xq7z030, xq7z045, and XQ7Z100 devices by package symbol description output divider speed grade units -2i -1i (1) -1q/-1lq (1) package type rf rb rf rb rf rb f gtxmax (2) maximum gtx transceiver data rate 10.3125 6.6 8.0 6.6 8.0 6.6 gb/s f gtxmin (2) minimum gtx transceiver data rate 0.500 0.500 0.500 0.500 0.500 0.500 gb/s f gtxcrange cpll line rate range 1 3.2?6.6 gb/s 2 1.6?3.3 gb/s 4 0.8?1.65 gb/s 8 0.5?0.825 gb/s 16 n/a gb/s f gtxqrange1 qpll line rate range 1 1 5.93?8.0 5.93?6.6 5.93?8.0 5 .93?6.6 5.93?8.0 5.93?6.6 gb/s 2 2.965?4.0 2.965?4.0 2.965?4.0 gb/s 4 1.4825?2.0 1.4825?2.0 1.4825?2.0 gb/s 8 0.74125?1.0 0.74125?1.0 0.74125?1.0 gb/s 16 n/a n/a n/a gb/s f gtxqrange2 qpll line rate range 2 (3) 1 9.8?10.3125 n/a n/a n/a gb/s 2 4.9?5.15625 n/a n/a gb/s 4 2.45?2.578125 n/a n/a gb/s 8 1.225?1.2890625 n/a n/a gb/s 16 0.6125?0.64453125 n/a n/a gb/s f gcpllrange gtx transceiver cpll frequency range 1.6?3.3 1.6?3.3 1.6?3.3 ghz f gqpllrange1 gtx transceiver qpll frequency range 1 5.93?8.0 5.93?8.0 5.93?8.0 ghz f gqpllrange2 gtx transceiver qpll frequency range 2 9.8?10.3125 n/a n/a ghz notes: 1. the -1 speed grade requires a 4-byte internal data width for operation above 5.0 gb/s. 2. data rates between 8.0 gb/s and 9.8 gb/s are not available. 3. for qpll line rate range 2, the maximum line rate with the divider n set to 66 is 10.3125gb/s. ta bl e 9 3 : gtx transceiver dynamic reconfiguration port (drp) switching characteristics symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq f gtxdrpclk gtxdrpclk maximum frequency 175.01 175.01 156.25 156.25 mhz s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 74 ta bl e 9 4 : gtx transceiver reference clock switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range -3e speed grade 60 ? 700 mhz all other speed grades 60 ? 670 mhz t rclk reference clock rise time 20% ? 80% ? 200 ? ps t fclk reference clock fall time 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle transceiver pll only 40 50 60 % x-ref target - figure 22 figure 22: reference clock timing parameters ta bl e 9 5 : gtx transceiver pll/lock time adaptation symbol description conditions all speed grades units min typ max t lock initial pll lock ? ? 1 ms t dlock clock recovery phase acquisition and adaptation time for decision feedback equalizer (dfe). after the pll is locked to the reference clock, this is the time it takes to lock the clock data recovery (cdr) to the data present at the input. ? 50,000 37 x10 6 ui clock recovery phase acquisition and adaptation time for low-power mode (lpm) when the dfe is disabled. ? 50,000 2.3 x10 6 ui d s 191_1 8 _ 01021 3 8 0 % 20 % t fclk t rclk s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 75 ta bl e 9 6 : gtx transceiver user clock switching characteristics (1)(2) symbol description data width conditions speed grade (3)(4) units internal logic interconnect logic -3e -2e/-2i/-2li -1c/-1i -1q/-1lq f txout txoutclk maximum frequency 412.500 412.500 312.500 312.500 mhz f rxout rxoutclk maximum frequency 412.500 412.500 312.500 312.500 mhz f txin txusrclk maximum frequency 16-bit 16-bit and 32-bit 412.500 412.500 312.500 312.500 mhz 32-bit 32-bit 390.625 322.266 250.000 250.000 mhz f rxin rxusrclk maximum frequency 16-bit 16-bit and 32-bit 412.500 412.500 312.500 312.500 mhz 32-bit 32-bit 390.625 322.266 250.000 250.000 mhz f txin2 txusrclk2 maximum frequency 16-bit 16-bit 412.500 412.500 312.500 312.500 mhz 16-bit and 32-bit 32-bit 390.625 322.266 250.000 250.000 mhz 64-bit 64-bit 195.313 161.133 125.000 125.000 mhz f rxin2 rxusrclk2 maximum frequency 16-bit 16-bit 412.500 412.500 312.500 312.500 mhz 16-bit and 32-bit 32-bit 390.625 322.266 250.000 250.000 mhz 64-bit 64-bit 195.313 161.133 125.000 125.000 mhz notes: 1. clocking must be implemented as described in the 7 series fpgas gtx/gth transceivers user guide ( ug476 ). 2. these frequencies are not supported for all possible transceiver configurations. 3. for speed grades -3 and -2, a 16-bit data path can only be used for speeds less than 6.6 gb/s. 4. for speed grade -1, a 16-bit data path can only be used for speeds less than 5.0 gb/s. ta bl e 9 7 : gtx transceiver transmitter switching characteristics symbol description cond ition min typ max units f gtxtx serial data rate range 0.500 ? f gtxmax gb/s t rtx tx rise time 20%?80% ? 40 ? ps t ftx tx fall time 80%?20% ? 40 ? ps t llskew tx lane-to-lane skew (1) ? ? 500 ps v txoobvdpp electrical idle amplitude ? ? 15 mv t txoobtransition electrical idle transition time ? ? 140 ns tj 12.5 total jitter (2)(4) 12.5 gb/s ? ? 0.28 ui dj 12.5 deterministic jitter (2)(4) ? ? 0.17 ui tj 11.18 total jitter (2)(4) 11.18 gb/s ? ? 0.28 ui dj 11.18 deterministic jitter (2)(4) ? ? 0.17 ui tj 10.3125 total jitter (2)(4) 10.3125 gb/s ? ? 0.28 ui dj 10.3125 deterministic jitter (2)(4) ? ? 0.17 ui tj 9.953 total jitter (2)(4) 9.953 gb/s ? ? 0.28 ui dj 9.953 deterministic jitter (2)(4) ? ? 0.17 ui tj 9.8 total jitter (2)(4) 9.8 gb/s ? ? 0.28 ui dj 9.8 deterministic jitter (2)(4) ? ? 0.17 ui tj 8.0 total jitter (2)(4) 8.0 gb/s ? ? 0.33 ui dj 8.0 deterministic jitter (2)(4) ? ? 0.17 ui s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 76 tj 6.6_qpll total jitter (2)(4) 6.6 gb/s ? ? 0.28 ui dj 6.6_qpll deterministic jitter (2)(4) ? ? 0.17 ui tj 6.6_cpll total jitter (3)(4) 6.6 gb/s ? ? 0.30 ui dj 6.6_cpll deterministic jitter (3)(4) ? ? 0.15 ui tj 5.0 total jitter (3)(4) 5.0 gb/s ? ? 0.33 ui dj 5.0 deterministic jitter (3)(4) ? ? 0.15 ui tj 4.25 total jitter (3)(4) 4.25 gb/s ? ? 0.33 ui dj 4.25 deterministic jitter (3)(4) ? ? 0.14 ui tj 3.75 total jitter (3)(4) 3.75 gb/s ? ? 0.34 ui dj 3.75 deterministic jitter (3)(4) ? ? 0.16 ui tj 3.2 total jitter (3)(4) 3.20 gb/s (5) ??0.2ui dj 3.2 deterministic jitter (3)(4) ??0.1ui tj 3.2l total jitter (3)(4) 3.20 gb/s (6) ? ? 0.35 ui dj 3.2l deterministic jitter (3)(4) ? ? 0.16 ui tj 2.5 total jitter (3)(4) 2.5 gb/s (7) ? ? 0.20 ui dj 2.5 deterministic jitter (3)(4) ? ? 0.08 ui tj 1.25 total jitter (3)(4) 1.25 gb/s (8) ? ? 0.15 ui dj 1.25 deterministic jitter (3)(4) ? ? 0.06 ui tj 500 total jitter (3)(4) 500 mb/s ??0.1ui dj 500 deterministic jitter (3)(4) ? ? 0.03 ui notes: 1. using same refclk input with tx phase alignment enabled for up to 12 consecutive transmitters (three fully populated gtx quad s). 2. using qpll_fbdiv = 40, 20-bit internal data width. these values are not intended for protocol specific compliance determination s. 3. using cpll_fbdiv = 2, 20-bit internal data width. these values are not intended for protocol specific compliance determinations . 4. all jitter values are based on a bit-error ratio of 1e -12 . 5. cpll frequency at 3.2 ghz and txout_div = 2. 6. cpll frequency at 1.6 ghz and txout_div = 1. 7. cpll frequency at 2.5 ghz and txout_div = 2. 8. cpll frequency at 2.5 ghz and txout_div = 4. ta bl e 9 7 : gtx transceiver transmitter switching characteristics (cont?d) symbol description cond ition min typ max units s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 77 ta bl e 9 8 : gtx transceiver receiver switching characteristics symbol description min typ max units f gtxrx serial data rate 0.500 ? f gtxmax gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data ? 10 ? ns rx oobvdpp oob detect threshold peak-to-peak 60 ? 150 mv rx sst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 ? 0 ppm rx rl run length (cid) ? ? 512 ui rx ppmtol data/refclk ppm offset tolerance bit rates 6.6 gb/s ?1250 ? 1250 ppm bit rates > 6.6 gb/s and 8.0 gb/s ?700 ? 700 ppm bit rates > 8.0 gb/s ?200 ? 200 ppm sj jitter tolerance (2) jt_sj 12.5 sinusoidal jitter (qpll) (3) 12.5 gb/s 0.3 ? ? ui jt_sj 11.18 sinusoidal jitter (qpll) (3) 11.18 gb/s 0.3 ? ? ui jt_sj 10.32 sinusoidal jitter (qpll) (3) 10.32 gb/s 0.3 ? ? ui jt_sj 9.95 sinusoidal jitter (qpll) (3) 9.95 gb/s 0.3 ? ? ui jt_sj 9.8 sinusoidal jitter (qpll) (3) 9.8 gb/s 0.3 ? ? ui jt_sj 8.0 sinusoidal jitter (qpll) (3) 8.0 gb/s 0.44 ? ? ui jt_sj 6.6_qpll sinusoidal jitter (qpll) (3) 6.6 gb/s 0.48 ? ? ui jt_sj 6.6_cpll sinusoidal jitter (cpll) (3) 6.6 gb/s 0.44 ? ? ui jt_sj 5.0 sinusoidal jitter (cpll) (3) 5.0 gb/s 0.44 ? ? ui jt_sj 4.25 sinusoidal jitter (cpll) (3) 4.25 gb/s 0.44 ? ? ui jt_sj 3.75 sinusoidal jitter (cpll) (3) 3.75 gb/s 0.44 ? ? ui jt_sj 3.2 sinusoidal jitter (cpll) (3) 3.2 gb/s (4) 0.45 ? ? ui jt_sj 3.2l sinusoidal jitter (cpll) (3) 3.2 gb/s (5) 0.45 ? ? ui jt_sj 2.5 sinusoidal jitter (cpll) (3) 2.5 gb/s (6) 0.5 ? ? ui jt_sj 1.25 sinusoidal jitter (cpll) (3) 1.25 gb/s (7) 0.5 ? ? ui jt_sj 500 sinusoidal jitter (cpll) (3) 500 mb/s 0.4 ? ? ui sj jitter tolerance with stressed eye (2) jt_tjse 3.2 total jitter with stressed eye (8) 3.2 gb/s 0.70 ? ? ui 6.6 gb/s 0.70 ? ? ui jt_sjse 3.2 sinusoidal jitter with stressed eye (8) 3.2 gb/s 0.1 ? ? ui 6.6 gb/s 0.1 ? ? ui notes: 1. using rxout_div = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 1e ?12 . 3. the frequency of the injected sinusoidal jitter is 10 mhz. 4. cpll frequency at 3.2 ghz and rxout_div = 2. 5. cpll frequency at 1.6 ghz and rxout_div = 1. 6. cpll frequency at 2.5 ghz and rxout_div = 2. 7. cpll frequency at 2.5 ghz and rxout_div = 4. 8. composite jitter with rx and lpm or dfe mode. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 78 gtx transceiver protocol jitter characteristics for ta b l e 9 9 through table 104 , the 7 series fpgas gtx/gth transceivers user guide ( ug476 ) contains recommended settings for optimal usage of prot ocol specific characteristics. ta bl e 9 9 : gigabit ethernet protocol characteristics description line rate (mb/s) min max units gigabit ethernet transmitter jitter generation total transmitter jitter (t_tj) 1250 ? 0.24 ui gigabit ethernet receiver high frequency jitter tolerance total receiver jitter tolerance 1250 0.749 ? ui table 100: xaui protocol characteristics description line rate (mb/s) min max units xaui transmitter jitter generation total transmitter jitter (t_tj) 3125 ? 0.35 ui xaui receiver high frequency jitter tolerance total receiver jitter tolerance 3125 0.65 ? ui table 101: pci express protocol characteristics (1) standard description line rate (mb/s) min max units pci express transmitter jitter generation pci express gen 1 total transmitter jitter 2500 ? 0.25 ui pci express gen 2 total transmitter jitter 5000 ? 0.25 ui pci express gen 3 total transmitter jitter uncorrelated 8000 ? 31.25 ps deterministic transmitter jitter uncorrelated ? 12 ps pci express receiver high frequency jitter tolerance pci express gen 1 total receiver jitter tolerance 2500 0.65 ? ui pci express gen 2 (2) receiver inherent timing error 5000 0.40 ? ui receiver inherent determin istic timing error 0.30 ? ui pci express gen 3 receiver sinusoidal jitter tolerance 0.03 mhz?1.0 mhz 8000 1.00 ? ui 1.0 mhz?10 mhz note 3 ?ui 10 mhz?100 mhz 0.10 ? ui notes: 1. tested per card electromechanical (cem) methodology. 2. using common refclk. 3. between 1 mhz and 10 mhz the minimum sinusoidal jitter roll-off with a slope of 20 db/decade. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 79 table 102: cei-6g and cei-11g protocol characteristics description line rate (m b/s) interface min max units cei-6g transmitter jitter generation total transmitter jitter (1) 4976?6375 cei-6g-sr ? 0.3 ui cei-6g-lr ? 0.3 ui cei-6g receiver high frequency jitter tolerance total receiver jitter tolerance (1) 4976?6375 cei-6g-sr 0.6 ? ui cei-6g-lr 0.95 ? ui cei-11g transmitter jitter generation total transmitter jitter (2) 9950?11100 cei-11g-sr ? 0.3 ui cei-11g-lr/mr ? 0.3 ui cei-11g receiver high frequency jitter tolerance total receiver jitter tolerance (2) 9950?11100 cei-11g-sr 0.65 ? ui cei-11g-mr 0.65 ? ui cei-11g-lr 0.825 ? ui notes: 1. tested at most commonly used line rate of 6250 mb/s using 390.625 mhz reference clock. 2. tested at line rate of 9950 mb/s using 155.46875 mhz reference clock and 11100 mb/s using 173.4375 mhz reference clock. table 103: sfp+ protocol characteristics description line rate (mb/s) min max units sfp+ transmitter jitter generation total transmitter jitter 9830.40 (1) ?0.28ui 9953.00 10312.50 10518.75 11100.00 sfp+ receiver frequency jitter tolerance total receiver jitter tolerance 9830.40 (1) 0.7 ? ui 9953.00 10312.50 10518.75 11100.00 notes: 1. line rated used for cpri over sfp+ applications. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 80 integrated interface block for pci ex press designs switching characteristics more information and documentation on soluti ons for pci express designs can be found at: http://www.xilinx.com /technology/protoco ls/pciexpress.htm table 104: cpri protocol characteristics description line rate (mb/s) min max units cpri transmitter jitter generation total transmitter jitter 614.4 ? 0.35 ui 1228.8 ? 0.35 ui 2457.6 ? 0.35 ui 3072.0 ? 0.35 ui 4915.2 ? 0.3 ui 6144.0 ? 0.3 ui 9830.4 ? note 1 ui cpri receiver frequency jitter tolerance total receiver jitter tolerance 614.4 0.65 ? ui 1228.8 0.65 ? ui 2457.6 0.65 ? ui 3072.0 0.65 ? ui 4915.2 0.95 ? ui 6144.0 0.95 ? ui 9830.4 note 1 ?ui notes: 1. tested per sfp+ specification, see ta b l e 1 0 3 . table 105: maximum performance for pci express designs symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq f pipeclk pipe clock maximum frequency 250 250 250 250 mhz f userclk user clock maximum frequency 500 500 250 250 mhz f userclk2 user clock 2 maximum frequency 250 250 250 250 mhz f drpclk drp clock maximum frequency 250 250 250 250 mhz notes: 1. pci express x8 gen 2 operation is only supported in -2 and -3 speed grades. refer to 7 series fpgas integrated block for pci express product guide ( pg054 ) for specific supported core configurations. s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 81 xadc specifications table 106: xadc specifications parameter symbol comments/conditions min typ max units v ccadc = 1.8v 5%, v refp =1.25v, v refn = 0v, adcclk = 26 mhz, ?55c t j 125c, typical values at t j =+40c adc accuracy (1) resolution 12 ? ? bits integral nonlinearity (2) inl ?40c t j 100c ? ? 2 lsbs ?55c t j < ?40c; 100c < t j 125c ? ? 3 lsbs differential nonlinearity dnl no missing codes, guaranteed monotonic ? ? 1 lsbs offset error unipolar ?40c t j 100c ? ? 8 lsbs ?55c t j < ?40c; 100c < t j 125c ? ? 12 lsbs bipolar ?55c t j 125c ? ? 4 lsbs gain error ??0.5% offset matching ? ? 4 lsbs gain matching ??0.3 % sample rate ?? 1ms/s signal to noise ratio (2) snr f sample = 500ks/s, f in = 20khz 60 ? ? db rms code noise external 1.25v reference ? ? 2 lsbs on-chip reference ? 3 ? lsbs total harmonic distortion (2) thd f sample = 500ks/s, f in = 20khz 70 ? ? db analog inputs (3) adc input ranges unipolar operation 0 ? 1 v bipolar operation ?0.5 ? +0.5 v unipolar common mode range (fs input) 0 ? +0.5 v bipolar common mode range (fs input) +0.5 ? +0.6 v maximum external channel input ranges adjacent analog channels set within these ranges should not corrupt measurements on adjacent channels ?0.1 ? v ccadc v auxiliary channel full resolution bandwidth frbw 250 ? ? khz on-chip sensors temperature sensor error ?40c t j 100c ? ? 4 c ?55c t j < ?40c; 100c < t j 125c ? ? 6 c supply sensor error ?40c t j 100c ? ? 1 % ?55c t j < ?40c; 100c < t j 125c ? ? 2 % conversion rate (4) conversion time - continuous t conv number of adcclk cycles 26 ? 32 cycles conversion time - event t conv number of clk cycles ? ? 21 cycles drp clock frequency dclk drp clock frequency 8 ? 250 mhz adc clock frequency adcclk derived from dclk 1 ? 26 mhz dclk duty cycle 40 ? 60 % s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 82 configuration switching characteristics xadc reference (5) external reference v refp externally supplied reference voltage 1.20 1.25 1.30 v on-chip reference ground v refp pin to agnd, ?40c t j 100c 1.2375 1.25 1.2625 v ground v refp pin to agnd, ?55c t j < ?40c; 100c < t j 125c 1.225 1.25 1.275 v notes: 1. offset and gain errors are removed by enabling the xadc automatic gain calibration feature. the values are specified for when this feature is enabled. 2. only specified for bitstream option xadcenhancedlinearity = on. 3. see the adc chapter in the 7 series fpgas and zynq-7000 all programmable soc xadc dual 12-bit 1 msps analog-to-digital converter user guide ( ug480 ) for a detailed description. 4. see the timing chapter in the 7 series fpgas and zynq-7000 all programmable so c xadc dual 12-bit 1 msps analog-to-digital converter user guide ( ug480 ) for a detailed description. 5. any variation in the reference voltage from the nominal v refp = 1.25v and v refn = 0v will result in a deviation from the ideal transfer function. this also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). however, for external ratiometric type applications allowing reference to vary by 4% is permitted. table 107: configuration switching characteristics symbol description speed grade units -3e -2e/-2i/-2li -1c/-1i -1q/-1lq power-up timing characteristics t pl (1) program latency 5.00 5.00 5.00 5.00 ms, max t por power-on reset (50 ms ramp rate time) 10/50 10/50 10/50 10/50 ms, min/max power-on reset (1 ms ramp rate time) with the power-on reset override function disabled; ( devcfg.ctrl.pcfg_por_cnt_4k = 0 ). (2) 10/35 10/35 10/35 10/35 ms, min/max power-on reset (1 ms ramp rate time) with the power-on reset override function enabled; ( devcfg.ctrl.pcfg_por_cnt_4k = 1 ). (2) 2/8 2/8 2/8 2/8 ms, min/max t program program pulse width 250.00 250.00 250.00 250.00 ns, min boundary-scan port timing specifications t taptck /t tcktap tms and tdi setup/hold 3.00/2.00 3.00 /2.00 3.00/2.00 3.00/2.00 ns, min t tcktdo tck falling edge to tdo output 7.00 7.00 7.00 7.00 ns, max f tck tck frequency 66.00 66.00 66.00 66.00 mhz, max internal configuration access port f icapck internal configuration access port (i cape2) 100.00 100.00 100 .00 100.00 mhz, max device dna access port f dnack dna access port (dna_port) 100.00 100.00 100.00 100.00 mhz, max notes: 1. to support longer delays in configuration, use the design solutions described in the 7 series fpga configuration user guide ( ug470 ). 2. for non-secure boot only. measurement is made when the ps is already powered and stable, before power cycling the pl. table 106: xadc specifications (cont?d) parameter symbol comments/conditions min typ max units s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 83 efuse programming conditions table 108 lists the programming conditio ns specifically for efuse. fo r more information, see the 7series fpga configuration user guide ( ug470 ). revision history the following table shows the revision history for this document: table 108: efuse programming conditions (1) symbol description min typ max units i plfs pl v ccaux supply current ? ? 115 ma i psfs ps v ccpaux supply current ? ? 115 ma t j temperature range 15 ? 125 c notes: 1. the zynq-7000 devices must not be configured during efuse programming. date version description 08/23/2012 1.0 initial xilinx release. 08/31/2012 1.1 updated t j and added note 3 to ta b l e 2 . updated r in_term in ta b l e 3 . updated standards in ta bl e 9 . revised ps performance characteristics section introduction. updated values in ta bl e 1 9 . added note 4 to ta b l e 3 6 . added notes to ta bl e 3 8 . revised f mspiclk in ta b l e 4 3 . 03/14/2013 1.2 updated the ac switching characteristics based upon ise tools 14.5 and vivado tools 2013.1, both at v1.06 for the -3, -2, and -1 speed specif ications throughout the document. updated ta bl e 1 7 and ta b l e 1 8 for production release of the xc7z045 in the -2 and -1 speed designations. added the xc7z100 device throughout document. updated description in introduction . added note 2 to ta bl e 2 . updated v pin in ta b l e 1 and ta bl e 2 . clarified ps specifications for c pin (2) and removed note 3 on i rpd in ta b l e 3 . updated ta b l e 6 . updated ta b l e 9 , including removal of lvttl, notes 2 and 3, and adding sstl135. added ta bl e 1 0 . many enhancements and additions to the figures and tables in the ps switching characteristics section including adding notes with test conditions where applicable. replaced or updated ta b l e 1 9 through ta b l e 2 1 . removed axi interconnects section. updated note 1 in ta bl e 7 3 . updated note 1 and note 2 in ta b l e 8 8 . in ta bl e 9 1 , increased -1 speed grade (ff package) f gtxmax value from 6.6 gb/s to 8.0 gb/s. updated the rows on offset error and gain error and matching in table 106 . added internal configuration access port section to ta bl e 1 0 7 . 03/27/2013 1.3 in ta b l e 7 , changed i ccintmin value for the xc7z030. updated ta b l e 1 7 and ta b l e 1 8 for production release of the xc7z030 in the -2 and -1 speed designations. in ta bl e 5 3 , updated the table title, lpddr2 values, and removed note 3. in ta b l e 5 4 , updated the table title and removed note 4. 04/24/2013 1.4 updated ta b l e 1 7 and ta b l e 1 8 for production release of the xc7z030 and xc7z045 in the -3 speed designations. removed the ps power-on reset section. updated the ps?pl power sequencing section. clarified the load conditions in ta b l e 3 6 by adding new data. in ta bl e 1 , revised v in (i/o input voltage) to match values in ta bl e 4 and ta b l e 5 , and combined note 4 with old note 5 and then added new note 6 . revised v in description and added note 10 , and updated note 3 in ta bl e 2 . updated first 3 rows in ta b l e 4 and ta bl e 5 . revised pci33_3 voltage minimum in ta b l e 1 1 to match values in ta b l e 1 , ta b l e 4 , and ta b l e 5 . added note 1 to ta bl e 1 4 and ta bl e 1 5 . added note 2 to ta b l e 2 0 . throughout the data sheet ( ta bl e 6 7 , ta b l e 6 8 , and ta b l e 8 3 ) removed the obvious note ?a zero ?0? hold time listing indicate s no hold time or a negative hold time.? updated and clarified usrclk data in ta b l e 9 6 . s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 84 06/26/2013 1.5 updated the ac switching characteristics based upon ise tools 14.6 and vivado tools 2013.2, both at v1.07 for the -3, -2, and -1 speed specif ications throughout the document. updated ta bl e 1 7 and ta b l e 1 8 for production release of the xc7z100 in the -1 and -2 speed designations. in ta bl e 1 , updated i dcin section for cases when floating, at v mgtavtt , or gnd and i dcout for cases when floating and at v mgtavtt . added note 6 to ta bl e 2 . added xc7z100 values to ta b l e 6 and ta b l e 7 . increased the frequency of -2 speed grade for cpu clock performance (6:2:1) in ta b l e 1 9 . updated the f ddr3l_max value in ta b l e 2 0 . moved ta bl e 2 1 and added f axi_max . removed note 1 from ta bl e 2 2 . updated the minimum t dqvalid values in ta bl e 2 7 and ta bl e 2 8 . added ta bl e 2 9 . in ta b l e 4 0 , corrected the f sdsclk maximum value and f sdidclk units typographical errors. updated the description of f gtxrx in ta b l e 9 8 . 09/12/2013 1.6 added the sbg485 package to ta b l e 8 8 . added usrcclk output section and clarified values for t por in ta b l e 1 0 7 . added i psfs to ta b l e 1 0 8 . updated notice of disclaimer . 11/26/2013 1.7 added specifications for the zynq-7000q devices (xq7z 030 and xq7z045) with the -1q speed specification/temperature range. removed note 1 and note 2 from ta bl e 7 . added ta b l e 1 6 . in ta b l e 3 6 , updated t qspicko1 . added ta b l e 9 2 . updated ta bl e 1 0 6 specifications. in table 107 , removed the usrcclk output section, added t pl , t program , note 1 , and the device dna access port section, and updated the t por description. 03/03/2014 1.8 added note 4 to v ccaux_io in ta b l e 1 . updated note 8 in ta bl e 2 and added note 9 . added note 2 to ta b l e 4 . added note 2 and note 3 to ta bl e 5 . clarified description in ta bl e 1 4 and ta b l e 1 5 . updated ta b l e 1 6 . moved the xq7z030 (all speed specifications/temperature range s) to production release in ta b l e 1 7 and ta bl e 1 8 . added hsul_12_f, diff_hsul_12_f, mobile_ddr_s, mobile_ddr_f, diff_mobile_ddr_s, and di ff_mobile_ddr_f standards to and updated values in ta b l e 5 5 . added hsul_12_f, diff_hsul_12_f, diff_hsul_12_dci_s, and diff_hsul_12_dci_f standards to and updated values in ta b l e 5 6 . added data for the rf900 and the sbg485 packages in ta b l e 8 8 . added note 1 to table 105 . 04/02/2014 1.9 updated ta b l e 1 7 and ta b l e 1 8 for production release of the xq7z045 in all speed designations. updated the speed specifications for t iotp and removed notes from ta bl e 5 5 and ta bl e 5 6 . 06/04/2014 1.10 added the xa7z030 devices (-1i and -1 q) in the fbg484 package throughout the document. in ta b l e 4 and ta bl e 5 , updated note 2 per the customer notice xcn14014 : 7 series fpga and zynq-7000 ap soc i/o undershoot voltage data sheet update . updated note 3 in ta b l e 6 . updated for clarification the ddr timing diagrams in figure 2 and figure 3 . removed note 1 from ta b l e 1 0 5 . 09/23/2014 1.11 removed 1.8v as descriptor of hp i/o b anks and 3.3v as descriptor of hr i/o banks throughout. updated note 3 in ta b l e 6 . in pl power-on/off power supply sequencing , added sentence about there being no recommended sequence for supplies not shown. in ps?pl power sequencing , removed list of pl power supplies. in ta bl e 1 7 , moved -1i and -1q xa7z030 speed grades from preliminary to production. in ta b l e 1 8 , added production software for xa7z030 -1i and -1q speed grades. updated f cpu_3x2x_621_max , f cpu_2x_621_max , f cpu_6x4x_421_max , and f cpu_1x_421_max values in ta bl e 1 9 . in ta bl e 2 2 , removed typical value and added maximum value for t rfpsclk . added note about measurement being taken from v ref to v ref in ta b l e 2 7 to ta bl e 3 4 . added note 3 to ta b l e 5 3 . added i/o standard adjustment measurement methodology . in ta b l e 6 4 , added attribute refclk frequency of 400 mhz to f idelayctrl_ref and average tap delay at 400 mhz to note 1 . updated description of t ickof in ta bl e 7 8 and added note 2 . updated description of t ickoffar in ta b l e 7 9 and added note 2 . in ta b l e 8 9 , moved dv ppout value of 1000 mv from max to min column, updated v in dc parameter description, and added note 2 . added peak-to-peak to labels in figure 20 and figure 21 . added note after figure 21 . added note 1 to ta bl e 1 0 5 . 10/09/2014 1.12 added xc7z035 device. added -2li speed grade throughout. updated introduction . added -2li (0.95v) to description of v ccint and v ccbram , and added pl to description of v ccint , v ccbram , v ccaux , v cco and v ccaux_io in ta b l e 2 . added note 1 to ta b l e 1 8 . 11/19/2014 1.13 added v ccbram and xa zynq-7000 all programmable soc overview to introduction . updated the ac switching characteristics based upon vivado 2014.4. updated vivado software version in ta b l e 1 6 . in ta b l e 1 7 , moved all speed grades from advance to production. in ta b l e 1 8 , added vivado 2014.4 software version for -2li speed grade in xc7z030 and xc7z045 devices and -3e, -2e, -2i, -2li, -1c, and -1i speed grades in xc7z035 device, and removed table note. added selecting the correct speed grade and voltage in the vivado tools . added note 1 to ta bl e 5 1 . date version description s e n d f e e d b a c k
zynq-7000 ap soc (z-7030, z-7035, z-7045, and z-7100): dc and ac switching characteristics ds191 (v1.17) november 24, 2015 www.xilinx.com product specification 85 notice of disclaimer the information disclosed to you hereunder (the ?materials?) is pr ovided solely for the selection and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are m ade available "as is" and with all faults, xilinx hereby disclai ms all warranties and conditions, express, implied, or stat utory, including but not limited to warranties of merchantability, non-infringement, or fitness for any pa rticular purpose; and (2) xilinx shall not be liable (whether in contract or tort, including negligence, or under an y other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the materials (includi ng your use of the materials), including for any direct, indire ct, special, incidental, or consequential loss or damage (including loss of da ta, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or xilinx had been advised of the p ossibility of the same. xilinx assumes no obligation to correct any errors c ontained in the materials or to notify you of updates to the m aterials or to product specifications. you may not reproduc e, modify, distribute, or publicly display the materials without prior written cons ent. certain products are subject to the terms and conditions of xilinx?s limi ted warranty, please refer to xilinx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos ; ip cores may be subject to warranty and support terms contained in a license issued to you by xilinx. xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of xilinx products in such critical applications, please refer to xilinx?s terms of sale which can be viewed at www.xilinx.com/legal.htm#tos . automotive applications disclaimer xilinx products are not designed or intended to be fail -safe, or for use in any application requiring fail- safe performance, such as applications related to: (i) the deployment of airbags, (ii) control of a vehicle, unless there is a fail-safe or redundancy fe ature (which does not incl ude use of software in the xilinx device to implement the redundancy) and a wa rning signal upon failure to the operator, or (iii) uses that could lead to death or personal injury. cu stomer assumes the sole risk and liability of any use of xilinx products in such applications. 02/23/2015 1.14 updated descriptions of v ccpint in ta b l e 1 and ta b l e 2 . in ta b l e 1 4 , changed maximum v icm value from 1.425v to 1.500v. updated ta bl e 2 4 title. added figure 1 and ta bl e 2 5 . updated first sentence in pl power-on/off power supply sequencing . in ta bl e 3 6 , updated minimum t qspidck2 and t qspickd2 to 6 ns and 12.5 ns, respectively, and removed note 5. in ta b l e 7 0 , updated symbols for t dspdck_ { a, b} _mreg_mult /t dspckd_ { a, b}_mreg_mult , t dspdck_ { a, d}_adreg / t dspckd_ { a, d}_adreg , t dspdck_ { a, b}_preg_mult /t dspckd_ { a, b}_preg_mult , t dspdck_ { a, b}_preg /t dspckd_ { a, b}_preg , t dspdck_ { cea, ceb}_ { areg, breg} / t dspckd_ { cea, ceb}_ { areg, breg} , and t dspdck_ { rsta, rstb}_ { areg, breg} / t dspckd_ { rsta, rstb}_ { areg, breg} . in ta b l e 7 6 , updated descriptions of t mmcmdck_daddr /t mmcmckd_daddr , t mmcmdck_di /t mmcmckd_di , t mmcmdck_den / t mmcmckd_den , and t mmcmdck_dwe /t mmcmckd_dwe . added descriptive row to ta b l e 8 6 . removed minimum sample rate specification from table 106 . 06/23/2015 1.15 added XQ7Z100 device throughout. added -1lq speed grade to xq7z045 device. updated the ac switching characteristics based upon ise tools 14.7 and vi vado tools 2015.2. updated ta bl e 5 3 title to refer to ff packages. updated ta bl e 5 4 title and note 3 to refer to fb, rb, and sb packages. removed ?fpga? from labels in figure 18 and figure 19 . added sbv485, fbv484, fbv676, ffv676, ffv900, ffv1156, rfg676, and rf1156 packages to ta bl e 8 8 . removed note about pci-sig 3.0 from ta bl e 1 0 1 . 09/28/2015 1.16 updated data s heet per the customer notice xcn15034 : zynq-7000 ap soc requirement for the ps power-off sequence . updated ps power-on/off power supply sequencing . added f smc_ref_clk to ta b l e 3 5 . changed -2e and -1c speed grade xc7z100 devices to n/a in ta b l e 6 , ta bl e 1 8 , ta bl e 7 5 , ta b l e 7 8 to ta bl e 8 1 , and ta b l e 8 3 to ta b l e 8 5 . added introductory paragraph before ta bl e 5 3 and updated note 3 . 11/24/2015 1.17 updated quiescent supply currents for xq7z 030, xq7z045, and XQ7Z100 in ta b l e 6 . updated the ac switching characteristics based upon vivado 2015.4. in ta b l e 1 7 , added -2li speed grade to production column for xq7z030 and xq7z045, and added -2i and -2li speed grades to production column for XQ7Z100. in ta b l e 1 8 , added vivado 2015.4 software version to -2li speed grade column for xq7z030, xq7z045, and XQ7Z100, and -2i speed gra de column for XQ7Z100. in figure 4 and figure 5 , added extra clock pulse on qspi_sclk_out. in ta bl e 7 5 , added t ckskew for xq7z030, xq7z045, and XQ7Z100 at -2li speed grade, and XQ7Z100 at -2i speed grade. updated device pin-to-pin output parameter tables ( ta bl e 7 8 to ta bl e 8 1 ) and input parameter tables ( ta bl e 8 3 to ta b l e 8 5 ) for xq7z030, xq7z045, and XQ7Z100 at -2li and -2i speed grades. date version description s e n d f e e d b a c k

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