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september 2013 doc id 14173 rev 9 1/36 1 l9951 l9951xp rear door actuator driver features one half bridge for 7.4 a load (r on = 150 m ) two half bridges for 5 a load (r on = 200 m ) two highside drivers for 1.25 a load (r on = 800 m ) programmable softstart function to drive loads with higher inrush currents (i.e.current > 7.4a, >5a, >1.25a) very low current consumption in standby mode (i s < 3a, typ. t j 85c) all outputs short circuit protected current monitor output for all highside drivers all outputs over temperature protected open-load diagnostic for all outputs overload diagnostic for all outputs programmable pwm control of all outputs charge pump output for reverse polarity protection applications rear door actuator driver with bridges for door lock and safe lock and two 5w or 10w - light bulbs. description the l9951 and l9951xp are microcontroller driven, multifunctional rear door actuator drivers for automotive applications. up to two dc motors and two grounded resistive loads can be driven with three half bridges and two hide side drivers. the integrated standard serial peripheral interface (spi) controls all operation modes (forward, reverse, brake and high impedance). all diagnostic information is available via the spi. type outputs (1) 1. see block diagram. r on (2) 2. typical values. i out v s l9951 l9951xp out1 out2 out3 out4 out5 150 m 200 m 200 m 800 m 800 m 7.4 a 5a 5a 1.25 a 1.25 a 28 v powerso-36 powersso-36 table 1. device summary package order codes tube tape and reel powerso-36 l9951 l9951tr powersso-36 l9951xp L9951XPTR www.st.com
contents l9951 / l9951xp 2/36 doc id 14173 rev 9 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 10 2.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 spi - electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1 dual power supply: vs and vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 standby - mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 inductive loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 over-voltage and under-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . 20 3.6 temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . 20 3.7 open-load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 over load detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 pwm input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11 cross-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12 programmable softstart function to drive loads with higher inrush current 21 4 functional description of the spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.1 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 chip select not (csn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.3 serial data in (di) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.4 serial data out (do) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.5 serial clock (clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.6 input data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
l9951 / l9951xp contents doc id 14173 rev 9 3/36 4.8 test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2 powerso-36? package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 powersso-36? package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4 powerso-36? packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.5 powersso-36? packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
list of tables l9951 / l9951xp 4/36 doc id 14173 rev 9 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 8. overvoltage and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 9. current monitor output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 10. charge pump output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 11. out 1 - out 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 12. delay time from standby to active mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 13. inputs: csn, clk, pwm1/2 and di . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 14. di timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 15. do . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 16. do timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 17. en, csn timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 18. test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 19. spi - input data and status register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 20. spi - input data and status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 21. powerso-36? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 22. powersso-36? mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 23. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
l9951 / l9951xp list of figures doc id 14173 rev 9 5/36 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. spi - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 4. spi - input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. spi - do valid data delay time and valid time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. spi - do enable and disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. spi - driver turn-on/off timing, minimum csn hi time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. spi - timing of status bit 0 (fault condition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. example of programmable softstart function for inductive loads . . . . . . . . . . . . . . . . . . . . 21 figure 10. packages thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 11. powerso-36? package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12. powersso-36? package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13. powerso-36 tm tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 14. powerso-36 tm tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 15. powersso-36 tm tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 16. powersso-36 tm tape and reel shipment (suffix ?tr?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
block diagram and pin description l9951 / l9951xp 6/36 doc id 14173 rev 9 1 block diagram and pin description figure 1. block diagram out1 driver interface & diagnostic out2 out3 m spi interface charge pump cm / pwm csn clk do di vs vcc vcc v bat c gnd lock 1k mux 5 en out4 out5 1k 1k 1k 1k 1k 100k 10k * note: value of capacitor has to be choosen carefully to limit the vs voltage below absolute maximum ratings in case of an unexpected freewheeling condition of inductive loads (e.g. tsd, por) * ** note: resistors between c and l9951 are recommended to limit currents for negative voltage transients at vbat (e.g. iso type 1 pulse) + note: using a ferrite instead of 10ohm w ill additionally improve emc behavior reverse polarity protection ** ** ** ** ** ** 100f safe lock m 100nf vreg 100 10 100nf cp emc optimization + exterior light safety light
l9951 / l9951xp block diagram and pin description doc id 14173 rev 9 7/36 table 2. pin definitions and functions pin symbol function 1, 18, 19, 36 gnd ground . reference potential. note: for the capability of driving the full current at the outputs all pins of gnd must be externally connected. 6, 7, 14, 15, 23, 24, 29, 32 vs power supply voltage (external reverse protection required). for emi reason a ceramic capacitor as close as possible to gnd is recommended. note: for the capability of driving the full current at the outputs all pins of vs must be externally connected. 3, 4, 34 out1 half-bridge output 1. the output is built by a high side and a low side switch, which are internally connected. the output stage of both switches is a power dmos transistor. each driver has an internal reverse diode (bulk-drain- diode: high side driver from output to vs, low side driver from gnd to output). this output is over-current and open-load protected. note: for the capability of driving the full current at the outputs all pins of out1 must be externally connected. 8di serial data input. the input requires cmos logic levels and receives serial data from the microcontroller. the data is a 16bit control word and the least significant bit (lsb, bit 0) is transferred first. 9 cm/pwm current monitor output/pwm input. depending on the selected multiplexer bits (bit 9, 10, 11) of input data register this output sources an image of the instant current through the corresponding high side driver with a ratio of 1/10.000. this pin is bidirectional. the microcontroller can overwrite the current monitor signal to provide a pwm input for all outputs. tes t mo de : if csn is raised above 7.5v the device will enter the test mode. in test mode this output can be used to measure some internal signals (see table 18 ). 10 csn chip select not input / testmode . this input is low active and requires cmos logic levels. the serial data transfer between l9951 and micro controller is enabled by pulling the input csn to low level. if an input voltage of more than 7.5v is applied to csn pin the l9951 will be switched into a test mode. 11 do serial data output . the diagnosis data is available via the spi and this tristate-output. the output will remain in tristate, if the chip is not selected by the input csn (csn = high). 12 vcc logic supply voltage . for this input a ceramic capacitor as close as possible to gnd is recommended. 13 clk serial clock input . this input controls the internal shift register of the spi and requires cmos logic levels.
block diagram and pin description l9951 / l9951xp 8/36 doc id 14173 rev 9 figure 2. configuration diagram (top view) 16, 17 out2 half-bridge output 2 (see out1 - pin 3, 4). note : for the capability of driving the full current at the outputs all pins of out2 must be externally connected. 20, 21 out3 half-bridge output 3 (see out1 - pin 3, 4). note: for the capability of driving the full current at the outputs all pins of out3 must be externally connected. 26 cp charge pump output . this output is provided to drive the gate of an external n-channel power mos used for reverse polarity protection (see figure 1 ). 27 en enable input. if enable input is forced to gnd the device will enter standby-mode. the outputs will be switched off and all registers will be cleared 33, 35 out4, out5 high side driver output 4, 5 . the output is built by a high side switch and is intended for resistive loads, hence the internal reverse diode from gnd to the output is missing. for esd reason a diode to gnd is present but the energy which can be dissipated is limited. the high side driver is a power dmos transistor with an internal reverse diode from the output to vs (bulk- drain-diode). the output is over-current and open-load protected. table 2. pin definitions and functions (continued) pin symbol function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 chip leadframe gnd n.c. out1 out1 n.c. vs vs csn do vcc clk vs vs out2 out2 gnd di gnd out5 out1 out4 vs n.c. n.c. n.c. en cp n.c. vs vs n.c. out3 out3 gnd vs . cm/pwm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 chip leadframe gnd n.c. out1 out1 n.c. vs vs csn do vcc clk vs vs out2 out2 gnd di gnd out5 out1 out4 vs n.c. n.c. n.c. en cp n.c. vs vs n.c. out3 out3 gnd vs . cm/pwm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 chip leadframe gnd n.c. out1 out1 n.c. vs vs csn do vcc clk vs vs out2 out2 gnd di gnd out5 out1 out4 vs n.c. n.c. n.c. en cp n.c. vs vs n.c. out3 out3 gnd vs . cm/pwm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 chip leadframe gnd n.c. out1 out1 n.c. vs vs csn do vcc clk vs vs out2 out2 gnd di gnd out5 out1 out4 vs n.c. n.c. n.c. en cp n.c. vs vs n.c. out3 out3 gnd vs . cm/pwm
l9951 / l9951xp electrical specifications doc id 14173 rev 9 9/36 2 electrical specifications 2.1 absolute maximum ratings stressing the device above the rating listed in the ?absolute maximum ratings? table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality document 2.2 esd protection 2.3 thermal data table 3. absolute maximum ratings symbol parameter value unit v s dc supply voltage -0.3 to 28 v single pulse t max < 400ms 40 v v cc stabilized supply voltage, logic supply -0.3 to 5.5 v v di, v do ,v clk ,v csn, v en digital input / output voltage -0.3 to v cc + 0.3 v v cm current monitor output -0.3 to v cc + 0.3 v v cp charge pump output -25 to v s + 11 v i out1,2,3 output current 10 a i out4,5 output current 5 a table 4. esd protection parameter value unit all pins 4 (1) 1. hbm according to cdf-aec-q100-002. kv output pins: out1 - out5 8 (2) 2. hbm with all unzapped pins grounded. kv table 5. thermal data symbol parameter value unit t j operating junction temperature -40 to 150 c
electrical specifications l9951 / l9951xp 10/36 doc id 14173 rev 9 2.4 temperature warning and thermal shutdown 2.5 electrical characteristics v s = 8 to 16 v, v cc = 4.5 to 5.3 v, t j = - 40 to 150 c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. table 6. temperature warning and thermal shutdown symbol parameter min. typ. max. unit t jtw on temperature warning threshold junction temperature t j increasing 150 c t jtw off temperature warning threshold junction temperature t j decreasing 130 c t jtw hys temperature warning hysteresis 5 k t jsd on thermal shutdown threshold junction temperature t j increasing 170 c t jsd off thermal shutdown threshold junction temperature t j decreasing 150 c t jsd hys thermal shutdown hysteresis 5 k table 7. supply symbol parameter test condition min. typ. max. unit v s operating supply voltage range 728v i s v s dc supply current v s = 13v, v cc = 5.0v active mode out1 - out5 floating 720ma v s quiescent supply current v s = 13v, v cc = 0v standby mode out1 - out5 floating t test =-40c, 25c 310a t test = 130c 6 20 a
l9951 / l9951xp electrical specifications doc id 14173 rev 9 11/36 i cc v cc dc supply current v s = 13v, v cc = 5.0v csn = v cc active mode 13ma v cc quiescent supply current v s = 13v, v cc = 5.0v csn = v cc standby mode out1 - out5 floating 13a i s + i cc sum quiescent supply current v s = 13v, v cc = 5.0v csn = v cc standby mode out1 - out5 floating 723a table 8. overvoltage and undervoltage detection symbol parameter test condition min. typ. max. unit v suv on vs uv-threshold voltage v s increasing 6.0 7.2 v v suv off vs uv-threshold voltage v s decreasing 5.4 6.5 v v suv hyst vs uv-hysteresis v suv on - v suv off 0.55 v v sov off vs ov-threshold voltage v s increasing 18 24.5 v v sov on vs ov-threshold voltage v s decreasing 17.5 v v sov hyst vs ov-hysteresis v sov off - v sov on 0.5 v v por off power-on-reset threshold v cc increasing 4.4 v v por on power-on-reset threshold v cc decreasing 3.1 v v por hyst power-on-reset hysteresis v por off - v por on 0.3 v table 9. current monitor output symbol parameter test condition min. typ. max. unit v cm functional voltage range v cc = 5v 0 4 v i cm,r current monitor output ratio: i cm /i out1,2,3,4,5 0v v cm 4v, vcc=5v 1:10000 - i cm acc current monitor accuracy 0v vcm 4v, v cc =5v, i out1-5,low =500ma i out1,high =6a i out2,3,high =4.9a i out4,5,high =1.2a (fs=full scale=600 a) 4% + 1%fs 8% + 2%fs - table 7. supply (continued) symbol parameter test condition min. typ. max. unit
electrical specifications l9951 / l9951xp 12/36 doc id 14173 rev 9 table 10. charge pump output symbol parameter test condition min. typ. max. unit v cp charge pump output voltage v s =8v, i cp = -60a 6 13 v v s =10v, i cp = -80a 8 13 v v s 12v, i cp = -100a 10 13 v i cp charge pump output current v cp = v s +10v v s =13.5v 100 150 300 a table 11. out 1 - out 5 symbol parameter test condition min. typ. max. unit r on out1 on-resistance to supply or gnd v s = 13.5 v, t j = 25 c, i out1 = 3 a 150 200 m v s = 13.5 v, t j = 125 c, i out1 = 3 a 225 300 m v s = 8.0 v, t j = 25 c, i out1 = 3 a 150 200 m r on out2 r on out3 on-resistance to supply or gnd v s = 13.5 v, t j = 25 c, i out2,3 = 3 a 200 270 m v s = 13.5 v, t j = 125 c, i out2,3 = 3 a 300 400 m v s = 8.0 v, t j = 25 c, i out2,3 = 3 a 200 270 m r on out4, r on out5 on-resistance to supply or gnd vs = 13.5 v, t j = 25 c, i out4,5 = 0.8 a 800 1100 m v s = 13.5 v, t j = 125 c, i out4,5 = 0.8 a 1250 1700 m v s = 8.0 v, t j = 25 c, i out4,5 = 0.8 a 800 1100 m |i out1 | output current limitation to supply or gnd sink and source 7.4 15.5 a |i out2 |, |i out3 | output current limitation to supply or gnd sink and source 5.0 10.5 a |i out4 |, |i out5 | output current limitation to gnd source 1.25 2.6 a t d on h output delay time, highside driver on v s = 13.5 v, corresponding lowside driver is not active 20 40 90 s t d off h output delay time, highside driver off v s = 13.5 v 80 200 300 s t d on l output delay time, lowside driver on v s = 13.5 v, corresponding highside driver is not active 20 60 80 s
l9951 / l9951xp electrical specifications doc id 14173 rev 9 13/36 t d off l output delay time, lowside driver off v s = 13.5 v 80 150 300 s t d hl cross current protection time, source to sink t d on l - t d off h, 200 400 s t d lh cross current protection time, sink to source t d on h - t d off l 200 400 s i qlh switched-off output current highside drivers of out1-5 v out1-5 = 0v, standby mode 0-2-5a v out1-5 = 0v, active mode -40 -15 0 a i qll switched-off output current lowside drivers of out1-3 v out1-3 = v s , standby mode 050100a v out1-3 = v s , active mode -40 -15 0 a i old1 open-load detection current of out1 70 160 240 ma i old23 open-load detection current of out2, out3 70 160 240 ma i old45 open-load detection current of out4 and out5 51540ma t dol minimum duration of open-load condition to set the status bit 500 3000 s t isc minimum duration of over-current condition to switch off the driver 10 100 s dv out1 /dt slew rate of out1 v s =13.5 v i load = 1.5 a 0.1 0.2 0.4 v/s dv out23 /dt slew rate of out2, out3 v s = 13.5 v i load = 1.5 a 0.1 0.2 0.4 v/s dv out45 /dt slew rate of out4, out5 v s = 13.5 v i load = - 0.8 a 0.1 0.2 0.4 v/s table 11. out 1 - out 5 (continued) symbol parameter test condition min. typ. max. unit
electrical specifications l9951 / l9951xp 14/36 doc id 14173 rev 9 2.6 spi - electrical characteristics (v s = 8 to 16 v, v cc = 4.5 to 5.3 v, t j = - 40 to 150 c, unless otherwise specified. the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin). note: value of input capacity is not measured in production test. parameter guaranteed by design. table 12. delay time from standby to active mode symbol parameter test condition min. typ. max. unit t set internal startup time switching from standby to active mode. time until not ready bit goes low. 80 300 s table 13. inputs: csn, clk, pwm1/2 and di symbol parameter test condition min. typ. max. unit v inl input low level v cc = 5v 1.5 2.0 v v inh input high level v cc = 5v 3.0 3.5 v v inhyst input hysteresis v cc = 5v 0.5 v i csn in pull up current at input csn v csn = 3.5v v cc = 5v -50 -25 -10 a i clk in pull down current at input clk v clk = 1.5v 10 25 50 a i di in pull down current at input di v di = 1.5v 10 25 50 a i en in pull down resistance at input en 100 210 480 k c in input capacitance at input clk, di and pwm v cc = 0 to 5.3v 10 15 pf table 14. di timing (1) symbol parameter test condition min. typ. max. unit t clk clock period v cc = 5v 1000 ns t clkh clock high time v cc = 5v 400 ns t clkl clock low time v cc = 5v 400 ns t set csn csn setup time, csn low before rising edge of clk v cc = 5v 400 ns t set clk clk setup time, clk high before rising edge of csn v cc = 5v 400 ns t set di di setup time v cc = 5v 200 ns t hold time di hold time v cc = 5v 200 ns
l9951 / l9951xp electrical specifications doc id 14173 rev 9 15/36 note: di timing parameters tested in production by a passed/failed test: tj= -40c/+25c: spi communication @2mhz. tj= +125c: spi communication @1.25mhz. t r in rise time of input signal di, clk, csn v cc = 5v 100 ns t f in fall time of input signal di, clk, csn v cc = 5v 100 ns 1. see figure 3 and figure 4 table 14. di timing (1) (continued) symbol parameter test condition min. typ. max. unit table 15. do symbol parameter test condition min. typ. max. unit v dol output low level vcc = 5 v, i d = -4ma 0.2 0.4 v v doh output high level vcc = 5 v, i d = 4 ma v cc -0.4 v cc -0.2 v i dolk tristate leakage current v csn = v cc , 0v < v do < v cc -10 10 a c do (1) 1. value of input capacity is not measured in production test. parameter guaranteed by design. tristate input capacitance v csn = v cc , 0v < v cc < 5.3v 10 15 pf table 16. do timing (1) 1. see figure 5 and figure 6 . symbol parameter test condition min. typ. max. unit t r do do rise time c l = 100 pf, i load = -1ma 80 140 ns t f do do fall time c l = 100 pf, i load = 1ma 50 100 ns t en do tri l do enable time from tristate to low level c l = 100 pf, i load = 1ma pull-up load to v cc 100 250 ns t dis do l tri do disable time from low level to tristate c l = 100 pf, i load = 4 ma pull-up load to v cc 380 450 ns t en do tri h do enable time from tristate to high level c l =100 pf, i load = -1ma pull-down load to gnd 100 250 ns t dis do h tri do disable time from high level to tristate c l = 100 pf, i load = -4ma pull-down load to gnd 380 450 ns t d do do delay time v do < 0.3 v cc , v do > 0.7v cc , c l = 100pf 50 250 ns
electrical specifications l9951 / l9951xp 16/36 doc id 14173 rev 9 figure 3. spi - transfer timing diagram figure 4. spi - input timing table 17. en, csn timing (1) 1. see figure 7 symbol parameter test condition min. typ. max. unit t en_csn_lo minimum en high before sending first spi frame, i.e. csn going low transfer of spi-command to input register 20 50 s t csn_hi,min minimum csn hi time between two spi frames transfer of spi-command to input register 24s 0 1 0 1 time time time time time csn high to low: do enabled actual data di: data will be accepted on the rising edge of clk signal new data csn clk di do e.g.out1 do: data will change on the falling edge of clk signal status information fault bit csn low to high: actual data is transfered to output power switches old data 1 2 3 4 5 6 7 8 9 10 11 0 12 13 14 15 1 0 actual data 1 2 3 4 5 6 7 8 9 10 11 0 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 0 12 13 14 15 0.8 vcc 0.8 vcc 0.8 vcc 0.2 vcc 0.2 vcc 0.2 vcc valid valid csn clk di t set csn t clkh t set clk t clkl t hold di t set di
l9951 / l9951xp electrical specifications doc id 14173 rev 9 17/36 figure 5. spi - do valid data delay time and valid time figure 6. spi - do enable and disable time 0 . 8 vcc 0 . 8 v c c 0 . 8 v c c 0 . 2 v c c 0 . 2 v c c 0 . 2 vcc c l k do ( l o w t o h i g h ) do (high to lo w ) 0 . 5 vcc t r i n t r do t f do t d do t f i n csn t f in r in t do do en do tri l t t dis do l tri 50% 0.8 vcc 0.2 vcc 50% 50% en do tri h t t dis do h tri c = 100 pf l c = 100 pf l pull-up load to vcc pull-down load to gnd
electrical specifications l9951 / l9951xp 18/36 doc id 14173 rev 9 figure 7. spi - driver turn-on/off timing, minimum csn hi time figure 8. spi - timing of st atus bit 0 (fault condition) csn don t 20% 80% t r in f in t off t doff t off state on state off state on state on t output current of a driver 50% 50% 80% 20% 20% 80% 50% output current of a driver csn low to high: data from shift register is transferred to output power switches t csn_hi,min csn clk di do csn high to low and clk stays low: status information of data bit 0 (fault condition) is transfered to do di: data is not accepted do: status information of data bit 0 (fault condition) will stay as long as csn is low time time time time 0 -
l9951 / l9951xp application information doc id 14173 rev 9 19/36 3 application information 3.1 dual power supply: v s and v cc the power supply voltage v s supplies the half bridges and the high side drivers. an internal charge-pump is used to drive the high side switches. the logic supply voltage v cc (stabilized 5v) is used for the logic part and the spi of the device. due to the independent logic supply voltage the control and status information will not be lost, if there are temporary spikes or glitches on the power supply voltage. in case of power-on (v cc increases from under voltage to v por off = 4.0v, typical) the circuit is initialized by an internally generated power-on-reset (por). if the voltage v cc decreases under the minimum threshold (v por on =3.6v, typical), the outputs are switched to tristate (high impedance) and the status registers are cleared. 3.2 standby - mode the standby mode of the l9951 is activated by switching the en input do gnd. all latched data will be cleared and the inputs and outputs are switched to high impedance. in the standby mode the current at v s (v cc ) is less than 3 a (1a) for csn = high (do in tristate). if en is switched to 5v the device will enter the active mode. in the active mode the charge- pump and the supervisor functions are activated. 3.3 inductive loads each half bridge is built by an internally connected high side and a low side power dmos transistor. due to the built-in reverse diodes of the output transistors, inductive loads can be driven at the outputs out1 to out3 without external free-wheeling diodes. the high side drivers out4 to out5 are intended to drive resistive loads. hence only a limited energy (e<0.5mj) can be dissipated by the internal esd-diodes in freewheeling condition. for inductive loads (l > 50h) an external free-wheeling diode connected to gnd and the corresponding output is needed. 3.4 diagnostic functions all diagnostic functions (over/open-load, power supply over-/undervoltage, temperature warning and thermal shutdown) are internally filtered and the condition has to be valid for at least 32s (open-load: 1ms, respectively) before the corresponding status bit in the status registers will be set. the filters are used to improve the noise immunity of the device. open- load and temperature warning function are intended for information purpose and will not change the state of the output drivers. on contrary, the over load and thermal shutdown condition will disable the corresponding driver (over load) or all drivers (thermal shutdown), respectively. without setting the over-current recovery bit in the input data register to logic high, the microcontroller has to clear the over-current status bit to reactivate the corresponding driver. each driver has a corresponding over-current recovery bit. if this bit is set, the device will automatically switch-on the outputs again after a short recovery time. the duty cycle in over-current condition can be programmed by the spi interface (12% or 25%). with this feature the device can drive loads with start-up currents higher than the over- current limits (e.g. inrush current of lamps, cold resistance of motors and heaters).
application information l9951 / l9951xp 20/36 doc id 14173 rev 9 3.5 over-voltage and under-voltage detection if the power supply voltage v s rises above the over-voltage threshold v sov off (typical 21v), the outputs out1 to out5 are switched to high impedance state to protect the load and the internal charge-pump is turned-off. when the voltage v s drops below the undervoltage threshold v suv off (uv-switch-off voltage), the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage (increased power dissipation). if the supply voltage v s recovers to normal operating voltage the output stages return to the programmed state (input register 0: bit 12=0). if the undervoltage / overvoltage recovery disable bit is set, the automatic turn-on of the drivers is deactivated. the microcontroller needs to clear the status bits to reactivate the drivers. 3.6 temperature warning and thermal shutdown if junction temperature rises above t j tw a temperature warning flag is set and is detectable via the spi. if junction temperature increases above the second threshold t j sd , the thermal shutdown bit will be set and power dmos transistors of all output stages are switched off to protect the device. in order to reactivate the output stages the junction temperature must decrease below t jsd - t jsd hys and the thermal shutdown bit has to be cleared by the microcontroller. 3.7 open-load detection the open-load detection monitors the load current in each activated output stage. if the load current is below the open-load detection threshold for at least 1 ms (t dol ) the corresponding open-load bit is set in the status register. due to mechanical/electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads. 3.8 over load detection in case of an over-current condition a flag is set in the status register in the same way as open-load detection. if the over-current signal is valid for at least t isc =32s, the over-current flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit. if the over-current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver. 3.9 current monitor the current monitor output sources a current image at the current monitor output which has a fixed ratio (1/10000) of the instantaneous current of the selected high side driver. the bits 9, 10 and 11 of the input data register 0 control which of the outputs out1 to out5 will be multiplexed to the current monitor output. the current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open- or overload condition. for example this can be used to detect the motor state (starting, free-running, stalled). moreover, it is possible to regulate the power of the defroster more precise by measuring the monitor current.
l9951 / l9951xp application information doc id 14173 rev 9 21/36 3.10 pwm input each driver has a corresponding pwm enable bit which can be programmed by the spi interface. if the pwm enable bit is set, the outputs out1 to out5 are controlled by the logically and-combination of the signal applied to the pwm input and the output control bit in input data register1. 3.11 cross-current protection the three half-brides of the device are cross-current protected by an internal delay time. if one driver (ls or hs) is turned-off the activation of the other driver of the same half bridge will be automatically delayed by the cross-current protection time. after the cross-current protection time is expired the slew-rate limited switch-off phase of the driver will be changed to a fast turn-off phase and the opposite driver is turned-on with slew-rate limitation. due to this behavior it is always guaranteed that the previously activated driver is totally turned-off before the opposite driver will start to conduct. 3.12 programmable softstart function to drive loads with higher inrush current loads with start-up currents higher than the over-current limits (e.g. inrush current of lamps, start current of motors and cold resistance of heaters) can be driven by using the programmable softstart function (i.e. overcurrent recovery mode). each driver has a corresponding over-current recovery bit. if this bit is set, the device will automatically switch- on the outputs again after a programmable recovery time. the duty cycle in over-current condition can be programmed by the spi interface to be about 12% or 25%. the pwm modulated current will provide sufficient average current to power up the load (e.g. heat up the bulb) until the load reaches operating condition. the device itself cannot distinguish between a real overload and a non linear load like a light bulb. a real overload condition can only be qualified by time. as an example the microcontroller can switch on light bulbs by setting the over-current recovery bit for the first 50ms. after clearing the recovery bit the output will be automatically disabled if the overload condition still exits. figure 9. example of programmable soft start function for inductive loads
functional description of the spi l9951 / l9951xp 22/36 doc id 14173 rev 9 4 functional description of the spi 4.1 serial peripheral interface (spi) this device uses a standard spi to communicate with a microcontroller. the spi can be driven by a microcontroller with its spi peripheral running in following mode: cpol = 0 and cpha = 0. for this mode, input data is sampled by the low to high transition of the clock clk, and output data is changed from the high to low transition of clk. this device is not limited to microcontroller with a build-in spi. only three cmos-compatible output pins and one input pin will be needed to communicate with the device. a fault condition can be detected by setting csn to low. if csn = 0, the do-pin will reflect the status bit 0 (fault condition) of the device which is a logical-or of all bits in the status registers 0 and 1. the microcontroller can poll the status of the device without the need of a full spi- communication cycle. note: in contrast to the spi-standard the least significant bit (lsb) will be transferred first (see figure 3 ). 4.2 chip select not (csn) the input pin is used to select the serial interface of this device. when csn is high, the output pin (do) will be in high impedance state. a low signal will activate the output driver and a serial communication can be started. the state when csn is going low until the rising edge of csn will be called a communication frame. if the csn-input pin is driven above 7.5v, the l9951 will go into a test mode. in the test mode the do will go from tristate to active mode. 4.3 serial data in (di) the input pin is used to transfer data serial into the device. the data applied to the di will be sampled at the rising edge of the clk signal and shifted into an internal 16 bit shift register. at the rising edge of the csn signal the contents of the shift register will be transferred to data input register. the writing to the selected data input register is only enabled if exactly 16 bits are transmitted within one communication frame (i.e. csn low). if more or less clock pulses are counted within one frame the complete frame will be ignored. this safety function is implemented to avoid an activation of the output stages by a wrong communication frame. note: due to this safety functionality a daisy chaining of spi is not possible. instead, a parallel operation of the spi bus by controlling the csn signal of the connected ics is recommended.
l9951 / l9951xp functional description of the spi doc id 14173 rev 9 23/36 4.4 serial data out (do) the data output driver is activated by a logical low level at the csn input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). the first rising edge of the clk input after a high to low transition of the csn pin will transfer the content of the selected status register into the data out shift register. each subsequent falling edge of the clk will shift the next bit out. 4.5 serial clock (clk) the clk input is used to synchronize the input and output serial bit streams. the data input (di) is sampled at the rising edge of the clk and the data output (do) will change with the falling edge of the clk signal. 4.6 input data register the device has two input registers. the first bit (bit 0) at the di-input is used to select one of the two input registers. all bits are first shifted into an input shift register. after the rising edge of csn the contents of the input shift register will be written to the selected input data register only if a frame of exact 16 data bits are detected. depending on bit 0 the contents of the selected status register will be transferred to do during the current communication frame. bit 1-8 control the behavior of the corresponding driver. the bits 9,10 and 11 are used to control the current monitor multiplexer. bit 15 is used to reset all status bits in both status registers. the bits in the status registers will be cleared after the current communication frame (rising edge of csn). 4.7 status register this devices uses two status registers to store and to monitor the state of the device. bit 0 is used as a fault bit and is a logical-nor combination of bits 1-14 in both status registers. the state of this bit can be polled by the microcontroller without the need of a full spi- communication cycle (see figure 8. ). if one of the over-current bits is set, the corresponding driver will be disabled. if the over-current recovery bit of the output is not set the microcontroller has to clear the over-current bit to enable the driver. if the thermal shutdown bit is set, all drivers will go into a high impedance state. again the microcontroller has to clear the bit to enable the drivers. 4.8 test mode the test mode can be entered by rising the csn input to a voltage higher than 7.5v. in the test mode the inputs clk, di, pwm and the internal 2mhz clk can be multiplexed to data output do for testing purpose. furthermore the over-current thresholds are reduced by a factor of 4 to allow ews testing at lower current. the internal logic prevents that the hi-side and low-side driver of the same half-bridge can be switched-on at the same time. in the test mode this combination is used to multiplex the desired signals to the cm output according to table 18 and 19.
functional description of the spi l9951 / l9951xp 24/36 doc id 14173 rev 9 table 18. test mode ls1 hs1 ls2 hs2 ls3 hs3 do ls1 hs1 ls2 hs2 ls3 hs3 cm ! (both hi) ! (both hi) ! (both hi) noerror ! (both hi) ! (both hi) ! (both hi) n.c both hi ! (both hi) ! (both hi) di both hi ! (both hi) ! (both hi) tsense1 ! (both hi) both hi ! (both hi) clk ! (both hi) both hi ! (both hi) tsense2 both hi both hi ! (both hi) int_clk both hi both hi ! (both hi) tsense3 ! (both hi) ! (both hi) both hi pwm ! (both hi) ! (both hi) both hi tsense4 both hi ! (both hi) both hi n.c ! (both hi) both hi both hi 5a iref both hi both hi both hi vbandgap table 19. spi - input data and status register 0 input register 0 (write) status register 0 (read) bit name comment name comment 15 reset bit if reset bit is set both status registers will be cleared after rising edge of csn input. always 1 a broken vcc-or spi- connection of the l9951 can be detected by the microcontroller, because all 16 bits low or high is not a valid frame. 14 disable open- load if the disable open-load bit is set, the open-load status bits will be ignored for the nonerrorbit calculation. v s over-voltage in case of an over-voltage or undervoltage event the corresponding bit is set and the outputs are deactivated. 13 oc recovery duty cycle 0: 12% 1: 25% this bit defines in combination with the over- current recovery bit (input register 1) the duty cycle in over-current condition of an activated driver. if temperature warning bit is set, l9951 will always use the lower duty cycle v s undervoltage if vs voltage recovers to normal operating conditions outputs are reactivated automatically. 12 overvoltage/ under-voltage recovery disable if this bit is set the microcontroller has to clear the status register after undervoltage/overvoltage event to enable the outputs. thermal shutdown in case of an thermal shutdown all outputs are switched off. the microcontroller has to clear the tsd bit by setting the reset bit to reactivate the outputs.
l9951 / l9951xp functional description of the spi doc id 14173 rev 9 25/36 11 current monitor select bits following current image (1/10.000) of the hs driver will be multiplexed to cm output: temperature warning this bit is for information purpose only. it can be used for a thermal management by the microcontroller to avoid a thermal shutdown. 10 not ready bit after switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. this bit is cleared automatically after start up time has finished. since this bit is controlled by internal clock it can be used for synchronizing testing events (e.g. measuring filter times). 9 0 not used 8 out5 - hs on/off if a bit is set the selected output driver is switched on. if the corresponding pwm enable bit is set (input register 1) the driver is only activated if pwm input signal is high. the outputs of out1-out3 are half bridges. if the bits of hs- and ls-driver of the same half bridge are set, the internal logic prevents that both drivers of this output stage can be switched on simultaneously in order to avoid a high internal current from vs to gnd. out5-hs over - current in case of an over-current event the corresponding status bit is set and the output driver is disabled. if the over-current recovery enable bit is set (input register 1) the output will be automatically reactivated after a delay time resulting in a pwm modulated current with a programmable duty cycle (bit 13). if the over-current recovery bit is not set the microcontroller has to clear the over-current bit (reset bit) to reactivate the output driver. 7 out4 - hs on/off out4-hs over - current 6 out3 - hs on/off out3-hs over - current 5 out3 - ls on/off out3-ls over - current 4 out2 - hs on/off out2-hs over - current 3 out2 - ls on/off out2-ls over - current 2 out1 - hs on/off out1-hs over - current 1 out1 - ls on/off out1-ls over - current 0 0 no error bit a logical nor-combination of all bits 1 to 14 in both status registers. if bit 14 (disable open-load) is set, the open- load status will be ignored. table 19. spi - input data and status register 0 (continued) input register 0 (write) status register 0 (read) bit name comment name comment bit 11 bit 10 bit 9 output 000out1 001out2 010out3 011out4 100out5
functional description of the spi l9951 / l9951xp 26/36 doc id 14173 rev 9 table 20. spi - input data and status register 1 input register 1 (write) status register 1 (read) bit name comment name comment 15 not used always 1 a broken vcc-or spi- connection of the l9951 can be detected by the microcontroller, because all 16 bits low or high is not a valid frame. 14 not used v s over-voltage in case of an over-voltage or undervoltage event the corresponding bit is set and the outputs are deactivated. 13 not used v s undervoltage in case of an over-voltage or undervoltage event the corresponding bit is set and the outputs are deactivated. 12 not used thermal shutdown in case of an thermal shutdown all outputs are switched off. the microcontroller has to clear the tsd bit by setting the reset bit to reactivate the outputs. 11 not used temperature warning this bit is for information purpose only. it can be used for a thermal management by the microcontroller to avoid a thermal shutdown.
l9951 / l9951xp functional description of the spi doc id 14173 rev 9 27/36 10 out5 oc recovery enable in case of an over-current event the over-current status bit (status register 0) is set and the output is switched off. if the over- current recovery enable bit is set the output will be automatically reactivated after a delay time resulting in a pwm modulated current with a programmable duty cycle (bit 13 of input data register 1). depending on occurrence of overcurrent event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero. not ready bit after switching the device from standby mode to active mode an internal timer is started to allow charge pump to settle before the outputs can be activated. this bit is cleared automatically after start up time has finished. since this bit is controlled by internal clock it can be used for synchronizing testing events(e.g. measuring filter times). 9 out4 oc recovery enable 0 not used. 8 out3 oc recovery enable out5-hs open-load the open-load detection monitors the load current in each activated output stage. if the load current is below the open-load detection threshold for at least 1 ms (t dol ) the corresponding open-load bit is set. due to mechanical /electrical inertia of typical loads a short activation of the outputs (e.g. 3ms) can be used to test the open-load status without changing the mechanical/electrical state of the loads. 7 out2 oc recovery enable out4-hs open-load 6 out1 oc recovery enable out3-hs open-load 5 out5 pwm enable if the pwm enable bit is set and the output is enabled (input register 0) the output is switched on if pwm input is high and switched off if pwm input is low. out3-ls open-load 4 out4 pwm enable out2-hs open-load 3 out3 pwm enable out2-ls open-load 2 out2 pwm enable out1-hs open-load 1 out1 pwm enable out1-ls open-load 0 1 no error bit a logical nor-combination of all bits 1 to 14 in both status registers. if bit 14 (disable open-load) is set, the open- load status will be ignored table 20. spi - input data and status register 1 (continued) input register 1 (write) status register 1 (read) bit name comment name comment
packages thermal data l9951 / l9951xp 28/36 doc id 14173 rev 9 5 packages thermal data figure 10. packages thermal data
l9951 / l9951xp package and packing information doc id 14173 rev 9 29/36 6 package and packing information 6.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 6.2 powerso-36? package information figure 11. powerso-36? package dimensions table 21. powerso-36? mechanical data symbol millimeters min. typ. max. a 3.60 a1 0.10 0.30 a2 3.30 a3 0 0.10 b0.22 0.38 c0.23 0.32
package and packing information l9951 / l9951xp 30/36 doc id 14173 rev 9 d * 15.80 16.00 d1 9.40 9.80 e 13.90 14.5 e1 * 10.90 11.10 e2 2.90 e3 5.80 6.20 e0.65 e3 11.05 g 0 0.10 h 15.50 15.90 h 1.10 l 0.8 1.10 m n 10 deg r s 8 deg table 21. powerso-36? mechanical data (continued) symbol millimeters min. typ. max.
l9951 / l9951xp package and packing information doc id 14173 rev 9 31/36 6.3 powersso-36? package information figure 12. powersso-36? package dimensions table 22. powersso-36? mechanical data symbol millimeters min. typ. max. a- -2.45 a2 2.15 - 2.35 a1 0 - 0.1 b 0.18 - 0.36 c 0.23 - 0.32 d * 10.10 - 10.50 e * 7.4 - 7.6 e-0.5- e3 - 8.5 - f2.3 g- -0.1 g1 - - 0.06 h 10.1 - 10.5 h- -0.4 k0 8 l 0.55 - 0.85 n - - 10 deg
package and packing information l9951 / l9951xp 32/36 doc id 14173 rev 9 6.4 powerso-36? packing information figure 13. powerso-36 tm tube shipment (no suffix) x 4.3 - 5.2 y 6.9 - 7.5 table 22. powersso-36? mechanical data (continued) symbol millimeters min. typ. max.
l9951 / l9951xp package and packing information doc id 14173 rev 9 33/36 figure 14. powerso-36 tm tape and reel shipment (suffix ?tr?) reel dimensions base qty 600 bulk qty 600 a (max) 330 b (min) 1.5 c (0.2) 13 d (min) 20.2 g (+2 / -0) 24.4 n (min) 60 t (max) 30.4 tape dimensions all dimensions are in mm. a0 15.20 0.1 b0 16.60 0.1 k0 3.90 0.1 k1 3.50 0.1 f 11.50 0.1 p1 24.00 0.1 w 24.00 0.3
package and packing information l9951 / l9951xp 34/36 doc id 14173 rev 9 6.5 powersso-36? packing information figure 15. powersso-36 tm tube shipment (no suffix) figure 16. powersso-36 tm tape and reel shipment (suffix ?tr?) all dimensions are in mm. base qty 49 bulk qty 1225 tube length (0.5) 532 a 3.5 b 13.8 c (0.1) 0.6 a c b base qty 1000 bulk qty 1000 a (max) 330 b (min) 1.5 c (0.2) 13 f 20.2 g (+2 / -0) 24.4 n (min) 100 t (max) 30.4 reel dimensions tape dimensions according to electronic industries association (eia) standard 481 rev. a, feb. 1986 all dimensions are in mm. tape width w 24 tape hole spacing p0 (0.1) 4 component spacing p 12 hole diameter d (0.05) 1.55 hole diameter d1 (min) 1.5 hole position f (0.1) 11.5 compartment depth k (max) 2.85 hole spacing p1 (0.1) 2 top cover tape end start no components no components components 500mm min 500mm min empty components pockets sealed with cover tape. user direction of feed
l9951 / l9951xp revision history doc id 14173 rev 9 35/36 7 revision history table 23. document revision history date revision description of changes mar-2004 1 first issue jun-2005 2 added powerso-36? package information , powerso-36? package information . jul-2005 3 updated figure 1.: block diagram . sep-2005 4 note 1 removal; updated figure 10.: packages thermal data . feb-2006 5 updated table 4.: esd protection . 15-nov-2007 6 document restructured and reformatted. added powerso-36? packing information and powersso-36? packing information . 24-jun-2009 7 table 22: powersso-36? mechanical data : ? deleted a (min) value ? changed a (max) value from 2.47 to 2.45 ? changed a2 (max) value from 2.40 to 2.35 ? changed a1 (max) value from 0.075 to 0.1 ? added f and k rows 14-may-2010 8 table 22: powersso-36? mechanical data : ? changed x: minimum value from 4.1 to 4.3 and maximum value from 4.7 to 5.2 ? changed y: minimum value from 6.5 to 6.9 and maximum value from 7.1 to 7.5 22-sep-2013 9 updated disclaimer.
l9951 / l9951xp 36/36 doc id 14173 rev 9 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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