small signal product - meet iec61000-4-2 (esd) 15kv (air), 8kv (contact) - meet iec61000-4-4 (eft) rating. 40a (5/50ns) - meet iec61000-4-5 (lightning) rating. 1a (8/20 s) - protects two directional i/o lines - working voltage: 5v - low capacitance : 0.5 pf typical (i/o to i/o) - pb free version and rohs compliant - packing code with suffix "g" means green compound (halogen-free) - case: 2510p10 (dson10) standard package, molded plastic - molding compound flammability rating : ul 94v-0 - weight: 15 0.5 mg - marking code : p524 - high definition multi-media interface (hdmi) - digital visual interface (dvi) note: output line (no internal connection) - pci express - serial ata - usb 3.0 super speed interface symbol unit p pp w i pp a t j , t stg o c symbol unit v rwm v v (br) v i r a v c v c j pf document number: ds_s1501021 version: d15 tesdh5v0a taiwan semiconductor ultra low capacitance esd protection array features 2510p10 (dson10) mechanical data - terminal: matte tin plat ed, lead free., solderable per mil-std-202, method 208 guaranteed - high temperature soldering guaranteed : 260c/10s applications maximum ratings and electrical characteristics (t a =25c unless otherwise noted) parameter value peak pulse power (tp=8/20 s waveform) 150 esd per iec 61000-4-2 (air) v esd 15 kv esd per iec 61000-4-2 (contact) 8 junction and storage temperature range -55 to +150 parameter min max reverse stand-off voltage - 5 i r = 1 ma 6- reverse leakage current v r = 5 v -1 junction capacitance v r = 0 v , f = 1.0 mhz 1 peak pulse current (tp=8/20 s) 1 clamping voltage i pp = 1 a -15 reverse breakdown voltage
small signal product (t a =25c unless otherwise noted) document number: ds_s1501021 version: d15 tesdh5v0 a taiwan semiconductor ratings and characteristics curves 0.01 0.1 1 10 0.1 1 10 100 1000 peak pulse power ppp (kw) fig. 1 non-repetitive peak pulse power vs. pulse time pulse duration ( s) 0 10 20 30 40 50 60 70 80 90 100 110 0 5 10 15 20 25 30 percent of i pp time (us) fig. 2 pulse waveform td = ipp / 2 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 180 power rating (%) ambient temperature ( o c) fig. 3 admissible power dissipation curve 0.0 0.5 1.0 1.5 012345 normalized capacitance (pf) reverse voltage (v) fig. 4 typical junction capacitance f = 1.0 mhz waveform parameters: tr = 8 s , td = 20 s e -1 0 5 10 15 20 25 30 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 clamping voltage (v) peak pulse current (a) fig. 5 clamping voltage vs. peak pulse current waveform parameters: tr = 8 s , td = 20 s -15 -12 -9 -6 -3 0 3 1 10 100 1000 10000 (db) f (mhz) fig. 6 insertion loss f = 1.0 mhz 1 2 4 5 3 1: -0.073db 900mhz 2: -0.065db 1.8ghz 3: -0.107db 2.5ghz 4: -0.06477db 3.0ghz 5: -0.18073db 4.3ghz
package outline dimensions min max min max a 2.40 2.60 0.094 0.102 b 0.90 1.10 0.035 0.043 c d e 0.30 0.43 0.012 0.017 f 0.45 0.55 0.018 0.022 g 0.50 0.65 0.020 0.026 h 0.15 0.25 0.006 0.010 i 0.35 0.45 0.014 0.018 suggested pad layout a b c d e f g h note: 1. the suggested land pattern dimensions have been provided for reference only, as actual pad layouts may vary depending on application. document number: ds_s1501021 version: d15 tesdh5v0 a taiwan semiconductor small signal product order information (example) 2510p10 (dson10) dim. unit (mm) unit (inch) dim. typ. 1.55 0.061 0.88 0.035 0.20 0.008 0.50 0.020 1.00 0.039 0.20 0.008 0.40 0.016 0.68 0.027 0.50 ref 0.020 ref 0.63 ref 0.025 ref unit (mm) unit (inch) typ. tesdh5v0a rdg green compound ? code packing ? code part ? no.
small signal product applications information and minimizes impact on signal integrity circuit board layout recommendations for hdmi application document number: ds_s1501021 version: d15 signal line enters at pin 1 and exits at pin 10 and the pcb tr ace connects pin 1 and 10 together. ground is connected at pin 3 and 8. the pcb traces are used to connect the pin pairs for each line (pin 1 to pin 10, pin 2 to pin 9, pin 4 to pin 7, pin 5 to pin 6) one large ground pad should be used in lieu of two separate pads tesdh5v0 a taiwan semiconductor designed for protection of high-speed interfaces such as hdmi ultra low capacitance between the paris while being rated to handle >8kv esd contact discharges and >15kv air discharge each device in a leadless package that is less than 1.1mm wide designed such that the traces flow straight through the device. the narrow package and flow-through design reduces discontinui ties tesdh5v0a is ultra low capacitance esd protection array designed to protect high speed data interfaces. this series has been specifically designed to protect sensitive components which are connected to high-speed data and transmission lines from overvoltage caused by esd, cde (cable discharge events), and eft (electrical fast transients) the combination of small size, low capacitance, and high level of esd protection makes them a flexible solution for applicatio ns of high speed interface, ex hdmi, displayporttm, mddi, and esata interfaces
small signal product assumes no responsibility or liability for any errors or inaccuracies. information contained herein is intended to provide a product description only. no license, express or implied,to any intellectual property rights is granted by this document. except as provided in tsc's terms and conditions of sale for such products, tsc assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of tsc products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. the products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. customers using or seling these products for use in such applications do so at their own risk and agree to fully indemnify tsc for any damages resulting from such improper use or sale. document number: ds_s1501021 version: d15 tesdh5v0 a taiwan semiconductor notice specifications of the products displayed herein are subject to change without notice. tsc or anyone on its behalf,
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