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| ? 2016 microchip technology inc. preliminary ds40001839a-page 1 pic16(l)f18326/18346 description pic16(l)f18326/18346 microcontrollers feature analog, core independent peripherals and communication peripherals, combined with extreme low power (xlp) for a wide range of general purpose and low-power a pplications. the peripheral pin select (pps) functionality enables pin mapping when using the digital peripherals (clc, cwg, ccp, pwm and communications) to add flexibility to the application design. core features c compiler optimized risc architecture only 49 instructions operating speed: - dc C 32 mhz clock input - 125 ns minimum instruction cycle interrupt capability 16-level deep hardware stack up to four 8-bit timers up to three 16-bit timers low-current power-on reset (por) configurable power-up timer (pwrte) brown-out reset (bor) with fast recovery low-power bor (lpbor) option extended watchdog timer (wdt) with dedicated on-chip oscillator for reliable operation programmable code protection memory 28 kbytes program flash memory 2 kb data sram memory 256b of eeprom direct, indirect and relative addressing modes operating characteristics operating voltage range: - 1.8v to 3.6v (pic16lf18326/18346) - 2.3v to 5.5v (pic16f18326/18346) temperature range: - industrial: -40c to 85c - extended: -40c to 125c extreme low-power (xlp) features sleep mode: 40 na @ 1.8v, typical watchdog timer: 250 na @ 1.8v, typical secondary oscillator: 300 na @ 32 khz operating current: -8 ? a @ 32 khz, 1.8v, typical -37 ? a/mhz @ 1.8v, typical power-saving functionality idle mode: ability to put the cpu core to sleep while internal peripherals continue operating from the system clock doze mode: ability to run the cpu core slower than the system clock used by the internal peripherals sleep mode: lowest power consumption peripheral module disable (pmd): peripheral power disable hardware module to minimize power consumption of unused peripherals digital peripherals configurable logic cell (clc): - four clcs - integrated combinational and sequential logic complementary waveform generator (cwg): - two cwgs - rising and falling edge dead-band control - full-bridge, half-bridge, 1-channel drive - multiple signal sources capture/compare/pwm (ccp) modules: - four ccps - 16-bit resolution for capture/compare modes - 10-bit resolution for pwm mode pulse-width modulators (pwm): -two 10-bit pwms numerically controlled oscillator (nco): - precision linear frequency generator (@50% duty cycle) with 0.0001% step size of source input clock - input clock: 0 hz < f nco < 32 mhz - resolution: f nco /2 20 serial communications: - eusart - rs-232, rs-485, lin compatible - auto-baud detect, auto-wake-up on start - master synchronous serial port (mssp) - spi -i 2 c, smbus, pmbus? compatible data signal modulator (dsm): - modulates a carrier signal with digital data to create custom carrier synchronized output waveforms full-featured, low pin count microcontrollers with xlp downloaded from: http:///
pic16(l)f18326/18346 ds40001839a-page 2 preliminary ? 2016 microchip technology inc. up to 18 i/o pins: - individually programmable pull-ups - slew rate control - interrupt-on-change with edge-select - input level selection control (st or ttl) - digital open-drain enable peripheral pin select (pps): - i/o pin remapping of digital peripherals timer modules: -timer0: - 8/16-bit timer/counter - synchronous or asynchronous operation - programmable prescaler/postscaler - time base for capture/compare function - timer1/3/5 with gate control: - 16-bit timer/counter - programmable internal or external clock sources - multiple gate sources - multiple gate modes - time base for capture/compare function - timer2/4/6: - 8-bit timers - programmable prescaler/postscaler - time base for pwm function analog peripherals 10-bit analog-to-digital converter (adc): - 17 external channels - conversion available during sleep comparator: - two comparators - fixed voltage reference at non-inverting input(s) - comparator outputs externally accessible 5-bit digital-to-analog converter (dac): - 5-bit resolution, rail-to-rail - positive reference selection - unbuffered i/o pin output - internal connections to adcs and comparators voltage reference: - fixed voltage reference with 1.024v, 2.048v and 4.096v output levels flexible oscillator structure high-precision internal oscillator: - software-selectable frequency range up to 32 mhz - 1% at nominal 4 mhz calibration point 4x pll with external sources low-power internal 31 khz oscillator (lfintosc) external low-power 32 khz crystal oscillator (sosc) external oscillator block with: - three crystal/resonator modes up to 20 mhz - three external clock modes up to 20 mhz - fail-safe clock monitor - allows for safe shutdown if peripheral clock stops - oscillator start-up timer (ost) - ensures stability of crystal oscillator sources downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 3 pic16(l)f18326/18346 table 1: pic16(l)f183xx family types device data sheet index program memory (kb) program memory (kw) eeprom (b) ram (b) i/os (1) 10-bit adcs comparators 5-bit dac timers 0/1/2 ccp/pwm cwg eusart spi i 2 c clc nco pps icd (2) pic16(l)f18313 ( a ) 3.5 2 256 256 6 5 1 1 1/1/1 2/2 1 1 1 1 2 1 y i pic16(l)f18323 ( a ) 3.5 2 256 256 12 11 2 1 1/1/1 2/2 1 1 1 1 2 1 y i pic16(l)f18324 ( b ) 7 4 256 512 12 11 2 1 1/3/3 4/2 2 1 1 1 4 1 y i pic16(l)f18325 ( c ) 14 8 256 1k 12 11 2 1 1/3/3 4/2 2 1 2 2 4 1 y i pic16(l)f18326 ( d ) 28 16 256 2k 12 11 2 1 1/3/3 4/2 2 1 2 2 4 1 y i pic16(l)f18344 ( b ) 7 4 256 512 18 17 2 1 1/3/3 4/2 2 1 1 1 4 1 y i pic16(l)f18345 ( c ) 14 8 256 1k 18 17 2 1 1/3/3 4/2 2 1 2 2 4 1 y i pic16(l)f18346 ( d ) 28 16 256 2k 18 17 2 1 1/3/3 4/2 2 1 2 2 4 1 y i note 1: one pin is input-only. 2: debugging methods: (i) C integrated on chip; e C using emulation header. data sheet index: (unshaded devices are described in this document.) note a: ds40001799 pic16(l)f18313/18323 data sheet,full-featured , low pin count microcontrollers with xlp b: ds40001800 pic16(l)f18324/18344 data sheet,full-featured, low pin count microcontrollers with xlp c: ds40001795 pic16(l)f18325/18345 data sheet,full-featured, low pin count microcontrollers with xlp d: ds40001839 pic16(l)f18326/18346 data sheet,full-featured, low pin count microcontrollers with xlp note: for other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 4 preliminary ? 2016 microchip technology inc. pin diagrams figure 1: 14-pin pdip, soic, tssop figure 2: 16-pin uqfn (4x4) figure 3: 20-pin pdip, soic, ssop 12 3 4 5 6 7 v dd ra5 ra4 v pp /mclr /ra3 rc5rc4 rc3 ra0/icspdat ra1/icspclk ra2 rc0 rc1 rc2 1413 12 11 10 9 8 v ss pic16(l)f18326 note: see table 2 for location of all peripheral functions. 23 1 9 10 11 12 rc4 4 v ss ra0/icspdat ra1/icspclk ra2 rc0 nc nc v dd ra5 ra4 ra3/mclr /v pp rc5 rc3 rc2 rc1 67 58 1514 16 13 pic16(l)f18326 note 1: see table 2 for location of all peripheral functions. 2: it is recommended that the exposed bottom pad be connected to v ss , but must not be the main v ss connection to the device. pic16(l)f18346 23 4 5 6 7 89 10 v dd ra5 ra4 mclr /v pp /ra3 rc5rc4 rc3 rc6 rc7 rb7 ra0 ra1 ra2 rc0 rc1 rc2 rb4 rb5 rb6 2019 18 17 16 15 14 1312 11 v ss 1 note: see table 3 for location of all peripheral functions. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 5 pic16(l)f18326/18346 figure 4: 20-pin uqfn (4x4) 23 4 5 1 67 8 9 20 19 18 17 16 10 12 13 14 15 11 pic16(l)f18346 rb4 rb5 rb6 rb7 rc7 m clr /v pp /ra3 rc5rc4 rc3 rc6 ra4 ra5 v dd v ss ra0 ra1 ra2 rc0 rc1 rc2 note 1: see ta b l e 3 for location of all peripheral functions. 2: it is recommended that the exposed bottom pad be connected to v ss , but must not be the main v ss connection to the device. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 6 preliminary ? 2016 microchip technology inc. pin allocation tables table 2: 14/16-pin allocation table (pic16(l)f18326) i/o (2) 14-pin pdip/soic/tssop 16-pin uqfn adc reference comparator nco dac dsm timers ccp pwm cwg mssp eusart clc clkr interrupt pull-up basic ra0 13 12 ana0 c1in0+ dac1out ss2 (1) ioc y icddat/ icspdat ra1 12 11 ana1 v ref + c1in0- c2in0- d a c 1 ref + ioc y icdclk/ icspclk ra2 11 10 ana2 v ref - dac1 ref - t0cki (1) ccp3 (1) cwg1in (1) cwg2in (1) int (1) ioc y ra3 4 3 ioc y mclr v pp ra4 3 2 ana4 t1g (1) sosco ioc y clkout osc2 ra5 2 1 ana5 t1cki (1) soscin sosci clcin3 (1) ioc y clkin osc1 rc0 10 9 anc0 c2in0+ t5cki (1) sck1 (1) scl1 (1,3,4) ioc y rc1 9 8 anc1 c1in1- c2in1- ccp4 (1) s d i 1 (1) sda1 (1,3,4) clcin2 (1) ioc y rc2 8 7 anc2 c1in2- c2in2- mdcin1 (1) ioc y rc3 7 6 anc3 c1in3- c2in3- m d m i n (1) t5g (1) ccp2 (1) ss1 (1) clcin0 (1) ioc y rc4 6 5 anc4 t3g (1) sck2 (1) scl2 (1,3,4) ? clcin1 (1) ioc y rc5 5 4 anc5 m d c i n 2 (1) t3cki (1) ccp1 (1) s d i 2 (1) sda2 (1,3,4) rx (1) dt (1,3) ioc y v dd 1 16 v dd note 1: default peripheral input. input can be moved to any other pin wit h the pps input selection registers. 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selectio n registers. 3: these peripheral functions are bidirectional. the output pin selections must be the same as the input pin select ions. 4: these pins are configured for i 2 c logic levels; clock and data signals may be assigned to any of these pins. assignments to th e other pins (e.g., ra5) will ope rate, but logic levels will be standard ttl/ st as selected by the inlvl register. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 7 pic16(l)f18326/18346 v ss 14 13 v ss out (2) c1out nco1 dsm tmr0 ccp1 pwm5 cwg1a cwg2a sda1 (3) sda2 (3) ck clc1out clkr c2out ccp2 pwm6 cwg1b cwg2b scl1 (3) scl2 (3) dt (3) clc2out ccp3 cwg1c cwg2c sdo1 sdo2 tx clc3out ccp4 cwg1d cwg2d sck1 sck2 clc4out table 2: 14/16-pin allocation table (pic16(l)f18326) (continued) i/o (2) 14-pin pdip/soic/tssop 16-pin uqfn adc reference comparator nco dac dsm timers ccp pwmcwg mssp eusart clc clkr interrupt pull-up basic note 1: default peripheral input. input can be moved to any other pin wit h the pps input selection registers. 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selectio n registers. 3: these peripheral functions are bidirectional. the output pin selections must be the same as the input pin select ions. 4: these pins are configured for i 2 c logic levels; clock and data signals may be assigned to any of these pins. assignments to th e other pins (e.g., ra5) will ope rate, but logic levels will be standard ttl/ st as selected by the inlvl register. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 8 preliminary ? 2016 microchip technology inc. table 3: 20-pin allocation table (pic16(l)f18346) i/o (2) 20-pin pdip/soic/ssop 20-pin uqfn adc reference comparator nco dac dsm timers ccp pwmcwg mssp eusart clc clkr interrupt pull-up basic ra0 19 16 ana0 c1in0+ dac1out ioc y icddat icspdat ra1 18 15 ana1 v ref + c1in0- c2in0- d a c 1 ref + ? s s 2 ioc y icdclk icspclk ra2 17 14 ana2 v ref - dac1 ref - t0cki (1) ccp3 (1) cwg1in (1) cwg2in (1) clcin0 (1) ioc int (1) y ra3 4 1 ioc y mclr v pp ra4 3 20 ana4 t1g (1) t3g (1) t5g (1) sosco ccp4 (1) ioc y clkout osc2 ra5 2 19 ana5 t1cki (1) t3cki (1) t5cki (1) soscin sosci ioc y clkin osc1 rb4 13 10 anb4 sdi1 (1) sda1 (1,3,4) clcin2 (1) ioc y rb5 12 9 anb5 sdi2 (1) sda2 (1,3,4) rx (1) dt (1) clcin3 (1) ioc y rb6 11 8 anb6 sck1 (1) scl1 (1,3,4) ioc y rb7 10 7 anb7 sck2 (1) scl2 (1,3,4) ioc y rc0 16 13 anc0 c2in0+ ioc y rc1 15 12 anc1 c1in1- c2in1- ioc y rc2 14 11 anc2 c1in2- c2in2- mdcin1 (1) ioc y note 1: default peripheral input. input can be moved to any other pin wit h the pps input selection registers. 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selectio n registers. 3: these peripheral functions are bidirectional. the output pin selections must be the same as the input pin select ions. 4: these pins are configured for i 2 c logic levels; clock and data signals may be assigned to any of these pins. assignment s to other pins (e.g., ra5) will operate , but logic levels will be standard ttl/st as selected by the inlvl register. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 9 pic16(l)f18326/18346 rc3 7 4 anc3 c1in3- c2in3- m d m i n (1) ccp2 (1) clcin1 (1) ioc y rc4 6 3 anc4 ioc y rc5 5 2 anc5 mdcin2 (1) ccp1 (1) ioc y rc6 8 5 anc6 ss 1 (1) ioc y rc7 9 6 anc7 ioc y v dd 1 18 v dd v ss 20 17 v ss out (2) c1out nco1 dsm tmr0 ccp1 pwm5 cwg1a cwg2a sdo1 sdo2 dt (3) clc1out clkr c2out ccp2 pwm6 cwg1b cwg2b sck1 sck2 ck clc2out ccp3 cwg1c cwg2c scl1 (3) scl2 (3) tx clc3out ccp4 cwg1d cwg2d sda1 (3) sda2 (3) clc4out table 3: 20-pin allocation table (pic16(l)f18346) (continued) i/o (2) 20-pin pdip/soic/ssop 20-pin uqfn adc reference comparator nco dac dsm timers ccp pwmcwg mssp eusart clc clkr interrupt pull-up basic note 1: default peripheral input. input can be moved to any other pin wit h the pps input selection registers. 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selectio n registers. 3: these peripheral functions are bidirectional. the output pin selections must be the same as the input pin select ions. 4: these pins are configured for i 2 c logic levels; clock and data signals may be assigned to any of these pins. assignment s to other pins (e.g., ra5) will operate , but logic levels will be standard ttl/st as selected by the inlvl register. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 10 preliminary ? 2016 microchip technology inc. table of contents 1.0 device overview ............................................................................ ................................. ........................................................... 11 2.0 enhanced mid-range cpu .......................................... ................................................... ......... .................................................. 22 3.0 memory organization .......................................... ................................................... ............ ........................................................ 24 4.0 device configuration .................................................................... .................................... .......................................................... 59 5.0 resets .......................................................................................... .............................................................................................. 66 6.0 oscillator module (with fail-safe clock monitor) .............. ....................................................................................................... .. 74 7.0 interrupts .................................................................................... ................................................................................................ 93 8.0 power-saving operation modes ....................................... ................................................... ...... .............................................. 110 9.0 watchdog timer (wdt) ........................................ ................................................... ............. ................................................... 116 10.0 nonvolatile memory (nvm) control....................... .................................................................... ............................................... 120 11.0 i/o ports ....................................................................................... ........................... ................................................................. 138 12.0 peripheral pin select (pps) module ....................................... .................................................. ............................................... 158 13.0 peripheral module disable ........................................... ................................................... .... ..................................................... 164 14.0 interrupt-on-change ............................................ ................................................... ......... ......................................................... 170 15.0 fixed voltage reference (fvr) ....................................... ................................................... ... ................................................. 177 16.0 temperature indicator module ........................................ ................................................... .... .................................................. 180 17.0 comparator module......................................... ................................................... .............. ........................................................ 182 18.0 pulse-width modulation (pwm) ................................... ................................................... ......... ................................................ 191 19.0 complementary waveform generator (cwg) module ........... ................................................................... .............................. 197 20.0 configurable logic cell (clc)........................................ ................................................... ... .................................................... 219 21.0 analog-to-digital converter (adc) module ..................................... .............................................. ........................................... 234 22.0 numerically controlled oscillator (nco1) module ................................. ........................................... ....................................... 248 23.0 5-bit digital-to-analog converter (dac1) module ....................................... ..................................... ........................................ 259 24.0 data signal modulator (dsm) module........................................ ................................................. ............................................. 263 25.0 timer0 module .............................................. ................................................... ............. ........................................................... 274 26.0 timer1/3/5 module with gate control.................................... ................................................... . ............................................... 281 27.0 timer 2/4/6 module .......................................... ................................................... ............ ......................................................... 294 28.0 capture/compare/pwm modules ........................................ ................................................... ..... ............................................ 299 29.0 master synchronous serial port (msspx) module ............................... ............................................... .................................... 312 30.0 enhanced universal synchronous asynchronous receiver transmitter (eusart1) ........................................ ......... ............ 365 31.0 reference clock output module ...................................... ................................................... ..... ................................................ 390 32.0 in-circuit serial programming? (icsp?) .......................... ........................................................... .......................................... 393 33.0 instruction set summary ....................................................... ............................................. ...................................................... 395 34.0 electrical specifications........................................... ....................................................... .......................................................... 409 35.0 dc and ac characteristics graphs and charts ................................... ............................................. ....................................... 439 36.0 development support............................................ ................................................... ......... ....................................................... 440 37.0 packaging information............................................. ......................................................... ........................................................ 444 appendix a: data sheet revision history.................................... ................................................... . .................................................. 467 the microchip website.................................................................... ...................................... ............................................................. 468 customer change notification service ....................................... ................................................... . ................................................... 468 customer support ............................................... ................................................... ............. ............................................................... 468 product identification system.................................................. ................................................................................................. .......... 469 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 11 pic16(l)f18326/18346 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide website at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the versi on number, (e.g., ds30000000a is ve rsion a of document ds30000000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: microchips worldwide website; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our website at www.microchip.com to receive the most current information on all of our products. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 12 preliminary ? 2016 microchip technology inc. 1.0 device overview the pic16(l)f18326/18346 devices are described within this data sheet. pic16(l)f18326 are available in 14-pin pdip, soic, tssop and 16-pin uqfn packages. pic16(l)f18346 are available in 20-pin pdip, soic, ssop and uqfn packages. see section 37.0 ?packaging information? for further packaging information. figure 1-1 shows a block diagram of the pic16(l)f18326/18346 devices. table 1-2 shows the pinout descriptions. reference table 1-1 for peripherals available per device. table 1-1: device peripheral summary peripheral pic16(l)f18326 pic16(l)f18346 analog-to-digital converter (adc) temperature indicator digital-to-analog converter (dac) dac1 fixed voltage reference (fvr) adcfvr cdafvr digital signal modulator (dsm) dsm1 numerically controlled oscillator (nco) nco1 capture/compare/pwm (ccp/eccp) modules ccp1 ccp2 ccp3 ccp4 comparators c1 c2 complementary waveform generator (cwg) cwg1 cwg2 configurable logic cell (clc) clc1 clc2 clc3 clc4 enhanced universal synchronous/asynchronous receiver/transmit- ter (eusart) eusart1 master synchronous serial port (mssp) mssp1 mssp2 pulse-width modulator (pwm) pwm5 pwm6 timers timer0 timer1 timer2 timer3 timer4 timer5 timer6 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 13 pic16(l)f18326/18346 figure 1-1: pic16(l)f18326/18346 block diagram porta portc cpu program flash memory ram timing generation lfintosc oscillator mclr clkin clkout adc 10-bit fvr te m p . indicator eusart1 comparators mssp1/2 timer2/4/6 timer1/3/5 timer0 dac ccps pwms nco1 hfintosc/ clcs cwg1/2 dsm note 1: pic16(l)f18346 only. portb (1) see figure 2-1 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 14 preliminary ? 2016 microchip technology inc. table 1-2: pic16(l)f18326 pinout description name function input type output type description ra0/ana0/c1in0+/dac1out/ ss2 (1) / icddat/icspdat ra0 ttl/st cmos general purpose i/o. ana0 an D adc channel a0 input. c1in0+ an D comparator c1 positive input. dac1out D an digital-to-analog converter output. ss2 ttl/st D slave select 2 input. icddat ttl/st cmos in-circuit debug data i/o. icspdat ttl/st cmos icsp? data i/o. ra1/ana1/v ref +/c1in0-/ c2in0-/dac1 ref +/ icdclk/ icspclk ra1 ttl/st cmos general purpose i/o. ana1 an D adc channel a1 input. v ref +a n D adc positive voltage reference input. c1in0- an comparator c1 negative input. c2in0- an D comparator c2 negative input. dac1 ref + D an digital-to-analog converter positive reference input. icdclk ttl/st cmos in-circuit debug clock i/o. icspclk ttl/st cmos icsp? clock i/o. ra2/ana2/v ref -/ dac1 ref -/ t0cki (1) / ccp3 (1) /cwg1in (1) / cwg2in (1) /int (1) ra2 ttl/st cmos general purpose i/o. ana2 an D adc channel a2 input. v ref -a n D adc negative voltage reference input. dac1 ref - D an digital-to-analog converter negative reference input. t0cki ttl/st D timer0 clock input. ccp3 ttl/st cmos capture/compare/pwm 3 input. cwg1in ttl/st D complementary waveform generator 1 input. cwg2in ttl/st D complementary waveform generator 2 input. int ttl/st D external interrupt input. ra3/mclr /v pp ra3 ttl/st cmos general purpose i/o. mclr ttl/st D master clear with internal pull-up. v pp hv D programming voltage. ra4/ana4/t1g (1) / sosco/ clkout/osc2 ra4 ttl/st cmos general purpose i/o. ana4 an D adc channel a4 input. t1g st D timer1 gate input. sosco D xtal secondary oscillator connection. clkout D cmos f osc /4 output. osc2 D xtal crystal/resonator (lp, xt, hs modes). legend: an = analog input or output cmos =cmos compatible input or output od = open-drain ttl = ttl compatible input st =schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal =crystal levels note 1: default peripheral input. input can be moved to any other pin with the pps input selection registers. see register 12-1 . 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selection registers. see register 12-2 . 3: these i 2 c functions are bidirectional. the output pin selections must be the same as the input pin selections. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 15 pic16(l)f18326/18346 ra5/ana5/t1cki (1) / soscin/ sosci/ clcin3 (1) /clkin/ osc1 ra5 ttl/st cmos general purpose i/o. ana5 an D adc channel a5 input. t1cki ttl/st D timer1 clock input. soscin ttl/st D secondary oscillator input connection. sosci xtal D secondary oscillator connection. clcin3 ttl/st D configurable logic cell 3 input. clkin ttl/st D external clock input. osc1 xtal D crystal/resonator (lp, xt, hs modes). rc0/anc0/c2in0+/ t5cki (1) / sck1 (1) / scl1 (1,3) rc0 ttl/st cmos general purpose i/o. anc0 an D adc channel c0 input. c2in0+ an D comparator c2 positive input. t5cki ttl/st D timer5 clock input. sck1 ttl/st cmos spi clock 1. scl1 i 2 co di 2 c clock 1. rc1/anc1/c1in1-/c2in1-/ ccp4 (1) /sdi1 (1) / sda1 (1,3) / clcin2 (1) rc1 ttl/st cmos general purpose i/o. anc1 an D adc channel c1 input. c1in1- an D comparator c1 negative input. c2in1- an D comparator c2 negative input. ccp4 ttl/st cmos capture/compare/pwm 4 input. sdi1 ttl/st cmos spi data input 1. sda1 i 2 co di 2 c data 1. clcin2 ttl/st D configurable logic cell 2 input. rc2/anc2/c1in2-/c2in2-/ mdcin1 (1) rc2 ttl/st cmos general purpose i/o. anc2 an D adc channel c2 input. c1in2- an D comparator c1 negative input. c2in2- an D comparator c2 negative input. mdcin1 ttl/st D modular carrier input 1. rc3/anc3/c1in3-/c2in3-/ mdmin (1) /t5g (1) / ccp2 (1) / ss1 (1) /clcin0 (1) rc3 ttl/st cmos general purpose i/o. anc3 an D adc channel c3 input. c1in3- an D comparator c1 negative input. c2in3- an D comparator c2 negative input. mdmin ttl/st D modular source input. t5g ttl/st D timer5 gate input. ccp2 ttl/st cmos capture/compare/pwm 2 input. ss1 ttl/st D slave select 1 input. clcin0 ttl/st D configurable logic cell 0 input. table 1-2: pic16(l)f18326 pinout description (continued) name function input type output type description legend: an = analog input or output cmos =cmos compatible input or output od = open-drain ttl = ttl compatible input st =schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal =crystal levels note 1: default peripheral input. input can be moved to any ot her pin with the pps input selection registers. see register 12-1 . 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selection registers. see register 12-2 . 3: these i 2 c functions are bidirectional. the output pin selections must be the same as the input pin selections. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 16 preliminary ? 2016 microchip technology inc. rc4/anc4/t3g (1) / sck2 (1) / scl2 (1,3) / clcin1 (1) rc4 ttl/st cmos general purpose i/o. anc4 an D adc channel c4 input. t3g ttl/st D timer3 gate input. sck2 ttl/st cmos spi clock 2. scl2 i 2 co di 2 c clock 2. clcin1 ttl/st D configurable logic cell 1 input. rc5/anc5/mdcin2 (1) / t3cki (1) /ccp1 (1) /sdi2 (1) / sda2 (1,3) /rx (1) / dt rc5 ttl/st cmos general purpose i/o. anc5 an D adc channel c5 input. mdcin2 ttl/st D modular carrier input 2. t3cki ttl/st D timer3 clock input. ccp1 ttl/st cmos capture/compare/pwm 1 input. sdi2 ttl/st cmos spi data 2. sda2 i 2 co di 2 c data 2. rx ttl/st cmos eusart asynchronous input. dt ttl/st cmos eusart synchronous data output. v dd v dd power D positive supply. v ss v ss power D ground reference. table 1-2: pic16(l)f18326 pinout description (continued) name function input type output type description legend: an = analog input or output cmos =cmos compatible input or output od = open-drain ttl = ttl compatible input st =schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal =crystal levels note 1: default peripheral input. input can be moved to any other pin with the pps input selection registers. see register 12-1 . 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selection registers. see register 12-2 . 3: these i 2 c functions are bidirectional. the output pin selections must be the same as the input pin selections. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 17 pic16(l)f18326/18346 out (2) c1 D cmos comparator c1 output. c2 D cmos comparator c2 output. nco1 D cmos numerically controlled oscillator output. dsm D cmos digital signal modulator output. tmr0 D cmos timer0 clock output. ccp1 D cmos capture/compare/pwm 1 output. ccp2 D cmos capture/compare/pwm 2 output. ccp3 D cmos capture/compare/pwm 3 output. ccp4 D cmos capture/compare/pwm 4 output. pwm5 D cmos pulse-width modulator 5 output. pwm6 D cmos pulse-width modulator 6 output. cwg1a D cmos complementary waveform generator 1 output a. cwg2a D cmos complementary waveform generator 2 output a. cwg1b D cmos complementary waveform generator 1 output b. cwg2b D cmos complementary waveform generator 2 output b. cwg1c D cmos complementary waveform generator 1 output c. cwg2c D cmos complementary waveform generator 2 output c. cwg1d D cmos complementary waveform generator 1 output d. cwg2d D cmos complementary waveform generator 2 output d. sda1 (3) i 2 co di 2 c data output. sda2 (3) i 2 co di 2 c data output. scl1 (3) i 2 co di 2 c clock output. scl2 (3) i 2 co di 2 c clock output. sdo1 D cmos spi1 data output. sd02 D cmos spi2 data output. sck1 D cmos spi1 clock output. sck2 D cmos spi2 clock output. tx/ck D cmos asynchronous tx data/synchronous clock output. dt (3) D cmos eusart synchronous data output. clc1out D cmos configurable logic cell 1 source output. clc2out D cmos configurable logic cell 2 source output. clc3out D cmos configurable logic cell 3 source output. clc4out D cmos configurable logic cell 4 source output. clkr D cmos clock reference output. table 1-2: pic16(l)f18326 pinout description (continued) name function input type output type description legend: an = analog input or output cmos =cmos compatible input or output od = open-drain ttl = ttl compatible input st =schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal =crystal levels note 1: default peripheral input. input can be moved to any ot her pin with the pps input selection registers. see register 12-1 . 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selection registers. see register 12-2 . 3: these i 2 c functions are bidirectional. the output pin selections must be the same as the input pin selections. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 18 preliminary ? 2016 microchip technology inc. table 1-3: pic16(l)f18346 pinout description name function input type output type description ra0/ana0/c1in0+/dac1out/ icddat/icspdat ra0 ttl/st cmos general purpose i/o. ana0 an D adc channel a0 input. c1in0+ an D comparator c1 positive input. dac1out D an digital-to-analog converter output. icddat ttl/st cmos in-circuit debug data i/o. icspdat ttl/st cmos icsp? data i/o. ra1/ana1/v ref +/c1in0-/ c2in0-/ dac1 ref +/ss2 (1) )/ icdclk/ icspclk ra1 ttl/st cmos general purpose i/o. ana1 an D adc channel a1 input. v ref +a n D adc positive voltage reference input. c1in0- an comparator c1 negative input. c2in0- an D comparator c2 negative input. dac1 ref +a n D digital-to-analog converter positive reference input. ss2 ttl/st D slave select 2 input. icdclk ttl/st cmos in-circuit debug clock i/o. icspclk ttl/st cmos icsp tm clock i/o. ra2/ana2/v ref -/ dac1 ref -/ t0cki (1) / ccp3 (1) /cwg1in (1) / cwg2in (1) /clcin0 (1) / int (1) ra2 ttl/st cmos general purpose i/o. ana2 an D adc channel a2 input. v ref -a n D adc negative voltage reference input. dac1 ref -a n D digital-to-analog converter negative reference input. t0cki ttl/st D timer0 clock input. ccp3 ttl/st cmos capture/compare/pwm 3 input. cwg1in ttl/st D complementary waveform generator 1 input. cwg2in ttl/st D complementary waveform generator 2 input. clcin0 ttl/st D configurable logic cell 0 input. int ttl/st D external interrupt input. ra3/mclr /v pp ra3 ttl/st cmos general purpose i/o. mclr ttl/st D master clear with internal pull-up. v pp hv D programming voltage. ra4/ana4/t1g(1)/t3g (1) / t5g (1) /sosco/ccp4 (1) / clkout/osc2 ra4 ttl/st cmos general purpose i/o. ana4 an D adc channel a4 input. t1g ttl/st D timer1 gate input. t3g ttl/st D timer3 gate input. t5g ttl/st D timer5 gate input. sosco D xtal secondary oscillator connection. ccp4 ttl/st cmos capture/compare/pwm 4 input. clkout D cmos fosc/4 output. osc2 D xtal crystal/resonator (lp, xt, hs modes). legend: an = analog input or output cmos= cmos compatible input or output od = open-drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: default peripheral input. input can be moved to any other pin with the pps input selection registers. see register 12-2 . 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selection registers. see register 12-2 . 3: these i 2 c functions are bidirectional. the output pin selections must be the same as the input pin selections. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 19 pic16(l)f18326/18346 ra5/ana5/t1cki (1) / t3cki (1) / t5cki (1) / soscin/sosci/ clkin/osc1 ra5 ttl/st cmos general purpose i/o. ana5 an D adc channel a5 input. t1cki ttl/st D timer1 clock input. t3cki ttl/st D timer3 clock input. t5cki ttl/st D timer5 clock input. soscin ttl/st D secondary oscillator input connection. sosci xtal D secondary oscillator connection. clkin ttl/st D external clock input. osc1 xtal D crystal/resonator (lp, xt, hs modes). rb4/anb4/sdi1 (1) / sda1 (1,3) / clcin2 (1) rb4 ttl/st cmos general purpose i/o. anb4 an D adc channel b4 input. sdi1 ttl/st cmos spi data input 1. sda1 i 2 co di 2 c data 1. clcin2 ttl/st D configurable logic cell 2 input. rb5/anb5/sdi2 (1) / sda2 (1,3) / rx (1) /dt/clcin3 (1) rb5 ttl/st cmos general purpose i/o. anb5 an D adc channel b5 input. sdi2 ttl/st cmos spi data input 2. sda2 i 2 co di 2 c data 2. rx ttl/st cmos eusart asynchronous input. dt ttl/st cmos eusart synchronous data output. clcin3 ttl/st D configurable logic cell 3 input. rb6/anb6/sck1 (1) / scl1 (1,3) rb6 ttl/st cmos general purpose i/o. anb6 an D adc channel b6 input. sck1 ttl/st cmos spi clock 1. scl1 i 2 co di 2 c clock 1. rb7/anb7/sck2 (1) / scl2 (1,3) rb7 ttl/st cmos general purpose i/o. anb7 an D adc channel b7 input. sck2 ttl/st cmos spi clock 2. scl2 i 2 co di 2 c clock 2. rc0/anc0/c2in0+ rc0 ttl/st cmos general purpose i/o. anc0 an D adc channel c0 input. c2in0+ an D comparator c2 positive input. rc1/anc1/c1in1-/c2in1- rc1 ttl/st cmos general purpose i/o. anc1 an D adc channel c1 input. c1in1- an D comparator c1 negative input. c2in1- an D comparator c2 negative input. rc2/anc2/c1in2-/c2in2-/ mdcin1 (1) rc2 ttl/st cmos general purpose i/o. anc2 an D adc channel c2 input. c1in2- an D comparator c1 negative input. c2in2- an D comparator c2 negative input. mdcin1 ttl/st D modular carrier input 1. table 1-3: pic16(l)f18346 pinout description (continued) name function input type output type description legend: an = analog input or output cmos= cmos compatible input or output od = open-drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: default peripheral input. input can be moved to any ot her pin with the pps input selection registers. see register 12-2 . 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selection registers. see register 12-2 . 3: these i 2 c functions are bidirectional. the output pin selections must be the same as the input pin selections. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 20 preliminary ? 2016 microchip technology inc. rc3/anc3/c1in3-/c2in3-/ mdmin (1) / ccp2 (1) /clcin1 (1) / rc3 ttl/st cmos general purpose i/o. anc3 an D adc channel c3 input. c1in3- an D comparator c1 negative input. c2in3- an D comparator c2 negative input. mdmin ttl/st D modular source input. ccp2 ttl/st cmos capture/compare/pwm 2 input. clcin1 ttl/st D configurable logic cell 1 input. rc4/anc4 rc4 ttl/st cmos general purpose i/o. anc4 an D adc channel c4 input. rc5/anc5/mdcin2 (1) / ccp1 (1) rc5 ttl/st cmos general purpose i/o. anc5 an D adc channel c5 input. mdcin2 ttl/st D modular carrier input 2. ccp1 ttl/st cmos capture/compare/pwm 1 input. rc6/anc6/ss1 (1) rc6 ttl/st cmos general purpose i/o. anc6 an D adc channel c6 input. ss1 ttl/st D slave select 1 input. rc7/anc7 rc7 ttl/st cmos general purpose i/o. anc7 an D adc channel c7 input. v dd v dd power D positive supply. v ss v ss power D ground reference. table 1-3: pic16(l)f18346 pinout description (continued) name function input type output type description legend: an = analog input or output cmos= cmos compatible input or output od = open-drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: default peripheral input. input can be moved to any other pin with the pps input selection registers. see register 12-2 . 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selection registers. see register 12-2 . 3: these i 2 c functions are bidirectional. the output pin selections must be the same as the input pin selections. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 21 pic16(l)f18326/18346 out (2) c1 D cmos comparator c1 output. c2 D cmos comparator c2 output. nco1 D cmos numerically controlled oscillator output. dsm D cmos digital signal modulator output. tmr0 D cmos timer0 clock output. ccp1 D cmos capture/compare/pwm 1 output. ccp2 D cmos capture/compare/pwm 2 output. ccp3 D cmos capture/compare/pwm 3 output. ccp4 D cmos capture/compare/pwm 4 output. pwm5 D cmos pulse-width modulator 5 output. pwm6 D cmos pulse-width modulator 6 output. cwg1a D cmos complementary waveform generator 1 output a. cwg2a D cmos complementary waveform generator 2 output a. cwg1b D cmos complementary waveform generator 1 output b. cwg2b D cmos complementary waveform generator 2 output b. cwg1c D cmos complementary waveform generator 1 output c. cwg2c D cmos complementary waveform generator 2 output c. cwg1d D cmos complementary waveform generator 1 output d. cwg2d D cmos complementary waveform generator 2 output d. sda1 (3) i 2 co di 2 c data output. sda2 (3) i 2 co di 2 c data output. scl1 (3) i 2 co di 2 c clock output. scl2 (3) i 2 co di 2 c clock output. sdo1 D cmos spi1 data output. sd02 D cmos spi2 data output. sck1 D cmos spi1 clock output. sck2 D cmos spi2 clock output. tx/ck D cmos asynchronous tx data/synchronous clock output. dt (3) D cmos eusart synchronous data output. clc1out D cmos configurable logic cell 1 source output. clc2out D cmos configurable logic cell 2 source output. clc3out D cmos configurable logic cell 3 source output. clc4out D cmos configurable logic cell 4 source output. clkr D cmos clock reference output. table 1-3: pic16(l)f18346 pinout description (continued) name function input type output type description legend: an = analog input or output cmos= cmos compatible input or output od = open-drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: default peripheral input. input can be moved to any ot her pin with the pps input selection registers. see register 12-2 . 2: all pin outputs default to port latch data. any pin can be selected as a digital peripheral output with the pps output selection registers. see register 12-2 . 3: these i 2 c functions are bidirectional. the output pin selections must be the same as the input pin selections. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 22 preliminary ? 2016 microchip technology inc. 2.0 enhanced mid-range cpu this family of devices contains an enhanced mid-range 8-bit cpu core. the cpu has 49 instructions. interrupt capability includes automatic context saving. the hardware stack is 16-levels deep and has overflow and underflow reset capability. direct, indirect, and relative addressing modes are available. two file select registers (fsrs) provide the ability to read program and data memory. automatic interrupt context saving 16-level stack with overflow and underflow file select registers instruction set figure 2-1: core block diagram data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 12 addr mux fsr reg status reg mux alu power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout v dd 8 8 brown-out reset 12 3 v ss internal oscillator block data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 addr mux fsr reg status reg mux alu w reg instruction decode & control timing generation v dd 8 8 3 v ss internal oscillator block 15 data bus 8 14 program bus instruction reg program counter 16-level stack (15-bit) direct addr 7 ram addr addr mux indirect addr fsr0 reg status reg mux alu instruction decode and control timing generation v dd 8 8 3 v ss internal oscillator block ram fsr reg fsr reg fsr1 reg 15 15 mux 15 program memory read (pmr) 12 fsr reg fsr reg bsr reg 5 configuration configuration configuration nonvolatile memory downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 23 pic16(l)f18326/18346 2.1 automatic interrupt context saving during interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. this saves stack space and user code. see section 7.5 ?automatic context saving? for more information. 2.2 16-level stack with overflow and underflow these devices have a hardware stack memory 15 bits wide and 16 words deep. a stack overflow or underflow will set the appropriate bit (stkovf or stkunf) in the pcon register, and if enabled, will cause a software reset. see section 3.4 ?stack? for more details. 2.3 file select registers there are two 16-bit file select registers (fsr). fsrs can access all file registers, program memory, and data eeprom, which allows one data pointer for all mem- ory. when an fsr points to program memory, there is one additional instruction cycle in instructions using indf to allow the data to be fetched. general purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. there are also new instructions to support the fsrs. see section 3.5 ?indirect addressing? for more details. 2.4 instruction set there are 49 instructions for the enhanced mid-range cpu to support the features of the cpu. see section 33.0 ?instruction set summary? for more details. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 24 preliminary ? 2016 microchip technology inc. 3.0 memory organization these devices contain the following types of memory: program memory - configuration words -device id -user id - program flash memory data memory - core registers - special function registers - general purpose ram - common ram - data eeprom the following features are associated with access and control of program memory and data memory: pcl and pclath stack indirect addressing nvmreg access 3.1 program memory organization the enhanced mid-range core has a 15-bit program counter capable of addressing 32k x 14 program memory space. table 3-1 shows the memory sizes implemented. accessing a location above these boundaries will cause a wrap-around within the implemented memory space. the reset vector is at 0000h and the interrupt vector is at 0004h (see figure 3-1 ). table 3-1: device sizes and addresses device program memory size (words) last program memory address pic16(l)f18326/18346 16384 3fffh downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 25 pic16(l)f18326/18346 figure 3-1: program memory map and stack for pic16(l)f18326/18346 3.1.1 reading program memory as data there are two methods of accessing constants in program memory. the first method is to use tables of retlw instructions. the second method is to set an fsr to point to the program memory. 3.1.1.1 retlw instruction the retlw instruction can be used to provide access to tables of constants. the recommended way to create such a table is shown in example 3-1 . example 3-1: retlw instruction the brw instruction makes this type of table very simple to implement. if your code must remain portable with previous generations of microcontrollers, the older table read method must be used because the brw instruction is not available in some devices, such as the pic16f6xx, pic16f7xx, pic16f8xx, and pic16f9xx devices. pc<14:0> 15 0000h 0004h stack level 0 stack level 15 reset vector interrupt vector stack level 1 0005h on-chip program memory page 0-3 3fffh wraps to page 0 wraps to page 0 wraps to page 0 4000h call , callw return , retlw interrupt, retfie rollover to page 0 rollover to page 0 7fffh constants brw ;add index in w to ;program counter to ;select data retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ; lots of code movlw data_index call constants ; the constant is in w downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 26 preliminary ? 2016 microchip technology inc. 3.1.1.2 indirect read with fsr the program memory can be accessed as data by setting bit 7 of the fsrxh register and reading the matching indfx register. the moviw instruction will place the lower eight bits of the addressed word in the w register. writes to the program memory cannot be performed via the indf registers. instructions that access the program memory via the fsr require one extra instruction cycle to complete. example 3-2 demonstrates accessing the program memory via an fsr. the high directive will set bit 7 if a label points to a location in the program memory. example 3-2: accessing program memory via fsr 3.2 data memory organization the data memory is partitioned into 32 memory banks with 128 bytes in each bank. each bank consists of ( figure 3-2 ): 12 core registers special function registers (sfr) up to 80 bytes of general purpose ram (gpr) 16 bytes of common ram the active bank is selected by writing the bank number into the bank select register (bsr). unimplemented memory will read as 0 . all data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two file select registers (fsr). see section 3.5 ?indirect addressing?? for more information. data memory uses a 12-bit address. the upper seven bits of the address define the bank address and the lower five bits select the registers/ram in that bank. figure 3-2: banked-memory partitioning 3.2.1 core registers the core registers contain the registers that directly affect the basic operation. the core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x80h through x0bh/x8bh). these registers are listed below in ta b l e 3 - 2 . for detailed information, see tab le 3- 4 . table 3-2: core registers constants retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ; lots of code movlw low constants movwf fsr1l movlw high constants movwf fsr1h moviw 0[fsr1] ;the program memory is in w 0bh 0ch 1fh 20h 6fh 70h 7fh 00h common ram (16 bytes) general purpose ram (80 bytes maximum) core registers (12 bytes) special function registers memory region 7-bit bank offset addresses bankx x00h or x80h indf0 x01h or x81h indf1 x02h or x82h pcl x03h or x83h status x04h or x84h fsr0l x05h or x85h fsr0h x06h or x86h fsr1l x07h or x87h fsr1h x08h or x88h bsr x09h or x89h wreg x0ah or x8ah pclath x0bh or x8bh intcon downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 27 pic16(l)f18326/18346 3.2.1.1 27 the status register, shown in register 3-1 , contains: the arithmetic status of the alu the reset status the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits (refer to section 3.0 ?memory organization? ). note 1: the c and dc bits operate as borrow and digit borrow out bits, respectively, in subtraction. register 3-1: status: status register u-0 u-0 u-0 r-1/q r-1/q r/w-0/u r/w-0/u r/w-0/u to pd zd c (1) c (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7-5 unimplemented: read as 0 bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/digit borrow bit ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (1) ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the twos complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 28 preliminary ? 2016 microchip technology inc. 3.2.2 special function register the special function registers are registers used by the application to control the desired operation of peripheral functions in the device. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh), with the exception of banks 27, 28, and 29 (pps and clc registers). the registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.3 general purpose ram there are up to 80 bytes of gpr in each data memory bank. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh), with the exception of banks 27, 28, and 29 (pps and clc registers). 3.2.3.1 linear access to gpr the general purpose ram can be accessed in a non-banked method via the fsrs. this can simplify access to large memory structures. see section 3.5.2 ?linear data memory? for more information. 3.2.4 common ram there are 16 bytes of common ram accessible from all banks. 3.2.5 device memory maps the memory maps for pic16(l)f18326/18346 are as shown in tab l e 3 - 4 . table 3-3: special function register summary banks 0-31 (all banks) (1) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets all banks 000h indf0 addressing this location uses contents of fsr0h/fsr0l to address data memo ry (not a physical register) xxxx xxxx xxxx xxxx 001h indf1 addressing this location uses contents of fsr1h/fsr1l to address data memo ry (not a physical register) xxxx xxxx xxxx xxxx 002h pcl program counter (pc) least significant byte 0000 0000 0000 0000 003h status t o pd zd cc ---1 1000 ---q quuu 004h fsr0l indirect data memory address 0 low pointer 0000 0000 uuuu uuuu 005h fsr0h indirect data memory address 0 high pointer 0000 0000 0000 0000 006h fsr1l indirect data memory address 1 low pointer 0000 0000 uuuu uuuu 007h fsr1h indirect data memory address 1 high pointer 0000 0000 0000 0000 008h bsr bsr4 bsr3 bsr2 bsr1 bsr0 ---0 0000 ---0 0000 009h wreg working register 0000 0000 uuuu uuuu 00ah pclath write buffer for the upper 7 bits of the program counter -000 0000 -000 0000 00bh intcon gie peie i n t e d g 00-- ---1 00-- ---1 legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: these registers can be accessed from any bank. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 29 pic16(l)f18326/18346 table 3-4: special function register summary banks 0-31 address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets bank 0 cpu core registers; see ta b l e 3 - 2 for specifics 00ch porta ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu 00dh portb x unimplemented x rb7 rb6 rb5 rb4 xxxx ---- uuuu ---- 00eh portc x rc5 rc4 rc3 rc2 rc1 rc0 --xx xxxx --uu uuuu x rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 00fh unimplemented 010h pir0 t m r 0 i fi o c i f i n t f --00 ---0 --00 ---0 011h pir1 tmr1gif adif rcif txif ssp1if bcl1if tmr2if tmr1if 0000 0000 0000 0000 012h pir2 tmr6if c2if c1if nvmif ssp2if bcl2if tmr4if nco1if 0000 0000 0000 0000 013h pir3 osfif cswif tmr3gif tmr3if clc4if clc3if clc2if clc1if 0000 0000 0000 0000 014h pir4 cwg2if cwg1if tmr5gif tmr5if ccp4if ccp3if ccp2if ccp1if 0000 0000 0000 0000 015h tmr0l tmr0l<7:0> xxxx xxxx xxxx xxxx 016h tmr0h tmr0h<7:0> 1111 1111 1111 1111 017h t0con0 t0en t0out t016bit t0outps<3:0> 0-00 0000 0-00 0000 018h t0con1 t0cs<2:0> t0async t0ckps<3:0> 0000 0000 0000 0000 019h tmr1l tmr1l<7:0> xxxx xxxx uuuu uuuu 01ah tmr1h tmr1h<7:0> xxxx xxxx uuuu uuuu 01bh t1con tmr1cs<1:0> t1ckps<1:0> t1sosc t1sync t m r 1 o n 0000 00-0 uuuu uu-u 01ch t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> 0000 0x00 uuuu uxuu 01dh tmr2 tmr2<7:0> 0000 0000 0000 0000 01eh pr2 pr2<7:0> 1111 1111 1111 1111 01fh t2con t2outps<3:0> tmr2on t2ckps<1:0> -000 0000 -000 0000 legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 30 preliminary ? 2016 microchip technology inc. bank 1 cpu core registers; see table 3-2 for specifics 08ch trisa trisa5 trisa4 trisa2 trisa1 trisa0 --11 -111 --11 -111 08dh trisb x unimplemented x trisb7 trisb6 trisb5 trisb4 1111 ---- 1111 ---- 08eh trisc x trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 --11 1111 --11 1111 x trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 08fh unimplemented 090h pie0 D tmr0ie iocie i n t e --00 ---0 --00 ---0 091h pie1 tmr1gie adie rcie txie ssp1ie bcl1ie tmr2ie tmr1ie 0000 0000 0000 0000 092h pie2 tmr6ie c2ie c1ie nvmie ssp2ie bcl2ie tmr4ie nco1ie 0000 0000 0000 0000 093h pie3 osfie cswie tmr3gie tmr 3ie clc4ie clc3ie clc2ie clc1ie 0000 0000 0000 0000 094h pie4 cwg2ie cwg1ie tmr5gie tmr5ie ccp4ie ccp3ie ccp2ie ccp1ie 0000 0000 0000 0000 095h unimplemented 096h unimplemented 097h wdtcon wdtps<4:0> swdten --01 0110 --01 0110 098h unimplemented 099h unimplemented 09ah unimplemented 09bh adresl adres<7:0> xxxx xxxx uuuu uuuu 09ch adresh adres<9:8> xxxx xxxx uuuu uuuu 09dh adcon0 chs<5:0> go/done adon 0000 0000 0000 0000 09eh adcon1 adfm adcs<2:0> adnref adpref<1:0> 0000 -000 0000 -000 09fh adact adact<3:0> ---0 0000 ---0 0000 table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 31 pic16(l)f18326/18346 bank 2 cpu core registers; see table 3-2 for specifics 10ch lata l a t a 5l a t a 4 lata2 lata1 lata0 --xx -xxx --uu -uuu 10dh latb x unimplemented x latb7 latb6 latb5 latb4 xxxx ---- uuuu ---- 10eh latc x latc5 latc4 latc3 latc2 latc1 latc0 --xx xxxx --uu uuuu x latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 xxxx xxxx uuuu uuuu 10fh unimplemented 110h unimplemented 111h cm1con0 c1on c1out c 1 p o l c1sp c1hys c1sync 00-0 -100 00-0 -100 112h cm1con1 c1intp c1intn c1pch<2:0> c1nch<2:0> 0000 0000 0000 0000 113h cm2con0 c2on c2out c 2 p o l c2sp c2hys c2sync 00-0 -100 00-0 -100 114h cm2con1 c2intp c2intn c2pch<2:0> c2nch<2:0> 0000 0000 0000 0000 115h cmout mc2out mc1out ---- --00 ---- --00 116h borcon sboren borrdy 1--- ---q u--- ---u 117h fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 0q00 0000 0q00 0000 118h daccon0 dac1en d a c 1 o e dac1pss<1:0> d a c 1 n s s 0-0- 00-0 0-0- 00-0 119h daccon1 d a c 1 r < 4 : 0 > ---0 0000 ---0 0000 11ah to 11fh unimplemented table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 32 preliminary ? 2016 microchip technology inc. bank 3 cpu core registers; see table 3-2 for specifics 18ch ansela D D ansa5 ansa4 D ansa2 ansa1 ansa0 --xx -xxx --uu -uuu 18dh anselb x D unimplemented D x ansb7 ansb6 ansb5 ansb4 D D D D xxxx ---- uuuu ---- 18eh anselc x D D ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 --xx xxxx --uu uuuu D x ansc7 ansc6 ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 xxxx xxxx uuuu uuuu 18fh D D unimplemented 190h D D unimplemented 191h D D unimplemented 192h D D unimplemented 193h D D unimplemented 194h D D unimplemented 195h D D unimplemented 196h D D unimplemented 197h vregcon (1) D D D D D D vregpm reserved ---- --01 ---- --01 198h D D unimplemented 199h rc1reg rc1reg<7:0> 0000 0000 0000 0000 19ah tx1reg tx1reg<7:0> 0000 0000 0000 0000 19bh sp1brgl sp1brg<7:0> 0000 0000 0000 0000 19ch sp1brgh sp1brg<15:8> 0000 0000 0000 0000 19dh rc1sta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19eh tx1sta csrc tx9 txen sync sendb brgh tmrt tx9d 0000 0010 0000 0010 19fh baud1con abdovf rcidl sckp brg16 wue abden 01-0 0-00 01-0 0-00 table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 33 pic16(l)f18326/18346 bank 4 cpu core registers; see table 3-2 for specifics 20ch wpua D D wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 --00 0000 --00 0000 20dh wpub x D unimplemented D D D x wpub7 wpub6 wpub5 wpub4 D D D D 0000 ---- 0000 ---- 20eh wpuc x D D D wpuc5 wpuc4 wpuc3 wpuc2 wpuc1 wpuc0 --00 0000 --00 0000 D x wpuc7 wpuc6 wpuc5 wpuc4 wpuc3 wpuc2 wpuc1 wpuc0 0000 0000 0000 0000 20fh D D unimplemented D D 210h D D unimplemented D D 211h ssp1buf ssp1buf<7:0> xxxx xxxx uuuu uuuu 212h ssp1add ssp1add<7:0> 0000 0000 0000 0000 213h ssp1msk ssp1msk<7:0> 1111 1111 1111 1111 214h ssp1stat smp cke d/a ps r / w ua bf 0000 0000 0000 0000 215h ssp1con1 wcol sspov sspen ckp sspm<3:0> 0000 0000 0000 0000 216h ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 217h ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 0000 0000 0000 0000 218h D D unimplemented D D 219h ssp2buf ssp2buf<7:0> xxxx xxxx uuuu uuuu 21ah ssp2add ssp2add<7:0> 0000 0000 0000 0000 21bh ssp2msk ssp2msk<7:0> 1111 1111 1111 1111 21ch ssp2stat smp cke d/a ps r / w ua bf 0000 0000 0000 0000 21dh ssp2con1 wcol sspov sspen ckp sspm<3:0> 0000 0000 0000 0000 21eh ssp2con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 21fh ssp2con3 acktim pcie scie boen sdaht sbcde ahen dhen 0000 0000 0000 0000 table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 34 preliminary ? 2016 microchip technology inc. bank 5 cpu core registers; see table 3-2 for specifics 28ch odcona D D odca5 odca4 D odca2 odca1 odca0 --00 -000 --00 -000 28dh odconb x D unimplemented D D D x odcb7 odcb6 odcb5 odcb4 D D D D 0000 ---- 0000 ---- 28eh odconc x D D D odcc5 odcc4 odcc3 odcc2 odcc1 odcc0 --00 0000 --00 0000 D x odcc7 odcc6 odcc5 odcc4 odcc3 odcc2 odcc1 odcc0 0000 0000 0000 0000 28fh D unimplemented D D 290h D D unimplemented D D 291h ccpr1l ccpr1<7:0> xxxx xxxx xxxx xxxx 292h ccpr1h ccpr1<15:8> xxxx xxxx xxxx xxxx 293h ccp1con ccp1en D ccp1out ccp1fmt ccp1mode<3:0> 0-x0 0000 0-x0 0000 294h ccp1cap D D D ccp1cts<3:0> ---- 0000 ---- xxxx 295h ccpr2l ccpr2<7:0> xxxx xxxx xxxx xxxx 296h ccpr2h ccpr2<15:8> xxxx xxxx xxxx xxxx 297h ccp2con ccp2en D ccp2out ccp2fmt ccp2mode<3:0> 0-x0 0000 0-x0 0000 298h ccp2cap D D D D ccp2cts<3:0> ---- 0000 ---- xxxx 299h D D unimplemented D D 29ah D D unimplemented D D 29bh D D unimplemented D D 29ch D D unimplemented D D 29dh D D unimplemented D D 29eh D D unimplemented D D 29fh ccptmrs c4tsel<1:0> c3tsel<1:0> c2tsel<1:0> c1tsel<1:0> 0101 0101 0101 0101 table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 35 pic16(l)f18326/18346 bank 6 cpu core registers; see table 3-2 for specifics 30ch slrcona D D slra5 slra4 D slra2 slra1 slra0 --11 -111 --11 -111 30dh slrconb x D unimplemented D D D x slrb7 slrb6 slrb5 slrb4 D D D D 1111 ---- 1111 ---- 30eh slrconc x D D D slrc5 slrc4 slrc3 slrc2 slrc1 slrc0 --11 1111 --11 1111 D x slrc7 slrc6 slrc5 slrc4 slrc3 slrc2 slrc1 slrc0 1111 1111 1111 1111 30fh D D unimplemented D D 310h D D unimplemented D D 311h ccpr3l ccpr3<7:0> xxxx xxxx xxxx xxxx 312h ccpr3h ccpr3<15:8> xxxx xxxx xxxx xxxx 313h ccp3con ccp3en D ccp3out ccp3fmt ccp3mode<3:0> 0-x0 0000 0-x0 0000 314h ccp3cap D D D D ccp3cts<3:0> ---- 0000 ---- xxxx 315h ccpr4l ccpr4<7:0> xxxx xxxx xxxx xxxx 316h ccpr4h ccpr4<15:8> xxxx xxxx xxxx xxxx 317h ccp4con ccp4en D ccp4out ccp4fmt ccp4mode<3:0> 0-x0 0000 0-x0 0000 318h ccp4cap D D D D ccp4cts<3:0> ---- 0000 ---- xxxx 319h to 31fh D D unimplemented D D table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 36 preliminary ? 2016 microchip technology inc. bank 7 cpu core registers; see table 3-2 for specifics 38ch inlvla D D inlvla5 inlvla4 inlvla3 inlvla2 inlvla1 inlvla0 --11 1111 --11 1111 38dh inlvlb x D unimplemented D D D x inlvlb7 inlvlb6 inlvlb5 inlvlb4 D D D D 1111 ---- 1111 ---- 38eh inlvlc x D D D inlvlc5 inlvlc4 inlvlc3 inlvlc2 inlvlc1 inlvlc0 --11 1111 --11 1111 D x inlvlc7 inlvlc6 inlvlc5 inlvlc4 inlvlc3 inlvlc2 inlvlc1 inlvlc0 1111 1111 1111 1111 38fh D D unimplemented D D 390h D D unimplemented D D 391h iocap D D iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 --00 0000 --00 0000 392h iocan D D iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 --00 0000 --00 0000 393h iocaf D D iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 --00 0000 --00 0000 394h iocbp x D unimplemented D D D x iocbp7 iocbp6 iocbp5 iocbp4 D D D D 0000 ---- 0000 ---- 395h iocbn x D unimplemented D D D x iocbn7 iocbn6 iocbn5 iocbn4 D D D D 0000 ---- 0000 ---- 396h iocbf x D unimplemented D D D x iocbf7 iocbf6 iocbf5 iocbf4 D D D D 0000 ---- 0000 ---- 397h ioccp x D D D ioccp5 ioccp4 ioccp3 ioccp2 ioccp1 ioccp0 --00 0000 --00 0000 D x ioccp7 ioccp6 ioccp5 ioccp4 ioccp3 ioccp2 ioccp1 ioccp0 0000 0000 0000 0000 398h ioccn x D D D ioccn5 ioccn4 ioccn3 ioccn2 ioccn1 ioccn0 --00 0000 --00 0000 D x ioccn7 ioccn6 ioccn5 ioccn4 ioccn3 ioccn2 ioccn1 ioccn0 0000 0000 0000 0000 399h ioccf x D D D ioccf5 ioccf4 ioccf3 ioccf2 ioccf1 ioccf0 --00 0000 --00 0000 D x ioccf7 ioccf6 ioccf5 ioccf4 ioccf3 ioccf2 ioccf1 ioccf0 0000 0000 0000 0000 table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 37 pic16(l)f18326/18346 bank 7 cpu core registers; see table 3-2 for specifics 39ah clkrcon clkren D D clkrdc<1:0> clkrdiv<2:0> 0--1 0000 0--1 0001 39bh D D unimplemented D D 39ch mdcon mden D D mdopol mdout D D mdbit 0--0 0--0 0--0 0--0 39dh mdsrc D D D D mdms<3:0> ---- xxxx 0--- uuuu 39eh mdcarh D mdchpol mdchsync D mdch<3:0> -xx- xxxx -uu- uuuu 39fh mdcarl D mdclpol mdclsync D mdcl<3:0> -xx- xxxx -uu- uuuu table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 38 preliminary ? 2016 microchip technology inc. bank 8 cpu core registers; see table 3-2 for specifics 40ch to 410h D D unimplemented D D 411h tmr3l tmr3l<7:0> xxxx xxxx uuuu uuuu 412h tmr3h tmr3h<7:0> xxxx xxxx uuuu uuuu 413h t3con tmr3cs<1:0> t3ckps<1:0> t3sosc t3sync D tmr3on 0000 00-0 uuuu uu-u 414h t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/ done t3gval t3gss<1:0> 0000 0x00 uuuu uxuu 415h tmr4 tmr4<7:0> 0000 0000 0000 0000 416h pr4 pr4<7:0> 1111 1111 1111 1111 417h t4con D t4outps<3:0> tmr4on t4ckps<1:0> -000 0000 -000 0000 418h tmr5l tmr5l<7:0> xxxx xxxx uuuu uuuu 419h tmr5h tmr5h<7:0> xxxx xxxx uuuu uuuu 41ah t5con tmr5cs<1:0> t5ckps<1:0> t5sosc t5sync D tmr5on 0000 00-0 uuuu uu-u 41bh t5gcon tmr5ge t5gpol t5gtm t5gspm t5ggo/ done t5gval t5gss<1:0> 0000 0x00 uuuu uxuu 41ch tmr6 tmr6<7:0> 0000 0000 0000 0000 41dh pr6 pr6<7:0> 1111 1111 1111 1111 41eh t6con D t6outps<3:0> tmr6on t6ckps<1:0> -000 0000 -000 0000 41fh D D unimplemented D D table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 39 pic16(l)f18326/18346 bank 9 cpu core registers; see table 3-2 for specifics 48ch to 497h D D unimplemented D D 498h nco1accl nco1acc<7:0> 0000 0000 0000 0000 499h nco1acch nco1acc<15:8> 0000 0000 0000 0000 49ah nco1accu D D D nco1acc<19:16> ---- 0000 ---- 0000 49bh nco1incl nco1inc<7:0> 0000 0001 0000 0001 49ch nco1inch nco1inc<15:8> 0000 0000 0000 0000 49dh nco1incu D D D D nco1inc<19:16> ---- 0000 ---- 0000 49eh nco1con n1en D n1out n1pol D D D n1pfm 0-00 ---0 0-00 ---0 49fh nco1clk n1pws<2:0> D D D n1cks<1:0> 000- --00 000- --00 table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 40 preliminary ? 2016 microchip technology inc. bank 10-11 cpu core registers; see table 3-2 for specifics 50ch to 51fh D D unimplemented D D 58ch to 59fh D D unimplemented D D bank 12 60ch D D unimplemented D D 60dh D D unimplemented D D 60eh D D unimplemented D D 60fh D D unimplemented D D 610h D D unimplemented D D 611h D D unimplemented D D 612h D D unimplemented D D 613h D D unimplemented D D 614h D D unimplemented D D 615h D D unimplemented D D 616h D D unimplemented D D 617h pwm5dcl pwm5dc<1:0> D D D D D D xx-- ---- uu-- ---- 618h pwm5dch pwm5dc<9:2> xxxx xxxx uuuu uuuu 619h pwm5con pwm5en D pwm5out pwm5pol D D D D 0-00 ---- 0-00 ---- 61ah pwm6dcl pwm6dc<1:0> D D D D D D xx-- ---- uu-- ---- 61bh pwm6dch pwm6dc<9:2> xxxx xxxx uuuu uuuu 61ch pwm6con pwm6en D pwm6out pwm6pol D D D D 0-00 ---- 0-00 ---- 61dh to 61eh D D unimplemented D D 61fh pwmtmrs D D D D p6tsel<1:0> p5tsel<1:0> ---- 0101 ---- 0101 table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 41 pic16(l)f18326/18346 bank 13 cpu core registers; see table 3-2 for specifics 68ch D D unimplemented D D 68dh D D unimplemented D D 68eh D D unimplemented D D 68fh D D unimplemented D D 690h D D unimplemented D D 691h cwg1clkcon D D D D D D D cs ---- ---0 ---- ---0 692h cwg1dat D D D D dat<3:0> ---- 0000 ---- 0000 693h cwg1dbr D D dbr<5:0> --00 0000 --00 0000 694h cwg1dbf D D dbf<5:0> --00 0000 --00 0000 695h cwg1con0 en ld D D D mode<2:0> 00-- -000 00-- -000 696h cwg1con1 D D in D pold polc polb pola --x- 0000 --x- 0000 697h cwg1as0 shutdown ren lsbd<1:0> lsac<1:0> D D 0001 01-- 0001 01-- 698h cwg1as1 D D D as4e as3e as2e as1e as0e ---0 0000 ---0 0000 699h cwg1str ovrd ovrc ovrb ovra strd strc strb stra 0000 0000 0000 0000 69ah to 69fh D D unimplemented D D table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 42 preliminary ? 2016 microchip technology inc. bank 14 cpu core registers; see table 3-2 for specifics 70ch D D unimplemented D D 70dh D D unimplemented D D 70eh D D unimplemented D D 70fh D D unimplemented D D 710h D D unimplemented D D 711h cwg2clkcon D D D D D D D cs ---- ---0 ---- ---0 712h cwg2dat D D D D dat<3:0> ---- 0000 ---- 0000 713h cwg2dbr D D dbr<5:0> --00 0000 --00 0000 714h cwg2dbf D D dbf<5:0> --00 0000 --00 0000 715h cwg2con0 en ld D D D mode<2:0> 00-- -000 00-- -000 716h cwg2con1 D D in D pold polc polb pola --x- 0000 --x- 0000 717h cwg2as0 shutdown ren lsbd<1:0> lsac<1:0> D D 0001 01-- 0001 01-- 718h cwg2as1 D D D as4e as3e as2e as1e as0e ---0 0000 ---0 0000 719h cwg2str ovrd ovrc ovrb ovra strd strc strb stra 0000 0000 0000 0000 71ah to 71fh D D unimplemented D D table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 43 pic16(l)f18326/18346 banks 15-16 cpu core registers; see table 3-2 for specifics 78ch to 79fh D D unimplemented D D 80ch to 81fh D D unimplemented D D bank 17 88ch D D unimplemented D D 88dh D D unimplemented D D 88eh D D unimplemented D D 88fh D D unimplemented D D 890h D D unimplemented D D 891h nvmadrl nvmadr<7:0> 0000 0000 0000 0000 892h nvmadrh D nvmadr<14:8> 1000 0000 1000 0000 893h nvmdatl nvmdat<7:0> 0000 0000 0000 0000 894h nvmdath D D nvmdat<13:8> --00 0000 --00 0000 895h nvmcon1 D nvmregs lwlo free wrerr wren wr rd -000 x000 -000 q000 896h nvmcon2 nvmcon2 0000 0000 0000 0000 897h D D unimplemented D D 898h D D unimplemented D D 899h D D unimplemented D D 89ah D D unimplemented D D 89bh pcon0 stkovf stkunf D rwdt rmclr ri por bor 00-1 110q qq-q qquu 89ch to 89fh D D unimplemented D D table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 44 preliminary ? 2016 microchip technology inc. bank 18 cpu core registers; see table 3-2 for specifics 90ch D D unimplemented D D 90dh D D unimplemented D D 90eh D D unimplemented D D 90fh D D unimplemented D D 910h D D unimplemented D D 911h pmd0 syscmd fvrmd D D D nvmmd clkrmd iocmd 00-- -000 00-- -000 912h pmd1 ncomd tmr6md tmr5md tmr4md tmr3md tmr2md tmr1md tmr0md 0--- -000 0--- -000 913h pmd2 D dacmd adcmd D D cmp2md cmp1md D -00- --0- -00- --0- 914h pmd3 cwg2md cwg1md pwm6md pwm5md ccp4md ccp3md ccp2md ccp1md -000 --00 -000 --00 915h pmd4 D D uart1md D D mssp2md mssp1md D --0- --0- --0- --0- 916h pmd5 D D D clc4md clc3md clc2md clc1md dsmmd ---- -000 ---- -000 917h D D unimplemented D D 918h cpudoze idlen dozen roi doe D doze<2:0> 000- -000 000- -000 919h osccon1 D nosc<2:0> ndiv<3:0> -qqq 0000 -qqq 0000 91ah osccon2 D cosc<2:0> cdiv<3:0> -qqq 0000 -qqq 0000 91bh osccon3 cswhold soscpwr soscbe ordy noscr D D D 0000 0--- 0000 0--- 91ch oscstat1 extor hfor D lfor sor ador D pllr qq-q qq-q qq-q qq-q 91dh oscen extoen hfoen D lfoen soscen adoen D D 00-0 00-- 00-0 00-- 91eh osctune D D hftun<5:0> --10 0000 --10 0000 91fh oscfrq D D D D hffrq<3:0> ---- -qqq ---- -qqq table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 45 pic16(l)f18326/18346 banks 19-27 cpu core registers; see table 3-2 for specifics 98ch to 9efh unimplemented a0ch to a6fh unimplemented a8ch to aefh unimplemented b0ch to b6fh unimplemented b8ch to befh unimplemented c0ch to c6fh unimplemented c8ch to cefh unimplemented d0ch to d6fh unimplemented d8ch to defh unimplemented table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 46 preliminary ? 2016 microchip technology inc. bank 28 cpu core registers; see table 3-2 for specifics e0ch D D unimplemented D D e0dh D D unimplemented D D e0eh D D unimplemented D D e0fh ppslock D D D D D D D ppslocked ---- ---0 ---- ---0 e10h intpps D D D intpps<4:0> ---0 0010 ---u uuuu e11h t0ckipps D D D t0ckipps<4:0> ---0 0010 ---u uuuu e12h t1ckipps D D D t1ckipps<4:0> ---0 0101 ---u uuuu e13h t1gpps D D D t1gpps<4:0> ---0 0100 ---u uuuu e14h ccp1pps D D D ccp1pps<4:0> ---1 0011 ---u uuuu e15h ccp2pps D D D ccp2pps<4:0> ---1 0101 ---u uuuu e16h ccp3pps D D D ccp3pps<4:0> ---0 0010 ---u uuuu e17h ccp4pps x D D D D ccp4pps<4:0> ---1 0001 ---u uuuu D x D D D ccp4pps<4:0> ---0 0100 ---u uuuu e18h cwg1pps D D D cwg1pps<4:0> ---0 0010 ---u uuuu e19h cwg2pps D D D cwg2pps<4:0> ---0 0010 ---u uuuu e1ah mdcin1pps D D D mdcin1pps<4:0> ---1 0010 ---u uuuu e1bh mdcin2pps D D D mdcin2pps<4:0> ---1 0101 ---u uuuu e1ch mdminpps D D D mdminpps<4:0> ---1 0011 ---u uuuu e1dh ssp2clkpps x D D D D ssp2clkpps<4:0> ---1 0100 ---u uuuu D x D D D ssp2clkpps<4:0> ---0 1111 ---u uuuu e1eh ssp2datpps x D D D D ssp2datpps<4:0> ---1 0101 ---u uuuu D x D D D ssp2datpps<4:0> ---0 1101 ---u uuuu e1fh ssp2sspps x D D D D ssp2sspps<4:0> ---0 0000 ---u uuuu D x D D D ssp2sspps<4:0> ---0 0001 ---u uuuu e20h ssp1clkpps x D D D D ssp1clkpps<4:0> ---1 0000 ---u uuuu D x D D D ssp1clkpps<4:0> ---0 1110 ---u uuuu table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 47 pic16(l)f18326/18346 bank 28 cpu core registers; see table 3-2 for specifics e21h ssp1datpps x D D D D ssp1datpps<4:0> ---1 0001 ---u uuuu D x D D D ssp1datpps<4:0> ---0 1100 ---u uuuu e22h ssp1sspps x D D D D ssp1sspps<4:0> ---1 0011 ---u uuuu D x D D D ssp1sspps<4:0> ---1 0100 ---u uuuu e23h D D unimplemented D D e24h rxpps x D D D D rxpps<4:0> ---1 0101 ---u uuuu D x D D D rxpps<4:0> ---0 1101 ---u uuuu e25h txpps x D D D D txpps<4:0> ---1 0100 ---u uuuu D x D D D txpps<4:0> ---0 1111 ---u uuuu e26h D D unimplemented D D e27h D D unimplemented D D e28h clcin0pps x D D D D clcin0pps<4:0> ---1 0011 ---u uuuu D x D D D clcin0pps<4:0> ---0 0010 ---u uuuu e29h clcin1pps x D D D D clcin1pps<4:0> ---0 0100 ---u uuuu D x D D D clcin1pps<4:0> ---1 0011 ---u uuuu e2ah clcin2pps x D D D D clcin2pps<4:0> ---1 0001 ---u uuuu D x D D D clcin2pps<4:0> ---0 1100 ---u uuuu e2bh clcin3pps x D D D D clcin3pps<4:0> ---0 0101 ---u uuuu D x D D D clcin3pps<4:0> ---0 1101 ---u uuuu e2ch t3ckipps x D D D D t3ckipps<4:0> ---1 0001 ---u uuuu D x D D D t3ckipps<4:0> ---0 0101 ---u uuuu e2dh t3gpps x D D D D t3gpps<4:0> ---1 0001 ---u uuuu D x D D D t3gpps<4:0> ---1 0100 ---u uuuu e2eh t5ckipps x D D D D t5ckipps<4:0> ---1 0001 ---u uuuu D x D D D t5ckipps<4:0> ---0 0101 ---u uuuu e2fh t5gpps x D D D D t5gpps<4:0> ---1 0001 ---u uuuu D x D D D t5gpps<4:0> ---1 0100 ---u uuuu table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 48 preliminary ? 2016 microchip technology inc. bank 29 cpu core registers; see table 3-2 for specifics e8dh D D unimplemented D D e8eh D D unimplemented D D e8fh D D unimplemented D D e90h ra0pps D D D ra0pps<4:0> ---0 0000 ---u uuuu e91h ra1pps D D D ra1pps<4:0> ---0 0000 ---u uuuu e92h ra2pps D D D ra2pps<4:0> ---0 0000 ---u uuuu e93h D D unimplemented D D e94h ra4pps D D D ra4pps<4:0> ---0 0000 ---u uuuu e95h ra5pps D D D ra5pps<4:0> ---0 0000 ---u uuuu e96h D D unimplemented D D e97h D D unimplemented D D e98h D D unimplemented D D e99h D D unimplemented D D e9ah D D unimplemented D D e9bh D D unimplemented D D e9ch rb4pps x D unimplemented D D D x D D D rb4pps<4:0> ---0 0000 ---u uuuu e9dh rb5pps x D unimplemented D D D x D D D rb5pps<4:0> ---0 0000 ---u uuuu e9eh rb6pps x D unimplemented D D D x D D D rb6pps<4:0> ---0 0000 ---u uuuu e9fh rb7pps x D unimplemented D D D x D D D rb7pps<4:0> ---0 0000 ---u uuuu table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 49 pic16(l)f18326/18346 bank 29 cpu core registers; see table 3-2 for specifics ea0h rc0pps D D D rc0pps<4:0> ---0 0000 ---u uuuu ea1h rc1pps D D D rc1pps<4:0> ---0 0000 ---u uuuu ea2h rc2pps D D D rc2pps<4:0> ---0 0000 ---u uuuu ea3h rc3pps D D D rc3pps<4:0> ---0 0000 ---u uuuu ea4h rc4pps D D D rc4pps<4:0> ---0 0000 ---u uuuu ea5h rc5pps D D D rc5pps<4:0> ---0 0000 ---u uuuu ea6h rc6pps x D unimplemented D D D x D D D rc6pps<4:0> ---0 0000 ---u uuuu ea7h rc7pps x D unimplemented D D D x D D D rc7pps<4:0> ---0 0000 ---u uuuu table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 50 preliminary ? 2016 microchip technology inc. bank 30 cpu core registers; see table 3-2 for specifics f0ch D D unimplemented D D f0dh D D unimplemented D D f0eh D D unimplemented D D f0fh clcdata D D D D mlc4out mlc3out mlc2out mlc1out ---- 0000 ---- 0000 f10h clc1con lc1en D lc1out lc1intp lc1intn lc1mode<2:0> 0-00 0000 0-00 0000 f11h clc1pol lc1pol D D D lc1g4pol lc1g3pol lc1g2pol lc1g1pol 0--- xxxx 0--- uuuu f12h clc1sel0 D D lc1d1s<5:0> --xx xxxx --uu uuuu f13h clc1sel1 D D lc1d2s<5:0> --xx xxxx --uu uuuu f14h clc1sel2 D D lc1d3s<5:0> --xx xxxx --uu uuuu f15h clc1sel3 D D lc1d4s<5:0> --xx xxxx --uu uuuu f16h clc1gls0 lc1g1d4t lc1g1d4n lc1g1d3t lc1g1d3n lc1g1d2t lc1g1d2n lc1g1d1t lc 1g1d1n xxxx xxxx uuuu uuuu f17h clc1gls1 lc1g2d4t lc1g2d4n lc1g2d3t lc1g2d3n lc1g2d2t lc1g2d2n lc1g2d1t lc 1g2d1n xxxx xxxx uuuu uuuu f18h clc1gls2 lc1g3d4t lc1g3d4n lc1g3d3t lc1g3d3n lc1g3d2t lc1g3d2n lc1g3d1t lc 1g3d1n xxxx xxxx uuuu uuuu f19h clc1gls3 lc1g4d4t lc1g4d4n lc1g4d3t lc1g4d3n lc1g4d2t lc1g4d2n lc1g4d1t lc 1g4d1n xxxx xxxx uuuu uuuu f1ah clc2con lc2en D lc2out lc2intp lc2intn lc2mode<2:0> 0-00 0000 0-00 0000 f1bh clc2pol lc2pol D D D lc2g4pol lc2g3pol lc2g2pol lc2g1pol 0--- xxxx 0--- uuuu f1ch clc2sel0 D D lc2d1s<5:0> --xx xxxx --uu uuuu f1dh clc2sel1 D D lc2d2s<5:0> --xx xxxx --uu uuuu f1eh clc2sel2 D D lc2d3s<5:0> --xx xxxx --uu uuuu f1fh clc2sel3 D D lc2d4s<5:0> --xx xxxx --uu uuuu table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 51 pic16(l)f18326/18346 bank 30 cpu core registers; see table 3-2 for specifics f20h clc2gls0 lc2g1d4t lc2g1d4n lc2g1d3t lc2g1d3n lc2g1d2t lc2g1d2n lc2g1d1t lc 2g1d1n xxxx xxxx uuuu uuuu f21h clc2gls1 lc2g2d4t lc2g2d4n lc2g2d3t lc2g2d3n lc2g2d2t lc2g2d2n lc2g2d1t lc 2g2d1n xxxx xxxx uuuu uuuu f22h clc2gls2 lc2g3d4t lc2g3d4n lc2g3d3t lc2g3d3n lc2g3d2t lc2g3d2n lc2g3d1t lc 2g3d1n xxxx xxxx uuuu uuuu f23h clc2gls3 lc2g4d4t lc2g4d4n lc2g4d3t lc2g4d3n lc2g4d2t lc2g4d2n lc2g4d1t lc 2g4d1n xxxx xxxx uuuu uuuu f24h clc3con lc3en D lc3out lc3intp lc3intn lc3mode<2:0> 0-00 0000 0-00 0000 f25h clc3pol lc3pol D D D lc3g4pol lc3g3pol lc3g2pol lc3g1pol 0--- xxxx 0--- uuuu f26h clc3sel0 D D lc3d1s<5:0> --xx xxxx --uu uuuu f27h clc3sel1 D D lc3d2s<5:0> --xx xxxx --uu uuuu f28h clc3sel2 D D lc3d3s<5:0> --xx xxxx --uu uuuu f29h clc3sel3 D D lc3d4s<5:0> --xx xxxx --uu uuuu f2ah clc3gls0 lc3g1d4t lc3g1d4n lc3g1d3t lc3g1d3n lc3g1d2t lc3g1d2n lc3g1d1t lc 3g1d1n xxxx xxxx uuuu uuuu f2bh clc3gls1 lc3g2d4t lc3g2d4n lc3g2d3t lc3g2d3n lc3g2d2t lc3g2d2n lc3g2d1t lc 3g2d1n xxxx xxxx uuuu uuuu f2ch clc3gls2 lc3g3d4t lc3g3d4n lc3g3d3t lc3g3d3n lc3g3d2t lc3g3d2n lc3g3d1t lc3g3d1n xxxx xxxx uuuu uuuu f2dh clc3gls3 lc3g4d4t lc3g4d4n lc3g4d3t lc3g4d3n lc3g4d2t lc3g4d2n lc3g4d1t lc3g4d1n xxxx xxxx uuuu uuuu f2eh clc4con lc4en D lc4out lc4intp lc4intn lc4mode<2:0> 0-00 0000 0-00 0000 f2fh clc4pol lc4pol D D D lc4g4pol lc4g3pol lc4g2pol lc4g1pol 0--- xxxx 0--- uuuu f30h clc4sel0 D D lc4d1s<5:0> --xx xxxx --uu uuuu f31h clc4sel1 D D lc4d2s<5:0> --xx xxxx --uu uuuu f32h clc4sel2 D D lc4d3s<5:0> --xx xxxx --uu uuuu f33h clc4sel3 D D lc4d4s<5:0> --xx xxxx --uu uuuu f34h clc4gls0 lc4g1d4t lc4g1d4n lc4g1d3t lc4g1d3n lc4g1d2t lc4g1d2n lc4g1d1t lc 4g1d1n xxxx xxxx uuuu uuuu f35h clc4gls1 lc4g2d4t lc4g2d4n lc4g2d3t lc4g2d3n lc4g2d2t lc4g2d2n lc4g2d1t lc 4g2d1n xxxx xxxx uuuu uuuu f36h clc4gls2 lc4g3d4t lc4g3d4n lc4g3d3t lc4g3d3n lc4g3d2t lc4g3d2n lc4g3d1t lc 4g3d1n xxxx xxxx uuuu uuuu f37h clc4gls3 lc4g4d4t lc4g4d4n lc4g4d3t lc4g4d3n lc4g4d2t lc4g4d2n lc4g4d1t lc 4g4d1n xxxx xxxx uuuu uuuu table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 52 preliminary ? 2016 microchip technology inc. bank 31 ? only accessible from debug executive, unless otherwise specified cpu core registers; see table 3-2 for specifics f8ch to fe3h unimplemented fe4h (2) status_shad zd cc ---- -xxx ---- -uuu fe5h (2) wreg_shad working register normal (non-icd) shadow xxxx xxxx uuuu uuuu fe6h (2) bsr_shad bank select register normal (non-icd) shadow ---x xxxx ---u uuuu fe7h (2) pclath_shad program counter latch high register normal (non-icd) shadow -xxx xxxx -uuu uuuu fe8h (2) fsr0l_shad indirect data memory address 0 low pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu fe9h (2) fsr0h_shad indirect data memory address 0 high pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu feah (2) fsr1l_shad indirect data memory address 1 low pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu febh (2) fsr1h_shad indirect data memory address 1 high pointer normal (non-icd) shadow xxxx xxxx uuuu uuuu fech unimplemented fedh (2) stkptr current stack pointer ---x xxxx ---1 1111 feeh (2) tosl top of stack low byte xxxx xxxx xxxx xxxx fefh (2) tosh top of stack high byte -xxx xxxx -xxx xxxx table 3-4: special function regist er summary banks 0-31 (continued) address name pic16(l)f18326 pic16(l)f18346 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets legend: x = unknown, u = unchanged, q = depends on condition, - = unimplemented, read as 0 , r = reserved. shaded locations unimplemented, read as 0 . note 1: only on pic16f18326/18346. 2: register accessible from both user and icd debugger. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 53 pic16(l)f18326/18346 3.3 pcl and pclath the program counter (pc) is 15 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<14:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 3-3 shows the five situations for the loading of the pc. figure 3-3: loading of pc in different situations 3.3.1 modifying pcl executing any instruction with the pcl register as the destination simultaneously causes the program counter pc<14:8> bits (pch) to be replaced by the contents of the pclath register. this allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the pclath register. when the lower eight bits are written to the pcl register, all 15 bits of the program counter will change to the values contained in the pclath register and those being written to the pcl register. 3.3.2 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when performing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to application note an556, implementing a table read (ds00556). 3.3.3 computed function calls a computed function call allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. when performing a table read using a computed function call , care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). if using the call instruction, the pch<2:0> and pcl registers are loaded with the operand of the call instruction. pch<6:3> is loaded with pclath<6:3>. the callw instruction enables computed calls by combining pclath and w to form the destination address. a computed callw is accomplished by loading the w register with the desired address and executing callw . the pcl register is loaded with the value of w and pch is loaded with pclath. 3.3.4 branching the branching instructions add an offset to the pc. this allows relocatable code and code that crosses page boundaries. there are two forms of branching, brw and bra . the pc will have incremented to fetch the next instruction in both cases. when using either branching instruction, a pcl memory boundary may be crossed. if using brw , load the w register with the desired unsigned address and execute brw . the entire pc will be loaded with the address pc + 1 + w . if using bra , the entire pc will be loaded with pc + 1 + the signed value of the operand of the bra instruction. pcl pch 0 14 pc pcl pch 0 14 pc alu result 8 7 6 pclath 0 instruction with pcl as destination goto, call opcode <10:0> 11 4 6 pclath 0 pcl pch 0 14 pc w 8 7 6 pclath 0 callw pcl pch 0 14 pc pc + w 15 brw pcl pch 0 14 pc pc + opcode <8:0> 15 bra downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 54 preliminary ? 2016 microchip technology inc. 3.4 stack all devices have a 16-level x 15-bit wide hardware stack (refer to figure 3-4 through figure 3-7 ). the stack space is not part of either program or data space. the pc is pushed onto the stack when call or callw instructions are executed or an interrupt causes a branch. the stack is poped in the event of a return , retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer if the stvren bit is programmed to 0 (configuration words). this means that after the stack has been pushed sixteen times, the seventeenth push overwrites the value that was stored from the first push. the eighteenth push overwrites the second push (and so on). the stkovf and stkunf flag bits will be set on an overflow/underflow, regardless of whether the reset is enabled. 3.4.1 accessing the stack the stack is available through the tosh, tosl and stkptr registers. stkptr is the current value of the stack pointer. tosh:tosl register pair points to the top of the stack. both registers are read/writable. tos is split into tosh and tosl due to the 15-bit size of the pc. to access the stack, adjust the value of stkptr, which will position tosh:tosl, then read/write to tosh:tosl. stkptr is five bits to allow detection of overflow and underflow. during normal program operation, call, callw and interrupts will increment stkptr while retlw , return , and retfie will decrement stkptr. at any time, stkptr can be inspected to see how much stack is left. the stkptr always points at the currently used place on the stack. therefore, a call or callw will increment the stkptr and then write the pc, and a return will unload the pc and then decrement the stkptr. reference figure 3-4 through figure 3-7 for examples of accessing the stack. figure 3-4: accessing the stack example 1 note 1: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, callw , return , retlw and retfie instructions or the vectoring to an interrupt address. note: care should be taken when modifying the stkptr while interrupts are enabled. 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 0x0000 stkptr = 0x1f initial stack configuration: after reset, the stack is empty. the empty stack is initialized so the stack pointer is pointing at 0x1f. if the stack overflow/underflow reset is enabled, the tosh/tosl registers will return 0 . if the stack overflow/underflow reset is disabled, the tosh/tosl registers will return the contents of stack address 0x0f. 0x1f stkptr = 0x1f stack reset disabled (stvren = 0 ) stack reset enabled (stvren = 1 ) tosh:tosl tosh:tosl downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 55 pic16(l)f18326/18346 figure 3-5: accessing the stack example 2 figure 3-6: accessing the stack example 3 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x00 this figure shows the stack configuration after the first call or a single interrupt. if a return instruction is executed, the return addre ss will be placed in the program counter and the stack pointer decremented to the empty state (0x1f). tosh:tosl 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 return address 0x06 return address 0x05 return address 0x04 return address 0x03 return address 0x02 return address 0x01 return address 0x00 stkptr = 0x06 after seven call s or six call s and an interrupt, the stack looks like the figure on the left. a series of return instructions will repeatedly place the return addresses into the program counter and pop the stack. tosh:tosl downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 56 preliminary ? 2016 microchip technology inc. figure 3-7: accessing the stack example 4 3.4.2 overflow/underflow reset if the stvren bit in configuration words is programmed to 1 , the device will be reset if the stack is pushed beyond the sixteenth level or poped beyond the first level, setting the appropriate bits (stkovf or stkunf, respectively) in the pcon register. 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x10 when the stack is full, the next call or an interrupt will set the stack pointer to 0x10. this is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. if the stack overflow/underflow reset is enabled, a reset will occur and location 0x00 will not be overwritten. return address return address return address return address return address return address return address return address return address return address return address return address return address return address return address tosh:tosl downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 57 pic16(l)f18326/18346 3.5 indirect addressing the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the file select registers (fsr). if the fsrn address specifies one of the two indfn registers, the read will return 0 and the write will not occur (though status bits may be affected). the fsrn register value is created by the pair fsrnh and fsrnl. the fsr registers form a 16- bit address that allows an addressing space with 65536 locations. these locations are divided into four memory regions: traditional data memory linear data memory program flash memory eeprom 3.5.1 traditional data memory the traditional data memory is a region from fsr address 0x000 to fsr address 0xfff. the addresses correspond to the absolute addresses of all sfr, gpr and common registers. figure 3-8: traditio nal data memory map indirect addressing direct addressing bank select location select 4b s r 6 0 from opcode fsrxl 70 bank select location select 00000 00001 00010 11111 0x00 0x7f bank 0 bank 1 bank 2 bank 31 0 fsrxh 70 0000 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 58 preliminary ? 2016 microchip technology inc. 3.5.2 linear data memory the linear data memory is the region from fsr address 0x2000 to fsr address 0x29af. this region is a virtual region that points back to the 80-byte blocks of gpr memory in all the banks. unimplemented memory reads as 0x00. use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the fsr beyond one bank will go directly to the gpr memory of the next bank. the 16 bytes of common memory are not included in the linear data memory region. figure 3-9: linear data memory map 3.5.3 program flash memory to make constant data access easier, the entire program flash memory is mapped to the upper half of the fsr address space. when the msb of fsrnh is set, the lower 15 bits are the address in program memory which will be accessed through indf. only the lower eight bits of each memory location are accessible via indf. writing to the program flash memory cannot be accomplished via the fsr/indf interface. all instructions that access program flash memory via the fsr/indf interface will require one additional instruction cycle to complete. figure 3-10: program flash memory map 7 0 1 7 0 0 location select 0x2000 fsrnh fsrnl 0x020 bank 0 0x06f 0x0a0 bank 1 0x0ef 0x120 bank 2 0x16f 0xf20 bank 30 0xf6f 0x29af 0 7 1 7 0 0 location select 0x8000 fsrnh fsrnl 0x0000 0x7fff 0xffff program flash memory (low 8 bits) downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 59 pic16(l)f18326/18346 4.0 device configuration device configuration consists of configuration words, code protection and device id. 4.1 configuration words there are several configuration word bits that allow different oscillator and memory protection options. these are implemented as configuration word 1 at 8007h, configuration word 2 at 8008h, configuration word 3 at 8009h, and configuration word 4 at 800ah. note: the debug bit in configuration words is managed automatically by device development tools including debuggers and programmers. for normal device operation, this bit should be maintained as a 1 . downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 60 preliminary ? 2016 microchip technology inc. 4.2 register definitions: configuration words register 4-1: configurat ion word 1: oscillators r/p-1 u-1 r/p-1 u-1 u-1 r/p-1 fcmen cswen c l k o u t e n bit 13 bit 8 u-1 r/p-1 r/p-1 r/p-1 u-1 r/p-1 r/p-1 r/p-1 rstosc2 rstosc1 rstosc0 fextosc2 fextosc1 fextosc0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as 1 0 = bit is cleared 1 = bit is set n = value when blank or after bulk erase bit 13 fcmen: fail-safe clock monitor enable bit 1 = on fscm timer enabled 0 = off fscm timer disabled bit 12 unimplemented: read as 1 bit 11 cswen: clock switch enable bit 1 = on writing to nosc and ndiv is allowed 0 = off the nosc and ndiv bits cannot be changed by user software bit 10-9 unimplemented: read as 1 bit 8 clkouten : clock out enable bit if fextosc = ec , hs, ht or lp, then this bit is ignored; otherwise: 1 = off clkout function is disabled; i/o or oscillator function on osc2 0 = on clkout function is enabled; f osc /4 clock appears at osc2 bit 7 unimplemented: read as 1 bit 6-4 rstosc<2:0>: power-up default value for cosc bits this value is the reset default value for cosc, and selects the oscillator first used by user software 111 = ext1x extosc operating per fextosc<2:0> bits 110 = hfint1 hfintosc (1 mhz) 101 = reserved 100 = lfint lfintosc 011 = sosc sosc (32.768 khz) 010 = reserved 001 = ext4x extosc with 4x pll; extosc operating per fextosc<2:0> bits 000 = hfint32 hfintosc (32 mhz) bit 3 unimplemented: read as 1 bit 2-0 fextosc<2:0>: fextosc external oscillator mode selection bits 111 = ech ec ( external clock) above 8 mhz 110 = ecm ec ( external clock) for 100 khz to 8 mhz 101 = ecl ec ( external clock) below 100 khz 100 = off oscillator not enabled 011 = unimplemented 010 = hs hs ( crystal oscillator) above 8 mhz 001 = xt ht ( crystal oscillator) above 100 khz, below 8 mhz 000 = lp lp ( crystal oscillator) optimized for 32.768 khz downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 61 pic16(l)f18326/18346 register 4-2: co nfiguration word 2: supervisors r/p-1 r/p-1 r/p-1 u-1 r/p-1 u-1 debug stvren pps1way b o r v bit 13 bit 8 r/p-1 r/p-1 r/p-1 u-1 r/p-1 r/p-1 r/p-1 r/p-1 boren1 boren0 lpboren wdte1 wdte0 pwrte mclre bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as 1 0 = bit is cleared 1 = bit is set n = value when blank or after bulk erase bit 13 debug : debugger enable bit (1) 1 = off background debugger disabled; icspclk and icspdat are general purpose i/o pins 0 = on background debugger enabled; icspclk and icspdat are dedicated to the debugger bit 12 stvren: stack overflow/underflow reset enable bit 1 = on stack overflow or underflow will cause a reset 0 = off stack overflow or underflow will not cause a reset bit 11 pps1way: ppslock one-way set enable bit 1 = on the ppslocked bit can be cleared and set only once; pps registers remain locked after one clear/set cycle 0 = off the ppslocked bit can be set and cleared repeatedly (subject to the unlock sequence) bit 10 unimplemented: read as 1 bit 9 borv: brown-out reset voltage selection bit (2) 1 = low brown-out reset voltage ( v bor ) set to 1.9v on lf, and 2.45v on f devices 0 = high brown-out reset voltage ( v bor ) set to 2.7v the higher voltage setting is recommended for operation at or above 16 mhz. bit 8 unimplemented: read as 1 bit 7-6 boren<1:0>: brown-out reset enable bits when enabled, brown-out reset voltage ( v bor ) is set by the borv bit 11 = on brown-out reset is enabled; sboren bit is ignored 10 = sleep brown-out reset is enabled while running, di sabled in sleep; sboren bit is ignored 01 = sboren brown-out reset is enabled according to sboren 00 = off brown-out reset is disabled bit 5 lpboren : low-power bor enable bit 1 = off ulpbor is disabled 0 = on ulpbor is enabled bit 4 unimplemented: read as 1 bit 3-2 wdte<1:0>: watchdog timer enable bit 11 = on wdt is enabled; swdten is ignored 10 = sleep wdt is enabled while running and disabled in sleep/idle; swdten is ignored 01 = swdten wdt is controlled by the swdten bit in the wdtcon register 00 = off wdt is disabled; swdten is ignored bit 1 pwrte : power-up timer enable bit 1 = off pwrt is disabled 0 = on pwrt is enabled bit 0 mclre: master clear (mclr ) enable bit if lvp = 1 : ra3 pin function is mclr . if lvp = 0 : 1 = on mclr pin is mclr . 0 = off mclr pin function is port-defined function. note 1: the debug bit in configuration words is managed automa tically by device development tools including debuggers and programmers. for normal device operation, this bit should be maintained as a 1 . 2: see v bor parameter for specific trip point voltages. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 62 preliminary ? 2016 microchip technology inc. register 4-3: config uration word 3: memory r/p-1 u-1 u-1 u-1 u-1 u-1 lvp (1) bit 13 bit 8 u-1 u-1 u-1 u-1 u-1 u-1 r/p-1 r/p-1 wrt1 wrt0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as 1 0 = bit is cleared 1 = bit is set n = value when blank or after bulk erase bit 13 lvp: low-voltage programming enable bit (1) 1 = on low-voltage programming is enabled. mclr /v pp pin function is mclr . mclre configuration bit is ignored. 0 = off hv on mclr /v pp must be used for programming. bit 12-2 unimplemented: read as 1 bit 1-0 wrt<1:0>: user nvm self-write protection bits 11 = off write protection off 10 = boot 0000h to 01ffh write-protected, 0200h to 07ffh may be modified 01 = half 0000h to 1fffh write-protected, 2000h to 3fffh may be modified 00 = all 0000h to 3fffh write-protected, no addresses may be modified wrt applies only to the self-write feature of the device; writing through icsp? is never protected. note 1: the lvp bit cannot be programmed to 0 when programming mode is entered via lvp. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 63 pic16(l)f18326/18346 register 4-4: conf iguration word 4: code protection u-1 u-1 u-1 u-1 u-1 u-1 bit 13 bit 8 u-1 u-1 u-1 u-1 u-1 u-1 r/p-1 r/p-1 c p d cp bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as 1 0 = bit is cleared 1 = bit is set n = value when blank or after bulk erase bit 13-2 unimplemented: read as 1 bit 1 cpd : data eeprom memory code protection bit 1 = off data eeprom code protection disabled 0 = on data eeprom code protection enabled bit 0 cp : program memory code protection bit 1 = off program memory code protection disabled 0 = on program memory code protection enabled downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 64 preliminary ? 2016 microchip technology inc. 4.3 code protection code protection allows the device to be protected from unauthorized access. program memory protection and data memory are controlled independently. internal access to the program memory is unaffected by any code protection setting. 4.3.1 program memory protection the entire program memory space is protected from external reads and writes by the cp bit in configuration words. when cp = 0 , external reads and writes of program memory are inhibited and a read will return all 0 s. the cpu can continue to read program memory, regardless of the protection bit settings. self-write writing the program memory is dependent upon the write protection setting. see section 4.4 ?write protection? for more information. 4.3.2 data memory protection the entire data eeprom is protected from external reads and writes by the cpd bit in the configuration words. when cpd = 0 , external reads and writes of eeprom memory are inhibited and a read will return all 0 s. the cpu can continue to read and write eeprom memory, regardless of the protection bit settings. 4.4 write protection write protection allows the device to be protected from unintended self-writes. applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. the wrt<1:0> bits in configuration words define the size of the program memory block that is protected. 4.5 user id four memory locations (8000h-8003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are readable and writable during normal execution. see section 10.4.7 ?nvmreg eeprom, user id, device id and configuration word access? for more information on accessing these memory locations. for more information on checksum calculation, see the ?pic16(l)f183xx memory programming specification? (ds40001738) . 4.6 device id and revision id the 14-bit device id word is located at 8006h and the 14-bit revision id is located at 8005h. these locations are read-only and cannot be erased or modified. see section 10.4 ?nvmreg access? for more information on accessing these memory locations. development tools, such as device programmers and debuggers, may be used to read the device id and revision id. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 65 pic16(l)f18326/18346 4.7 register definitions: device and revision register 4-5: devid: device id register rrrrrr dev<13:8> bit 13 bit 8 rrrrrrrr dev<7:0> bit 7 bit 0 legend: r = readable bit 1 = bit is set 0 = bit is cleared bit 13-0 dev<13:0>: device id bits register 4-6: revid: revision id register r - 1r - 0rrrr rev<13:8> bit 13 bit 8 rrrrrrrr rev<7:0> bit 7 bit 0 legend: r = readable bit 1 = bit is set 0 = bit is cleared bit 13-0 rev<13:0>: revision id bits note: the upper two bits of the revision id register will always read 10 . device devid<13:0> values pic16f18326 11 0000 1010 0100 (30a4) pic16lf18326 11 0000 1010 0110 (30a6) pic16f18346 11 0000 1010 0101 (30a5) pic16lf18346 11 0000 1010 0111 (30a7) downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 66 preliminary ? 2016 microchip technology inc. 5.0 resets there are multiple ways to reset this device: power-on reset (por) brown-out reset (bor) low-power brown-out reset (lpbor) mclr reset wdt reset reset instruction stack overflow stack underflow programming mode exit to allow v dd to stabilize, an optional power-up timer can be enabled to extend the reset time after a bor or por event. a simplified block diagram of the on-chip reset circuit is shown in figure 5-1 . figure 5-1: simplified block di agram of on-chip reset circuit note 1: see table 5-1 for bor active conditions. device reset power-on reset wdt time-out brown-out reset lpbor reset reset instruction mclre sleep bor active (1) pwrte lfintosc v dd icsp programming mode exit stack underflow stack overlfow v pp /mclr r power-up timer rev. 10-000006a 8/14/2013 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 67 pic16(l)f18326/18346 5.1 power-on reset (por) the por circuit holds the device in reset until v dd has reached an acceptable level for minimum operation. slow rising v dd , fast operating speeds or analog performance may require greater than minimum v dd . the pwrt, bor or mclr features can be used to extend the start-up period until all device operation conditions have been met. 5.2 brown-out reset (bor) the bor circuit holds the device in reset while v dd is below a selectable minimum level. between the por and bor, complete voltage range coverage for execu- tion protection can be implemented. the brown-out reset module has four operating modes controlled by the boren<1:0> bits in configuration words. the four operating modes are: bor is always on bor is off when in sleep bor is controlled by software bor is always off refer to table 5-1 for more information. the brown-out reset voltage level is selectable by configuring the borv bit in configuration words. a v dd noise rejection filter prevents the bor from triggering on small events. if v dd falls below v bor for a duration greater than parameter t bordc , the device will reset. see figure 5-2 for more information. 5.2.1 bor is always on when the boren bits of configuration words are programmed to 11 , the bor is always on. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is active during sleep. the bor does not delay wake-up from sleep. 5.2.2 bor is off in sleep when the boren bits of configuration words are programmed to 10 , the bor is on, except in sleep. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is not active during sleep, but device wake-up will be delayed until the bor can determine that v dd is higher than the bor threshold. the device wake-up will be delayed until the bor is ready. table 5-1: bor operating modes boren<1:0> sboren device mode bor mode instruction execution upon: release of por or wake-up from sleep 11 x x active waits for release of bor (1) (borrdy = 1 ) 10 x awake active waits for release of bor (borrdy = 1 ) sleep disabled bor ignored when asleep 01 1 x active waits for release of bor (1) (borrdy = 1 ) 0 x disabled begins immediately (borrdy = x ) 00 x x disabled note 1: in these specific cases, release of por and wake-up from sleep, there is no delay in start-up. the bor ready flag, (borrdy = 1 ), will be set before the cpu is ready to execute instructions because the bor circuit is forced on by the boren<1:0> bits. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 68 preliminary ? 2016 microchip technology inc. 5.2.3 bor controlled by software when the boren bits of configuration words are programmed to 01 , the bor is controlled by the sboren bit of the borcon register. the device wake from sleep is not delayed by the bor ready condition or the v dd level. bor protection begins as soon as the bor circuit is ready. the status of the bor circuit is reflected in the borrdy bit of the borcon register. 5.2.3.1 bor protection is unchanged by sleep figure 5-2: brown -out situations 5.2.4 bor always off when the boren bits of configuration word 2 are programmed to 00 , the bor is always disable. in the configuration, setting the swboren bit will have no affect on bor operation. t pwrt (1) v bor v dd internal reset v bor v dd internal reset t pwrt (1) < t pwrt t pwrt (1) v bor v dd internal reset note 1: t pwrt delay only if pwrte bit is programmed to 0 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 69 pic16(l)f18326/18346 5.3 low-power brown-out reset (lpbor) the low-power brown-out reset (lpbor) is an essential part of the reset subsystem. refer to figure 5-1 to see how the bor interacts with other modules. the lpbor is used to monitor the external v dd pin. when too low of a voltage is detected, the device is held in reset. when this occurs, a register bit (bor ) is changed to indicate that a bor reset has occurred. the same bit is set for both the bor and the lpbor. refer to register 5-2 . 5.3.1 enabling lpbor the lpbor is controlled by the lpbor bit of configuration words. when the device is erased, the lpbor module defaults to disabled. 5.3.1.1 lpbor module output the output of the lpbor module is a signal indicating whether or not a reset is to be asserted. this signal is ord together with the reset signal of the bor module to provide the generic bor signal, which goes to the pcon register and to the power control block. 5.4 mclr the mclr is an optional external input that can reset the device. the mclr function is controlled by the mclre bit of configuration words and the lvp bit of configuration words ( table 5-2 ). 5.4.1 mclr enabled when mclr is enabled and the pin is held low, the device is held in reset. the mclr pin is connected to v dd through an internal weak pull-up. the device has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. 5.4.2 mclr disabled when mclr is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. see section 11.2 ?porta registers? for more information. 5.5 watchdog timer (wdt) reset the watchdog timer generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the to and pd bits in the status register as well as the rwdt bit in the pcon register, are changed to indicate the wdt reset. see section 9.0 ?watchdog timer (wdt)? for more information. 5.6 reset instruction a reset instruction will cause a device reset. the ri bit in the pcon register will be set to 0 . see ta b l e 5 - 4 for default conditions after a reset instruction has occurred. 5.7 stack overflow/underflow reset the device can reset when the stack overflows or underflows. the stkovf or stkunf bits of the pcon register indicate the reset condition. these resets are enabled by setting the stvren bit in configuration words. see section 3.4.2 ?overflow/underflow reset? for more information. 5.8 programming mode exit upon exit of programming mode, the device will behave as if a device reset had just occurred. 5.9 power-up timer the power-up timer provides a nominal 64 ms time-out on por or brown-out reset. the device is held in reset as long as pwrt is active. the pwrt delay allows additional time for the v dd to rise to an acceptable level. the power-up timer is enabled by clearing the pwrte bit in configuration words. the power-up timer starts after the release of the por and bor. for additional information, refer to application note an607 , power-up trouble shooting (ds00607). table 5-2: m clr configuration mclre lvp mclr 00 disabled 10 enabled x1 enabled note: a reset does not drive the mclr pin low. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 70 preliminary ? 2016 microchip technology inc. 5.10 start-up sequence upon the release of a por or bor, the following must occur before the device will begin executing: 1. power-up timer runs to completion (if enabled). 2. mclr must be released (if enabled). 3. oscillator start-up timer runs to completion (if required for oscillator source). the total time out will vary based on oscillator configuration and power-up timer configuration. see section 6.0, oscillator module (with fail-safe clock monitor) for more information. the power-up timer and oscillator start-up timer run independently of mclr reset. if mclr is kept low long enough, the power-up timer will expire. upon bringing mclr high, the device will begin execution after ten f osc cycles (see figure 5-3 ). this is useful for testing purposes or to synchronize more than one device operating in parallel. figure 5-3: reset start-up sequence t ost t mclr t pwrt v dd internal por power-up timer mclr internal reset oscillator modes oscillator start-up timer oscillator f osc internal oscillator oscillator f osc external clock (ec) clkin f osc external crystal downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 71 pic16(l)f18326/18346 5.11 determining the cause of a reset upon any reset, multiple bits in the status and pcon registers are updated to indicate the cause of the reset. ta b l e 5 - 3 and tab le 5 - 4 show the reset conditions of these registers. table 5-3: reset status bits and their significance stkovf stkunf rwdt rmclr ri por bor to pd condition 001110x1 1 power-on reset 001110x0 x illegal, to is set on por 001110xx 0 illegal, pd is set on por 00u11u01 1 brown-out reset uu0uuuu0 u wdt reset uuuuuuu0 0 wdt wake-up from sleep uuuuuuu1 0 interrupt wake-up from sleep uuu0uuuu u mclr reset during normal operation uuu0uuu1 0 mclr reset during sleep u u u u 0 u u u u reset instruction executed 1uuuuuuu u stack overflow reset (stvren = 1 ) u1uuuuuu u stack underflow reset (stvren = 1 ) table 5-4: reset condition for special registers condition program counter status register pcon0 register power-on reset 0000h ---1 1000 00-- 110x mclr reset during normal operation 0000h ---u uuuu uu-- 0uuu mclr reset during sleep 0000h ---1 0uuu uu-- 0uuu wdt reset 0000h ---0 uuuu uu-0 uuuu wdt wake-up from sleep pc + 1 ---0 0uuu uu-u uuuu brown-out reset 0000h ---1 1000 00-1 11u0 interrupt wake-up from sleep pc + 1 (1) ---1 0uuu uu-u uuuu reset instruction executed 0000h ---u uuuu uu-u u0uu stack overflow reset (stvren = 1 ) 0000h ---u uuuu 1u-u uuuu stack underflow reset (stvren = 1 ) 0000h ---u uuuu u1-u uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as 0 . note 1: when the wake-up is due to an interrupt and global enable bit (gie) is set, the return address is pushed on the stack and pc is loaded with the interrupt vector (0004h) after execution of pc + 1. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 72 preliminary ? 2016 microchip technology inc. 5.12 power control (pcon) register the power control (pcon) register contains flag bits to differentiate between a: power-on reset (por ) brown-out reset (bor ) reset instruction reset (ri ) mclr reset (rmclr ) watchdog timer reset (rwdt ) stack underflow reset (stkunf) stack overflow reset (stkovf) the pcon0 register bits are shown in register 5-2 . hardware will change the corresponding register bit during the reset process; if the reset was not caused by the condition, the bit remains unchanged ( ta b l e 5 - 4 ). software should reset the bit to the inactive state after the restart (hardware will not reset the bit). software may also set any pcon bit to the active state, so that user code may be tested, but no reset action will be generated. register 5-1: borco n: brown-out reset control register r/w-1/u r/w-0-0 u-0 u-0 u-0 u-0 u-0 r-q/u sboren (1) reserved borrdy bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 sboren: software brown-out reset enable bit (1) if boren <1:0> in configuration words ? 01 : sboren is read/write, but has no effect on the bor. if boren <1:0> in configuration words = 01 : 1 =bor enabled 0 =bor disabled bit 6 reserved: bit must be maintained as 0 bit 5-1 unimplemented: read as 0 bit 0 borrdy: brown-out reset circuit ready status bit 1 = the brown-out reset circuit is active 0 = the brown-out reset circuit is inactive note 1: boren<1:0> bits are located in configuration words. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 73 pic16(l)f18326/18346 5.13 register definitions: power control register 5-2: pcon0: power control register 0 r/w/hs-0/q r/w/hs-0/q u-0 r/w/hc-1/q r/w/ hc-1/q r/w/hc-1/q r/w/hc-q/u r/w/hc-q/u stkovf stkunf rwdt rmclr ri por bor bit 7 bit 0 legend: hc = bit is cleared by hardware hs = bit is set by hardware r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -m/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 stkovf: stack overflow flag bit 1 = a stack overflow occurred 0 = a stack overflow has not occurred or cleared by firmware bit 6 stkunf: stack underflow flag bit 1 = a stack underflow occurred 0 = a stack underflow has not occurred or cleared by firmware bit 5 unimplemented: read as 0 bit 4 rwdt : watchdog timer reset flag bit 1 = a watchdog timer reset has not occurred or set to 1 by firmware 0 = a watchdog timer reset has occurred (cleared by hardware) bit 3 rmclr : mclr reset flag bit 1 =a mclr reset has not occurred or set to 1 by firmware 0 =a mclr reset has occurred (cleared by hardware) bit 2 ri : reset instruction flag bit 1 =a reset instruction has not been executed or set to 1 by firmware 0 =a reset instruction has been executed (cleared by hardware) bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a power-on reset or brown-out reset occurs) table 5-5: summary of registers associated with resets name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page borcon sboren borrdy 72 pcon0 stkovf stkunf r w d t rmclr ri por bor 73 status t o pd z dc c 27 wdtcon wdtps<4:0> swdten 118 legend: = unimplemented location, read as 0 . shaded cells are not used by resets. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 74 preliminary ? 2016 microchip technology inc. 6.0 oscillator module (with fail-safe clock monitor) 6.1 overview the oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. figure 6-1 illustrates a block diagram of the oscillator module. clock sources can be supplied from external oscillators, quartz-crystal resonators and ceramic resonators. in addition, the system clock source can be supplied from one of two internal oscillators and pll circuits, with a choice of speeds selectable via software. additional clock features include: selectable system clock source between external or internal sources via software. fail-safe clock monitor (fscm) designed to detect a failure of the external clock source (lp, xt, hs, ech, ecm, ecl) and switch automatically to the internal oscillator. oscillator start-up timer (ost) ensures stability of crystal oscillator sources. the rstosc bits of configuration word 1 determine the type of oscillator that will be used when the device is reset, including when it is first powered-up. the internal clock modes, lfintosc, hfintosc (set at 1 mhz), or hfintosc (set at 32 mhz) can be set through the rstosc bits. if an external clock source is selected, the fextosc bits of configuration word 1 must be used in conjunction with the rstosc bits to select the external clock mode. the external oscillator module can be configured in one of the following clock modes by setting the fextosc<2:0> bits of configuration word 1: 1. ecl C external clock low-power mode (below 500 khz) 2. ecm C external clock medium-power mode (500 khz to 8 mhz) 3. ech C external clock high-power mode (above 8 mhz) 4. lp C 32 khz low-power crystal mode. 5. xt C medium gain crystal or ceramic resonator oscillator mode (between 500 khz and 8 mhz) 6. hs C high gain crystal or ceramic resonator mode (above 8 mhz) the ech, ecm, and ecl clock modes rely on an external logic level signal as the device clock source. the lp, xt, and hs clock modes require an external crystal or resonator to be connected to the device. each mode is optimized for a different frequency range. the intosc internal oscillator block produces low and high-frequency clock sources, designated lfintosc and hfintosc. (see internal oscillator block, figure 6-1 ). downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 75 pic16(l)f18326/18346 figure 6-1: simplified pic ? mcu clock source block diagram rev. 10-000208e 1/22/2015 hffrq< :0> hfintosc secondary oscillator (sosc) external oscillator (extosc) clkin/ osc1 clkout/ osc2 soscin/sosci sosco 31khz oscillator 4x pll 0 000 000 0 00 00 cosc<2:0> lfintosc 1 C 32 mhz oscillator 9-bit postscaler divider 000 000000 00000 000 000 00 00 0 512 256 128 6432 16 84 2 1 cdiv<4:0> sleep idle sleep syscmd system clock peripheral clock fscm sosc_clk to peripherals to peripherals downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 76 preliminary ? 2016 microchip technology inc. 6.2 clock source types clock sources can be classified as external or internal. external clock sources rely on external circuitry for the clock source to function. examples are: oscillator modules (ech, ecm, ecl mode), quartz crystal resonators or ceramic resonators (lp, xt and hs modes). there is also a secondary oscillator block which is optimized for a 32.768 khz external clock source, which can be used as an alternate clock source. there are two internal oscillator blocks: -hfintosc -lfintosc the hfintosc can produce clock frequencies from 1-16 mhz. the lfintosc generates a 31 khz clock frequency. there is a pll that can be used by the external oscilla- tor. see section 6.2.1.4 ?4x pll? for more details. additionally, there is a pll that can be used by the hfintosc at certain frequencies. see section 6.2.2.2 ?2x pll? for more details. 6.2.1 external clock sources an external clock source can be used as the device system clock by performing one of the following actions: program the rstosc<2:0> bits in the configuration words to select an external clock source that will be used as the default system clock upon a device reset. write the nosc<2:0> and ndiv<3:0> bits in the osccon1 register to switch the system clock source. see section 6.3 ?clock switching? for more information. 6.2.1.1 ec mode the external clock (ec) mode allows an externally generated logic level signal to be the system clock source. when operating in this mode, an external clock source is connected to the clkin input. osc2/clkout is available for general purpose i/o or clkout. figure 6-2 shows the pin connections for ec mode. ec mode has three power modes to select from through configuration words: ech C high power, 8-32 mhz ecm C medium power, 0.5-8 mhz ecl C low power, 0-0.5 mhz the oscillator start-up timer (ost) is disabled when ec mode is selected. therefore, there is no delay in operation after a power-on reset (por) or wake-up from sleep. because the pic ? mcu design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 6-2: external clock (ec) mode operation osc1/clkin osc2/clkout clock from ext. system pic ? mcu f osc /4 or i/o (1) note 1: output depends upon clkouten bit of the configuration words. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 77 pic16(l)f18326/18346 6.2.1.2 lp, xt, hs modes the lp, xt and hs modes support the use of quartz crystal resonators or ceramic resonators connected to osc1 and osc2 ( figure 6-3 ). the three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. lp oscillator mode selects the lowest gain setting of the internal inverter-amplifier. lp mode current consumption is the least of the three modes. this mode is designed to drive only 32.768 khz tun- ing-fork type crystals (watch crystals). xt oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. xt mode current consumption is the medium of the three modes. this mode is best suited to drive resona- tors with a medium drive level specification. hs oscillator mode selects the highest gain set- ting of the internal inverter-amplifier. hs mode current consumption is the highest of the three modes. this mode is best suited for resonators that require a high-drive setting. figure 6-3 and figure 6-4 show typical circuits for quartz crystal and ceramic resonators, respectively. figure 6-3: quartz crystal operation (lp, xt or hs mode) figure 6-4: ceramic resonator operation (xt or hs mode) note 1: a series resistor (r s ) may be required for quartz crystals with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . c1 c2 quartz r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu crystal osc2/clkout note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip application notes: an826 , crystal oscillator basics and crystal selection for rfpic ? and pic ? devices (ds00826) an849 , basic pic ? oscillator design (ds00849) an943 , practical pic ? oscillator analysis and design (ds00943) an949 , making your oscillator work (ds00949) note 1: a series resistor (r s ) may be required for ceramic resonators with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . 3: an additional parallel feedback resistor (r p ) may be required for proper ceramic resonator operation. c1 c2 ceramic r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu r p (3) resonator osc2/clkout downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 78 preliminary ? 2016 microchip technology inc. 6.2.1.3 oscillator start-up timer (ost) if the oscillator module is configured for lp, xt or hs modes, the oscillator start-up timer (ost) counts 1024 oscillations from osc1. this occurs following a power-on reset (por) or a wake-up from sleep. the ost ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. 6.2.1.4 4x pll the oscillator module contains a pll that can be used with external clock sources to provide a system clock source. the input frequency for the pll must fall within specifications. see the pll clock timing specifications in tab l e 3 4- 9 . the pll may be enabled for use by one of two methods: 1. program the rstosc bits in the configuration word 1 to enable the extosc with 4x pll. 2. write the nosc<2:0> bits in the osccon1 register to enable the extosc with 4x pll. 6.2.1.5 secondary oscillator the secondary oscillator is a separate oscillator block that can be used as an alternate system clock source. the secondary oscillator is optimized for 32.768 khz, and can be used with an external crystal oscillator connected to the sosci and sosco device pins, or an external clock source connected to the soscin pin. the secondary oscillator can be selected during run-time using clock switching. refer to section 6.3 ?clock switching? for more information. figure 6-5: quartz crystal operation (secondary oscillator) c1 c2 32.768 khz sosci to internal logic pic ? mcu crystal sosco quartz note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip application notes: an826, crystal oscillator basics and crystal selection for rfpic ? and pic ? devices (ds00826) an849, basic picmicro ? oscillator design (ds00849) an943, practical picmicro ? oscillator analysis and design (ds00943) an949, making your oscillator work (ds00949) tb097, interfacing a micro crystal ms1v-t1k 32.768 khz tuning fork crystal to a pic16f690/ss (ds91097) an1288, design practices for low-power external oscillators (ds01288) downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 79 pic16(l)f18326/18346 6.2.2 internal clock sources the device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: program the rstosc<2:0> bits in configuration words to select the intosc clock source, which will be used as the default system clock upon a device reset. write the nosc<2:0> bits in the osccon1 register to switch the system clock source to the internal oscillator during run-time. see section 6.3 ?clock switching? for more information. the function of the osc2/clkout pin is determined by the clkouten bit in configuration words. the internal oscillator block has two independent oscillators that can produce two internal system clock sources. 1. the hfintosc (high-frequency internal oscillator) is factory-calibrated and operates up to 32 mhz. the frequency of hfintosc can be selected through the oscfrq frequency selection register, and fine-tuning can be done via the osctune register. 2. the lfintosc (low-frequency internal oscillator) is factory-calibrated and operates at 31 khz. 6.2.2.1 hfintosc the high-frequency internal oscillator (hfintosc) is a precision digitally-controlled internal clock source that produces a stable clock up to 32 mhz. the hfintosc can be enabled through one of the following methods: programming the rstosc<2:0> bits in configuration word 1 to 110 (1 mhz) or 000 (32 mhz) to set the oscillator upon device power-up or reset write to the nosc<2:0> bits of the osccon1 register during run-time the hfintosc frequency can be selected by setting the hffrq<3:0> bits of the oscfrq register. the ndiv<3:0> bits of the osccon1 register allow for division of the output of the selected clock source by a range between 1:1 and 1:512. 6.2.2.2 2x pll the oscillator module contains a pll that can be used with the hfintosc clock source to provide a system clock source. the input frequency to the pll is limited to 8, 12, or 16 mhz, which will yield a system clock source of 16, 24, or 32 mhz, respectively. the pll may be enabled for use by one of two methods: 1. program the rstosc bits in the configuration word 1 to 000 to enable the hfintosc (32 mhz). this setting configures the hffrq<3:0> bits to 110 (16 mhz) and activates the 2x pll. 2. write 000 to the nosc<2:0> bits in the osccon1 register to enable the 2x pll, and write the correct value into the hffrq<3:0> bits of the oscfrq register to select the desired system clock frequency. see register 6-6 for more information. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 80 preliminary ? 2016 microchip technology inc. 6.2.2.3 internal oscillator frequency adjustment the internal oscillator is factory-calibrated. this internal oscillator can be adjusted in software by writing to the osctune register ( register 6-3 ). the default value of the osctune register is 00h. the value is a 6-bit twos complement number. a value of 3fh will provide an adjustment to the maximum frequency. a value of 0h will provide an adjustment to the minimum frequency. when the osctune register is modified, the oscillator frequency will begin shifting to the new frequency. code execution continues during this shift. there is no indication that the shift has occurred. osctune does not affect the lfintosc frequency. operation of features that depend on the lfintosc clock source frequency, such as the power-up timer (pwrt), watchdog timer (wdt), fail-safe clock monitor (fscm) and peripherals, are not affected by the change in frequency. 6.2.2.4 lfintosc the low-frequency internal oscillator (lfintosc) is a factory-calibrated 31 khz internal clock source. the lfintosc is the clock source for the power-up timer (pwrt), watchdog timer (wdt) and fail-safe clock monitor (fscm). the lfintosc is selected as the clock source through one of the following methods: programming the rstosc<2:0> bits of configuration word 1 to enable lfintosc. write to the nosc<2:0> bits of the osccon1 register. 6.2.2.5 oscillator status and manual enable the ready status of each oscillator is displayed in the oscstat1 register ( register 6-4 ). the oscillators can also be manually enabled through the oscen register ( register 6-5 ). manual enables make it possible to verify the operation of the extosc or sosc crystal oscillators. this can be achieved by enabling the selected oscillator, then watching the corresponding ready state of the oscillator in the oscstat1 register. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 81 pic16(l)f18326/18346 6.3 clock switching the system clock source can be switched between external and internal clock sources via software using the new oscillator source (nosc) and new divider selection request (ndiv) bits of the osccon1 register. the following clock sources can be selected: external oscillator (extosc) high-frequency internal oscillator (hfintosc) low-frequency internal oscillator (lfintosc) secondary oscillator (sosc) extosc with 4x pll hfintosc with 2x pll 6.3.1 new oscillator source (nosc) and new divider selection request (ndiv) bits the new oscillator source (nosc) and new divider selection request (ndiv) bits of the osccon1 register select the system clock source that is used for the cpu and peripherals. when the new values of nosc<2:0> and ndiv<3:0> are written to osccon1, the current oscillator selection will continue to operate as the system clock while waiting for the new source to indicate that it is stable and ready. in some cases, the newly requested source may already be in use, and is ready immediately. in the case of a divider-only change, the new and old sources are the same, so the source will be ready immediately, as well. the device may enter sleep while waiting for the switch as described in section 6.3.3 ?clock switch and sleep? . when the new oscillator is ready, the new oscillator is ready (noscr) bit of osccon3 and the clock switch interrupt flag (cswif) bit of pir3 become set (cswif = 1 ). if clock switch interrupts are enabled (clksie = 1 ), an interrupt will be generated at that time. the oscillator ready (ordy) bit of osccon3 can also be polled to determine when the oscillator is ready in lieu of an interrupt. if the clock switch hold (cswhold) bit of osccon3 is clear, the oscillator switch will occur when the new oscillator ready bit (noscr) is set and the interrupt (if enabled) will be serviced at the new oscillator setting. if cswhold is set, the oscillator switch is suspended, while execution continues using the current (old) clock source. when the noscr bit is set, software should: set cswhold = 0 so the switch can complete, or copy cosc into nosc<2:0> to abandon the switch. if doze is in effect, the switch occurs on the next clock cycle, whether or not the cpu is operating during that cycle. changing the clock post-divider without changing the clock source (i.e., changing f osc from 1 mhz to 2 mhz) is handled in the same manner as a clock source change, as described previously. the clock source will already be active, so the switch is relatively quick. cswhold must be clear (cswhold = 0 ) for the switch to complete. the current cosc and cdiv are indicated in the osccon2 register up to the moment when the switch actually occurs, at which time osccon2 is updated and ordy is set. noscr is cleared by hardware to indicate that the switch is complete. 6.3.2 pll input switch switching between the pll and any non-pll source is managed as described above. the input to the pll is established when nosc<2:0> selects the pll, and maintained by the cosc setting. when nosc<2:0> and cosc select the pll with different input sources, the system continues to run using the cosc setting, and the new source is enabled per nosc<2:0>. when the new oscillator is ready (and cswhold = 0 ), system operation is suspended while the pll input is switched and the pll acquires lock. 6.3.3 clock switch and sleep if osccon1 is written with a new value and the device is put to sleep before the switch completes, the switch will not take place and the device will enter sleep mode. when the device wakes from sleep and the cswhold bit is clear, the device will wake with the new clock active, and the clock switch interrupt flag bit (cswif) will be set. when the device wakes from sleep and the cswhold bit is set, the device will wake with the old clock active and the new clock will be requested again. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 82 preliminary ? 2016 microchip technology inc. figure 6-6: clock sw itch (cswhold = 0 ) figure 6-7: clock sw itch (cswhold = 1 ) note 1: cswif is asserted coincident with noscr; interrupt is serviced at osc#2 speed. 2: the assertion of noscr is hidden from the user because it appears only for the duration of the switch. cswhold noscr osc #2 cswif osccon1 written note 1 user clear osc #1 note 2 ordy note 1: cswif is asserted coincident with noscr, and may be cleared before or after clearing cswhold = 0 . cswhold noscr osc #1 osc #2 cswif osccon1 written note 1 ordy user clear downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 83 pic16(l)f18326/18346 figure 6-8: clo ck switch abandoned note 1: cswif may be cleared before or after rewriting osccon1; cswif is not automatically cleared. 2: ordy = 0 if osccon1 does not match osccon2; a new switch will begin. cswhold noscr osc #1 cswif osccon1 written osccon1 written note 2 ordy note 1 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 84 preliminary ? 2016 microchip technology inc. 6.4 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the device to continue operating should the external oscillator fail. the fscm is enabled by setting the fcmen bit in the configuration words. the fscm is applicable to all external oscillator modes (lp, xt, hs, ec and secondary oscillator). figure 6-9: fscm block diagram 6.4.1 fail-safe detection the fscm module detects a failed oscillator by comparing the external oscillator to the fscm sample clock. the sample clock is generated by dividing the lfintosc by 64 (see figure 6-9 ). inside the fail detector block is a latch. the external clock sets the latch on each falling edge of the external clock. the sample clock clears the latch on each rising edge of the sample clock. a failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 6.4.2 fail-safe operation when the external clock fails, the fscm switches the device clock to the hfintosc at 1 mhz clock frequency and sets the bit flag osfif of the pir3 register. setting this flag will generate an interrupt if the osfie bit of the pie3 register is also set. the device firmware can then take steps to mitigate the problems that may arise from a failed clock. the system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation, by writing to the nosc<2:0> and ndiv<3:0>bits of the osccon1 register. 6.4.3 fail-safe condition clearing the fail-safe condition is cleared after a reset, executing a sleep instruction or changing the nosc<2:0> and ndiv<3:0> bits of the osccon1 register. when switching to the external oscillator or pll, the ost is restarted. while the ost is running, the device continues to operate from the intosc selected in osccon1. when the ost times out, the fail-safe condition is cleared after successfully switching to the external clock source. the osfif bit should be cleared prior to switching to the external clock source. if the fail-safe condition still exists, the osfif flag will again become set by hardware. external lfintosc 64 s r q 31 khz (~32 ? s) 488 hz (~2 ms) clock monitor latch clock failure detected oscillator clock q sample clock downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 85 pic16(l)f18326/18346 6.4.4 reset or wake-up from sleep the fscm is designed to detect an oscillator failure after the oscillator start-up timer (ost) has expired. the ost is used after waking up from sleep and after any type of reset. the ost is not used with the ec clock modes so that the external clock signal can be stopped if required. therefore, the device will always be executing code while the ost is operating. figure 6-10: fscm timing diagram oscfif system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q) te s t test test clock monitor output downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 86 preliminary ? 2016 microchip technology inc. 6.5 register definitions: oscillator control register 6-1: osccon1: osci llator control register 1 u-0 r/w-f/f (1) r/w-f/f (1) r/w-f/f (1) r/w-q/q (4) r/w-q/q (4) r/w-q/q (4) r/w-q/q (4) n o s c < 2 : 0 > (2,3) ndiv<3:0> (2,3) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared f = determined by fuse setting bit 7 unimplemented: read as 0 bit 6-4 nosc<2:0>: new oscillator source request bits the setting requests a source oscillator and pll combination per ta b l e 6 - 1 . por value = rstosc ( register 4-2 ). bit 3-0 ndiv<3:0>: new divider selection request bits the setting determines the new postscaler division ratio per ta bl e 6 - 2 . note 1: the default value (f/f) is set equal to the rstosc configuration bits. 2: if nosc is written with a reserved value ( table 6-1 ), the hfintosc will be automatically selected as the clock source. 3: when cswen = 0 , this register is read-only and cannot be changed from the por value. 4: when rstosc = 110 (hfintosc 1 mhz) the ndiv bits will default to ' 0010 ' upon reset; for all other nosc settings, the nvid bits will default to ' 0000 ' upon reset. register 6-2: osccon2: osci llator control register 2 u-0 r-q/q (1) r-q/q (1) r-q/q (1) r-q/q (1) r-q/q (1) r-q/q (1) r-q/q (1) cosc<2:0> cdiv<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6-4 cosc<2:0>: current oscillator source select bits (read-only) indicates the current source oscillator and pll combination per tab l e 6 - 1 . bit 3-0 cdiv<3:0>: current divider select bits (read-only) indicates the current postscaler division ratio per tab l e 6 - 2 . note 1: the reset value (n/n) will match the nosc<2:0>/ndiv<3:0> bits. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 87 pic16(l)f18326/18346 table 6-1: nosc/cosc bit settings nosc<2:0> cosc<2:0> clock source 111 extosc (1) 110 hfintosc (1 mhz) 101 reserved 100 lfintosc 011 sosc 010 reserved 001 extosc with 4xpll (1) 000 hfintosc with 2x pll (32 mhz) note 1: extosc configured by the fextosc bits of configuration word 1 ( register 4-1 ). table 6-2: ndiv/cdiv bit settings ndiv<3:0> cdiv<3:0> clock divider 1111 C 1010 reserved 1001 512 1000 256 0111 128 0110 64 0101 32 0100 16 0011 8 0010 4 0001 2 0000 1 register 6-3: osccon3: osci llator control register 3 r/w/hc-0/0 r/w-0/0 r/w-0/0 r-0/0 r-0/0 u-0 u-0 u-0 cswhold soscpwr soscbe ordy noscr bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 cswhold: clock switch hold bit 1 = clock switch will hold (with interrupt) when the oscillator selected by nosc is ready 0 = clock switch may proceed when the oscillator selected by nosc is ready; if this bit is set at the time that noscr becomes 1 , the switch and interrupt will occur. bit 6 soscpwr: secondary oscillator power mode select bit if soscbe = 0 1 = secondary oscillator operating in high-power mode 0 = secondary oscillator operating in low-power mode if soscbe = 1 x = bit is ignored bit 5 soscbe: secondary oscillator bypass enable bit 1 = secondary oscillator sosci is configured as an external clock input (st-buffer); sosco is not used. 0 = secondary oscillator is configured as a crystal oscillator using sosco and sosci pins. bit 4 ordy: oscillator ready bit (read-only) 1 = osccon1 = osccon2; the current system clock is the clock specified by nosc 0 = a clock switch is in progress bit 3 noscr: new oscillator is ready bit (read-only) 1 = a clock switch is in progress and the oscillator selected by nosc indicates a ready condition 0 = a clock switch is not in progress, or the nosc-selected oscillator is not yet ready bit 2-0 unimplemented: read as 0 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 88 preliminary ? 2016 microchip technology inc. register 6-4: oscstat1: oscillator status register 1 r-q/q r-q/q u-0 r-q/q r-q/q r-q/q u-0 r-q/q extor hfor l f o rs o ra d o r p l l r bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 extor: extosc (external) oscillator ready bit 1 = the oscillator is ready to be used 0 = the oscillator is not enabled, or is not yet ready to be used. bit 6 hfor: hfintosc oscillator ready bit 1 = the oscillator is ready to be used 0 = the oscillator is not enabled, or is not yet ready to be used. bit 5 unimplemented: read as 0 bit 4 lfor: lfintosc oscillator ready bit 1 = the oscillator is ready to be used 0 = the oscillator is not enabled, or is not yet ready to be used. bit 3 sor: secondary oscillator ready bit 1 = the oscillator is ready to be used 0 = the oscillator is not enabled, or is not yet ready to be used. bit 2 ador: adcrc oscillator ready bit 1 = the oscillator is ready to be used 0 = the oscillator is not enabled, or is not yet ready to be used bit 1 unimplemented: read as 0 bit 0 pllr: pll is ready bit 1 = the pll is ready to be used 0 = the pll is not enabled, the required input so urce is not ready, or the pll is not ready. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 89 pic16(l)f18326/18346 register 6-5: oscen: oscill ator manual enable register r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 extoen hfoen lfoen soscen adoen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 extoen: external oscillator manual request enable bit 1 = extosc is explicitly enabled, operating as specified by fextosc 0 = extosc could be enabled by another module bit 6 hfoen: hfintosc oscillator manual request enable bit 1 = hfintosc is explicitly enabled, operating as specified by oscfrq ( register 6-6 ) 0 = hfintosc could be enabled by another module bit 5 unimplemented: read as 0 bit 4 lfoen: lfintosc (31 khz) oscillator manual request enable bit 1 = lfintosc is explicitly enabled 0 = lfintosc could be enabled by another module bit 3 soscen: secondary (timer1) oscillator manual request enable bit 1 = secondary oscillator is explicitly enabled, operating as specified by soscbe and soscpwr 0 = secondary oscillator could be enabled by another module bit 2 adoen: adosc (600 khz) oscillator manual request enable bit 1 = adosc is explicitly enabled 0 = adosc could be enabled by another module bit 1-0 unimplemented: read as 0 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 90 preliminary ? 2016 microchip technology inc. register 6-6: oscfrq: hfintosc frequency selection register u-0 u-0 u-0 u-0 r/w-0/0 r/w-1/1 r/w-1/1 r/w-0/0 hffrq<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 unimplemented: read as 0 bit 3-0 hffrq<3:0>: hfintosc frequency selection bits hffrq<3:0> nominal freq. (mhz) (nosc = 110 ) 2x pll freq. (mhz) (nosc = 000 ) 0000 1 reserved 0001 2 0010 reserved 0011 4 0100 81 6 0101 12 24 0110 16 32 0111 32 reserved 1xxx 32 reserved downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 91 pic16(l)f18326/18346 register 6-7: osctune: hfintosc tuning register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 hftun<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 hftun<5:0>: hfintosc frequency tuning bits 01 1111 = maximum frequency 01 1110 00 0001 00 0000 = center frequency. oscillator module is running at the calibrated frequency (default value). 11 1111 10 0000 = minimum frequency. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 92 preliminary ? 2016 microchip technology inc. table 6-3: summary of registers associated with clock sources name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon1 nosc<2:0> ndiv<3:0> 86 osccon2 cosc<2:0> cdiv<3:0> 86 osccon3 cwshold soscpwr soscbe ordy noscr 87 oscstat1 extor hfor l f o r sor ador pllr 88 oscen extoen hfoen l f o e n soscen adoen 89 oscfrq hffrq<3:0> 90 osctune h f t u n < 5 : 0 > 91 legend: = unimplemented location, read as 0 . shaded cells are not used by clock sources. table 6-4: summary of configurat ion word with clock sources name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 fcmen cswen c l k o u t e n 60 7:0 rstosc2 rstosc1 rstosc0 fextosc2 fextosc1 fextosc0 legend: = unimplemented location, read as 0 . shaded cells are not used by clock sources. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 93 pic16(l)f18326/18346 7.0 interrupts the interrupt feature allows certain events to preempt normal program flow. firmware is used to determine the source of the interrupt and act accordingly. some interrupts can be configured to wake the mcu from sleep mode. this chapter contains the following information for interrupts: operation interrupt latency interrupts during sleep int pin automatic context saving many peripherals produce interrupts. refer to the corresponding chapters for details. a block diagram of the interrupt logic is shown in figure 7-1 . figure 7-1: interrupt logic tmr0if tmr0ie intf inte iocif iocie interrupt to cpu wake-up (if in sleep mode) gie (tmr1if) pir1<0> pirn<7> peie (tmr1ie) pie1<0> peripheral interrupts pien<7> downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 94 preliminary ? 2016 microchip technology inc. 7.1 operation interrupts are disabled upon any device reset. they are enabled by setting the following bits: gie bit of the intcon register interrupt enable bit(s) for the specific interrupt event(s) peie bit of the intcon register (if the interrupt enable bit of the interrupt event is contained in the piex registers) the pir1, pir2, pir3 and pir4 registers record individual interrupts via interrupt flag bits. interrupt flag bits will be set, regardless of the status of the gie, peie and individual interrupt enable bits. the following events happen when an interrupt event occurs while the gie bit is set: current prefetched instruction is flushed gie bit is cleared current program counter (pc) is pushed onto the stack critical registers are automatically saved to the shadow registers (see ? section 7.5 ?automatic context saving? ) pc is loaded with the interrupt vector 0004h the firmware within the interrupt service routine (isr) should determine the source of the interrupt by polling the interrupt flag bits. the interrupt flag bits must be cleared before exiting the isr to avoid repeated interrupts. because the gie bit is cleared, any interrupt that occurs while executing the isr will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. the retfie instruction exits the isr by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the gie bit. for additional information on a specific interrupts operation, refer to its peripheral chapter. 7.2 interrupt latency interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. the latency for synchronous interrupts is three or four instruction cycles. for asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. see figure 7-2 and figure 7-3 for more details. note 1: individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: all interrupts will be ignored while the gie bit is cleared. any interrupt occurring while the gie bit is clear will be serviced when the gie bit is set again. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 95 pic16(l)f18326/18346 figure 7-2: interrupt latency q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkr pc 0004h 0005h pc inst(0004h) nop gie q1 q2 q3 q4 q1 q2 q3 q4 1 cycle instruction at pc pc inst(0004h) nop 2 cycle instruction at pc fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc execute interrupt inst(pc) interrupt sampled during q1 inst(pc) pc-1 pc+1 nop pc new pc/ pc+1 0005h pc-1 pc+1/fsr addr 0004h nop interrupt gie interrupt inst(pc) nop nop fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc interrupt inst(pc) nop nop nop inst(0005h) execute execute execute downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 96 preliminary ? 2016 microchip technology inc. figure 7-3: int pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf gie instruction flow pc instruction fetched instruction executed interrupt latency pc pc + 1 pc + 1 0004h 0005h inst (0004h) inst (0005h) forced nop inst (pc) inst (pc + 1) inst (pc C 1) inst (0004h) forced nop inst (pc) note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-5 t cy . synchronous latency = 3-4 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout not available in all oscillator modes. 4: for minimum width of int pulse, refer to ac specifications in section 34.0 ?electrical specifications? ? . 5: intf is enabled to be set any time during the q4-q1 cycles. (1) (2) (3) (4) (5) (1) downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 97 pic16(l)f18326/18346 7.3 interrupts during sleep some interrupts can be used to wake from sleep. to wake from sleep, the peripheral must be able to operate without the system clock. the interrupt source must have the appropriate interrupt enable bit(s) set prior to entering sleep. on waking from sleep, if the gie bit is also set, the processor will branch to the interrupt vector. otherwise, the processor will continue executing instructions after the sleep instruction. the instruction directly after the sleep instruction will always be executed before branching to the isr. refer to section 8.0 ?power-saving operation modes? for more details. 7.4 int pin the int pin can be used to generate an asynchronous edge-triggered interrupt. this interrupt is enabled by setting the inte bit of the pie0 register. the intedg bit of the intcon register determines on which edge the interrupt will occur. when the intedg bit is set, the rising edge will cause the interrupt. when the intedg bit is clear, the falling edge will cause the interrupt. the intf bit of the pir0 register will be set when a valid edge appears on the int pin. if the gie and inte bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 automatic context saving upon entering an interrupt, the return pc address is saved on the stack. additionally, the following registers are automatically saved in the shadow registers: w register status register (except for to and pd ) bsr register fsr registers pclath register upon exiting the interrupt service routine, these registers are automatically restored. any modifications to these registers during the isr will be lost. if modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the isr. the shadow registers are available in bank 31 and are readable and writable. depending on the users application, other registers may also need to be saved. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 98 preliminary ? 2016 microchip technology inc. 7.6 register definitions: interrupt control register 7-1: intcon: interrupt control register r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 u-0 r-1/1 gie peie i n t e d g bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 gie: global interrupt enable bit 1 = enables all active interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all active peripheral interrupts 0 = disables all peripheral interrupts bit 5-1 unimplemented: read as 0 bit 0 intedg: interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 99 pic16(l)f18326/18346 register 7-2: pie0: peripheral interrupt enable register 0 u-0 u-0 r/w/hs-0/0 r/w-0/0 u-0 u-0 u-0 r/w/hs-0/0 t m r 0 i ei o c i e i n t e bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs = hardware set bit 7-6 unimplemented : read as 0 bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 iocie: interrupt-on-change interrupt enable bit 1 = enables the ioc change interrupt 0 = disables the ioc change interrupt bit 3-1 unimplemented : read as 0 bit 0 inte: int external interrupt flag bit (1) 1 = enables the int external interrupt 0 = disables the int external interrupt note 1: the external interrupt gpio pin is selected by intpps ( register 12-1 ). downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 100 preliminary ? 2016 microchip technology inc. register 7-3: pie1: peripheral interrupt enable register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tmr1gie adie rcie txie ssp1ie bcl1ie tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 tmr1gie: timer1 gate interrupt enable bit 1 = enables the timer1 gate acquisition interrupt 0 = disables the timer1 gate acquisition interrupt bit 6 adie: analog-to-digital converter (adc) interrupt enable bit 1 = enables the adc interrupt 0 = disables the adc interrupt bit 5 rcie: eusart receive interrupt enable bit 1 = enables the eusart receive interrupt 0 = disables the eusart receive interrupt bit 4 txie: eusart transmit interrupt enable bit 1 = enables the eusart transmit interrupt 0 = disables the eusart transmit interrupt bit 3 ssp1ie: synchronous serial port (mssp) interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 bcl1ie: mssp1 bus collision interrupt enable bit 1 = mssp bus collision interrupt enabled 0 = mssp bus collision interrupt not enabled bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the timer2 to pr2 match interrupt 0 = disables the timer2 to pr2 match interrupt bit 0 tmr1ie: timer1 overflow interrupt enable bit 1 = enables the timer1 overflow interrupt 0 = disables the timer1 overflow interrupt note: bit peie of the intcon register must be set to enable any peripheral interrupt. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 101 pic16(l)f18326/18346 register 7-4: pie2: peripheral interrupt enable register 2 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tmr6ie c2ie c1ie nvmie ssp2ie bcl2ie tmr4ie nco1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 tmr6ie: tmr6 to pr6 match interrupt enable bit 1 = tmr6 to pr6 match interrupt is enabled 0 = tmr6 to pr6 match is not enabled bit 6 c2ie: comparator c2 interrupt enable bit 1 = enables the comparator c2 interrupt 0 = disables the comparator c2 interrupt bit 5 c1ie: comparator c1 interrupt enable bit 1 = enables the comparator c1 interrupt 0 = disables the comparator c1 interrupt bit 4 nvmie: nvm interrupt enable bit 1 = envm task complete interrupt enabled 0 = nvm interrupt not enabled bit 3 ssp2ie: master synchronous serial port (mssp2) interrupt enable bit 1 = enables the mssp2 interrupt 0 = disables the mssp2 interrupt bit 2 bcl2ie: mssp2 bus collision interrupt enable bit 1 = mssp bus collision interrupt enabled 0 = mssp bus collision interrupt not enabled bit 1 tmr4ie: tmr4 to pr4 match interrupt enable bit 1 = tmr4 to pr4 match interrupt is enabled 0 = tmr4 to pr4 match is not enabled bit 0 nco1ie: nco interrupt enable bit 1 = nco rollover interrupt enabled 0 = nco rollover interrupt not enabled note: bit peie of the intcon register must be set to enable any peripheral interrupt. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 102 preliminary ? 2016 microchip technology inc. register 7-5: pie3: peripheral interrupt enable register 3 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 osfie cswie tmr3gie tmr3ie clc4ie clc3ie clc2ie clc1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 osfie : oscillator fail interrupt enable bit 1 = enables the oscillator fail interrupt 0 = disables the oscillator fail interrupt bit 6 cswie: clock switch complete interrupt enable bit 1 = the clock switch module interrupt is enabled 0 = the clock switch module interrupt is not enabled bit 5 tmr3gie: timer3 gate interrupt enable bit 1 = timer3 gate interrupt is enabled 0 = timer3 gate interrupt is not enabled bit 4 tmr3ie: tmr3 overflow interrupt enable bit 1 = tmr3 overflow interrupt is enabled 0 = tmr3 overflow interrupt is not enabled bit 3 clc4ie: clc4 interrupt flag bit 1 = clc4 interrupt is enabled 0 = clc4 interrupt is not enabled bit 2 clc3ie: clc3 interrupt flag bit 1 = clc3 interrupt is enabled 0 = clc3 interrupt is not enabled bit 1 clc2ie: clc2 interrupt enable bit 1 = clc2 interrupt enabled 0 = clc2 interrupt disabled bit 0 clc1ie: clc1 interrupt enable bit 1 = clc1 interrupt enabled 0 = clc1 interrupt disabled note: bit peie of the intcon register must be set to enable any peripheral interrupt. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 103 pic16(l)f18326/18346 register 7-6: pie4: peripheral interrupt enable register 4 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 cwg2ie cwg1ie tmr5gie tmr5ie ccp4ie ccp3ie ccp2ie ccp1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs = hardware set bit 7 cwg2ie: cwg 2 interrupt enable bit 1 = cwg2 interrupt enabled 0 = cwg2 interrupt not enabled bit 6 cwg1ie: cwg 1 interrupt enable bit 1 = cwg1 interrupt enabled 0 = cwg1 interrupt not enabled bit 5 tmr5gie: timer5 gate interrupt enable bit 1 = tmr5 gate interrupt is enabled 0 = tmr5 gate interrupt is not enabled bit 4 tmr5ie: tmr5 overflow interrupt enable bit 1 = tmr5 overflow interrupt is enabled 0 = tmr5 overflow interrupt is not enabled bit 3 ccp4ie: ccp4 interrupt enable bit 1 = ccp4 interrupt is enabled 0 = ccp4 interrupt is not enabled bit 2 ccp3ie: ccp3 interrupt enable bit 1 = ccp3 interrupt is enabled 0 = ccp3 interrupt is not enabled bit 1 ccp2ie: ccp2 interrupt enable bit 1 = ccp2 interrupt is enabled 0 = ccp2 interrupt is not enabled bit 0 ccp1ie: ccp1 interrupt enable bit 1 = ccp1 interrupt is enabled 0 = ccp1 interrupt is not enabled note: bit peie of the intcon register must be set to enable any peripheral interrupt. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 104 preliminary ? 2016 microchip technology inc. register 7-7: pir0: peripheral interrupt request register 0 u-0 u-0 r/w/hs-0/0 r-0 u-0 u-0 u-0 r/w/hs-0/0 t m r 0 i fi o c i f intf (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs= hardware set bit 7-6 unimplemented: read as 0 bit 5 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 4 iocif: interrupt-on-change interrupt flag bit (read-only) 1 = an enabled edge was detected by the ioc module. one of the iocf bits is set. 0 = no enabled edge is was detected by the ioc module. none of the iocf bits is set. pins are individually masked via iocxp and iocxn. bit 3-1 unimplemented: read as 0 bit 0 intf: int external interrupt flag bit (1) 1 = the int external interrupt occurred (must be cleared in software) 0 = the int external interrupt did not occur note 1: the external interrupt gpio pin is selected by intpps ( register 12-1 ). note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 105 pic16(l)f18326/18346 register 7-8: pir1: peripheral interrupt request register 1 r/w/hs-0/0 r/w/hs-0/0 r/w-0/0 r/w-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 tmr1gif adif rcif txif ssp1if bcl1if tmr2if tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs = hardware set bit 7 tmr1gif : timer1 gate interrupt flag bit 1 = the timer1 gate has gone inactive (the gate is closed) 0 = the timer1 gate has not gone inactive. bit 6 adif: analog-to-digital converter (adc) interrupt flag bit 1 = the a/d conversion completed 0 = the a/d conversion is not completed bit 5 rcif: eusart receive interrupt flag bit 1 = the eusart1 receive buffer is not empty 0 = the eusart1 receive buffer is empty bit 4 txif : eusart transmit interrupt flag bit 1 = the eusart1 receive buffer is not empty 0 = the eusart1 receive buffer is empty bit 3 ssp1if : synchronous serial port (mssp) interrupt flag bit 1 = the transmission/reception/bus condition is complete (must be cleared in software) 0 = waiting for the transmission/reception/bus condition in progress bit 2 bcl1if: mssp bus collision interrupt flag bit 1 = a bus collision was detected (must be cleared in software) 0 = no bus collision was detected bit 1 tmr2if: timer2 to pr2 interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: timer1 overflow interrupt flag bit 1 = tmr1 overflow occurred (must be cleared in software) 0 = no tmr1 overflow occurred note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 106 preliminary ? 2016 microchip technology inc. register 7-9: pir2: peripheral interrupt request register 2 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 tmr6if c2if c1if nvmif ssp2if bcl2if tmr4if nco1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs = hardware set bit 7 tmr6if: tmr6 to pr6 match interrupt flag bit 1 = tmr6 to pr6 match occurred (must be cleared in software) 0 = no tmr6 to pr6 match occurred bit 6 c2if: comparator c2 interrupt flag bit 1 = comparator 2 interrupt asserted 0 = comparator 2 interrupt not asserted bit 5 c1if: comparator c1 interrupt flag bit 1 = comparator 1 interrupt asserted 0 = comparator 1 interrupt not asserted bit 4 nvmif : nvm interrupt flag bit 1 = the nvm has completed a programming task 0 = nvm interrupt not asserted bit 3 ssp2if: master synchronous serial port (mssp2) interrupt flag bit 1 = the transmission/reception/bus condition is complete (must be cleared in software) 0 = waiting for the transmission/reception/bus condition in progress bit 2 bcl2if: mssp2 bus collision interrupt flag bit 1 = a bus collision was detected (must be cleared in software) 0 = no bus collision was detected bit 1 tmr4if: tmr4 to pr4 match interrupt flag bit 1 = tmr4 to pr4 match occurred (must be cleared in software) 0 = no tmr4 to pr4 match occurred bit 0 nco1if: nco interrupt flag bit 1 = the nco has rolled over. 0 = no nco interrupt is asserted. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 107 pic16(l)f18326/18346 register 7-10: pir3: peripheral interrupt request register 3 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 osfif cswif tmr3gif tmr3if clc4if clc3if clc2if clc1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs = hardware set bit 7 osfif: oscillator fail-safe interrupt flag bit 1 = oscillator fail-safe interrupt has occurred 0 = no oscillator fail-safe interrupt bit 6 cswif: clock switch complete interrupt flag bit 1 = the clock switch module indicates an interrupt condition 0 = the clock switch module does not indicate an interrupt condition bit 5 tmr3gif: timer3 gate interrupt flag bit 1 = the tmr3 gate has gone inactive (the gate is closed) 0 = the tmr3 gate has not gone inactive. bit 4 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 overflow occurred (must be cleared in software) 0 = no tmr3 overflow occurred bit 3 clc4if: clc4 interrupt flag bit 1 = the clc4out interrupt condition has been met 0 = no clc4 interrupt bit 2 clc3if: clc3 interrupt flag bit 1 = the clc3out interrupt condition has been met 0 = no clc3 interrupt bit 1 clc2if: clc2 interrupt flag bit 1 = the clc2out interrupt condition has been met 0 = no clc2 interrupt bit 0 clc1if: clc1 interrupt flag bit 1 = the clc1out interrupt condition has been met 0 = no clc1 interrupt note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 108 preliminary ? 2016 microchip technology inc. register 7-11: pir4: peripheral interrupt request register 4 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 cwg2if cwg1if tmr5gif tmr5if ccp4if ccp3if ccp2if ccp1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs = hardware set bit 7 cwg2if: cwg 2 interrupt flag bit 1 = cwg2 has gone into shutdown 0 = cwg2 is operating normally, or interrupt cleared bit 6 cwg1if: cwg1 interrupt flag bit 1 = cwg1 has gone into shutdown 0 = cwg1 is operating normally, or interrupt cleared bit 5 tmr5gif: timer5 gate interrupt flag bit 1 = the tmr5 gate has gone inactive (the gate is closed). 0 = the tmr5 gate has not gone inactive. bit 4 tmr5if: timer5 overflow interrupt flag bit 1 = tmr5 overflow occurred (must be cleared in software) 0 = no tmr5 overflow occurred bit 3 ccp4if: ccp4 interrupt flag bit bit 2 ccp3if: ccp3 interrupt flag bit value ccpm mode capture compare pwm 1 capture occurred (must be cleared in software) compare match occurred (must be cleared in software) output trailing edge occurred (must be cleared in software) 0 capture did not occur compare match did not occur output trailing edge did not occur value ccpm mode capture compare pwm 1 capture occurred (must be cleared in software) compare match occurred (must be cleared in software) output trailing edge occurred (must be cleared in software) 0 capture did not occur compare match did not occur output trailing edge did not occur downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 109 pic16(l)f18326/18346 bit 1 ccp2if: ccp2 interrupt flag bit bit 0 ccp1if: ccp1 interrupt flag bit note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. table 7-1: summary of registers associated with interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie i n t e d g 98 pie0 t m r 0 i ei o c i e i n t e 99 pie1 tmr1gie adie rcie txie ssp1ie bcl1ie tmr2ie tmr1ie 100 pie2 tmr6ie c2ie c1ie nvmie ssp2ie bcl2ie tmr4ie nco1ie 101 pie3 osfie cswie tmr3gie tmr3ie clc4ie clc3ie clc2ie clc1ie 102 pie4 cwg2ie cwg1ie tmr5gie tmr5ie ccp4ie ccp3ie ccp2ie ccp1ie 103 pir0 t m r 0 i fi o c i f i n t f 104 pir1 tmr1gif adif rcif txif ssp1if bcl1if tmr2if tmr1if 105 pir2 tmr6if c2if c1if nvmif ssp2if bcl2if tmr4if nco1if 106 pir3 osfif cswif tmr3gif tmr3if clc4if clc3if clc2if clc1if 107 pir4 cwg2if cwg1if tmr5gif tmr5if ccp4if ccp3if ccp2if ccp1if 108 legend: = unimplemented location, read as 0 . shaded cells are not used by interrupts. register 7-11: pir4: peripheral interrupt request register 4 (continued) value ccpm mode capture compare pwm 1 capture occurred (must be cleared in software) compare match occurred (must be cleared in software) output trailing edge occurred (must be cleared in software) 0 capture did not occur compare match did not occur output trailing edge did not occur value ccpm mode capture compare pwm 1 capture occurred (must be cleared in software) compare match occurred (must be cleared in software) output trailing edge occurred (must be cleared in software) 0 capture did not occur compare match did not occur output trailing edge did not occur downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 110 preliminary ? 2016 microchip technology inc. 8.0 power-saving operation modes the purpose of the power-down modes is to reduce power consumption. there are two power-down modes: doze mode and sleep mode. 8.1 doze mode doze mode allows for power savings by reducing cpu operation and program memory access, without affecting peripheral operation. doze mode differs from sleep mode because the system oscillators continue to operate, while only the cpu and program memory are affected. the reduced execution saves power by eliminating unnecessary operations within the cpu and memory. when the doze enable (dozen) bit is set (dozen = 1 ), the cpu executes only one instruction cycle out of every n cycles as defined by the doze<2:0> bits of the cpudoze register. for example, if doze<2:0> = 100 , the instruction cycle ratio is 1:32. the cpu and memory execute for one instruction cycle and then lay idle for 31 instruction cycles. during the unused cycles, the peripherals continue to operate at the system clock speed. figure 8-1: doze mode operation example sstem clock /v????]}v w ?]}? cpu clock pfm ops cpu ops 1111111111111 1234 2 22222 22 2 22 22 2 2 22 2 1 11111 3 33333 4 44444 2 3333333333333 4 4 4 4 4 4 4 4 4 4 4 4 4 fetch fetch fetch fetch exec exec exec (1,2) exec exec exec push nop 0004h interrup t here (roi = 1) downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 111 pic16(l)f18326/18346 8.1.1 doze operation the doze operation is illustrated in figure 8-1 . for this example: doze enable (dozen) bit set (dozen = 1 ) doze<2:0>= 001 (1:4) ratio recover-on-interrupt (roi) bit set (roi = 1 ) as with normal operation, the program memory fetches for the next instruction cycle. the instruction clocks to the peripherals continue throughout. 8.1.2 interrupts during doze if an interrupt occurs and the recover-on-interrupt (roi) bit is clear (roi = 0 ) at the time of the interrupt, the interrupt service routine (isr) continues to exe- cute at the rate selected by doze<2:0>. interrupt latency is extended by the doze<2:0> ratio. if an interrupt occurs and the roi bit is set (roi = 1 ) at the time of the interrupt, the dozen bit is cleared and the cpu executes at full speed. the prefetched instruc- tion is executed and then the interrupt vector sequence is executed. in figure 8-1 , the interrupt occurs during the 2 nd instruction cycle of the doze period, and imme- diately brings the cpu out of doze. if the doze-on-exit (doe) bit is set (doe = 1 ) when the retfie operation is executed, dozen is set, and the cpu executes at the reduced rate based on the doze<2:0> ratio. 8.2 sleep mode sleep mode is entered by executing the sleep instruction, while the idle enable (idlen) bit of the cpudoze register is clear (idlen = 0 ). if the sleep instruction is executed while the idlen bit is set (idlen = 1 ), the cpu will enter the idle mode ( section 8.2.3 ?low-power sleep mode? ). upon entering sleep mode, the following conditions exist: 1. wdt will be cleared but keeps running if enabled for operation during sleep 2. the pd bit of the status register is cleared 3. the to bit of the status register is set 4. the cpu clock is disabled 5. 31 khz lfintosc, hfintosc and sosc are unaffected and peripherals using them may continue operation in sleep. 6. timer1 and peripherals that use it continue to operate in sleep when the timer1 clock source selected is: lfintosc t1cki secondary oscillator 7. adc is unaffected if the dedicated adcrc oscillator is selected 8. i/o ports maintain the status they had before sleep was executed (driving high, low, or high-impedance) 9. resets other than wdt are not affected by sleep mode refer to individual chapters for more details on peripheral operation during sleep. to minimize current consumption, the following conditions should be considered: - i/o pins should not be floating - external circuitry sinking current from i/o pins - internal circuitry sourcing current from i/o pins - current draw from pins with internal weak pull-ups - modules using any oscillator i/o pins that are high-impedance inputs should be pulled to v dd or v ss externally to avoid switching currents caused by floating inputs. examples of internal circuitry that might be sourcing current include modules such as the dac and fvr modules. see section 23.0 ?5-bit digital-to-analog converter (dac1) module? and section 15.0 ?fixed voltage reference (fvr)? for more information on these modules. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 112 preliminary ? 2016 microchip technology inc. 8.2.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin, if enabled 2. bor reset, if enabled. 3. por reset. 4. watchdog timer, if enabled 5. any external interrupt. 6. interrupts by peripherals capable of running during sleep (see individual peripheral for more information). the first three events will cause a device reset. the last three events are considered a continuation of program execution. to determine whether a device reset or wake-up event occurred, refer to section 5.11 ?determining the cause of a reset? . when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. wake-up will occur regardless of the state of the gie bit. if the gie bit is disabled, the device continues execution at the instruction after the sleep instruction. if the gie bit is enabled, the device executes the instruction after the sleep instruction, the device will then call the interrupt service routine. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes-up from sleep, regardless of the source of wake-up. 8.2.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source, with the exception of the clock switch interrupt, has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction - sleep instruction will execute as a nop - wdt and wdt prescaler will not be cleared -to bit of the status register will not be set -pd bit of the status register will not be cleared if the interrupt occurs during or after the execution of a sleep instruction - sleep instruction will be completely executed - device will immediately wake-up from sleep - wdt and wdt prescaler will be cleared -to bit of the status register will be set -pd bit of the status register will be cleared even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . figure 8-2: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 clkin (1) clkout (2) interrupt flag gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (4) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) forced nop pc + 2 0004h 0005h forced nop t ost (3) pc + 2 note 1: external clock. high, medium, low mode assumed. 2: clkout is shown here for timing reference. 3: t ost = 1024 t osc . this delay does not apply to ec and intosc oscillator modes. 4: gie = 1 assumed. in this case after wake-up, the processor calls the isr at 0004h. if gie = 0 , execution will continue in-line. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 113 pic16(l)f18326/18346 8.2.3 low-power sleep mode the pic16f18326/18346 device contains an internal low dropout (ldo) voltage regulator, which allows the device i/o pins to operate at voltages up to 5.5v while the internal device logic operates at a lower voltage. the ldo and its associated reference circuitry must remain active when the device is in sleep mode. the pic16f18326/18346 allows the user to optimize the operating current in sleep, depending on the application requirements. low-power sleep mode can be selected by setting the vregpm bit of the vregcon register. depending on the configuration of these bits, the ldo and reference circuitry are placed in a low-power state when the device is in sleep. 8.2.3.1 sleep current vs. wake-up time in the default operating mode, the ldo and reference circuitry remain in the normal configuration while in sleep. the device is able to exit sleep mode quickly since all circuits remain active. in low-power sleep mode, when waking-up from sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. the low-power sleep mode is beneficial for applications that stay in sleep mode for long periods of time. the normal mode is beneficial for applications that need to wake from sleep quickly and frequently. 8.2.3.2 peripheral usage in sleep some peripherals that can operate in sleep mode will not operate properly with the low-power sleep mode selected. the low-power sleep mode is intended for use with these peripherals: brown-out reset (bor) watchdog timer (wdt) external interrupt pin/interrupt-on-change pins timer 1 (with external clock source) it is the responsibility of the end user to determine what is acceptable for their application when setting the vregpm settings in order to ensure operation in sleep. 8.2.4 idle mode when the idle enable (idlen) bit is clear (idlen = 0 ), the sleep instruction will put the device into full sleep mode (see section 8.2 ?sleep mode? ). when idlen is set (idlen = 1 ), the sleep instruction will put the device into idle mode. in idle mode, the cpu and mem- ory operations are halted, but the peripheral clocks continue to run. this mode is similar to doze mode, except that in idle both the cpu and program memory are shut off. 8.2.4.1 idle and interrupts idle mode ends when an interrupt occurs (even if gie = 0 ), but idlen is not changed. the device can re-enter idle by executing the sleep instruction. if recover-on-interrupt is enabled (roi = 1 ), the interrupt that brings the device out of idle also restores full-speed cpu execution when doze is also enabled. 8.2.4.2 idle and wdt when in idle, the wdt reset is blocked and will instead wake the device. the wdt wake-up is not an interrupt, therefore roi does not apply. note: the pic16lf18326/18346 does not have a configurable low-power sleep mode. pic16lf18326/18346 is an unregulated device and is always in the lowest power state when in sleep, with no wake-up time penalty. this device has a lower maximum v dd and i/o voltage than the pic16f18326/18346. see section 34.0 ?electrical specifications? for more information. note: peripherals using f osc will continue running while in idle (but not in sleep). note: if clkout is enabled (clkout = 0 , configuration word 1), the output will continue operating while in idle. note: the wdt can bring the device out of idle, in the same way it brings the device out of sleep. the dozen bit is not affected. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 114 preliminary ? 2016 microchip technology inc. 8.3 register definitions: voltage regulator control register 8-1: vregcon: voltag e regulator control register (1) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-1/1 vregpm reserved bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-2 unimplemented: read as 0 bit 1 vregpm: voltage regulator power mode selection bit 1 = low-power sleep mode enabled in sleep (2) ; draws lowest current in sleep, slower wake-up 0 = normal-power sleep mode enabled in sleep (2) ; draws higher current in sleep, faster wake-up bit 0 reserved: read as 1 . maintain this bit set. note 1: pic16f18326/18346 only. 2: see section 34.0 ?electrical specifications? . register 8-2: cpudoze: doze and idle register r/w-0/u r/w/hc/hs-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 idlen dozen (1,2) roi doe doze<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 idlen: idle enable bit 1 =a sleep instruction inhibits the cpu cloc k, but not the peripheral clock(s) 0 =a sleep instruction places the device into full-sleep mode bit 6 dozen: doze enable bit (1,2) 1 = the cpu executes instruction cycles according to doze setting 0 = the cpu executes all instruction cycles (fastest, highest power operation) bit 5 roi: recover-on-interrupt bit 1 = entering the interrupt service routine (isr) makes dozen = 0 bit, bringing the cpu to full-speed operation. 0 = interrupt entry does not change dozen bit 4 doe: doze-on-exit bit 1 = executing retfie makes dozen = 1 , bringing the cpu to reduced speed operation. 0 = retfie does not change dozen bit 3 unimplemented: read as 0 bit 2-0 doze<2:0>: ratio of cpu instruction cycles to peripheral instruction cycles 111 = 1:256 110 =1:128 101 =1:64 100 =1:32 011 =1:16 010 =1:8 001 =1:4 000 =1:2 note 1: when roi = 1 or doe = 1 , dozen is changed by hardware interrupt entry and/or exit. 2: entering icd overrides dozen, returning the cpu to full execution speed; this bit is not affected. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 115 pic16(l)f18326/18346 table 8-1: summary of registers as sociated with power-down mode name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie i n t e d g 98 pie0 t m r 0 i ei o c i e i n t e 99 pie1 tmr1gie adie rcie txie ssp1ie bcl1ie tmr2ie tmr1ie 100 pie2 tmr6ie c2ie c1ie nvmie ssp2ie bcl2ie tmr4ie nco1ie 101 pie3 osfie cswie tmr3gie tmr3ie clc4ie clc3ie clc2ie clc1ie 102 pie4 cwg2ie cwg1ie tmr5gie tmr5ie ccp4ie ccp3ie ccp2ie ccp1ie 103 pir0 t m r 0 i fi o c i f intf 104 pir1 tmr1gif adif rcif txif ssp1if bcl1if tmr2if tmr1if 105 pir2 tmr6if c2if c1if nvmif ssp2if bcl2if tmr4if nco1if 106 pir3 osfif cswif tmr3gif tmr3if clc4if clc3if clc2if clc1if 107 pir4 cwg2if cwg1if tmr5gif tmr5if ccp4if ccp3if ccp2if ccp1if 108 iocap iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 172 iocan iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 172 iocaf iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 173 iocbp (1) iocbp7 iocbp6 iocbp5 iocbp4 173 iocbn (1) iocbn7 iocbn6 iocbn5 iocbn4 174 iocbf (1) iocbf7 iocbf6 iocbf5 iocbf4 174 ioccp ioccp7 (1) ioccp6 (1) ioccp5 ioccp4 ioccp3 ioccp2 ioccp1 ioccp0 175 ioccn ioccn7 (1) ioccn6 (1) ioccn5 ioccn4 ioccn3 ioccn2 ioccn1 ioccn0 175 ioccf ioccf7 (1) ioccf6 (1) ioccf5 ioccf4 ioccf3 ioccf2 ioccf1 ioccf0 176 status t o pd zd c c 27 vregcon (2) v r e g p m 114 cpudoze idlen dozen roi doe doze<2:0> 114 wdtcon w d t p s < 4 : 0 >s w d t e n 118 legend: = unimplemented location, read as 0 . shaded cells are not used in power-down mode. note 1: pic16(l)f18346 only. 2: pic16f18326/18346 only. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 116 preliminary ? 2016 microchip technology inc. 9.0 watchdog timer (wdt) the watchdog timer is a system timer that generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the watchdog timer is typically used to recover the system from unexpected events. the wdt has the following features: independent clock source multiple operating modes - wdt is always on - wdt is off when in sleep - wdt is controlled by software - wdt is always off configurable time-out period is from 1 ms to 256 seconds (nominal) multiple reset conditions operation during sleep figure 9-1: watchdog ti mer block diagram lfintosc 23-bit programmable prescaler wdt wdt time-out wdtps<4:0> swdten sleep wdte<1:0> = 11 wdte<1:0> = 01 wdte<1:0> = 10 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 117 pic16(l)f18326/18346 9.1 independent clock source the wdt derives its time base from the 31 khz lfintosc internal oscillator. time intervals in this chapter are based on a nominal interval of 1 ms. see table 34-8 for the lfintosc specification. 9.2 wdt operating modes the watchdog timer module has four operating modes controlled by the wdte<1:0> bits in configuration words (see tab le 9 - 1 ). 9.2.1 wdt is always on when the wdte bits of configuration words are set to 11 , the wdt is always on. wdt protection is active during sleep. 9.2.2 wdt is off in sleep when the wdte bits of configuration words are set to 10 , the wdt is on, except in sleep. wdt protection is not active during sleep. 9.2.3 wdt controlled by software when the wdte bits of configuration words are set to 01 , the wdt is controlled by the swdten bit of the wdtcon register. wdt protection is unchanged by sleep. see table 9-1 for more details. 9.3 time-out period the wdtps<4:0> bits of the wdtcon register set the time-out period from 1 ms to 256 seconds (nominal). after a reset, the default time-out period is two seconds. 9.4 clearing the wdt the wdt is cleared when any of the following conditions occur: any reset clrwdt instruction is executed device enters sleep device wakes up from sleep oscillator fail wdt is disabled oscillator start-up timer (ost) is running see table 9-2 for more information. 9.5 operation during sleep when the device enters sleep, the wdt is cleared. if the wdt is enabled during sleep, the wdt resumes counting. when the device exits sleep, the wdt is cleared again. the wdt remains clear until the ost, if enabled, completes. see section 6.0 ?oscillator module (with fail-safe clock monitor)? for more information on the ost. when a wdt time-out occurs while the device is in sleep, no reset is generated. instead, the device wakes up and resumes operation. the to and pd bits in the status register are changed to indicate the event. see status register ( register 3-1 ) for more information. table 9-1: wdt operating modes wdte<1:0> swdten device mode wdt mode 11 x xa c t i v e 10 x awake active sleep disabled 01 1 x active 0 disabled 00 x x disabled table 9-2: wdt clearing conditions conditions wdt wdte = 00 cleared and disabled wdte = 01 and swdten = 0 exit sleep due to a reset + system clock = xt, hs, lp cleared until the end of ost exit sleep due to a reset + system clock = hfintosc, lfintosc, ec, sosc exit sleep due to an interrupt cleared enter sleep clrwdt command oscillator failure (see section 6.4 ?fail-safe clock monitor? ) system reset any clock switch or divider change (see section 6.3 ?clock switching? )u n a f f e c t e d downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 118 preliminary ? 2016 microchip technology inc. 9.6 register definitions: watchdog control register 9-1: wdtcon: wat chdog timer control register u-0 u-0 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 r/w-1/1 r/w-0/0 wdtps<4:0> (1) swdten bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -m/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-1 wdtps<4:0>: watchdog timer period select bits (1) bit value = prescale rate 11111 = reserved. results in minimum interval (1:32) 10011 = reserved. results in minimum interval (1:32) 10010 = 1:8388608 (2 23 ) (interval 256s nominal) 10001 = 1:4194304 (2 22 ) (interval 128s nominal) 10000 = 1:2097152 (2 21 ) (interval 64s nominal) 01111 = 1:1048576 (2 20 ) (interval 32s nominal) 01110 = 1:524288 (2 19 ) (interval 16s nominal) 01101 = 1:262144 (2 18 ) (interval 8s nominal) 01100 = 1:131072 (2 17 ) (interval 4s nominal) 01011 = 1:65536 (interval 2s nominal) (reset value) 01010 = 1:32768 (interval 1s nominal) 01001 = 1:16384 (interval 512 ms nominal) 01000 = 1:8192 (interval 256 ms nominal) 00111 = 1:4096 (interval 128 ms nominal) 00110 = 1:2048 (interval 64 ms nominal) 00101 = 1:1024 (interval 32 ms nominal) 00100 = 1:512 (interval 16 ms nominal) 00011 = 1:256 (interval 8 ms nominal) 00010 = 1:128 (interval 4 ms nominal) 00001 = 1:64 (interval 2 ms nominal) 00000 = 1:32 (interval 1 ms nominal) bit 0 swdten: software enable/disable for watchdog timer bit if wdte<1:0> = 1x : this bit is ignored. if wdte<1:0> = 01 : 1 = wdt is turned on 0 = wdt is turned off if wdte<1:0> = 00 : this bit is ignored. note 1: times are approximate. wdt time is based on 31 khz lfintosc. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 119 pic16(l)f18326/18346 table 9-3: summary of registers associated with watchdog timer name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page s t a t u s t o pd zd cc 27 wdtcon wdtps<4:0> swdten 118 legend: x = unknown, u = unchanged, C = unimplemented locations read as 0 . shaded cells are not used by watchdog timer. table 9-4: summary of configurat ion word with watchdog timer name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config2 13:8 debug stvren pps1way borv 61 7:0 boren1 boren0 lpboren w d t e 1w d t e 0 pwrte mclre legend: = unimplemented location, read as 0 . shaded cells are not used by watchdog timer. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 120 preliminary ? 2016 microchip technology inc. 10.0 nonvolatile memory (nvm) control nvm is separated into two types: program flash memory and data eeprom. nvm is accessible by using both the fsr and indf registers, or through the nvmreg register interface. the write time is controlled by an on-chip timer. the write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. nvm can be protected in two ways; by either code protection or write protection. code protection (cp and cpd bits in configuration word 4) disables access, reading and writing, to both the program flash memory and eeprom via external device programmers. code protection does not affect the self-write and erase functionality. code protection can only be reset by a device programmer performing a bulk erase to the device, clearing all nonvolatile memory, configuration bits, and user ids. write protection prohibits self-write and erase to a portion or all of the program flash memory, as defined by the wrt<1:0> bits of configuration word 3. write protection does not affect a device programmers ability to read, write, or erase the device. 10.1 program flash memory program flash memory consists of 8192 14-bit words as user memory, with additional words for user id information, configuration words, and interrupt vectors. program flash memory provides storage locations for: user program instructions user defined data program flash memory data can be read and/or written to through: cpu instruction fetch (read-only) fsr/indf indirect access (read-only) ( section 10.3 ?fsr and indf access? ) nvmreg access ( section 10.4 ?nvmreg access? in-circuit serial programming? (icsp?) read operations return a single word of memory. when write and erase operations are done on a row basis, the row size is defined in table 10-1 . program flash memory will erase to a logic 1 and program to a logic 0 . it is important to understand the program flash memory structure for erase and programming operations. program flash memory is arranged in rows. a row consists of 32 14-bit program memory words. a row is the minimum size that can be erased by user software. after a row has been erased, all or a portion of this row can be programmed. data to be written into the program memory row is written to 14-bit wide data write latches. these latches are not directly accessible to the user, but may be loaded via sequential writes to the nvmdath:nvmdatl register pair. 10.1.1 program memory voltages the program flash memory is readable and writable during normal operation over the full v dd range. 10.1.1.1 programming externally the program memory cell and control logic support write and bulk erase operations down to the minimum device operating voltage. special bor operation is enabled during bulk erase ( section 5.2.3.1 ?bor protection is unchanged by sleep? ). 10.1.1.2 self-programming the program memory cell and control logic will support write and row erase operations across the entire v dd range. bulk erase is not supported when self-programming. table 10-1: flash memory organization by device device row erase (words) write latches (words) pic16(l)f18326 32 32 pic16(l)f18346 note: to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in ram prior to the erase. then, the new data and retained data can be written into the write latches to reprogram the row of program flash memory. however, any unprogrammed locations can be written without first erasing the row. in this case, it is not necessary to save and rewrite the other previously programmed locations downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 121 pic16(l)f18326/18346 10.2 data eeprom data eeprom consists of 256 bytes of user data memory. the eeprom provides storage locations for 8-bit user defined data. eeprom can be read and/or written through: fsr/indf indirect access ( section 10.3 ?fsr and indf access? ) nvmreg access ( section 10.4 ?nvmreg access? ) in-circuit serial programming (icsp) unlike program flash memory, which must be written to by row, eeprom can be written to word by word. 10.3 fsr and indf access the fsr and indf registers allow indirect access to the program flash memory or eeprom. 10.3.1 fsr read with the intended address loaded into an fsr register, a moviw instruction or read of indf will read data from the program flash memory or eeprom. reading from nvm requires one instruction cycle. the cpu operation is suspended during the read, and resumes immediately after. read operations return a single word of memory. 10.3.2 fsr write writing/erasing the nvm through the fsr registers (ex. movwi instruction) is not supported in the pic16(l)f18326/18346 devices. 10.4 nvmreg access the nvmreg interface allows read/write access to all the locations accessible by fsrs, and also read/write access to the user id locations, and read-only access to the device identification, revision, and configuration data. reading, writing, or erasing of nvm via the nvmreg interface is prevented when the device is code-protected. 10.4.1 nvmreg read operation to read a nvm location using the nvmreg interface, the user must: 1. clear the nvmregs bit of the nvmcon1 register if the user intends to access program flash memory locations, or set nvmregs if the user intends to access user id, configuration, or eeprom locations. 2. write the desired address into the nvmadrh:nvmadrl register pair ( table 10-2 ). 3. set the rd bit of the nvmcon1 register to initiate the read. once the read control bit is set, the cpu operation is suspended during the read, and resumes immediately after. the data is available in the very next cycle, in the nvmdath:nvmdatl register pair; therefore, it can be read as two bytes in the following instructions. nvmdath:nvmdatl register pair will hold this value until another read or until it is written to by the user. upon completion, the rd bit is cleared by hardware. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 122 preliminary ? 2016 microchip technology inc. figure 10-1: program flash memory read flowchart example 10-1: program flash memory read end read operation select memory: program flash memory, eeprom, config. words, user id (nvmregs) select word address (nvmadrh:nvmadrl) start read operation initiate read operation (rd = 1 ) data read now in nvmdath:nvmdatl * this code block will read 1 word of program * memory at the memory address: prog_addr_hi : prog_addr_lo * data will be returned in the variables; * prog_data_hi, prog_data_lo banksel nvmadrl ; select bank for nvmcon registers movlw prog_addr_lo ; movwf nvmadrl ; store lsb of address movlw prog_addr_hi ; movwf nvmadrh ; store msb of address bcf nvmcon1,nvmregs ; do not select configuration space bsf nvmcon1,rd ; initiate read movf nvmdatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf nvmdath,w ; get msb of word movwf prog_data_hi ; store in user location downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 123 pic16(l)f18326/18346 10.4.2 nvm unlock sequence the unlock sequence is a mechanism that protects the nvm from unintended self-write programming or eras- ing. the sequence must be executed and completed without interruption to successfully complete any of the following operations: program flash memory row erase load of program flash memory write latches write of program flash memory write latches to program flash memory memory write of program flash memory write latches to user ids write to eeprom the unlock sequence consists of the following steps and must be completed in order: write 55h to nvmcon2 write aah to nmvcon2 set the wr bit of nvmcon1 once the wr bit is set, the processor will stall internal operations until the operation is complete and then resume with the next instruction. since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. figure 10-2: nvm unlock sequence flowchart example 10-2: nvm unlock sequence note: the two nop instructions after setting the wr bit, which were required in previous devices, are not required for pic16(l)f18326/18346 devices. see figure 10-2 . end unlock operation write 55h to nvmcon2 write aah to nvmcon2 initiate write or erase operation (wr = 1 ) nop instruction (not required for pic16(l)f18326/18346 devices) nop instruction (not required for pic16(l)f18326/18346 devices) start unlock sequence note 1: sequence begins when nvmcon2 is written; steps 1-4 must occur in the cy cle-accurate order shown. 2: opcodes shown are illustrative; any instruction that has the indicated eff ect may be used. banksel nvmcon1 bsf nvmcon1,wren ; enable write/erase movlw 55h ; load 55h bcf intcon,gie ; recommended so sequence is not interrupted movwf nvmcon2 ; step 1: load 55h into nvmcon2 movlw aah ; step 2: load w with aah movwf nvmcon2 ; step 3: load aah into nvmcon2 bsf nvmcon1,wr ; step 4: set wr bit to begin write/erase bsf intcon,gie ; re-enable interrupts downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 124 preliminary ? 2016 microchip technology inc. 10.4.3 nvmreg write to eeprom writing to the eeprom is accomplished by the following steps: 1. set the nvmregs and wren bits of the nvmcon1 register. 2. write the desired address (address +7000h) into the nvmadrh:nvmadrl register pair ( ta b l e 1 0 - 2 ). 3. perform the unlock sequence as described in section 10.4.2 ?nvm unlock sequence? . a single eeprom word is written with nvmdata. the operation includes an implicit erase cycle for that word (it is not necessary to set the free bit), and requires many instruction cycles to finish. cpu execution continues in parallel and, when complete, wr is cleared by hardware, nvmif is set, and an interrupt will occur if nvmie is also set. software must poll the wr bit to determine when writing is complete, or wait for the interrupt to occur. wren will remain unchanged. once the eeprom write operation begins, clearing the wr bit will have no effect; the operation will continue to run to completion. 10.4.4 nvmreg erase of program flash memory before writing to program flash memory, the word(s) to be written must be erased or previously unwritten. pro- gram flash memory can only be erased one row at a time. no automatic erase occurs upon the initiation of the write to program flash memory. to erase a program flash memory row: 1. clear the nvmregs bit of the nvmcon1 register to erase program flash memory locations, or set the nvmregs bit to erase user id locations. 2. write the desired address into the nvmadrh:nvmadrl register pair ( ta b l e 1 0 - 2 ). 3. set the free and wren bits of the nvmcon1 register. 4. perform the unlock sequence as described in section 10.4.2 ?nvm unlock sequence? . if the program flash memory address is write-pro- tected, the wr bit will be cleared and the erase opera- tion will not take place. while erasing program flash memory, cpu operation is suspended, and resumes when the operation is complete. upon completion, the nvmif is set, and an interrupt will occur if the nvmie bit is also set. write latch data is not affected by erase operations, and wren will remain unchanged. figure 10-3: nvm erase flowchart unlock sequence ( figure 10-2 ) end erase operation select memory: program flash memory, config. words, user id (nvmregs) disable write/erase operation (wren = 0 ) select word address (nvmadrh:nvmadrl) start erase operation cpu stalls while erase operation completes (2 ms typical) select erase operation (free = 1 ) disable interrupts (gie = 0 ) enable interrupts (gie = 1 ) enable write/erase operation (wren = 1 ) downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 125 pic16(l)f18326/18346 example 10-3: erasing one row of program flash memory ; this sample row erase routine assumes the following: ; 1.a valid address within the erase row is loaded in variables addrh:addrl ; 2.addrh and addrl are located in common ram (locations 0x70 - 0x7f) banksel nvmadrl movf addrl,w movwf nvmadrl ; load lower 8 bits of erase address boundary movf addrh,w movwf nvmadrh ; load upper 6 bits of erase address boundary bcf nvmcon1,nvmregs ; choose program flash memory area bsf nvmcon1,free ; specify an erase operation bsf nvmcon1,wren ; enable writes bcf intcon,gie ; disable interrupts during unlock sequence ; -------------------------------required unlock sequence:------------------------------ movlw 55h ; load 55h to get ready for unlock sequence movwf nvmcon2 ; first step is to load 55h into nvmcon2 movlw aah ; second step is to load aah into w movwf nvmcon2 ; third step is to load aah into nvmcon2 bsf nvmcon1,wr ; final step is to set wr bit ; -------------------------------------------------------------------------------------- bsf intcon,gie ; re-enable interrupts, erase is complete bcf nvmcon1,wren ; disable writes table 10-2: nvm organization and access information master values nvmreg access fsr access memory function program counter (pc), icsp? address memory type nvmregs bit (nvmcon1) nvmadr <14:0> allowed operations fsr address fsr programming address reset vector 0000h program flash memory 0 0000h read write 8000h read-only user memory 0001h 0 0001h 8001h 0003h 0003h 8003h int vector 0004h 0 0004h 8004h user memory 0005h 0 0005h 8005h 17ffh 17ffh ffffh user id no pc address program flash memory 1 0000h read no access 0003h reserved 0004h rev id program flash memory 1 0005h read device id 1 0006h config1 1 0007h config2 1 0008h config3 1 0009h config4 000ah user memory eeprom 1 7000h read f000h read-only 70ffh write f0ffh downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 126 preliminary ? 2016 microchip technology inc. 10.4.5 nvmreg write to program flash memory program memory is programmed using the following steps: 1. load the address of the row to be programmed into nvmadrh:nvmadrl. 2. load each write latch with data. 3. initiate a programming operation. 4. repeat steps 1 through 3 until all data is written. before writing to program memory, the word(s) to be written must be erased or previously unwritten. program memory can only be erased one row at a time. no automatic erase occurs upon the initiation of the write. program memory can be written one or more words at a time. the maximum number of words written at one time is equal to the number of write latches. see figure 10-4 (row writes to program memory with 32 write latches) for more details. the write latches are aligned to the flash row address boundary defined by the upper ten bits of nvmadrh:nvmadrl, (nvmadrh<6:0>:nvmadrl<7:5>) with the lower five bits of nvmadrl, (nvmadrl<4:0>) determining the write latch being loaded. write opera- tions do not cross these boundaries. at the completion of a program memory write operation, the data in the write latches is reset to contain 0x3fff. the following steps should be completed to load the write latches and program a row of program memory. these steps are divided into two parts. first, each write latch is loaded with data from the nvmdath:nvmdatl using the unlock sequence with lwlo = 1 . when the last word to be loaded into the write latch is ready, the lwlo bit is cleared and the unlock sequence executed. this initiates the programming operation, writing all the latches into flash program memory. 1. set the wren bit of the nvmcon1 register. 2. clear the nvmregs bit of the nvmcon1 register. 3. set the lwlo bit of the nvmcon1 register. when the lwlo bit of the nvmcon1 register is 1 , the write sequence will only load the write latches and will not initiate the write to flash program memory. 4. load the nvmadrh:nvmadrl register pair with the address of the location to be written. 5. load the nvmdath:nvmdatl register pair with the program memory data to be written. 6. execute the unlock sequence ( section 10.4.2 ?nvm unlock sequence? ). the write latch is now loaded. 7. increment the nvmadrh:nvmadrl register pair to point to the next location. 8. repeat steps 5 through 7 until all but the last write latch has been loaded. 9. clear the lwlo bit of the nvmcon1 register. when the lwlo bit of the nvmcon1 register is 0 , the write sequence will initiate the write to flash program memory. 10. load the nvmdath:nvmdatl register pair with the program memory data to be written. 11. execute the unlock sequence ( section 10.4.2 ?nvm unlock sequence? ). the entire program memory latch content is now written to flash program memory. an example of the complete write sequence is shown in example 10-4 . the initial address is loaded into the nvmadrh:nvmadrl register pair; the data is loaded using indirect addressing. note: the special unlock sequence is required to load a write latch with data or initiate a flash programming operation. if the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. note: the program memory write latches are reset to the blank state (0x3fff) at the completion of every write or erase operation. as a result, it is not necessary to load all the program memory write latches. unloaded latches will remain in the blank state. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 127 pic16(l)f18326/18346 figure 10-4: block writes to program flash memory with 32 write latches 6 8 14 14 14 write latch #31 1fh 14 14 program memory write latches 14 14 14 nvmadrh<6:0> nvmadrl<7:5> program flash memory row row address decode addr write latch #30 1eh write latch #1 01h write latch #0 00h addr addr addr 000h 001fh 001eh 0000h 0001h 001h 003fh 003eh 0020h 0021h 002h 005fh 005eh 0040h 0041h 3feh 7fdfh 7fdeh 7fc0h 7fc1h 3ffh 7fffh 7ffeh 7fe0h 7fe1h 14 nvmadrl<4:0> 400h 800bh - 801fh 8000h - 8003h configuration words user id 0 - 3 8007h C 800ah 8005h -8006h device id dev / rev reserved reserved configuration memory nvmregs = 0 nvmregs = 1 nvmadrh nvmadrl 7 6 0 7 5 4 0 c4 c3 c2 c1 c0 r9 r8 r7 r6 r5 r4 r3 - r1 r0 r2 5 10 nvmdath nvmdatl 7 5 0 7 0 - - 8004h downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 128 preliminary ? 2016 microchip technology inc. figure 10-5: program flash memory write flowchart start write operation determine number of words to be written into pfm or configuration memory. the number of words cannot exceed the number of words per row (word_cnt) select pfm or config. memory (nvmregs) select row address (nvmadrh:nvmadrl) select write operation (free = 0 ) load write latches only (lwlo = 1 ) disable interrupts (gie = 0 ) enable write/erase operation (wren = 1 ) load the value to write (nvmdath:nvmdatl) update the word counter (word_cnt--) last word to write? unlock sequence no delay when writing to pfm latches re-enable interrupts (gie = 1 ) write latches to pfm (lwlo = 0 ) disable interrupts (gie = 0 ) cpu stalls while write operation completes (2 ms typical) disable write/erase operation (wren = 0 ) end write operation increment address (nvmadrh:nvmadrl++) unlock sequence re-enable interrupts (gie = 1 ) yes no ( figure 10-2 ) ( figure 10-2 ) downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 129 pic16(l)f18326/18346 example 10-4: writing to program flash memory ; this write routine assumes the following: ; 1. 64 bytes of data are loaded, starting at the address in data_addr ; 2. each word of data to be written is made up of two adjacent bytes in data_addr, ; stored in little endian format ; 3. a valid starting address (the least significant bits = 00000) is loaded in addrh:addrl ; 4. addrh and addrl are located in common ram (locations 0x70 - 0x7f) ; 5. nvm interrupts are not taken into account banksel nvmadrh movf addrh,w movwf nvmadrh ; load initial address movf addrl,w movwf nvmadrl movlw low data_addr ; load initial data address movwf fsr0l movlw high data_addr movwf fsr0h bcf nvmcon1,nvmregs ; set program flash memory as write location bsf nvmcon1,wren ; enable writes bsf nvmcon1,lwlo ; load only write latches loop moviw fsr0++ movwf nvmdatl ; load first data byte moviw fsr0++ movwf nvmdath ; load second data byte movf nvmadrl,w xorlw 0x1f ; check if lower bits of address are 00000 andlw 0x1f ; and if on last of 32 addresses btfsc status,z ; last of 32 words? goto start_write ; if so, go write latches into memory call unlock_seq ; if not, go load latch incf nvmadrl,f ; increment address goto loop start_write bcf nvmcon1,lwlo ; latch writes complete, now write memory call unlock_seq ; perform required unlock sequence bcf nvmcon1,wren ; disable writes unlock_seq movlw 55h bcf intcon,gie ; disable interrupts movwf nvmcon2 ; begin unlock sequence movlw aah movwf nvmcon2 bsf nvmcon1,wr bsf intcon,gie ; unlock sequence complete, re-enable interrupts return downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 130 preliminary ? 2016 microchip technology inc. 10.4.6 modifying program flash memory when modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a ram image. program memory is modified using the following steps: 1. load the starting address of the row to be modified. 2. read the existing data from the row into a ram image. 3. modify the ram image to contain the new data to be written into program memory. 4. load the starting address of the row to be rewritten. 5. erase the program memory row. 6. load the write latches with data from the ram image. 7. initiate a programming operation. figure 10-6: program flash memory modify flowchart start modify operation read operation (figure x.x) erase operation (figure x.x) modify image the words to be modified are changed in the ram image end modify operation write operation use ram image (figure x.x) an image of the entire row read must be stored in ram figure 10-1 figure 10-3 figure 10-5 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 131 pic16(l)f18326/18346 10.4.7 nvmreg eeprom, user id, device id and configuration word access instead of accessing program flash memory, the eeprom, the user ids, device id/revision id and configuration words can be accessed when nvmregs = 1 in the nvmcon1 register. this is the region that would be pointed to by pc<15> = 1 , but not all addresses are accessible. different access may exist for reads and writes. refer to tab l e 1 0- 3 . when read access is initiated on an address outside the parameters listed in table 10-3 , the nvmdath: nvmdatl register pair is cleared, reading back 0 s. table 10-3: eeprom, user id, dev/re v id and configuration word access (nvmregs = 1 ) address function read access write access 8000h-8003h user ids yes yes 8005h-8006h device id/revision id yes no 8007h-800ah configuration words 1-4 yes no f000h-f0ffh eeprom yes yes downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 132 preliminary ? 2016 microchip technology inc. example 10-5: device id access ; this write routine assumes the following: ; 1. 64 bytes of data are loaded, starting at the address in data_addr ; 2. each word of data to be written is made up of two adjacent bytes in data_addr, ; stored in little endian format ; 3. a valid starting address (the least significant bits = 00000) is loaded in addrh:addrl ; 4. addrh and addrl are located in common ram (locations 0x70 - 0x7f) ; 5. nvm interrupts are not taken into account banksel nvmadrh movf addrh,w movwf nvmadrh ; load initial address movf addrl,w movwf nvmadrl movlw low data_addr ; load initial data address movwf fsr0l movlw high data_addr movwf fsr0h bcf nvmcon1,nvmregs ; set program flash memory as write location bsf nvmcon1,wren ; enable writes bsf nvmcon1,lwlo ; load only write latches loop moviw fsr0++ movwf nvmdatl ; load first data byte moviw fsr0++ movwf nvmdath ; load second data byte movf nvmadrl,w xorlw 0x1f ; check if lower bits of address are 00000 andlw 0x1f ; and if on last of 32 addresses btfsc status,z ; last of 32 words? goto start_write ; if so, go write latches into memory call unlock_seq ; if not, go load latch incf nvmadrl,f ; increment address goto loop start_write bcf nvmcon1,lwlo ; latch writes complete, now write memory call unlock_seq ; perform required unlock sequence bcf nvmcon1,wren ; disable writes unlock_seq movlw 55h bcf intcon,gie ; disable interrupts movwf nvmcon2 ; begin unlock sequence movlw aah movwf nvmcon2 bsf nvmcon1,wr bsf intcon,gie ; unlock sequence complete, re-enable interrupts return downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 133 pic16(l)f18326/18346 10.4.8 write verify it is considered good programming practice to verify that program memory writes agree with the intended value. since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in ram after the last write is complete. figure 10-7: program flash memory verify flowchart start verify operation read operation end verify operation this routine assumes that the last row of data written was from an image saved in ram. this image will be used to verify the data currently stored in flash program memory. nvmdat = ram image? last word? fail verify operation no yes yes no figure 10-1 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 134 preliminary ? 2016 microchip technology inc. 10.4.9 wrerr bit the wrerr bit can be used to determine if a write error occurred. wrerr will be set if one of the following conditions occurs: if wr is set while the nvmadrh:nmvadrl points to a write-protected address a reset occurs while a self-write operation was in progress an unlock sequence was interrupted the wrerr bit is normally set by hardware, but can be set by the user for test purposes. once set, wrerr must be cleared in software. table 10-4: actions for progra m flash memory when wr = 1 free lwlo actions for program flash memory when wr = 1 comments 00 write the write latch data to program flash memory row. see section 10.4.4 ?nvmreg erase of pro- gram flash memory? if wp is enabled, wr is cleared and wrerr is set write latches are reset to 3ffh nvmdath:nvmdatl is ignored 01 copy nvmdath:nvmdatl to the write latch corre- sponding to nvmadr lsbs. see section 10.4.4 ?nvmreg erase of program flash memory? write protection is ignored no memory access occurs 1x erase the 32-word row of nvmadrh:nvmadrl location. see section 10.4.3 ?nvmreg write to eeprom? if wp is enabled, wr is cleared and wrerr is set all 32 words are erased nvmdath:nvmdatl is ignored downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 135 pic16(l)f18326/18346 10.5 register definitions: program flash memory control register 10-1: nvmdatl: nonvolatil e memory data low byte register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 nvmdat<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 nvmdat<7:0> : read/write value for least signifi cant bits of program memory register 10-2: nvmdath: nonvolatil e memory data high byte register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 nvmdat<13:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 nvmdat<13:8> : read/write value for most signi ficant bits of program memory register 10-3: nvmadrl: nonvolatile memory address low byte register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 nvmadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 nvmadr<7:0> : specifies the least significant bits for program memory address register 10-4: nvmadrh: nonvolatile memory address high byte register u-1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 nvmadr<14:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 1 bit 6-0 nvmadr<14:8> : specifies the most significant bits for program memory address downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 136 preliminary ? 2016 microchip technology inc. register 10-5: nvmcon1: nonvolat ile memory control 1 register u-0 r/w-0/0 r/w-0/0 r/w/hc-0/0 r/w/hc-x/q r/w-0/0 r/s/hc-0/0 r/s/hc-0/0 nvmregs lwlo free wrerr wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hc = bit is cleared by hardware bit 7 unimplemented: read as 0 bit 6 nvmregs: configuration select bit 1 = access eeprom, configuration, user id and device id registers 0 = access program flash memory bit 5 lwlo: load write latches only bit when free = 0 : 1 = the next wr command updates the write latch for this word within the row; no memory op eration is initiated. 0 = the next wr command writes data or erases otherwise: the bit is ignored. bit 4 free: program flash memory erase enable bit when nvmregs:nvmadr points to a program flash memory location: 1 = performs an erase operation with the next wr command; the 32-word pseudo-row containing the indicated address is erased (to all 1s) to prepare for writing. 0 = all write operations have completed normally bit 3 wrerr: program/erase error flag bit (1,2,3) this bit is normally set by hardware. 1 = a write operation was interrupted by a reset, interrupted unlock sequence, or wr was written to one while nvmadr points to a write-protected address. 0 = the program or erase operation completed normally bit 2 wren: program/erase enable bit 1 = allows program/erase cycles 0 = inhibits programming/erasing of program flash bit 1 wr: write control bit (4,5,6) when nvmreg:nvmadr points to a eeprom location: 1 = initiates an erase/program cycle at the corresponding eeprom location 0 = nvm program/erase operation is complete and inactive when nvmreg:nvmadr points to a program flash memory location: 1 = initiates the operation indicated by table 10-5 0 = nvm program/erase operation is complete and inactive otherwise: this bit is ignored. bit 0 rd: read control bit (7) 1 = initiates a read at address = nvmadr1, and loads data to nvmdat read takes one instruction cycle and the bit is cleared when the operation is complete. the bit can only be set (not cleared) in software. 0 = nvm read operation is complete and inactive. note 1: bit is undefined while wr = 1 (during the eeprom write operation it may be 0 or 1 ). 2: bit must be cleared by software; hardware will not clear this bit. 3: bit may be written to 1 by software in order to implement test sequences. 4: this bit can only be set by following the unlock sequence of section 10.4.2 ?nvm unlock sequence? . 5: operations are self-timed, and the wr bit is cleared by hardware when complete. 6: once a write operation is initiated, setting this bit to zero will have no effect. 7: reading from eeprom loads only nvmdatl<7:0> ( register 10-1 ). downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 137 pic16(l)f18326/18346 register 10-6: nvmcon2: nonvolat ile memory control 2 register w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 nvmcon2 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 nvmcon2<7:0>: flash memory unlock pattern bits to unlock writes, a 55h must be written first, followed by an aah, before setting the wr bit of the nvmcon1 register. the value written to this register is used to unlock the writes. table 10-5: summary of registers associ ated with nonvolat ile memory (nvm) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie intedg 98 pir2 tmr6if c2if c1if nvmif ssp2if blc2if tmr4if nco1if 106 pie2 tmr6ie c2ie c1ie nvmie ssp2ie blc2ie tmr4ie nco1ie 101 nvmcon1 nvmregs lwlo free wrerr wren wr rd 136 nvmcon2 nvmcon2 137 nvmadrl nvmadr<7:0> 135 nvmadrh (1) nvmadr<14:8> 135 nvmdatl nvmdat<7:0> 135 nvmdath nvmdat<13:8> 135 legend: ? = unimplemented location, read as 0 . shaded cells are not used by nvm. note 1: unimplemented, read as 1 . table 10-6: summary of co nfiguration word with no nvolatile memory (nvm) name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config3 13:8 lvp 62 7:0 w r t < 1 : 0 > config4 13:8 63 7:0 c p d cp legend: ? = unimplemented location, read as 0 . shaded cells are not used by nvm. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 138 preliminary ? 2016 microchip technology inc. 11.0 i/o ports each port has ten standard registers for its operation. these registers are: portx registers (reads the levels on the pins of the device) latx registers (output latch) trisx registers (data direction) anselx registers (analog select) wpux registers (weak pull-up) inlvlx (input level control) slrconx registers (slew rate) odconx registers (open-drain) most port pins share functions with device peripherals, both analog and digital. in general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output; however, the pin can still be read. the data latch (latx registers) is useful for read-modify-write operations on the value that the i/o pins are driving. a write operation to the latx register has the same effect as a write to the corresponding portx register. a read of the latx register reads of the values held in the i/o port latches, while a read of the portx register reads the actual i/o pin value. ports that support analog inputs have an associated anselx register. when an ansel bit is set, the digital input buffer associated with that bit is disabled. disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 11-1. figure 11-1: generic i/o port operation 11.1 i/o priorities each pin defaults to the port data latch after reset. other functions are selected with the peripheral pin select logic. see section 12.0 ?peripheral pin select (pps) module? for more information. analog input functions, such as adc and comparator inputs, are not shown in the peripheral pin select lists. these inputs are active when the i/o pin is set for analog mode using the anselx register. digital output functions may continue to control the pin when it is in analog mode. analog outputs, when enabled, take priority over the digital outputs and force the digital output driver to the high-impedance state. table 11-1: port availability per device device porta portb portc pic16(l)f18326 pic16(l)f18346 q d ck write latx data register i/o pin read portx write portx trisx read latx data bus to digital peripherals anselx v dd v ss to analog peripherals downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 139 pic16(l)f18326/18346 11.2 porta registers 11.2.1 data register porta is a 6-bit wide, bidirectional port. the corresponding data direction register is trisa ( register 11-2 ). setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., disable the output driver). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). the exception is ra3, which is input-only and its tris bit will always read as 1 . example 11-1 shows how to initialize porta. reading the porta register ( register 11-1 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (lata). the port data latch lata ( register 11-3 ) holds the output port data, and contains the latest value of a lata or porta write. example 11-1: initializing porta 11.2.2 direction control the trisa register ( register 11-2 ) controls the porta pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisa register are maintained set when using them as analog inputs. i/o pins configured as analog inputs always read 0 . 11.2.3 open-drain control the odcona register ( register 11-6 ) controls the open-drain feature of the port. open-drain operation is independently selected for each pin. when an odcona bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. when an odcona bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.2.4 slew rate control the slrcona register ( register 11-7 ) controls the slew rate option for each port pin. slew rate control is independently selectable for each port pin. when an slrcona bit is set, the corresponding port pin drive is slew rate limited. when an slrcona bit is cleared, the corresponding port pin drive slews at the maximum rate possible. 11.2.5 input threshold control the inlvla register ( register 11-8 ) controls the input voltage threshold for each of the available porta input pins. a selection between the schmitt trigger cmos or the ttl compatible thresholds is available. the input threshold is important in determining the value of a read of the porta register and also the level at which an interrupt-on-change occurs, if that feature is enabled. see table 34-4 for more information on threshold levels. ; this code example illustrates ; initializing the porta register. the ; other ports are initialized in the same ; manner. banksel porta ; clrf porta ;init porta banksel lata ;data latch clrf lata ; banksel ansela ; clrf ansela ;digital i/o banksel trisa ; movlw b'00111000' ;set ra<5:3> as inputs movwf trisa ;and set ra<2:0> as ;outputs note: it is not necessary to set open-drain control when using the pin for i 2 c; the i 2 c module controls the pin and makes the pin open-drain. note: changing the input threshold selection should be performed while all peripheral modules are disabled. changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 140 preliminary ? 2016 microchip technology inc. 11.2.6 analog control the ansela register ( register 11-4 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate ansela bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly. the state of the ansela bits has no effect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 11.2.7 weak pull-up control the wpua register ( register 11-5 ) controls the individual weak pull-ups for each port pin. porta pin ra3 includes the mclr /v pp input. the m clr input allows the device to be reset, and can be disabled by the mclre bit of configuration word 2. a weak pull-up is present on the ra3 port pin. this weak pull-up is enabled when mclr is enabled (mclre = 1 ) or the wpua3 bit is set. the weak pull-up is disabled when the mclr is disabled and the wpua3 bit is clear. 11.2.8 porta functions and output priorities each porta pin is multiplexed with other functions. each pin defaults to the port latch data after reset. other output functions are selected with the peripheral pin select logic. see section 12.0 ?peripheral pin select (pps) module? for more information. analog input functions, such as adc and comparator inputs are not shown in the peripheral pin select lists. digital output functions may continue to control the pin when it is in analog mode. note: the ansela bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to 0 by user software. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 141 pic16(l)f18326/18346 11.3 register definitions: porta register 11-1: porta: porta register u-0 u-0 r/w-x/u r/w-x/u r-x/u r/w-x/u r/w-x/u r/w-x/u r a 5r a 4r a 3 (2) ra2 ra1 ra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 ra<5:0> : porta i/o value bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to porta are actually written to corresponding lata register. reads from porta register is return of actual i/o pin values. 2: bit ra3 is read-only, and will read 1 when mclre = 1 (master clear enabled). register 11-2: trisa: porta tri-state register u-0 u-0 r/w-1/1 r/w-1/1 u-1 r/w-1/1 r/w-1/1 r/w-1/1 trisa5 trisa4 trisa2 trisa1 trisa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-4 trisa<5:4>: porta tri-state control bit 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output bit 3 unimplemented: read as 1 bit 2-0 trisa<2:0>: porta tri-state control bit 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 142 preliminary ? 2016 microchip technology inc. register 11-3: lata: porta data latch register u-0 u-0 r/w-x/u r/w-x/u u-0 r/w-x/u r/w-x/u r/w-x/u l a t a 5l a t a 4 lata2 lata1 lata0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-4 lata<5:4> : ra<5:4> output latch value bits (1) bit 3 unimplemented: read as 0 bit 2-0 lata<2:0> : ra<2:0> output latch value bits (1) note 1: writes to porta are actually written to corresponding lata register. reads from porta register is return of actual i/o pin values. register 11-4: ansela: porta analog select register u-0 u-0 r/w-1/1 r/w-1/1 u-0 r/w-1/1 r/w-1/1 r/w-1/1 ansa5 ansa4 ansa2 ansa1 ansa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-4 ansa<5:4> : analog select between analog or digital function on pins ra<5:4>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. bit 3 unimplemented: read as 0 bit 2-0 ansa<2:0> : analog select between analog or digital function on pins ra<2:0>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 143 pic16(l)f18326/18346 register 11-5: wpua: weak pull-up porta register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 wpua5 wpua4 wpua3 (1) wpua2 wpua1 wpua0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 wpua<5:0> : weak pull-up register bits (2) 1 = pull-up enabled 0 = pull-up disabled note 1: if mclre = 1 , the weak pull-up in ra3 is always enabled; bit wpua3 is not affected. 2: the weak pull-up device is automatically disabled if the pin is configured as an output. register 11-6: odcona: porta open-drain control register u-0 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 odca5 odca4 odca2 odca1 odca0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-4 odca<5:4>: porta open-drain enable bits for ra<5:4> pins, respectively 1 = port pin operates as open-drain drive (sink current only) 0 = port pin operates as standard push-pull drive (source and sink current) bit 3 unimplemented: read as 0 bit 2-0 odca<2:0>: porta open-drain enable bits for ra<2:0> pins, respectively 1 = port pin operates as open-drain drive (sink current only) 0 = port pin operates as standard push-pull drive (source and sink current) downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 144 preliminary ? 2016 microchip technology inc. register 11-7: slrcona: port a slew rate control register u-0 u-0 r/w-1/1 r/w-1/1 u-0 r/w-1/1 r/w-1/1 r/w-1/1 slra5 slra4 slra2 slra1 slra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-4 slra<5:4>: porta slew rate enable bits for ra<5:4> pins, respectively 1 = port pin slew rate is limited 0 = port pin slews at maximum rate bit 3 unimplemented: read as 0 bit 2-0 slra<2:0>: porta slew rate enable bits for ra<2:0> pins, respectively 1 = port pin slew rate is limited 0 = port pin slews at maximum rate register 11-8: inlvla: porta input level control register u-0 u-0 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 inlvla5 inlvla4 inlvla3 inlvla2 inlvla1 inlvla0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 inlvla<5:0>: porta input level select bits for ra<5:0> pins, respectively 1 = st input used for port reads and interrupt-on-change 0 = ttl input used for port reads and interrupt-on-change downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 145 pic16(l)f18326/18346 table 11-3: summary of conf iguration word with porta table 11-2: summary of regist ers associated with porta name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page porta ra5 ra4 ra3 ra2 ra1 ra0 141 trisa trisa5 trisa4 trisa2 trisa1 trisa0 141 lata l a t a 5l a t a 4 lata2 lata1 lata0 142 ansela ansa5 ansa4 ansa2 ansa1 ansa0 142 wpua wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 143 odcona odca5 odca4 odca2 odca1 odca0 143 slrcona slra5 slra4 slra2 slra1 slra0 144 inlvla inlvla5 inlvla4 inlvla3 inlvla2 inlvla1 inlvla0 144 legend: x = unknown, u = unchanged, C = unimplemented locations read as 0 . shaded cells are not used by porta. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config2 13:8 debug stvren pps1way b o r v 61 7:0 boren1 boren0 lpboren wdte1 wdte0 pwrte mclre legend: = unimplemented location, read as 0 . shaded cells are not used by porta. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 146 preliminary ? 2016 microchip technology inc. 11.4 portb registers (pic16(l)f18346 only) 11.4.1 data register portb is a 4-bit wide bidirectional port and is only available in the pic16(l)f18346 devices. the corresponding data direction register is trisb ( register 11-10 ). setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 11-1 shows how to initialize an i/o port. reading the portb register ( register 11-9 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read; this value is modified and then written to the port data latch (latb). the port data latch latb ( register 11-11 ) holds the output port data, and contains the latest value of a latb or portb write. 11.4.2 direction control the trisb register ( register 11-10 ) controls the portb pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisb register are maintained set when using them as analog inputs. i/o pins configured as analog inputs always read 0 . 11.4.3 input threshold control the inlvlb register ( register 11-16 ) controls the input voltage threshold for each of the available portb input pins. a selection between the schmitt trigger cmos or the ttl compatible thresholds is available. the input threshold is important in determining the value of a read of the portb register and also the level at which an interrupt-on-change occurs, if that feature is enabled. see table 34-4 for more information on threshold levels. 11.4.4 open-drain control the odconb register ( register 11-14 ) controls the open-drain feature of the port. open-drain operation is independently selected for each pin. when an odconb bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. when an odconb bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.4.5 slew rate control the slrconb register ( register 11-15 ) controls the slew rate option for each port pin. slew rate control is independently selectable for each port pin. when an slrconb bit is set, the corresponding port pin drive is slew rate limited. when an slrconb bit is cleared, the corresponding port pin drive slews at the maximum rate possible. 11.4.6 analog control the anselb register ( register 11-12 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselb bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly. the state of the anselb bits has no effect on digital output functions. a pin with tris clear and anselb set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 11.4.7 weak pull-up control the wpub register ( register 11-13 ) controls the individual weak pull-ups for each port pin. 11.4.8 portb functions and output priorities each pin defaults to the port latch data after reset. other output functions are selected with the peripheral pin select logic. see section 12.0 ?peripheral pin select (pps) module? for more information. analog input functions, such as adc and comparator inputs, are not shown in the peripheral pin select lists. digital output functions may continue to control the pin when it is in analog mode. note: changing the input threshold selection should be performed while all peripheral modules are disabled. changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. note: it is not necessary to set open-drain control when using the pin for i 2 c; the i 2 c module controls the pin and makes the pin open-drain. note: the anselb bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to 0 by user software. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 147 pic16(l)f18326/18346 11.5 register definitions: portb register 11-9: portb: portb register r/w-x/x r/w-x/x r/w-x/x r/w-x/x u-0 u-0 u-0 u-0 rb7 rb6 rb5 rb4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 rb<7:4> : portb i/o value bits (1) 1 = port pin is > v ih 0 = port pin is < v il bit 3-0 unimplemented: read as 0 note 1: writes to portb are actually written to corresponding latb register. reads from portb register return actual i/o pin values. register 11-10: trisb: portb tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 u-0 u-0 u-0 u-0 trisb7 trisb6 trisb5 trisb4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 trisb<7:4>: portb i/o tri-state control bits 1 = portb pin configured as an output 0 = portb pin configured as an input (tri-stated) bit 3-0 unimplemented: read as 0 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 148 preliminary ? 2016 microchip technology inc. register 11-11: latb: portb data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u u-0 u-0 u-0 u-0 latb7 latb6 latb5 latb4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 latb<7:4> : rb<5:4> output latch value bits (1) bit 3-0 unimplemented: read as 0 note 1: writes to latb are equivalent with writes to the corresponding portb register.reads from latb register return register values, not i/o pin values. register 11-12: anselb: portb analog select register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 u-0 u-0 u-0 u-0 ansb7 ansb6 ansb5 ansb4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 ansb<7:4> : analog select between analog or digital function 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. bit 3-0 unimplemented: read as 0 note 1: setting ansb[n] = 1 disables the digital input circuitry. weak pull-ups, if available, are unaffected. the corresponding tris bit must be set to input mode by the user to allow external control of the voltage on the pin. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 149 pic16(l)f18326/18346 register 11-13: wpub: weak pull-up portb register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 wpub7 wpub6 wpub5 wpub4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 wpub<7:4> : weak pull-up register bits 1 = weak pull-up enabled 0 = weak pull-up disabled bit 3-0 unimplemented: read as 0 register 11-14: odco nb: portb open-drain control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 odcb7 odcb6 odcb5 odcb4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 odcb<7:4>: portb open-drain configuration bits for rb<7:4> pins, respectively: 1 = port pin operates as open-drain drive (sink current only) 0 = port pin operates as standard push-pull drive (source and sink current) bit 3-0 unimplemented: read as 0 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 150 preliminary ? 2016 microchip technology inc. register 11-15: slrconb: port b slew rate control register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 u-0 u-0 u-0 u-0 slrb7 slrb6 slrb5 slrb4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 slrb<7:4>: portb slew rate control on pins rb<7:4>, respectively 1 = slew rate enabled 0 = slew rate disabled bit 3-0 unimplemented: read as 0 register 11-16: inlvlb: portb input level control register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 u-0 u-0 u-0 u-0 inlvlb7 inlvlb6 inlvlb5 inlvlb4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 inlvlb<7:4>: portb input level select on pins rb<7:4>, respectively 1 = st input used for port reads 0 = ttl input used for port reads bit 3-0 unimplemented: read as 0 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 151 pic16(l)f18326/18346 table 11-4: summary of regist ers associated with portb name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page portb rb7 rb6 rb5 rb4 147 trisb trisb7 trisb6 trisb5 trisb4 147 latb latb7 latb6 latb5 latb4 148 anselb ansb7 ansb6 ansb5 ansb4 148 wpub wpub7 wpu6 wpub5 wpub4 149 odconb odcb7 odcb6 odcb5 odcb4 149 slrconb slrb7 slrb6 slrb5 slrb4 150 inlvlb inlvlb7 inlvlb6 inlvlb5 inlvlb4 150 legend: x = unknown, u = unchanged, C = unimplemented locations read as 0 . shaded cells are not used by portb. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 152 preliminary ? 2016 microchip technology inc. 11.6 portc registers 11.6.1 data register portc is a bidirectional port that is either 6-bit wide (pic16(l)f18326) or 8-bit wide (pic16(l)f18346). the corresponding data direction register is trisc ( register 11-18 ). setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 11-1 shows how to initialize an i/o port. reading the portc register ( register 11-17 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latc). the port data latch latc ( register 11-19 ) holds the output port data, and contains the latest value of a latc or portc write. 11.6.2 direction control the trisc register ( register 11-18 ) controls the portc pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisc register are maintained set when using them as analog inputs. i/o pins configured as analog inputs always read 0 . 11.6.3 input threshold control the inlvlc register ( register 11-24 ) controls the input voltage threshold for each of the available portc input pins. a selection between the schmitt trigger cmos or the ttl compatible thresholds is available. the input threshold is important in determining the value of a read of the portc register and also the level at which an interrupt-on-change occurs, if that feature is enabled. see table 34-4 for more information on threshold levels. 11.6.4 open-drain control the odconc register ( register 11-22 ) controls the open-drain feature of the port. open-drain operation is independently selected for each pin. when an odconc bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. when an odconc bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.6.5 slew rate control the slrconc register ( register 11-23 ) controls the slew rate option for each port pin. slew rate control is independently selectable for each port pin. when an slrconc bit is set, the corresponding port pin drive is slew rate limited. when an slrconc bit is cleared, the corresponding port pin drive slews at the maximum rate possible. 11.6.6 analog control the anselc register ( register 11-20 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselc bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly. the state of the anselc bits has no effect on digital out- put functions. a pin with tris clear and anselc set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when exe- cuting read-modify-write instructions on the affected port. 11.6.7 weak pull-up control the wpuc register ( register 11-21 ) controls the individual weak pull-ups for each port pin. 11.6.8 portc functions and output priorities each pin defaults to the port latch data after reset. other functions are selected with the peripheral pin select logic. see section 12.0 ?peripheral pin select (pps) module? for more information. analog output functions, such as adc and comparator inputs, are not shown in the peripheral pin select lists. digital output functions may continue to control the pin when it is in analog mode. note: changing the input threshold selection should be performed while all peripheral modules are disabled. changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. note: it is not necessary to set open-drain control when using the pin for i 2 c; the i 2 c module controls the pin and makes the pin open-drain. note: the anselc bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to 0 by user software. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 153 pic16(l)f18326/18346 11.7 register definitions: portc register 11-17: portc: portc register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rc7 (1) rc6 (1) rc5 rc4 rc3 rc2 rc1 rc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 rc<7:6> : portc i/o value bits (1,2) 1 = port pin is > v ih 0 = port pin is < v il bit 5-0 rc<5:0> : portc general purpose i/o pin bits (2) 1 = port pin is > v ih 0 = port pin is < v il note 1: pic16(l)f18346 only; otherwise read as 0 . 2: writes to portc are actually written to corresponding latc register. reads from portc register is return of actual i/o pin values. register 11-18: trisc: portc tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 trisc<7:6> : portc tri-state control bits (1) 1 = portc pin configured as an input (tri-stated) 0 = portc pin configured as an output bit 5-0 trisc<5:0>: portc tri-state control bits 1 = portc pin configured as an input (tri-stated) 0 = portc pin configured as an output note 1: pic16(l)f18346 only; otherwise read as 0 . downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 154 preliminary ? 2016 microchip technology inc. register 11-19: latc: portc data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latc7 (1) latc6 (1) latc5 latc4 latc3 latc2 latc1 latc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 latc<7:6> : portc output latch value bits (1) bit 5-0 latc<5:0> : portc output latch value bits note 1: pic16(l)f18346 only; otherwise read as 0 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 155 pic16(l)f18326/18346 register 11-20: anselc: portc analog select register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 ansc<7:6> : analog select between analog or digital function on pins rc<7:6>, respectively (1) 1 = analog input. pin is assigned as analog input (2) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. bit 5-0 ansc<5:0> : analog select between analog or digital function on pins rc<5:0>, respectively 1 = analog input. pin is assigned as analog input (2) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. note 1: pic16(l)f18346 only; otherwise read as 0 . 2: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. register 11-21: wpuc: weak pull-up portc register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 wpuc7 (1) wpuc6 (1) wpuc5 wpuc4 wpuc3 wpuc2 wpuc1 wpuc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 wpuc<7:6> (1) : weak pull-up register bits (2) 1 = pull-up enabled 0 = pull-up disabled bit 5-0 wpuc<5:0> : weak pull-up register bits (2) 1 = pull-up enabled 0 = pull-up disabled note 1: pic16(l)f18346 only; otherwise read as 0 . 2: the weak pull-up device is automatically disabled if the pin is configured as an output. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 156 preliminary ? 2016 microchip technology inc. register 11-22: odconc: portc open-drain control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 odcc7 (1) odcc6 (1) odcc5 odcc4 odcc3 odcc2 odcc1 odcc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 odcc<7:6> : portc open-drain enable bits (1) for rc<7:6> pins, respectively 1 = port pin operates as open-drain drive (sink current only) 0 = port pin operates as standard push-pull drive (source and sink current) bit 5-0 odcc<5:0>: portc open-drain enable bits for rc<5:0> pins, respectively 1 = port pin operates as open-drain drive (sink current only) 0 = port pin operates as standard push-pull drive (source and sink current) note 1: pic16(l)f18346 only; otherwise read as 0 . register 11-23: slrconc: port c slew rate control register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 slrc7 (1) slrc6 (1) slrc5 slrc4 slrc3 slrc2 slrc1 slrc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 slrc<7:6>: portc slew rate enable bits (1) for rc<7:6> pins, respectively 1 = port pin slew rate is limited 0 = port pin slews at maximum rate bit 5-0 slrc<5:0>: portc slew rate enable bits for rc<5:0> pins, respectively 1 = port pin slew rate is limited 0 = port pin slews at maximum rate note 1: pic16(l)f18346 only; otherwise read as 0 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 157 pic16(l)f18326/18346 register 11-24: inlvlc: portc input level control register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 inlvlc7 (1) inlvlc6 (1) inlvlc5 inlvlc4 inlvlc3 inlvlc2 inlvlc1 inlvlc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 inlvlc<7:6>: portc input level select bits (1) for rc<7:6> pins, respectively 1 = st input used for port reads and interrupt-on-change 0 = ttl input used for port reads and interrupt-on-change bit 5-0 inlvlc<5:0>: portc input level select bits for rc<5:0> pins, respectively 1 = st input used for port reads and interrupt-on-change 0 = ttl input used for port reads and interrupt-on-change note 1: pic16(l)f18346 only; otherwise read as 0 . table 11-5: summary of regist ers associated with portc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page portc rc7 (1) rc6 (1) rc5 rc4 rc3 rc2 rc1 rc0 153 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 latc latc7 (1) latc6 (1) latc5 latc4 latc3 latc2 latc1 latc0 154 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 wpuc wpuc7 (1) wpuc6 (1) wpuc5 wpuc4 wpuc3 wpuc2 wpuc1 wpuc0 155 odconc odcc7 (1) odcc6 (1) odcc5 odcc4 odcc3 odcc2 odcc1 odcc0 156 slrconc slrc7 (1) slrc6 (1) slrc5 slrc4 slrc3 slrc2 slrc1 slrc0 156 inlvlc inlvlc7 (1) inlvlc6 (1) inlvlc5 inlvlc4 inlvlc3 inlvlc2 inlvlc1 inlvlc0 157 note 1: pic16(l)f18346 only. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 158 preliminary ? 2016 microchip technology inc. 12.0 peripheral pin select (pps) module the peripheral pin select (pps) module connects peripheral inputs and outputs to the device i/o pins. only digital signals are included in the selections. all analog inputs and outputs remain fixed to their assigned pins. input and output selections are independent as shown in the simplified block diagram figure 12-1 . 12.1 pps inputs each peripheral has a pps register with which the inputs to the peripheral are selected. inputs include the device pins. although every peripheral has its own pps input selec- tion register, the selections are identical for every peripheral as shown in register 12-1 . 12.2 pps outputs each i/o pin has a pps register with which the pin output source is selected. with few exceptions, the port tris control associated with that pin retains control over the pin output driver. peripherals that control the pin output driver as part of the peripheral operation will override the tris control as needed. these peripherals include: eusart1 (synchronous operation) mssp (i 2 c) although every pin has its own pps peripheral selection register, the selections are identical for every pin as shown in register 12-2 . figure 12-1: simplified pps block diagram note: the notation xxx in the register name is a place holder for the peripheral identifier. for example, clc1pps. note: the notation rxy is a place holder for the pin identifier. for example, ra0pps. ra0 rxy ra0pps rxypps rc7 (1) rc7pps (1) pps outputs pps inputs peripheral abc peripheral xyz abcpps xyzpps ra0 rc7 (1) note 1: rb<7:4> and rc<7:6> are available on pic16(l)f18346 only. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 159 pic16(l)f18326/18346 12.3 bidirectional pins pps selections for peripherals with bidirectional signals on a single pin must be made so that the pps input and pps output select the same pin. this requires configuring both the appropriate xxxpps input and rxypps output registers. for example, if the scl1 line is routed to pin rc0, the ssp1sclpps input register would be set to ' 10000 ' (routes to rc0) and the rc0pps output register would be set to ' 11000 ' (routes the scl1 internal connection to rc0). peripherals that have bidirectional signals include: eusart1 (synchronous operation) mssp (i 2 c) 12.4 pps lock the pps includes a mode in which all input and output selections can be locked to prevent inadvertent changes. pps selections are locked by setting the ppslocked bit of the ppslock register. setting and clearing this bit requires a special sequence as an extra precaution against inadvertent changes. examples of setting and clearing the ppslocked bit are shown in example 12-1 . example 12-1: pps lock/unlock sequence 12.5 pps permanent lock the pps can be permanently locked by setting the pps1way configuration bit. when this bit is set, the ppslocked bit can only be cleared and set one time after a device reset. this allows for clearing the ppslocked bit so that the input and output selections can be made during initialization. when the ppslocked bit is set after all selections have been made, it will remain set and cannot be cleared until after the next device reset event. 12.6 operation during sleep pps input and output selections are unaffected by sleep. 12.7 effects of a reset a device power-on-reset (por) clears all pps input and output selections to their default values. all other resets leave the selections unchanged. default input selections are shown in pin allocation table 2 and tab l e 3 . note: the i 2 c default input pins are i 2 c and smbus compatible and are the only pins on the pic16(l)f18326 with this compati- bility. for the pic16(l)f18346, in addition to the default pins as described above, rc0, rc1, rc4, and rc5 are also i 2 c and smbus compatible. clock and data signals can be routed to any pin, however pins without i 2 c compatibility will operate at standard ttl/st logic levels as selected by the invlv register. ; suspend interrupts bcf intcon,gie ; banksel ppslock ; set bank ; required sequence, next 5 instructions movlw 0x55 movwf ppslock movlw 0xaa movwf ppslock ; set ppslocked bit to disable writes or ; clear ppslocked bit to enable writes bsf ppslock,ppslocked ; restore interrupts bsf intcon,gie downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 160 preliminary ? 2016 microchip technology inc. 12.8 register definitions: pps input selection register 12-1: xxxpps: peripheral xxx input selection u-0 u-0 u-0 r/w-q/u r/w-q/u r/w-q/u r/w-q/u r/w-q/u xxxpps<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on peripheral bit 7-5 unimplemented: read as 0 bit 4-0 xxxpps<4:0>: peripheral xxx input selection bits 11xxx = reserved. do not use. 10111 = peripheral input is rc7 (1) 10110 = peripheral input is rc6 (1) 10101 = peripheral input is rc5 10100 = peripheral input is rc4 10011 = peripheral input is rc3 10010 = peripheral input is rc2 10001 = peripheral input is rc1 10000 = peripheral input is rc0 ...01111 = peripheral input is rb7 (1) 01110 = peripheral input is rb6 (1) 01101 = peripheral input is rb5 (1) 01100 = peripheral input is rb4 (1) ...0011x = reserved. do not use. 00101 = peripheral input is ra5 00100 = peripheral input is ra4 00011 = peripheral input is ra3 00010 = peripheral input is ra2 00001 = peripheral input is ra1 00000 = peripheral input is ra0 note 1: pic16(l)f18346 only. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 161 pic16(l)f18326/18346 register 12-2: rxypps: pin rxy output source selection register u-0 u-0 u-0 r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u rxypps<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-5 unimplemented: read as 0 bit 4-0 rxypps<4:0>: pin rxy output source selection bits 11111 = rxy source is dsm 11110 = rxy source is clkr 11101 = rxy source is nco1 11100 = rxy source is tmr0 11011 = rxy source is sdo2/sda2 (1) 11010 = rxy source is sck2/scl2 (1) 11001 = rxy source is sdo1/sda1 11000 = rxy source is sck1/scl1 (1) 10111 = rxy source is c2 10110 = rxy source is c1 10101 = rxy source is dt (1) 10100 = rxy source is tx/ck (1) 10011 = rxy source is cwg2d (1) 10010 = rxy source is cwg2c (1) 10001 = rxy source is cwg2b (1) 10000 = rxy source is cwg2a (1) 01111 = rxy source is ccp4 01110 = rxy source is ccp3 01101 = rxy source is ccp2 01100 = rxy source is ccp1 01011 = rxy source is cwg1d (1) 01010 = rxy source is cwg1c (1) 01001 = rxy source is cwg1b (1) 01000 = rxy source is cwg1a (1) 00111 = rxy source is clc4out 00110 = rxy source is clc3out 00101 = rxy source is clc2out 00100 = rxy source is clc1out 00011 = rxy source is pwm6 00010 = rxy source is pwm5 00001 = reserved 00000 = rxy source is latxy note 1: tris control is overridden by the peripheral as required. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 162 preliminary ? 2016 microchip technology inc. register 12-3: ppslo ck: pps lock register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0/0 ppslocked bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-1 unimplemented: read as 0 bit 0 ppslocked: pps locked bit 1 = pps is locked. pps selections can not be changed. 0 = pps is not locked. pps selections can be changed. table 12-1: summary of registers associated with the pps module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ppslock ppslocked 162 intpps intpps<4:0> 160 t0ckipps t0ckipps<4:0> 160 t1ckipps t1ckipps<4:0> 160 t1gpps t1gpps<4:0> 160 t3ckipps t3ckipps<4:0> 160 t3gpps t3gpps<4:0> 160 t5ckipps t5ckipps<4:0> 160 t5gpps t5gpps<4:0> 160 ccp1pps ccp1pps<4:0> 160 ccp2pps ccp2pps<4:0> 160 ccp3pps ccp3pps<4:0> 160 ccp4pps ccp4pps<4:0> 160 cwg1pps cwg1pps<4:0> 160 cwg2pps cwg2pps<4:0> 160 mdcin1pps mdcin1pps<4:0> 160 mdcin2pps mdcin2pps<4:0> 160 mdminpps mdminpps<4:0> 160 ssp1clkpps ssp1clkpps<4:0> 160 ssp1datpps ssp1datpps<4:0> 160 ssp1sspps ssp1sspps<4:0> 160 ssp2clkpps ssp2clkpps<4:0> 160 ssp2datpps ssp2datpps<4:0> 160 ssp2sspps ssp2sspps<4:0> 160 legend: = unimplemented, read as 0 . shaded cells are unused by the pps module. note 1: pic16(l)f18346 only. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 163 pic16(l)f18326/18346 rxpps rxpps<4:0> 160 txpps txpps<4:0> 160 clcin0pps clcin0pps<4:0> 160 clcin1pps clcin1pps<4:0> 160 clcin2pps clcin2pps<4:0> 160 clcin3pps clcin3pps<4:0> 160 ra0pps ra0pps<4:0> 161 ra1pps ra1pps<4:0> 161 ra2pps ra2pps<4:0> 161 ra4pps ra4pps<4:0> 161 ra5pps ra5pps<4:0> 161 rb4pps (1) rb4pps<4:0> 161 rb5pps (1) rb5pps<4:0> 161 rb6pps (1) rb6pps<4:0> 161 rb7pps (1) rb7pps<4:0> 161 rc0pps rc0pps<4:0> 161 rc1pps rc1pps<4:0> 161 rc2pps rc2pps<4:0> 161 rc3pps rc3pps<4:0> 161 rc4pps rc4pps<4:0> 161 rc5pps rc5pps<4:0> 161 rc6pps (1) rc6pps<4:0> 161 rc7pps (1) rc7pps<4:0> 161 table 12-1: summary of registers associated with the pps module (continued) name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page legend: = unimplemented, read as 0 . shaded cells are unused by the pps module. note 1: pic16(l)f18346 only. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 164 preliminary ? 2016 microchip technology inc. 13.0 peripheral module disable the pic16(l)f18326/18346 provides the ability to disable selected modules, placing them into the lowest possible power mode. for legacy reasons, all modules are on by default following any reset. 13.1 disabling a module disabling a module has the following effects: all clock and control inputs to the module are suspended; there are no logic transitions, and the module will not function. the module is held in reset. any sfrs become unimplemented - writing is disabled - reading returns 00h module outputs are disabled; i/o goes to the next module according to pin priority. 13.2 enabling a module when the register bit is cleared, the module is re- enabled and will be in its reset state; sfr data will reflect the por reset values. depending on the module, it may take up to one full instruction cycle for the module to become active. there should be no interaction with the module (e.g., writing to registers) for at least one instruction after it has been re-enabled. 13.3 disabling a module when a module is disabled, any and all associated input selection registers (isms) are also disabled. 13.4 system clock disable setting syscmd (pmd0, register 13-1 ) disables the system clock (f osc ) distribution network to the peripherals. not all peripherals make use of sysclk, so not all peripherals are affected. refer to the specific peripheral description to see if it will be affected by this bit. register 13-1: pmd0: pmd control register 0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 syscmd fvrmd nvmmd clkrmd iocmd 7 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 syscmd: disable peripheral system clock network bit see description in section 13.4 ?system clock disable? . 1 = system clock network disabled (a.k.a. f osc ) 0 = system clock network enabled bit 6 fvrmd: disable fixed voltage reference fvr bit 1 = fvr module disabled 0 = fvr module enabled bit 5-3 unimplemented: read as 0 bit 2 nvmmd: nvm module disable bit (1) 1 = data eeprom (a.k.a. user memory, eeprom) reading and writing is disabled; nvmcon registers cannot be written; fsr access to eeprom returns zero. 0 = nvm module enabled bit 1 clkrmd: disable clock reference clkr bit 1 = clkr module disabled 0 = clkr module enabled bit 0 iocmd: disable interrupt-on-change bit, all ports 1 = ioc module(s) disabled 0 = ioc module(s) enabled note 1: when enabling nvm, a delay of up to 1 s may be required before accessing data. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 165 pic16(l)f18326/18346 register 13-2: pmd1: pmd control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ncomd tmr6md tmr5md tmr4md tmr3md tmr2md tmr1md tmr0md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 ncomd: disable numerically control oscillator bit 1 = nco1 module disabled 0 = nco1 module enabled bit 6 tmr6md: disable timer tmr6 bit 1 = tmr6 module disabled 0 = tmr6 module enabled bit 5 tmr5md: disable timer tmr5 bit 1 = tmr5 module disabled 0 = tmr5 module enabled bit 4 tmr4md: disable timer tmr4 bit 1 = tmr4 module disabled 0 = tmr4 module enabled bit 3 tmr3md: disable timer tmr3 bit 1 = tmr3 module disabled 0 = tmr3 module enabled bit 2 tmr2md: disable timer tmr2 bit 1 = tmr2 module disabled 0 = tmr2 module enabled bit 1 tmr1md: disable timer tmr1 bit 1 = tmr1 module disabled 0 = tmr1 module enabled bit 0 tmr0md: disable timer tmr0 bit 1 = tmr0 module disabled 0 = tmr0 module enabled downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 166 preliminary ? 2016 microchip technology inc. register 13-3: pmd2: pmd control register 2 u-0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 u-0 dacmd adcmd cmp2md cmp1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 unimplemented: read as 0 bit 6 dacmd: disable dac bit 1 = dac module disabled 0 = dac module enabled bit 5 adcmd: disable adc bit 1 = adc module disabled 0 = adc module enabled bit 4-3 unimplemented: read as 0 bit 2 cmp2md: disable comparator c2 bit 1 = c2 module disabled 0 = c2 module enabled bit 1 cmp1md: disable comparator c1 bit 1 = c1 module disabled 0 = c1 module enabled bit 0 unimplemented: read as 0 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 167 pic16(l)f18326/18346 register 13-4: pmd3: pmd control register 3 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 cwg2md cwg1md pwm6md pwm5md ccp4md ccp3md ccp2md ccp1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 cwg2md: disable cwg2 bit 1 = cwg2 module disabled 0 = cwg2 module enabled bit 6 cwg1md: disable cwg1 bit 1 = cwg1 module disabled 0 = cwg1 module enabled bit 5 pwm6md: disable pulse-width modulator pwm6 bit 1 = pwm6 module disabled 0 = pwm6 module enabled bit 4 pwm5md: disable pulse-width modulator pwm5 bit 1 = pwm5 module disabled 0 = pwm5 module enabled bit 3 ccp4md: disable pulse-width modulator ccp4 bit 1 = ccp4 module disabled 0 = ccp4 module enabled bit 2 ccp3md: disable pulse-width modulator ccp3 bit 1 = ccp3 module disabled 0 = ccp3 module enabled bit 1 ccp2md: disable pulse-width modulator ccp2 bit 1 = ccp2 module disabled 0 = ccp2 module enabled bit 0 ccp1md: disable pulse-width modulator ccp1 bit 1 = ccp1 module disabled 0 = ccp1 module enabled downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 168 preliminary ? 2016 microchip technology inc. register 13-5: pmd4: pmd control register 4 u-0 u-0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 u-0 u a r t 1 m d mssp2md mssp1md bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7-6 unimplemented: read as 0 bit 5 uart1md: disable eusart1 bit 1 = eusart1 module disabled 0 = eusart1 module enabled bit 4-3 unimplemented: read as 0 bit 2 mssp2md: disable mssp2 bit 1 = mssp2 module disabled 0 = mssp2 module enabled bit 1 mssp1md: disable mssp1 bit 1 = mssp1 module disabled 0 = mssp1 module enabled bit 0 unimplemented: read as 0 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 169 pic16(l)f18326/18346 register 13-6: pmd5: pmd control register 5 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 clc4md clc3md clc2md clc1md dsmmd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7-5 unimplemented: read as 0 bit 4 clc4md: disable clc4 bit 1 = clc4 module disabled 0 = clc4 module enabled bit 3 clc3md: disable clc3 bit 1 = clc3 module disabled 0 = clc3 module enabled bit 2 clc2md: disable clc2 bit 1 = clc2 module disabled 0 = clc2 module enabled bit 1 clc1md: disable clc1 bit 1 = clc1 module disabled 0 = clc1 module enabled bit 0 dsmmd: disable data signal modulator bit 1 = dsm module disabled 0 = dsm module enabled downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 170 preliminary ? 2016 microchip technology inc. 14.0 interrupt-on-change all pins on all ports can be configured to operate as interrupt-on-change (ioc) pins. an interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. any individual pin, or combination of pins, can be configured to generate an interrupt. the interrupt-on-change module has the following features: interrupt-on-change enable (master switch) individual pin configuration rising and falling edge detection individual pin interrupt flags figure 14-1 is a block diagram of the ioc module. 14.1 enabling the module to allow individual pins to generate an interrupt, the iocie bit of the pie0 register must be set. if the iocie bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 14.2 individual pin configuration for each pin, a rising edge detector and a falling edge detector are present. to enable a pin to detect a rising edge, the associated bit of the iocxp register is set. to enable a pin to detect a falling edge, the associated bit of the iocxn register is set. a pin can be configured to detect rising and falling edges simultaneously by setting the associated bits in both of the iocxp and iocxn registers. 14.3 interrupt flags the bits located in the iocxf registers are status flags that correspond to the interrupt-on-change pins of each port. if an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the iocie bit is set. the iocif bit of the pir0 register reflects the status of all iocxf bits. 14.4 clearing interrupt flags the individual status flags, (iocxf register bits), can be cleared by resetting them to zero. if another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. in order to ensure that no detected edge is lost while clearing flags, only and operations masking out known changed bits should be performed. the following sequence is an example of what should be performed. example 14-1: clearing interrupt flags (porta example) 14.5 operation in sleep the interrupt-on-change interrupt sequence will wake the device from sleep mode, if the iocie bit is set. if an edge is detected while in sleep mode, the affected iocxf register will be updated prior to the first instruction executed out of sleep. movlw 0xff xorwf iocaf, w andwf iocaf, f downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 171 pic16(l)f18326/18346 figure 14-1: interrupt-on-change bl ock diagram (porta example) iocanx iocapx q2 q4q1 data bus = 0or1 write iocafx iocie to data bus iocafx edge detect ioc interrupt to cpu core from all other iocnfx individual pin detectors dqr s dq r dq r rax q1q2 q3 q4 q4q1 q1 q2 q3 q4 q1 q2 q3 q4 q4q1 q4q1 q4q1 f osc rev. 10-000037a 7/30/2013 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 172 preliminary ? 2016 microchip technology inc. 14.6 register definitions: interrupt-on-change control register 14-1: iocap: interrupt-on-c hange porta positive edge register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 iocap<5:0>: interrupt-on-change porta positive edge enable bits 1 = interrupt-on-change enabled on the pin for a positive going edge. iocafx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin register 14-2: iocan: interrupt-on-change porta negative edge register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 iocan<5:0>: interrupt-on-change porta negative edge enable bits 1 = interrupt-on-change enabled on the pin for a negative going edge. iocafx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 173 pic16(l)f18326/18346 register 14-3: iocaf: interrupt- on-change porta flag register u-0 u-0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs - bit is set in hardware bit 7-6 unimplemented: read as 0 bit 5-0 iocaf<5:0>: interrupt-on-change porta flag bits 1 = an enabled change was detected on the associated pin set when iocapx = 1 and a rising edge was detected on rax, or when iocanx = 1 and a falling edge was detected on rax. 0 = no change was detected, or the user cleared the detected change. register 14-4: iocbp: interrupt-on-c hange portb positive edge register (1) r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 iocbp7 iocbp6 iocbp5 iocbp4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 iocbp<7:4>: interrupt-on-change portb positive edge enable bits 1 = interrupt-on-change enabled on the pin for a positive going edge. iocafx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin bit 3-0 unimplemented: read as 0 note 1: pic16(l)f18346 only. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 174 preliminary ? 2016 microchip technology inc. register 14-5: iocbn: interrupt-on-change portb negative edge register (1) r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 iocbn7 iocbn6 iocbn5 iocbn4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 iocbn<7:4>: interrupt-on-change portb negative edge enable bits 1 = interrupt-on-change enabled on the pin for a negative going edge. iocafx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin bit 3-0 unimplemented: read as 0 note 1: pic16(l)f18346 only. register 14-6: iocbf: interrupt- on-change portb flag register (1) r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 u-0 u-0 u-0 u-0 iocbf7 iocbf6 iocbf5 iocbf4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs - bit is set in hardware bit 7-4 iocbf<7:4>: interrupt-on-change portb flag bits 1 = an enabled change was detected on the associated pin set when iocbpx = 1 and a rising edge was detected on rbx, or when iocbnx = 1 and a falling edge was detected on rbx. 0 = no change was detected, or the user cleared the detected change. bit 3-0 unimplemented: read as 0 note 1: pic16(l)f18346 only. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 175 pic16(l)f18326/18346 register 14-7: ioccp: interrupt-on-c hange portc positive edge register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ioccp7 (1) ioccp6 (1) ioccp5 ioccp4 ioccp3 ioccp2 ioccp1 ioccp0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 ioccp<7:6>: interrupt-on-change portc positive edge enable bits (1) 1 = interrupt-on-change enabled on the pin for a positive going edge. ioccfx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin bit 5-0 ioccp<5:0>: interrupt-on-change portc positive edge enable bits 1 = interrupt-on-change enabled on the pin for a positive going edge. ioccfx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin note 1: pic16(l)f18346 only. register 14-8: ioccn: interrupt-on-change portc negative edge register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ioccn7 (1) ioccn6 (1) ioccn5 ioccn4 ioccn3 ioccn2 ioccn1 ioccn0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 ioccn<7:6>: interrupt-on-change portc negative edge enable bits (1) 1 = interrupt-on-change enabled on the pin for a negative going edge. ioccfx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin bit 5-0 ioccn<5:0>: interrupt-on-change portc negative edge enable bits 1 = interrupt-on-change enabled on the pin for a negative going edge. ioccfx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin note 1: pic16(l)f18346 only. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 176 preliminary ? 2016 microchip technology inc. register 14-9: ioccf: interrupt- on-change portc flag register r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 ioccf7 (1) ioccf6 (1) ioccf5 ioccf4 ioccf3 ioccf2 ioccf1 ioccf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs - bit is set in hardware bit 7-6 i occf<7:6>: interrupt-on-change portc flag bits 1 = an enabled change was detected on the associated pin. set when ioccpx = 1 and a rising edge was detected on rcx, or when ioccnx = 1 and a falling edge was detected on rcx. 0 = no change was detected, or the user cleared the detected change. bit 5-0 ioccf<5:0>: interrupt-on-change portc flag bits 1 = an enabled change was detected on the associated pin. set when ioccpx = 1 and a rising edge was detected on rcx, or when ioccnx = 1 and a falling edge was detected on rcx. 0 = no change was detected, or the user cleared the detected change. note 1: pic16(l)f18346 only. table 14-1: summary of registers as sociated with interrupt-on-change name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ansa4 ansa4 ansa2 ansa1 ansa0 142 anselb (1) ansb7 ansb6 ansb5 ansb4 148 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 trisa trisa5 trisa4 (2) trisa2 trisa1 trisa0 141 trisb (1) trisb7 trisb6 trisb5 trisb4 147 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 intcon gie peie i n t e d g 98 pie0 tmr0ie iocie inte 99 iocap iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 172 iocan iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 172 iocaf iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 173 iocbp (1) iocbp7 iocbp6 iocbp5 iocbp4 173 iocbn (1) iocbn7 iocbn6 iocbn5 iocbn4 174 iocbf (1) iocbf7 iocbf6 iocbf5 iiocbf4 174 ioccp ioccp7 (1) ioccp6 (1) ioccp5 ioccp4 ioccp3 ioccp2 ioccp1 ioccp0 175 ioccn ioccn7 (1) ioccn6 (1) ioccn5 ioccn4 ioccn3 ioccn2 ioccn1 ioccn0 175 ioccf ioccf7 (1) ioccf6 (1) ioccf5 ioccf4 ioccf3 ioccf2 ioccf1 ioccf0 176 legend: = unimplemented location, read as 0 . shaded cells are not used by interrupt-on-change. note 1: pic16(l)f18346 only. 2: unimplemented, read as 1 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 177 pic16(l)f18326/18346 15.0 fixed voltage reference (fvr) the fixed voltage reference, or fvr, is a stable voltage reference, independent of v dd , with 1.024v, 2.048v or 4.096v selectable output levels. the output of the fvr can be configured to supply a reference voltage to the following: adc input channel adc positive reference comparator positive input digital-to-analog converter (dac) the fvr can be enabled by setting the fvren bit of the fvrcon register. 15.1 independent gain amplifiers the output of the fvr, which is supplied to the adc, comparators and dac, is routed through two independent programmable gain amplifiers. each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. the adfvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the adc module. reference section 21.0 ?analog-to-digital converter (adc) module? for additional information. the cdafvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the dac and comparator module. reference section 23.0 ?5-bit digital-to-analog converter (dac1) module? and section 17.0 ?comparator module? for additional information. 15.2 fvr stabilization period when the fixed voltage reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. once the circuits stabilize and are ready for use, the fvrrdy bit of the fvrcon register will be set. figure 15-1: voltage reference block diagram note: fixed voltage reference output cannot exceed v dd . 1x 2x 4x 1x 2x 4x adfvr<1:0> cdafvr<1:0> fvr_buffer1 (to adc module) fvr_buffer2 (to comparators and dac) + _ fvren fvrrdy note 1 2 2 rev. 10 -000 053c 12 /9/201 3 note: any peripheral requiring the fixed reference (see table 15-1 ). downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 178 preliminary ? 2016 microchip technology inc. 15.3 register definitions: fvr control register 15-1: fvrcon: fixed voltage reference control register r/w-0/0 r-q/q r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 fvren fvrrdy (1) tsen (3) tsrng (3) cdafvr<1:0> adfvr<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 fvren: fixed voltage reference enable bit 1 = fixed voltage reference is enabled 0 = fixed voltage reference is disabled bit 6 fvrrdy: fixed voltage reference ready flag bit (1) 1 = fixed voltage reference output is ready for use 0 = fixed voltage reference output is not ready or not enabled bit 5 tsen: temperature indicator enable bit (3) 1 = temperature indicator is enabled 0 = temperature indicator is disabled bit 4 tsrng: temperature indicator range selection bit (3) 1 =v out = v dd - 4v t (high range) 0 =v out = v dd - 2v t (low range) bit 3-2 cdafvr<1:0>: comparator fvr buffer gain selection bits 11 = comparator fvr buffer gain is 4x, (4.096v) (2) 10 = comparator fvr buffer gain is 2x, (2.048v) (2) 01 = comparator fvr buffer gain is 1x, (1.024v) 00 = comparator fvr buffer is off bit 1-0 adfvr<1:0>: adc fvr buffer gain selection bit 11 = adc fvr buffer gain is 4x, (4.096v) (2) 10 = adc fvr buffer gain is 2x, (2.048v) (2) 01 = adc fvr buffer gain is 1x, (1.024v) 00 = adc fvr buffer is off note 1: fvrrdy is always 1 . 2: fixed voltage reference output cannot exceed v dd . 3: see section 16.0 ?temperature indicator module? for additional information. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 179 pic16(l)f18326/18346 table 15-1: summary of registers asso ciated with fixed voltage reference name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 178 adcon0 chs<5:0> go/done adon 242 adcon1 adfm adcs<2:0> adnref adpref<1:0> 243 cmxcon1 cxintp cxintn cxpch<2:0> cxnch<2:0> 189 dac1con0 dac1en dac1oe dac1pps<1:0> dac1nss 261 legend: shaded cells are not used with the fixed voltage reference. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 180 preliminary ? 2016 microchip technology inc. 16.0 temperature indicator module this family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. the circuits range of operating temperature falls between -40c and +85c. the output is a voltage that is proportional to the device temperature. the output of the temperature indicator is internally connected to the device adc. the circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. a one- point calibration allows the circuit to indicate a temperature closely surrounding that point. a two-point calibration allows the circuit to sense the entire range of temperature more accurately. reference application note an1333, use and calibration of the internal temperature indicator (ds01333) for more details regarding the calibration process. 16.1 circuit operation figure 16-1 shows a simplified block diagram of the temperature circuit. the proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. equation 16-1 describes the output characteristics of the temperature indicator. equation 16-1: v out ranges the temperature sense circuit is integrated with the fixed voltage reference (fvr) module. see section 15.0 ?fixed voltage reference (fvr)? for more information. the circuit is enabled by setting the tsen bit of the fvrcon register. when disabled, the circuit draws no current. the circuit operates in either high or low range. the high range, selected by setting the tsrng bit of the fvrcon register, provides a wider output voltage. this provides more resolution over the temperature range, but may be less consistent from part to part. this range requires a higher bias voltage to operate and thus, a higher v dd is needed. the low range is selected by clearing the tsrng bit of the fvrcon register. the low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. the low range is provided for low voltage operation. figure 16-1: temperature circuit diagram 16.2 minimum operating v dd when the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. when the temperature circuit is operated in high range, the device operating voltage, v dd , must be high enough to ensure that the temperature circuit is correctly biased. table 16-1 shows the recommended minimum v dd vs. range setting. 16.3 temperature output the output of the circuit is measured using the internal analog-to-digital converter. a channel is reserved for the temperature circuit output. refer to section 21.0 ?analog-to-digital converter (adc) module? for detailed information. high range: v out = v dd - 4v t low range: v out = v dd - 2v t table 16-1: recommended v dd vs. range min. v dd , tsrng = 1 min. v dd , tsrng = 0 3.6v 1.8v tsen tsrng v dd v out to a d c temp. indicator downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 181 pic16(l)f18326/18346 16.4 adc acquisition time to ensure accurate temperature measurements, the user must wait at least 200 ? s after the adc input multiplexer is connected to the temperature indicator output before the conversion is performed. in addition, the user must wait 200 ? s between consecutive conversions of the temperature indicator output. table 16-2: summary of registers asso ciated with the temperature indicator name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 178 legend: shaded cells are unused by the temperature indicator module. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 182 preliminary ? 2016 microchip technology inc. 17.0 comparator module comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. the analog comparator module includes the following features: programmable input selection programmable output polarity rising/falling output edge interrupts wake-up from sleep programmable speed/power optimization cwg auto-shutdown source selectable voltage reference 17.1 comparator overview a single comparator is shown in figure 17-1 along with the relationship between the analog input levels and the digital output. when the analog voltage at v in + is less than the analog voltage at v in -, the output of the comparator is a digital low level. when the analog voltage at v in + is greater than the analog voltage at v in -, the output of the comparator is a digital high level. the comparators available for this device are located in table 17-1 . figure 17-1: single comparator table 17-1: available comparators device c1 c2 pic16(l)f18326 pic16(l)f18346 C + v in + v in - output output v in + v in - note: the black areas of the output of the comparator represents the uncertainty due to input offsets and response time. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 183 pic16(l)f18326/18346 figure 17-2: comparat or module simplified block diagram note 1: when cxon = 0 , the comparator will produce a 0 at the output. 2: when cxon = 0 , all multiplexer inputs are disconnected. mux cx cxon (1) cxnch<2:0> 3 01 c x pch<2:0> c x in1- c x in2- c x in3- c x in+ mux - + cxvn cxvp q1 den q set cxif 01 c x sync c x out dq dac_ o utput fvr buffer 2 c x in0- 2 cxsp cxhys det interrupt det interrupt cxintn cxintp 3 3 agnd tris bit cxon (2) (2) from timer1 tmr1_clk fvr buffer 2 0 1 2 3 4 5 6 7 agnd 45 6 7 reserved reserved reserved reserved reserved sync_cxout to ti m e r 1 to cm x con0 (c x out) and cm2con1 (mc x out) c x pol 01 cxzlf zlf async_cxout reserved downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 184 preliminary ? 2016 microchip technology inc. 17.2 comparator control each comparator has two control registers: cmxcon0 and cmxcon1. the cmxcon0 register (see register 17-1 ) contains control and status bits for the following: enable output output polarity speed/power selection hysteresis enable timer1 output synchronization the cmxcon1 register (see register 17-2 ) contains control bits for the following: interrupt on positive/negative edge enables positive input channel selection negative input channel selection 17.2.1 comparator enable setting the cxon bit of the cmxcon0 register enables the comparator for operation. clearing the cxon bit disables the comparator resulting in minimum current consumption. 17.2.2 comparator output the output of the comparator can be monitored by reading either the cxout bit of the cmxcon0 register or the mcxout bit of the cmout register. the comparator output can also be routed to an external pin through the rxypps register ( register 12-2 ). the corresponding tris bit must be clear to enable the pin as an output. 17.2.3 comparator output polarity inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. the polarity of the comparator output can be inverted by setting the cxpol bit of the cmxcon0 register. clearing the cxpol bit results in a non-inverted output. table 17-2 shows the output state versus input conditions, including polarity control. 17.3 comparator hysteresis a selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. hysteresis is enabled by setting the cxhys bit of the cmxcon0 register. see comparator specifications in table 34-14 for more information. 17.4 timer1 gate operation the output resulting from a comparator operation can be used as a source for gate control of timer1. see section 26.6 ?timer1 gate? for more information. this feature is useful for timing the duration or interval of an analog event. it is recommended that the comparator output be synchronized to timer1. this ensures that timer1 does not increment while a change in the comparator is occurring. 17.4.1 comparator output synchronization the output from a comparator can be synchronized with timer1 by setting the cxsync bit of the cmxcon0 register. once enabled, the comparator output is latched on the falling edge of the timer1 source clock. if a prescaler is used with timer1, the comparator output is latched after the prescaling function. to prevent a race condition, the comparator output is latched on the falling edge of the timer1 clock source and timer1 increments on the rising edge of its clock source. see the comparator block diagram ( figure 17-2 ) and the timer1 block diagram ( figure 26-1 ) for more information. note 1: the internal output of the comparator is latched with each instruction cycle. unless otherwise specified, external outputs are not latched. table 17-2: comparator output state vs. input conditions input condition cxpol cxout cxv n > cxv p 00 cxv n < cxv p 01 cxv n > cxv p 11 cxv n < cxv p 10 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 185 pic16(l)f18326/18346 17.5 comparator interrupt an interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. when either edge detector is triggered and its associ- ated enable bit is set (cxintp and/or cxintn bits of the cmxcon1 register), the corresponding interrupt flag bit (cxif bit of the pir2 register) will be set. to enable the interrupt, you must set the following bits: cxon, cxpol and cxsp bits of the cmxcon0 register cxie bit of the pie2 register cxintp bit of the cmxcon1 register (for a rising edge detection) cxintn bit of the cmxcon1 register (for a falling edge detection) peie and gie bits of the intcon register the associated interrupt flag bit, cxif bit of the pir2 register, must be cleared in software. if another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 17.6 comparator positive input selection configuring the cxpch<2:0> bits of the cmxcon1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: cxin0+ analog pin dac output fvr (fixed voltage reference) v ss (ground) see section 15.0 ?fixed voltage reference (fvr)? for more information on the fixed voltage reference module. see section 23.0 ?5-bit digital-to-analog converter (dac1) module? for more information on the dac input signal. any time the comparator is disabled (cxon = 0 ), all comparator inputs are disabled. 17.7 comparator negative input selection the cxnch<2:0> bits of the cmxcon1 register direct an analog input pin and internal reference voltage or analog ground to the inverting input of the comparator: cxin- pin fvr (fixed voltage reference) analog ground some inverting input selections share a pin with the operational amplifier output function. enabling both functions at the same time will direct the operational amplifier output to the comparator inverting input. 17.8 comparator response time the comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. this period is referred to as the response time. the response time of the comparator differs from the settling time of the voltage reference. therefore, both of these times must be considered when determining the total response time to a comparator input change. see the comparator and voltage reference specifications in table 34-14 for more details. note: although a comparator is disabled, an interrupt can be generated by changing the output polarity with the cxpol bit of the cmxcon0 register, or by switching the comparator on or off with the cxon bit of the cmxcon0 register. note: to use cxiny+ and cxiny- pins as analog input, the appropriate bits must be set in the ansel register and the corresponding tris bits must also be set to disable the output drivers. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 186 preliminary ? 2016 microchip technology inc. 17.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 17-3 . since the analog input pins share their connection with a digital input, they have reverse biased esd protection diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. also, any external component connected to an analog input pin, such as a capacitor or a zener diode, may have very little leakage current to minimize inaccuracies introduced. figure 17-3: analog input model note 1: when reading a port register, all pins configured as analog inputs will read as a 0 . pins configured as digital inputs will convert as an analog input, according to the input specification. 2: analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. v a rs < 10k c pin 5 pf v dd v t ? 0.6v v t ? 0.6v r ic i leakage (1) vss legend: c pin = input capacitance i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance v a = analog voltage v t = threshold voltage to comparator note 1: see i/o ports in table 34-4 . analog input pin downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 187 pic16(l)f18326/18346 17.10 cwg auto-shutdown source the output of the comparator module can be used as an auto-shutdown source for the cwg module. when the output of the comparator is active and the corresponding asxe is enabled, the cwg operation will be suspended immediately ( section 19.7.1.2 ?external input source shutdown? ). 17.11 operation in sleep mode the comparator module can operate during sleep. the comparator clock source is based on the timer1 clock source. if the timer1 clock source is either the system clock (f osc ) or the instruction clock (f osc /4), timer1 will not operate during sleep, and synchronized comparator outputs will not operate. a comparator interrupt will wake the device from sleep. the cxie bits of the pie2 register must be set to enable comparator interrupts. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 188 preliminary ? 2016 microchip technology inc. 17.12 register definitions: comparator control register 17-1: cmxcon0: comparator cx control register 0 r/w-0/0 r-0/0 u-0 r/w-0/0 u-0 r/w-1/1 r/w-0/0 r/w-0/0 cxon cxout cxpol cxsp cxhys cxsync bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 cxon: comparator enable bit 1 = comparator is enabled 0 = comparator is disabled and consumes no active power bit 6 cxout: comparator output bit if cxpol = 1 (inverted polarity): 1 = cxvp < cxvn 0 = cxvp > cxvn if cxpol = 0 (non-inverted polarity): 1 = cxvp > cxvn 0 = cxvp < cxvn bit 5 unimplemented: read as 0 bit 4 cxpol: comparator output polarity select bit 1 = comparator output is inverted 0 = comparator output is not inverted bit 3 unimplemented: read as 0 bit 2 cxsp: comparator speed/power select bit 1 = comparator operates in normal-power, high-speed mode 0 = reserved. (do not use) bit 1 cxhys: comparator hysteresis enable bit 1 = comparator hysteresis enabled 0 = comparator hysteresis disabled bit 0 cxsync: comparator output synchronous mode bit 1 = comparator output to timer1 and i/o pin is synchronous to changes on timer1 clock source. output updated on the falling edge of timer1 clock source. 0 = comparator output to timer1 and i/o pin is asynchronous downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 189 pic16(l)f18326/18346 register 17-2: cmxcon1: comparator cx control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 cxintp cxintn cxpch<2:0> cxnch<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 cxintp: comparator interrupt on positive going edge enable bits 1 = the cxif interrupt flag will be set upon a positive going edge of the cxout bit 0 = no interrupt flag will be set on a positive going edge of the cxout bit bit 6 cxintn: comparator interrupt on negative going edge enable bits 1 = the cxif interrupt flag will be set upon a negative going edge of the cxout bit 0 = no interrupt flag will be set on a negative going edge of the cxout bit bit 5-3 cxpch<2:0>: comparator positive input channel select bits 111 = cxvp connects to av ss 110 = cxvp connects to fvr buffer 2 101 = cxvp connects to dac output 100 = cxvp unconnected 011 = cxvp unconnected 010 = cxvp unconnected 001 = cxvn unconnected 000 = cxvp connects to cxin0+ pin bit 2-0 cxnch<2:0>: comparator negative input channel select bits 111 = cxvn connects to av ss 110 = cxvn connects to fvr buffer 2 101 = cxvn unconnected 100 = cxvn unconnected 011 = cxvn connects to cxin3- pin 010 = cxvn connects to cxin2- pin 001 = cxvn connects to cxin1- pin 000 = cxvn connects to cxin0- pin downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 190 preliminary ? 2016 microchip technology inc. register 17-3: cmout: comparator output register u-0 u-0 u-0 u-0 u-0 u-0 r-0/0 r-0/0 mc2out mc1out bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-2 unimplemented: read as 0 bit 1 mc2out: mirror copy of c2out bit bit 0 mc1out: mirror copy of c1out bit table 17-3: summary of registers as sociated with co mparator module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela D D ansa5 ansa4 D ansa2 ansa1 ansa0 142 anselb (1) ansb7 ansb6 ansb5 ansb4 D D D D 148 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 trisa D D trisa5 trisa4 D trisa2 trisa1 trisa0 141 trisb (1) trisb7 trisb6 trisb5 trisb4 D D D D 147 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 cmxcon0 cxon cxout D cxpol D cxsp cxhys cxsync 188 cmxcon1 cxintp cxintn cxpch<2:0> cxnch<2:0> 189 cmout D D D D D D mc2out mc1out 190 fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 178 daccon0 dac1en D dac1oe D dac1pss<1:0> D dac1nss 261 daccon1 D D D dac1r<4:0> 262 intcon gie peie D D D D D intedg 98 pie2 tmr6ie c2ie c1ie nvmie ssp2ie blc2ie tmr4ie nco1ie 101 pir2 tmr6if c2if c1if nvmif ssp2if blc2if tmr4if nco1if 106 cmpxpps D D D cmpxpps<4:0> 160 clcinxpps D D D clcinxpps<4:0> 160 mdminpps D D D mdminpps<4:0> 160 t1gpps D D D t1gpps<4:0> 160 cwgxas1 D D D as4e as3e as2e as1e as0e 216 legend: = unimplemented location, read as 0 . shaded cells are unused by the comparator module. note 1: pic16(l)f18346 only. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 191 pic16(l)f18326/18346 18.0 pulse-width modulation (pwm) the pwmx modules generate pulse-width modulated (pwm) signals of varying frequency and duty cycle. in addition to the ccp modules, the pic16(l)f18326/18346 devices contain two pwm modules. these modules are essentially the same as the ccp modules without the capture or compare functionality. pulse-width modulation (pwm) is a scheme that provides power to a load by switching quickly between fully on and fully off states. the pwm signal resembles a square wave where the high portion of the signal is considered the on state (pulse width), and the low portion of the signal is considered the off state. the term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. a lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. the pwm period is defined as the duration of one complete cycle or the total amount of on and off time combined. pwm resolution defines the maximum number of steps that can be present in a single pwm period. a higher resolution allows for more precise control of the pulse-width time and in turn the power that is applied to the load. figure 18-1 shows a typical waveform of the pwm signal. figure 18-1: pwm output 18.1 standard pwm mode the standard pwm mode generates a pulse-width modulation (pwm) signal on the pwmx pin with up to ten bits of resolution. the period, duty cycle, and resolution are controlled by the following registers: tmr2, tmr4 or tmr6 registers pr2, pr4 or pr6 registers pwmxcon registers pwmxdch registers pwmxdcl registers figure 28-2 shows a simplified block diagram of the pwm operation. if pwmpol = 0 , the default state of the output is 0 . if pwmpol = 1 , the default state is 1 . if pwmen = 0 , the output will be the default state. period pulse width tmr2 = 0 tmr2 = pwmdc tmr2 = pr2 note: the corresponding tris bit must be cleared to enable the pwm output on the pwmx pin note: the formulas and text refer to tmr2 and pr2, for simplicity. the same formulas and text apply to tmr4/6 and pr4/6. the timer sources can be selected in register 18-4 . for additional information on tmr2/4/6, please refer to section 27.0 ?timer 2/4/6 module? downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 192 preliminary ? 2016 microchip technology inc. figure 18-2: simplified pwm block diagram 18.1.1 pwm period referring to figure 18-1 , the pwm output has a period and a pulse width. the frequency of the pwm is the inverse of the period (1/period). the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following formula: equation 18-1: pwm period when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the pwmx pin is set (exception: if the pwm duty cycle = 0%, the pin will not be set.) the pwm pulse width is latched from pwmxdc. 18.1.2 pwm duty cycle the pwm duty cycle is specified by writing a 10-bit value to the pwmxdc register. the pwmxdch contains the eight msbs and bits <7:6> of the pwmxdcl register contain the two lsbs. the pwmdc register is double-buffered and can be updated at any time. this double buffering is essential for glitch-free pwm operation. new values take effect when tmr2 = pr2. note that pwmdc is left-justified. the 8-bit timer tmr2 register is concatenated with either the 2-bit internal system clock (f osc ), or two bits of the prescaler, to create the 10-bit time base. the system clock is used if the timer2 prescaler is set to 1:1. equation 18-2 is used to calculate the pwm pulse width. equation 18-3 is used to calculate the pwm duty cycle ratio. equation 18-2: pulse width equation 18-3: duty cycle ratio r s qq dut ccle reg isters pwmdch pwmdcl<7:6> comparator comparator tmr2 pr2 output polarit (pwmpol) pwmx r note: if the pulse-width value is greater than the period, the assigned pwm pin(s) will remain unchanged. pwm period pr 2 ?? 1+ ?? 4t osc ? ? ? = (tmr2 prescale value) note: t osc = 1/f osc pulse width pwmxdc ?? t osc ? ? = ? (tmr2 prescale value) duty cycle ratio pwmxdc ?? 4 pr 21 + ?? ------------------------------ - = downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 193 pic16(l)f18326/18346 18.1.3 pwm resolution the resolution determines the number of available duty cycles for a given period. for example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. the maximum pwm resolution is ten bits when pr2 is 255. the resolution is a function of the pr2 register value as shown by equation 18-4 . equation 18-4: pwm resolution 18.1.4 operation in sleep mode in sleep mode, the tmr2 register will not increment and the state of the module will not change. if the pwmx pin is driving a value, it will continue to drive that value. when the device wakes up, tmr2 will continue from its previous state. 18.1.5 changes in system clock frequency the pwm frequency is derived from the system clock frequency. any changes in the system clock frequency will result in changes to the pwm frequency. see section 6.0, oscillator module (with fail-safe clock monitor) for additional details. 18.1.6 effects of reset any reset will force all ports to input mode and the pwmx registers to their reset states. 18.1.7 setup for pwm operation the following steps will be taken when configuring the module for using the pwmx outputs: 1. disable the pwmx pin output driver(s) by setting the associated tris bit(s). 2. configure the pwm output polarity by configuring the pwmxpol bit of the pwmxcon register. 3. load the pr2 register with the pwm period value, as determined by equation 18-1 . 4. load the pwmxdch register and bits <7:6> of the pwmxdcl register with the pwm duty cycle value, as determined by equation 18-2 . 5. configure and start timer2: clear the tmr2if interrupt flag bit of the pir1 register. select the timer2 prescale value by configuring the t2ckps bit of the t2con register. enable timer2 by setting the tmr2on bit of the t2con register. 6. wait until the tmr2if is set. 7. when the tmr2if flag bit is set: clear the associated tris bit(s) to enable the output driver. route the signal to the desired pin by configuring the rxypps register. enable the pwmx module by setting the pwmxen bit of the pwmxcon register. in order to send a complete duty cycle and period on the first pwm output, the above steps must be followed in the order given. if it is not critical to start with a complete pwm signal, then the pwm module can be enabled during step 2 by setting the pwmxen bit of the pwmxcon register. note: if the pulse-width value is greater than the period, the assigned pwm pin(s) will remain unchanged. resolution 4 pr 21 + ?? ?? log 2 ?? log ----------------------------------------- bits = downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 194 preliminary ? 2016 microchip technology inc. 18.2 register definitions: pwm control register 18-1: pwmxcon: pwm control register r/w-0/0 u-0 r-0 r/w-0/0 u-0 u-0 u-0 u-0 pwmxen pwmxout pwmxpol bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 pwmxen: pwm module enable bit 1 = pwm module is enabled 0 = pwm module is disabled bit 6 unimplemented: read as 0 bit 5 pwmxout: pwm module output level when bit is read. bit 4 pwmxpol: pwmx output polarity select bit 1 = pwm output is active-low. 0 = pwm output is active-high. bit 3-0 unimplemented: read as 0 register 18-2: pwmxdch: pwm duty cycle high bits r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u pwmxdc<9:2> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 pwmxdc<9:2>: pwm duty cycle most significant bits these bits are the msbs of the pwm duty cycle. the two lsbs are found in pwmxdcl register. register 18-3: pwmxdcl: pwm duty cycle low bits r/w-x/u r/w-x/u u-0 u-0 u-0 u-0 u-0 u-0 pwmxdc<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 pwmxdc<1:0>: pwm duty cycle least significant bits these bits are the lsbs of the pwm duty cycle. the msbs are found in pwmx dch register. bit 5-0 unimplemented: read as 0 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 195 pic16(l)f18326/18346 table 18-1: example pwm frequencies and resolutions (f osc = 20 mhz) pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 table 18-2: example pwm frequencies and resolutions (f osc = 8 mhz) pwm frequency 1.22 khz 4.90 khz 19.61 khz 76.92 khz 153.85 khz 200.0 khz t i m e r p r e s c a l e 1 641111 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 register 18-4: pwmtmrs: pw m timers control register u-0 u-0 u-0 u-0 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 p6tsel<1:0> p5tsel<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 unimplemented: read as 0 bit 3-2 p6tsel<1:0>: pwm6 mode timer selection bits 11 = pwm6 is based on tmr6 10 = pwm6 is based on tmr4 01 = pwm6 is based on tmr2 00 = reserved bit 1-0 p5tsel<1:0>: pwm5 mode timer selection bits 11 = pwm5 is based on tmr6 10 = pwm5 is based on tmr4 01 = pwm5 is based on tmr2 00 = reserved downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 196 preliminary ? 2016 microchip technology inc. table 18-3: summary of registers associated with pwmx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page trisa trisa5 trisa4 (2) trisa2 trisa1 trisa0 141 ansela ansa5 ansa4 ansa2 ansa1 ansa0 142 trisb (1) trisb7 trisb6 trisb5 trisb4 147 anselb (1) ansb7 ansb6 ansb5 ansb4 148 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 pwm5con pwm5en p w m 5 o u t p w m 5 p o l 194 pwm5dch pwm5dc<9:2> 194 pwm5dcl pwm5dc<1:0> 194 pwm6con pwm6en p w m 6 o u t p w m 6 p o l 194 pwm6dch pwm6dc<9:2> 194 pwm6dcl pwm6dc<1:0> 194 pwmtmrs p6tsel<1:0> p5tsel<1:0> 195 intcon gie peie i n t e d g 98 pir1 tmr1gif adif rcif txif ssp1if bcl1if tmr2if tmr1if 105 pir2 tmr6if c2if c1if nvmif ssp2if bcl2if tmr4if nco1if 106 pie1 tmr1gie adie rcie txie ssp1ie bcl1ie tmr2ie tmr1ie 100 pie2 tmr6ie c2ie c1ie nvmie ssp2ie bcl2ie tmr4ie nco1ie 101 t2con t2outps<3:0> tmr2on t2ckps<1:0> 296 t4con t4outps<3:0> tmr4on t4ckps<1:0> 290 t6con t6outps<3:0> tmr6on t6ckps<1:0> 290 tmr2 tmr2<7:0> 297 tmr4 tmr4<7:0> 297 tmr6 tmr6<7:0> 297 pr2 pr2<7:0> 297 pr4 pr4<7:0> 297 pr6 pr6<7:0> 297 rxypps rxypps<4:0> 161 cwgxdat d a t < 3 : 0 > 213 clcxsely l c x d y s < 5 : 0 > 227 mdsrc mdms<3:0> 270 mdcarh mdchpol mdchsync mdch<3:0> 271 mdcarl mdclpol mdclsync mdcl<3:0> 272 legend: - = unimplemented locations, read as 0 . shaded cells are not used by the pwm module. note 1: pic16(l)f18346 only. 2: unimplemented, read as 1 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 197 pic16(l)f18326/18346 19.0 complementary waveform generator (cwg) module the complementary waveform generator (cwgx) produces complementary waveforms with dead-band delay from a selection of input sources. the cwgx module has the following features: selectable dead-band clock source control selectable input sources output enable control output polarity control dead-band control with independent 6-bit rising and falling edge dead-band counters auto-shutdown control with: - selectable shutdown sources - auto-restart enable - auto-shutdown pin override control 19.1 fundamental operation the cwg generates two output waveforms from the selected input source. the off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time delay immediately where neither output is driven. this is referred to as dead time and is covered in section 19.6 ?dead-band control? . it may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. in this case, the active drive must be terminated before the fault condition causes damage. this is referred to as auto-shutdown and is covered in section 19.7 ?auto-shutdown control? . 19.2 operating modes the cwgx module can operate in six different modes, as specified by the mode<2:0> bits of the cwgxcon0 register: half-bridge mode push-pull mode asynchronous steering mode synchronous steering mode full-bridge mode, forward full-bridge mode, reverse all modes accept a single pulse data input, and provide up to four outputs as described in the following sections. all modes include auto-shutdown control as described in section 19.11 ?register definitions: cwg control? 19.2.1 half-bridge mode in half-bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in figure 19-1 . a non-overlap (dead-band) time is inserted between the two outputs to prevent shoot- through current in various power supply applications. dead-band control is described in section 19.6 ?dead-band control? . steering modes are not used in half-bridge mode. the unused outputs, cwgxc and cwgxd, drive similar signals with polarity independently controlled by polc and pold, respectively. figure 19-1: cwgx half- bridge mode operation note: except as noted for full-bridge mode ( section 19.2.4 ?full-bridge modes? ), mode changes may only be performed while en = 0 ( register 19-1 ). cwg [ clock input source cwg [ a cwg [ b falling event dead band rising event dead band rising event dead band falling event dead band falling event dead band rising event dead band downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 198 preliminary ? 2016 microchip technology inc. 19.2.2 push-pull mode in push-pull mode, two output signals are generated, alternating copies of the input as illustrated in figure 19-2 . this alternation creates the push-pull effect required for driving some transformer based power supply designs. dead-band control is not used in push-pull mode. steering modes are not used in push-pull mode. the push-pull sequencer is reset whenever en = 0 or if an auto-shutdown event occurs. the sequencer is clocked by the first input pulse, and the first output appears on cwgxa. the unused outputs cwgxc and cwgxd drive copies of cwgxa and cwgxb, respectively, but with polarity controlled by polc and pold. figure 19-2: cwgx push -pull mode operation 19.2.3 steering modes in both synchronous and asynchronous steering modes, the modulated input signal can be steered to any combination of four cwg outputs and a fixed-value will be presented on all the outputs not used for the pwm output. each output has independent polarity, steering, and shutdown options. dead-band control is not used in either steering mode. when stry = 0 ( register 19-5 ), the corresponding pin is held at the level defined by sdaty ( register 19-5 ). when stry = 1 , the pin is driven by the modulated input signal. the poly bits ( register 19-2 ) control the signal polarity only when stry = 1 . the cwg auto-shutdown operation also applies to steering modes as described in section 19.11 ?register definitions: cwg control? . cwg [ clock cwg [ a cwg [ b input source note: only the wgstry bits are synchronized; the wgsdaty (data) bits are not synchronized. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 199 pic16(l)f18326/18346 19.2.3.1 synchronous steering mode in synchronous steering mode (mode<2:0> bits = 001 , register 19-1 ), changes to steering selection registers take effect on the next rising edge of the modulated data input ( figure 19-3) . in synchronous steering mode, the output will always produce a complete waveform. figure 19-3: example of synchrono us steering (mode<2:0> = 001 ) 19.2.3.2 asynchronous steering mode in asynchronous mode (mode<2:0> bits = 000 , register 19-1 ), steering takes effect at the end of the instruction cycle that writes to wgxstr. in asynchronous steering mode, the output signal may be an incomplete waveform ( register 19-4 ). this operation may be useful when the user firmware needs to immediately remove a signal from the output pin. figure 19-4: example of asynchro nous steering (mode<2:0> = 000 ) 19.2.3.3 start-up considerations the application hardware must use the proper external pull-up and/or pull-down resistors on the cwg output pins. this is required because all i/o pins are forced to high-impedance at reset. the poly bits ( register 19-2 ) allow the user to choose whether the output signals are active-high or active- low. rising edge of input rising edge of input cwg [ a follows cwg [ input cwg [ input cwg [ a wgstra cwg [ input cwg [ a wgstra end of instruction cycle end of instruction cycle cwg [ a follows cwg [ input downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 200 preliminary ? 2016 microchip technology inc. 19.2.4 full-bridge modes in forward and reverse full-bridge modes, three out- puts drive static values while the fourth is modulated by the data input. dead-band control is described in section 19.2.3 ?steering modes? and section 19.6 ?dead-band control? . steering modes are not used with either of the full-bridge modes. the mode selection may be toggled between forward and reverse (changing mode<2:0>) without clearing en. when connected as shown in figure 19-5 , the outputs are appropriate for a full-bridge motor driver. each cwg output signal has independent polarity control, so the circuit can be adapted to high-active and low-active drivers. figure 19-5: example of full-bridge application v+ v- fet driver fet driver fet driver fet driver cwg [ a cwg [ b cwg [ c cwg [ d load qaqb qc qd downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 201 pic16(l)f18326/18346 19.2.4.1 full-bridge forward mode in full-bridge forward mode (mode<2:0> = 010 ), cwgxa is driven to its active state and cwgxd is modulated while cwgxb and cwgxc are driven to their inactive state, as illustrated at the top of figure 19-6. 19.2.4.2 full-bridge reverse mode in full-bridge reverse mode (mode<2:0> = 011 ), cwgxc is driven to its active state and cwgxb is modulated while cwgxa and cwgxd are driven to their inactive state, as illustrated at the bottom of figure 19-6. figure 19-6: example of full-bridge output 19.2.4.3 direction change in full-bridge mode in full-bridge mode, changing mode<2:0> controls the forward/reverse direction. changes to mode<2:0> change to the new direction on the next rising edge of the modulated input. a direction change is initiated in software by changing the mode<2:0> bits of the wgxcon0 register. the sequence is illustrated in figure 19-7 . the associated active output cwgxa and the inactive output cwgxc are switched to drive in the opposite direction. the previously modulated output cwgxd is switched to the inactive state, and the previously inactive output cwgxb begins to modulate. cwg modulation resumes after the direction-switch dead band has elapsed. note 1: a rising cwg data input creates a rising event on the modulated output. 2: output signals shown as active-high; all poly bits are clear. cwg1a (2) cwg1b (2) cwg1c (2) cwg1d (2) period pulse width (1) (1) forward mode pulse width period reverse mode cwg1a (2) cwg1b (2) cwg1c (2) cwg1d (2) (1) (1) note 1: a rising cwg1 data input creates a rising event on the modulated output. 2: output signals shown as active-hi gh; all wgpoly bits are clear. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 202 preliminary ? 2016 microchip technology inc. 19.2.4.4 dead-band delay in full-bridge mode dead-band delay is important when either of the following conditions is true: 1. the direction of the cwg output changes when the duty cycle of the data input is at or near 100%, or 2. the turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. the dead-band delay is inserted only when changing directions, and only the modulated output is affected. the statically-configured outputs (cwgxa and cwgxc) are not afforded dead band, and switch essentially simultaneously. figure 19-7 shows an example of the cwg outputs changing directions from forward to reverse, at near 100% duty cycle. in this example, at time t1, the output of cwgxa and cwgxd become inactive, while output cwgxc becomes active. since the turn-off time of the power devices is longer than the turn-on time, a shoot- through current will flow through power devices qc and qd for the duration of t. the same phenomenon will occur to power devices qa and qb for the cwg direction change from reverse to forward. if changing the cwg direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. reduce the cwg duty cycle for one period before changing directions. 2. use switch drivers that can drive the switches off faster than they can drive them on. figure 19-7: example of pwm direct ion change at near 100% duty cycle forward period reverse period t1 pulse width pulse width t on t off t = t off - t on cwg1a cwg1b cwg1c cwg1d external switch c external switch d potential shoot- through current downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 203 pic16(l)f18326/18346 figure 19-8: simplified cwgx block diagram (half-bridge mode, mode<2:0> = 100 ) rev. 10-000209a 10/16/2014 10 10 10 10 0011 10 01 0011 10 01 0011 10 01 0011 10 01 lsac<1:0> lsbd<1:0> lsac<1:0> lsbd<1:0> clock data in data out clock data in data out e d q as0e c1out as1e as2e c2out clc2 as3e shutdown = 1 ren shutdown = 0 s r q pola polb polc pold cwg data freeze dq cwg data cwgxd cwgxc cwgxb cwgxa 1 1 0 1 1 0 0 0 high-z high-z high-z high-z rising dead-band block falling dead-band block cwg data a cwg data b en auto- shutdown source shutdown cwgxpps clc4 as4e cwg data input cwg clock cwg data downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 204 preliminary ? 2016 microchip technology inc. figure 19-9: simplified cwg block diagram (push-pull mode, mode <2:0> = 101 ) rev. 10-000210a 10/16/2014 10 10 10 10 0011 10 01 0011 10 01 0011 10 01 0011 10 01 lsac<1:0> lsbd<1:0> lsac<1:0> lsbd<1:0> cwg data cwg data input e d q shutdown = 1 ren shutdown = 0 s r q pola polb polc pold cwg data freeze dq cwg data cwgxd cwgxc cwgxb cwgxa 1 1 0 1 1 0 0 0 high-z high-z high-z high-z dq q cwg data a cwg data b en auto- shutdown source shutdown as0e c1out as1e as2e c2out clc2 as3e cwgxpps clc4 as4e downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 205 pic16(l)f18326/18346 figure 19-10: simplified cwg block diagram (output steering modes) rev. 10-000211a 10/16/2014 10 10 10 10 0011 10 01 0011 10 01 0011 10 01 0011 10 01 lsac<1:0> lsbd<1:0> lsac<1:0> lsbd<1:0> cwg data input e d q shutdown = 1 ren shutdown = 0 s r q pola polb polc pold cwg data freeze dq cwgxd cwgxc cwgxb cwgxa 1 1 0 1 1 0 0 0 high-z high-z high-z high-z 10 datd strd 10 datc strc 10 datb strb 10 data stra cwg data shutdown auto- shutdown source cwg data d cwg data c cwg data b cwg data a en mode<2:0> = 000: asynchronous mode<2:0> = 001: synchronous as0e c1out as1e as2e c2out clc2 as3e cwgxpps clc4 as4e downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 206 preliminary ? 2016 microchip technology inc. figure 19-11: simplified cwg block di agram (forward and reverse full-bridge modes) rev. 10-000212a 10/16/2014 10 10 10 10 0011 10 01 0011 10 01 0011 10 01 0011 10 01 lsac<1:0> lsbd<1:0> lsac<1:0> lsbd<1:0> cwg data cwg clock clock signal in signal out clock signal in signal out cwgx data input e d q shutdown = 1 ren shutdown = 0 s r q pola polb polc pold cwg data freeze dq cwg data cwgxd cwgxc cwgxb cwgxa 1 1 0 1 1 0 0 0 high-z high-z high-z high-z rising dead-band block falling dead-band block cwg data a cwg data b en auto- shutdown source shutdown mode<2:0> = 010: forward mode<2:0> = 011: reverse cwg clock mode<2:0> cwg data cwg data cwg data c cwg data d dq q as0e c1out as1e as2e c2out clc2 as3e cwgxpps clc4 as4e downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 207 pic16(l)f18326/18346 19.3 clock source the clock source is used to drive the dead-band timing circuits. the cwgx module allows the following clock sources to be selected: f osc (system clock) hfintosc (16 mhz only) when the hfintosc is selected the hfintosc will be kept running during sleep. therefore, cwg modes requiring dead band can operate in sleep provided that the cwg data input is also active during sleep. the clock sources are selected using the cs bit of the cwgxclkcon register ( register 19-3 ). 19.4 selectable input sources the cwg generates the output waveforms from the input sources in tab le 1 9- 1 . the input sources are selected using the dat<3:0> bits in the cwgxdat register ( register 19-4 ). 19.5 output control immediately after the cwg module is enabled, the complementary drive is configured with all output drives cleared. 19.5.1 cwgx outputs each cwg output can be routed to a peripheral pin select (pps) output via the rxypps register (see section 12.0 ?peripheral pin select (pps) module? ). 19.5.2 polarity control the polarity of each cwg output can be selected independently. when the output polarity bit is set, the corresponding output is active-low. clearing the output polarity bit configures the corresponding output as active-high. however, polarity does not affect the override levels. output polarity is selected with the poly bits of the cwgxcon1 register. 19.6 dead-band control dead-band control provides for non-overlapping output signals to prevent current shoot-through in power switches. the cwgx modules contain two 6-bit dead-band counters. these counters can be loaded with values that will determine the length of the dead band initiated on either the rising or falling edges of the input source. dead-band control is used in either half- bridge or full-bridge modes. the rising-edge dead-band delay is determined by the rising dead-band count register ( register 19-8, cwgxdbr) and the falling-edge dead-band delay is determined by the falling dead-band count register ( register 19-9, cwgxdbf). dead-band duration is established by counting the cwg clock periods from zero up to the value loaded into either the rising or fall- ing dead-band counter registers. the dead-band counters are incremented on every rising edge of the cwg clock source. 19.6.1 rising edge and reverse dead band in half-bridge mode, the rising edge dead band delays the turn-on of the cwgxa output after the rising edge of the cwg data input. in full-bridge mode, the reverse dead-band delay is only inserted when changing directions from forward mode to reverse mode, and only the modulated output cwgxb is affected. the cwgxdbr register determines the duration of the dead-band interval on the rising edge of the input source signal. this duration is from 0 to 64 periods of the cwg clock. dead band is always initiated on the edge of the input source signal. a count of zero indicates that no dead band is present. if the input source signal reverses polarity before the dead-band count is completed then no output will be seen on the respective output. the cwgxdbr register value is double-buffered. if en = 0 ( register 19-1 ), the buffer is loaded when cwgxdbr is written. if en = 1 , then the buffer will be loaded at the rising edge, following the first falling edge of the data input after the ld bit ( register 19-1 ) is set. table 19-1: selectable input sources source peripheral signal name cwgxpps cwg pps input connection c1out comparator 1 output c2out comparator 2 output ccp1 capture/compare/pwm output ccp2 capture/compare/pwm output ccp3 capture/compare/pwm output ccp4 capture/compare/pwm output pwm5 pwm5 output pwm6 pwm6 output nco1 numerically controlled oscillator (nco) output clc1 configurable logic cell 1 output clc2 configurable logic cell 2 output clc3 configurable logic cell 3 output clc4 configurable logic cell 4 output downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 208 preliminary ? 2016 microchip technology inc. 19.6.2 falling edge and forward dead band in half-bridge mode, the falling edge dead band delays the turn-on of the cwgxb output at the falling edge of the cwgx data input. in full-bridge mode, the forward dead-band delay is only inserted when changing direc- tions from reverse mode to forward mode, and only the modulated output cwgxd is affected. the cwgxdbf register determines the duration of the dead-band interval on the falling edge of the input source signal. this duration is from zero to 64 periods of the cwg clock. dead band is always initiated on the edge of the input source signal. a count of zero indicates that no dead band is present. if the input source signal reverses polarity before the dead-band count is completed, then no output will be seen on the respective output. the cwgxdbf register value is double-buffered. when en = 0 ( register 19-1 ), the buffer is loaded when cwgxdbf is written. if en = 1 , then the buffer will be loaded at the rising edge following the first falling edge of the data input after the ld ( register 19-1 ) is set. 19.6.3 dead-band jitter the cwg input data signal may be asynchronous to the cwg input clock, so some jitter may occur in the observed dead band in each cycle. the maximum jitter is equal to one cwg clock period. see equation 19-1 for details and an example. equation 19-1: dead-band delay time calculation t dead band_min ? 1 f cwg_clock -------------------------------- -dbx4:0> ? ? = t dead band_max ? 1 f cwg_clock -------------------------------- -dbx4:0> 1 + ? ? = t jitter t dead band_max ? t dead band_min ? ? = t jitter 1 f cwg_clock -------------------------------- - = t dead band_max ? t dead band_min ? t jitter + = example: dbr 4:0> 0x0a 10 == ? f cwg_clock 8 mhz = t jitter 1 8 mhz ----------------- = t dead band_min ? 125 ns 10 1.25 ? s = ? = t dead band_max ? 1.25 ? s0.125 ? s1.37 ? s = + = downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 209 pic16(l)f18326/18346 19.7 auto-shutdown control auto-shutdown is a method to immediately override the cwg output levels with specific overrides that allow for safe shutdown of the circuit. the shutdown state can be either cleared automatically or held until cleared by software. 19.7.1 shutdown the shutdown state can be entered by either of the following two methods: software generated external input the shutdown bit indicates when a shutdown condition exists. the bit may be set or cleared in software or by hardware. 19.7.1.1 software-generated shutdown setting the shutdown bit of the cwgxas0 register will force the cwg into the shutdown state. when auto-restart is disabled, the shutdown state will persist as long as the shutdown bit is set. when auto-restart is enabled, the shutdown bit will clear automatically and resume operation on the next rising edge event. 19.7.1.2 external input source shutdown any of the auto-shutdown external inputs can be selected to suspend the cwg operation. these sources are individually enabled by the asxe bits of the cwgxas1 register ( register 19-7 ). when any of the selected inputs goes active (pins are active-low), the cwg outputs will immediately switch to the override levels selected by the lsbd<1:0> and lsac<1:0> bits without any software delay ( section 19.7.1.3 ?pin override levels? ). any of the following external input sources can be selected to cause a shutdown condition: comparator c1 comparator c2 clc2 cwgxpps 19.7.1.3 pin override levels the levels driven to the cwg outputs during an auto- shutdown event are controlled by the lsbd<1:0> and lsac<1:0> bits of the cwgxas0 register ( register 19-6 ). the lsbd<1:0> bits control cwgxb/d output levels, while the lsac<1:0> bits control the cwgxa/c output levels. 19.7.1.4 auto-shutdown interrupts when an auto-shutdown event occurs, either by software or hardware setting shutdown, the cwgxif flag bit of the pir4 register is set ( register 7-11 ). 19.8 auto-shutdown restart after an auto-shutdown event has occurred, there are two ways to resume operation: software controlled auto-restart in either case, the shutdown source must be cleared before the restart can take place. that is, either the shutdown condition must be removed, or the corresponding wgasxe bit must be cleared. 19.8.1 software-controlled restart if the ren bit of the cwgxasd0 register is clear (ren = 0 ), the cwgx module must be restarted after an auto-shutdown event through software. once all auto-shutdown conditions are removed, the software must clear shutdown. once shutdown is cleared, the cwg module will resume operation upon the first rising edge of the cwg data input. 19.8.2 auto-restart if the ren bit of the cwgxasd0 register is set (ren = 1 ), the cwgx module will restart from the shutdown state automatically. once all auto-shutdown conditions are removed, the hardware will automatically clear shutdown. once shutdown is cleared, the cwg module will resume operation upon the first rising edge of the cwg data input. note: shutdown inputs are level sensitive, not edge sensitive. the shutdown state cannot be cleared, except by disabling auto-shutdown, as long as the shutdown input level persists. note: shutdown bit cannot be cleared in software if the auto-shutdown condition is still present. note: shutdown bit cannot be cleared in software if the auto-shutdown condition is still present. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 210 preliminary ? 2016 microchip technology inc. 19.9 operation during sleep the cwgx module will operate during sleep, provided that the input sources remain active. if the hfintosc is selected as the module clock source, dead-band generation will remain active. this will have a direct effect on the sleep mode current. 19.10 configuring the cwg 1. ensure that the tris control bits corresponding to cwg outputs are set so that all are configured as inputs, ensuring that the outputs are inactive during setup. external hardware may ensure that pin levels are held to safe levels. 2. clear the en bit, if not already cleared. 3. configure the mode<2:0> bits of the cwgxcon0 register to set the output operating mode. 4. configure the poly bits of the cwgxcon1 register to set the output polarities. 5. configure the dat<3:0> bits of the cwgxdat register to select the data input source. 6. if a steering mode is selected, configure the stry bits to select the desired output on the cwg outputs. 7. configure the lsbd<1:0> and lsac<1:0> bits of the cwgxas0 register to select the auto- shutdown output override states (this is necessary even if not using auto-shutdown because start-up will be from a shutdown state). 8. if auto-restart is desired, set the ren bit of cwgxas0. 9. if auto-shutdown is desired, configure the asxe bits of the cwgxas1 register to select the shutdown source. 10. set the desired rising and falling dead-band times with the cwgxdbr and cwgxdbf registers. 11. select the clock source in the cwgxclkcon register. 12. set the en bit to enable the module. 13. clear the tris bits that correspond to the cwg outputs to set them as outputs. 14. if auto-restart is to be used, set the ren bit and the shutdown bit will be cleared automatically. otherwise, clear the shutdown bit in software to start the cwg. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 211 pic16(l)f18326/18346 19.11 register definitions: cwg control register 19-1: cwgxcon0: cw gx control register 0 r/w-0/0 r/w/hc-0/0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 en ld (1) m o d e < 2 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs/hc = bit is set/cleared by hardware bit 7 en: cwgx enable bit 1 = cwgx is enabled 0 = cwgx is disabled bit 6 ld: cwg load buffers bit (1) 1 = dead-band count buffers to be loaded on cwg data rising edge following first falling edge after this bit is set. 0 = buffers remain unchanged bit 5-3 unimplemented : read as 0 bit 2-0 mode<2:0> : cwgx mode bits 111 = reserved 110 = reserved 101 = cwg outputs operate in push-pull mode 100 = cwg outputs operate in half-bridge mode 011 = cwg outputs operate in reverse full-bridge mode 010 = cwg outputs operate in forward full-bridge mode 001 = cwg outputs operate in synchronous steering mode 000 = cwg outputs operate in asynchronous steering mode note 1: this bit can only be set after en = 1 ; it cannot be set in the same cycle when en is set. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 212 preliminary ? 2016 microchip technology inc. register 19-2: cwgxcon1: cw gx control register 1 u-0 u-0 r-x u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 in pold polc polb pola bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7-6 unimplemented: read as 0 bit 5 in: cwgx data input signal (read-only) bit 4 unimplemented: read as 0 bit 3 pold: wgxd output polarity bit 1 = signal output is inverted polarity 0 = signal output is normal polarity bit 2 polc: wgxc output polarity bit 1 = signal output is inverted polarity 0 = signal output is normal polarity bit 1 polb: wgxb output polarity bit 1 = signal output is inverted polarity 0 = signal output is normal polarity bit 0 pola: wgxa output polarity bit 1 = signal output is inverted polarity 0 = signal output is normal polarity register 19-3: cwgxclkcon: cwgx clock input selection register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0/0 cs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7-1 unimplemented: read as 0 bit 0 cs: cwg clock source selection select bits wgclk clock source 0 f osc 1 hfintosc (remains operating during sleep) downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 213 pic16(l)f18326/18346 register 19-4: cwgxdat: cwgx data input selection register u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 dat<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7-4 unimplemented: read as 0 bit 3-0 dat<3:0>: cwg data input selection bits wgdat data source 0000 cwgxpps 0001 c1out 0010 c2out 0011 ccp1 0100 ccp2 0101 ccp3 0110 ccp4 0111 pwm5 1000 pwm6 1001 nco1 1010 clc1 1011 clc2 1100 clc3 1101 clc4 1110 reserved 1111 reserved downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 214 preliminary ? 2016 microchip technology inc. register 19-5: cwgxstr (1) : cwg steering control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ovrd ovrc ovrb ovra strd (2) strc (2) strb (2) stra (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 ovrd: steering data d bit bit 6 ovrc: steering data c bit bit 5 ovrb: steering data b bit bit 4 ovra: steering data a bit bit 3 strd: steering enable bit d (2) 1 = cwgxd output has the cwgx data input waveform with polarity control from pold bit 0 = cwgxd output is assigned to value of ovrd bit bit 2 strc: steering enable bit c (2) 1 = cwgxc output has the cwgx data input waveform with polarity control from polc bit 0 = cwgxc output is assigned to value of ovrc bit bit 1 strb: steering enable bit b (2) 1 = cwgxb output has the cwgx data input waveform with polarity control from polb bit 0 = cwgxb output is assigned to value of ovrb bit bit 0 stra: steering enable bit a (2) 1 = cwgxa output has the cwgx data input waveform with polarity control from pola bit 0 = cwgxa output is assigned to value of ovra bit note 1: the bits in this register apply only when mode<2:0> = 00x ( register 19-1 , steering modes). 2: this bit is double-buffered when mode<2:0> = 001 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 215 pic16(l)f18326/18346 register 19-6: cwgxas0: cwg auto -shutdown control register 0 r/w/hs/sc-0/0 r/w-0/0 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 u-0 u-0 shutdown ren lsbd<1:0> lsac<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7 shutdown: auto-shutdown event status bit (1,2) 1 = an auto-shutdown state is in effect 0 = no auto-shutdown event has occurred bit 6 ren: auto-restart enable bit 1 = auto-restart is enabled 0 = auto-restart is disabled bit 5-4 lsbd<1:0>: cwgxb and cwgxd auto-shutdown state control bits 11 =a logic 1 is placed on cwgxb/d when an auto-shutdown event occurs. 10 =a logic 0 is placed on cwgxb/d when an auto-shutdown event occurs. 01 = pin is tri-stated on cwgxb/d when an auto-shutdown event occurs. 00 = the inactive state of the pin, including polarity, is placed on cwgxb/d after the required dead-band interval when an auto-shutdown event occurs. bit 3-2 lsac<1:0>: cwgxa and cwgxc auto-shutdown state control bits 11 =a logic 1 is placed on cwgxa/c when an auto-shutdown event occurs. 10 =a logic 0 is placed on cwgxa/c when an auto-shutdown event occurs. 01 = pin is tri-stated on cwg1a/c when an auto-shutdown event occurs. 00 = the inactive state of the pin, including polarity, is placed on cwgxa/c after the required dead-band interval when an auto-shutdown event occurs. bit 1-0 unimplemented: read as 0 note 1: this bit may be written while en = 0 ( register 19-1 ), to place the outputs into the shutdown configuration. 2: the outputs will remain in auto-shutdown state until the next rising edge of the cwg data input after th is bit is cleared. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 216 preliminary ? 2016 microchip technology inc. register 19-7: cwgxas1: cwg auto -shutdown control register 1 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 as4e as3e as2e as1e as0e bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7-5 unimplemented: read as 0 bit 4 as4e: cwg auto-shutdown source 4 (clc4) enable bit 1 = auto-shutdown for clc4 is enabled 0 = auto-shutdown for clc4 is disabled bit 3 as3e: cwg auto-shutdown source 3 (clc2) enable bit 1 = auto-shutdown from clc2 is enabled 0 = auto-shutdown from clc2 is disabled bit 2 as2e: cwg auto-shutdown source 2 (c2) enable bit 1 = auto-shutdown from comparator 2 is enabled 0 = auto-shutdown from comparator 2 is disabled bit 1 as1e: cwg auto-shutdown source 1 (c1) enable bit 1 = auto-shutdown from comparator 1 is enabled 0 = auto-shutdown from comparator 1 is disabled bit 0 as0e: cwg auto-shutdown source 0 (cwgxpps) enable bit 1 = auto-shutdown from cwgxpps is enabled 0 = auto-shutdown from cwgxpps is disabled register 19-8: cwgxdbr: cwgx rising dead-band count register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 d b r < 5 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7-6 unimplemented: read as 0 bit 5-0 dbr<5:0>: cwg rising edge triggered dead-band count bits 11 1111 = 63-64 cwg clock periods 11 1110 = 62-63 cwg clock periods .. . 00 0010 = 2-3 cwg clock periods 00 0001 = 1-2 cwg clock periods 00 0000 = 0 cwg clock periods. dead-band generation is bypassed. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 217 pic16(l)f18326/18346 register 19-9: cwgxdbf: cwgx falling dead-band count register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 d b f < 5 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared q = value depends on condition bit 7-6 unimplemented: read as 0 bit 5-0 dbf<5:0>: cwg falling edge triggered dead-band count bits 11 1111 = 63-64 cwg clock periods 11 1110 = 62-63 cwg clock periods .. . 00 0010 = 2-3 cwg clock periods 00 0001 = 1-2 cwg clock periods 00 0000 = 0 cwg clock periods. dead-band generation is bypassed. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 218 preliminary ? 2016 microchip technology inc. table 19-2: summary of registers associated with cwgx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page trisa D D trisa5 trisa4 D (2) trisa2 trisa1 trisa0 141 ansela D D ansa5 ansa4 D ansa2 ansa1 ansa0 142 trisb (1) trisb7 trisb6 trisb5 trisb4 D D D D 147 anselb (1) ansb7 ansb6 ansb5 ansb4 D D D D 148 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 pir4 cwg2if cwg1if tmr5gif tmr5if ccp4if ccp3if ccp2if ccp1if 108 pie4 cwg2ie cwg1ie tmr5gie tmr5ie ccp4ie ccp3ie ccp2ie ccp1ie 103 cwg1con0 en ld D D D mode<2:0> 211 cwg1con1 D D in D pold polc polb pola 212 cwg1clkcon D D D D D D D cs 212 cwg1dat D D D D dat<3:0> 213 cwg1str ovrd ovrc ovrb ovra strd strc strb stra 214 cwg1as0 shutdown ren lsbd<1:0> lsac<1:0> D D 215 cwg1as1 D D D as4e as3e as2e as1e as0e 216 cwg1dbr D D dbr<5:0> 216 cwg1dbf D D dbf<5:0> 217 cwg1pps D D D cwg1pps<4:0> 160 cwg2con0 en ld D D D mode<2:0> 211 cwg2con1 D D in D pold polc polb pola 212 cwg2clkcon D D D D D D D cs 212 cwg2dat D D D D dat<3:0> 213 cwg2str ovrd ovrc ovrb ovra strd strc strb stra 214 cwg2as0 shutdown ren lsbd<1:0> lsac<1:0> D D 215 cwg2as1 D D D as4e as3e as2e as1e as0e 216 cwg2dbr D D dbr<5:0> 216 cwg2dbf D D dbf<5:0> 217 cwg2pps D D D cwg2pps<4:0> 160 rxypps D D D rxypps<4:0> 161 note 1: pic16(l)f18346 only. 2: unimplemented, read as 0 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 219 pic16(l)f18326/18346 20.0 configurable logic cell (clc) the configurable logic cell (clcx) provides programmable logic that operates outside the speed limitations of software execution. the logic cell takes up to 32 input signals and, through the use of configurable gates, reduces the 32 inputs to four logic lines that drive one of eight selectable single-output logic functions. input sources are a combination of the following: i/o pins internal clocks peripherals register bits the output can be directed internally to peripherals and to an output pin. refer to figure 20-1 for a simplified diagram showing signal flow through the clcx. possible configurations include: combinatorial logic -and -nand - and-or - and-or-invert -or-xor -or-xnor latches -s-r - clocked d with set and reset - transparent d with set and reset - clocked j-k with reset figure 20-1: clcx simplifi ed block diagram note 1: see figure 20-2 . 2: see figure 20-3 . input data selection gates (1) logic function (2) lcxg2 lcxg1 lcxg3 lcxg4 lcxmode<2:0> lcxq lcxen lcxpol det interrupt det interrupt set bit clcxif lcxintn lcxintp clcx to peripherals q1 lcx_out lcxout mlcxout dq pps module lcx_in[0] lcx_in[1] lcx_in[2] lcx_in[29] lcx_in[30] lcx_in[35] .. . rev. 10-000025c 3/6/2014 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 220 preliminary ? 2016 microchip technology inc. 20.1 clcx setup programming the clcx module is performed by configuring the four stages in the logic signal flow. the four stages are: data selection data gating logic function selection output polarity each stage is setup at run time by writing to the corresponding clcx special function registers. this has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 20.1.1 data selection there are 36 signals available as inputs to the configurable logic. four 36-input multiplexers are used to select the inputs to pass on to the next stage. data selection is through four multiplexers as indicated on the left side of figure 20-2 . data inputs in the figure are identified by a generic numbered input name. table 20-1 correlates the generic input name to the actual signal for each clc module. the column labeled lcxdys<5:0> value indicates the mux selection code for the selected data input. lcxdys is an abbreviation for the mux select input codes: lcxd1s<5:0> through lcxd4s<5:0>. data inputs are selected with clcxsel0 through clcxsel3 registers ( register 20-3 through register 20-6 ). table 20-1: clcx data input selection note: data selections are undefined at power-up. lcxdys<5:0> value clcx input source 100011 [35] tmr6/pr6 match 100010 [34] tmr5 overflow 100001 [33] tmr4/pr4 match 100000 [32] tmr3 overflow 11111 [31] f osc 11110 [30] hfintosc 11101 [29] lfintosc 11100 [28] adcrc 11011 [27] iocif int flag bit 11010 [26] tmr2/pr2 match 11001 [25] tmr1 overflow 11000 [24] tmr0 overflow 10111 [23] eusart1 (dt) output 10110 [22] eusart1 (tx/ck) output 10101 [21] sda2 10100 [20] scl2 10011 [19] sda1 10010 [18] scl1 10001 [17] pwm6 output 10000 [16] pwm5 output 01111 [15] ccp4 output 01110 [14] ccp3 output 01101 [13] ccp2 output 01100 [12] ccp1 output 01011 [11] clkr output 01010 [10] dsm output 01001 [9] c2 output 01000 [8] c1 output 00111 [7] clc4 output 00110 [6] clc3 output 00101 [5] clc2 output 00100 [4] clc1 output 00011 [3] clcin3pps 00010 [2] clcin2pps 00001 [1] clcin1pps 00000 [0] clcin0pps downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 221 pic16(l)f18326/18346 20.1.2 data gating outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. each data gate can direct any combination of the four selected inputs. the gate stage is more than just signal direction. the gate can be configured to direct each input signal as inverted or non-inverted data. directed signals are anded together in each gate. the output of each gate can be inverted before going on to the logic function stage. the gating is in essence a 1-to-4 input and/nand/or/nor gate. when every input is inverted and the output is inverted, the gate is an or of all enabled data inputs. when the inputs and output are not inverted, the gate is an and or all enabled inputs. table 20-2 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. the table shows the logic of four input variables, but each gate can be configured to use less than four. if no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. it is possible (but not recommended) to select both the true and negated values of an input. when this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). if the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity bit to set the desired level. data gating is configured with the logic gate select registers as follows: gate 1: clcxgls0 ( register 20-7 ) gate 2: clcxgls1 ( register 20-8 ) gate 3: clcxgls2 ( register 20-9 ) gate 4: clcxgls3 ( register 20-10 ) register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register. data gating is indicated in the right side of figure 20-2 . only one gate is shown in detail. the remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate. 20.1.3 logic function there are eight available logic functions, including: and-or or-xor and s-r latch d flip-flop with set and reset d flip-flop with reset j-k flip-flop with reset transparent latch with set and reset logic functions are shown in figure 20-3 . each logic function has four inputs and one output. the four inputs are the four data gate outputs of the previous stage. the output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the clcx itself. 20.1.4 output polarity the last stage in the configurable logic cell is the output polarity. setting the lcxpol bit of the clcxpol register inverts the output signal from the logic stage. changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. note: data gating is undefined at power-up. table 20-2: data gating logic clcxglsy lcxgypol gate logic 0x55 1 and 0x55 0 nand 0xaa 1 nor 0xaa 0 or 0x00 0 logic 0 0x00 1 logic 1 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 222 preliminary ? 2016 microchip technology inc. 20.2 clcx interrupts an interrupt will be generated upon a change in the output value of the clcx when the appropriate interrupt enables are set. a rising edge detector and a falling edge detector are present in each clc for this purpose. the clcxif bit of the associated pir3 register will be set when either edge detector is triggered and its associated enable bit is set. the lcxintp bit enables rising edge interrupts and the lcxintn bit enables fall- ing edge interrupts. both are located in the clcxcon register. to fully enable the interrupt, set the following bits: clcxie bit of the pie3 register lcxintp bit of the clcxcon register (for a rising edge detection) lcxintn bit of the clcxcon register (for a falling edge detection) peie and gie bits of the intcon register the clcxif bit of the pir3 register, must be cleared in software as part of the interrupt service. if another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 20.3 output mirror copies mirror copies of all lcxcon output bits are contained in the clcdata register. reading this register reads the outputs of all clcs simultaneously. this prevents any reading skew introduced by testing or reading the lcxout bits in the individual clcxcon registers. 20.4 effects of a reset the clcxcon register is cleared to zero as the result of a reset. all other selection and gating values remain unchanged. 20.5 operation during sleep the clc module operates independently from the system clock and will continue to run during sleep, provided that the input sources selected remain active. the hfintosc remains active during sleep when the clc module is enabled and the hfintosc is selected as an input source, regardless of the system clock source selected. in other words, if the hfintosc is simultaneously selected as the system clock and as a clc input source, when the clc is enabled, the cpu will go idle during sleep, but the clc will continue to operate and the hfintosc will remain active. this will have a direct effect on the sleep mode current. 20.6 clcx setup steps the following steps will be followed when setting up the clcx: disable clcx by clearing the lcxen bit. select desired inputs using clcxsel0 through clcxsel3 registers (see table 20-1 ). clear any associated ansel bits. set all tris bits associated with inputs. clear all tris bits associated with outputs. enable the chosen inputs through the four gates using clcxgls0, clcxgls1, clcxgls2, and clcxgls3 registers. select the gate output polarities with the lcxgypol bits of the clcxpol register. select the desired logic function with the lcxmode<2:0> bits of the clcxcon register. select the desired polarity of the logic output with the lcxpol bit of the clcxpol register. (this step may be combined with the previous gate out- put polarity step). if driving a device pin, set the desired pin pps control register and also clear the tris bit corresponding to that output. if interrupts are desired, configure the following bits: - set the lcxintp bit in the clcxcon register for rising event. - set the lcxintn bit in the clcxcon register for falling event. - set the clcxie bit of the pie3 register. - set the gie and peie bits of the intcon register. enable the clcx by setting the lcxen bit of the clcxcon register. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 223 pic16(l)f18326/18346 figure 20-2: input data selection and gating lcxg1 lcxg1pol data gate 1 lcxd1g1t lcxg2 lcxg3 lcxg4 data gate 2 data gate 3 data gate 4 lcxd1g1n lcxd2g1t lcxd2g1n lcxd3g1t lcxd3g1n lcxd4g1t lcxd4g1n lcxd1s<5:0> lcxd2s<5:0> lcxd3s<5:0> lcxd4s<5:0> lcx_in[0] lcx_in[35] 000000 100011 data selection note: all controls are undefined at power-up. lcxd1t lcxd1n lcxd2t lcxd2n lcxd3t lcxd3n lcxd4t lcxd4n (same as data gate 1) (same as data gate 1) (same as data gate 1) lcx_in[0] lcx_in[35] 000000 100011 lcx_in[0] lcx_in[35] 000000 100011 lcx_in[0] lcx_in[35] 000000 100011 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 224 preliminary ? 2016 microchip technology inc. figure 20-3: programm able logic functions lcxg1lcxg2 lcxg3 lcxg4 lcxq and-or or-xor lcxmode<2:0> = 000 lcxmode<2:0> = 001 4-input and s-r latch lcxmode<2:0> = 010 lcxmode<2:0> = 011 lcxg1lcxg2 lcxg3 lcxg4 lcxq s r q lcxq lcxg1lcxg2 lcxg3 lcxg4 lcxg1lcxg2 lcxg3 lcxg4 lcxq 1-input d flip-flop with s and r 2-input d flip-flop with r j-k flip-flop with r 1-input transparent latch with s and r lcxmode<2:0> = 100 lcxmode<2:0> = 101 lcxmode<2:0> = 110 lcxmode<2:0> = 111 d r q lcxq lcxg1 lcxg2 lcxg3 lcxg4 d r q s lcxg1 lcxg2lcxg3 lcxg4 lcxq j r q k lcxg1 lcxg2lcxg3 lcxg4 lcxq d r q s le lcxq lcxg1 lcxg2lcxg3 lcxg4 rev. 10-000122a 7/30/2013 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 225 pic16(l)f18326/18346 20.7 register definitions: clc control register 20-1: clcxcon: configurable logic cell control register r/w-0/0 u-0 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 lcxen lcxout lcxintp lcxintn lcxmode<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 lcxen: configurable logic cell enable bit 1 = configurable logic cell is enabled and mixing input signals 0 = configurable logic cell is disabled and has logic zero output bit 6 unimplemented: read as 0 bit 5 lcxout: configurable logic cell data output bit read-only: logic cell output data, after lcpol; sampled from clcxout. bit 4 lcxintp: configurable logic cell positive edge going interrupt enable bit 1 = clcxif will be set when a rising edge occurs on clcxout 0 = clcxif will not be set bit 3 lcxintn: configurable logic cell negative edge going interrupt enable bit 1 = clcxif will be set when a falling edge occurs on clcxout 0 = clcxif will not be set bit 2-0 lcxmode<2:0>: configurable logic cell functional mode bits 111 = cell is 1-input transparent latch with s and r 110 = cell is j-k flip-flop with r 101 = cell is 2-input d flip-flop with r 100 = cell is 1-input d flip-flop with s and r 011 = cell is s-r latch 010 = cell is 4-input and 001 = cell is or-xor 000 = cell is and-or downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 226 preliminary ? 2016 microchip technology inc. register 20-2: clcxpol: signal polarity control register r/w-0/0 u-0 u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxpol lcxg4pol lcxg3pol lcxg2pol lcxg1pol bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 lcxpol: clcxout output polarity control bit 1 = the output of the logic cell is inverted 0 = the output of the logic cell is not inverted bit 6-4 unimplemented: read as 0 bit 3 lcxg4pol: gate 3 output polarity control bit 1 = the output of gate 3 is inverted when applied to the logic cell 0 = the output of gate 3 is not inverted bit 2 lcxg3pol: gate 2 output polarity control bit 1 = the output of gate 2 is inverted when applied to the logic cell 0 = the output of gate 2 is not inverted bit 1 lcxg2pol: gate 1 output polarity control bit 1 = the output of gate 1 is inverted when applied to the logic cell 0 = the output of gate 1 is not inverted bit 0 lcxg1pol: gate 0 output polarity control bit 1 = the output of gate 0 is inverted when applied to the logic cell 0 = the output of gate 0 is not inverted downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 227 pic16(l)f18326/18346 register 20-3: clcxsel0: generic clcx data 0 select register u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxd1s<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 lcxd1s<5:0>: clcx data1 input selection bits see table 20-1 . register 20-4: clcxsel1: generic clcx data 1 select register u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxd2s<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 lcxd2s<5:0>: clcx data 2 input selection bits see table 20-1 . register 20-5: clcxsel2: generic clcx data 2 select register u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxd3s<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 lcxd3s<5:0>: clcx data 3 input selection bits see table 20-1 . downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 228 preliminary ? 2016 microchip technology inc. register 20-6: clcxsel3: generic clcx data 3 select register u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxd4s<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 unimplemented: read as 0 bit 5-0 lcxd4s<5:0>: clcx data 4 input selection bits see table 20-1 . register 20-7: clcxgls0: gate 0 logic select register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxg1d4t lcxg1d4n lcxg1d3t lcxg1d3n lcxg1d2t lcxg1d2n lcxg1d1t lcxg1d1n bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 lcxg1d4t: gate 0 data 4 true (non-inverted) bit 1 = clcin3 (true) is gated into clcx gate 0 0 = clcin3 (true) is not gated into clcx gate 0 bit 6 lcxg1d4n: gate 0 data 4 negated (inverted) bit 1 = clcin3 (inverted) is gated into clcx gate 0 0 = clcin3 (inverted) is not gated into clcx gate 0 bit 5 lcxg1d3t: gate 0 data 3 true (non-inverted) bit 1 = clcin2 (true) is gated into clcx gate 0 0 = clcin2 (true) is not gated into clcx gate 0 bit 4 lcxg1d3n: gate 0 data 3 negated (inverted) bit 1 = clcin2 (inverted) is gated into clcx gate 0 0 = clcin2 (inverted) is not gated into clcx gate 0 bit 3 lcxg1d2t: gate 0 data 2 true (non-inverted) bit 1 = clcin1 (true) is gated into clcx gate 0 0 = clcin1 (true) is not gated into clcx gate 0 bit 2 lcxg1d2n: gate 0 data 2 negated (inverted) bit 1 = clcin1 (inverted) is gated into clcx gate 0 0 = clcin1 (inverted) is not gated into clcx gate 0 bit 1 lcxg1d1t: gate 0 data 1 true (non-inverted) bit 1 = clcin0 (true) is gated into clcx gate 0 0 = clcin0 (true) is not gated into clcx gate 0 bit 0 lcxg1d1n: gate 0 data 1 negated (inverted) bit 1 = clcin0 (inverted) is gated into clcx gate 0 0 = clcin0 (inverted) is not gated into clcx gate 0 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 229 pic16(l)f18326/18346 register 20-8: clcxgls1: gate 1 logic select register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxg2d4t lcxg2d4n lcxg2d3t lcxg2d3n lcxg2d2t lcxg2d2n lcxg2d1t lcxg2d1n bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 lcxg2d4t: gate 1 data 4 true (non-inverted) bit 1 = clcin3 (true) is gated into clcx gate 1 0 = clcin3 (true) is not gated into clcx gate 1 bit 6 lcxg2d4n: gate 1 data 4 negated (inverted) bit 1 = clcin3 (inverted) is gated into clcx gate 1 0 = clcin3 (inverted) is not gated into clcx gate 1 bit 5 lcxg2d3t: gate 1 data 3 true (non-inverted) bit 1 = clcin2 (true) is gated into clcx gate 1 0 = clcin2 (true) is not gated into clcx gate 1 bit 4 lcxg2d3n: gate 1 data 3 negated (inverted) bit 1 = clcin2 (inverted) is gated into clcx gate 1 0 = clcin2 (inverted) is not gated into clcx gate 1 bit 3 lcxg2d2t: gate 1 data 2 true (non-inverted) bit 1 = clcin1 (true) is gated into clcx gate 1 0 = clcin1 (true) is not gated into clcx gate 1 bit 2 lcxg2d2n: gate 1 data 2 negated (inverted) bit 1 = clcin1 (inverted) is gated into clcx gate 1 0 = clcin1 (inverted) is not gated into clcx gate 1 bit 1 lcxg2d1t: gate 1 data 1 true (non-inverted) bit 1 = clcin0 (true) is gated into clcx gate 1 0 = clcin0 (true) is not gated into clcx gate 1 bit 0 lcxg2d1n: gate 1 data 1 negated (inverted) bit 1 = clcin0 (inverted) is gated into clcx gate 1 0 = clcin0 (inverted) is not gated into clcx gate 1 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 230 preliminary ? 2016 microchip technology inc. register 20-9: clcxgls2: gate 2 logic select register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxg3d4t lcxg3d4n lcxg3d3t lcxg3d3n lcxg3d2t lcxg3d2n lcxg3d1t lcxg3d1n bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 lcxg3d4t: gate 2 data 4 true (non-inverted) bit 1 = clcin3 (true) is gated into clcx gate 2 0 = clcin3 (true) is not gated into clcx gate 2 bit 6 lcxg3d4n: gate 2 data 4 negated (inverted) bit 1 = clcin3 (inverted) is gated into clcx gate 2 0 = clcin3 (inverted) is not gated into clcx gate 2 bit 5 lcxg3d3t: gate 2 data 3 true (non-inverted) bit 1 = clcin2 (true) is gated into clcx gate 2 0 = clcin2 (true) is not gated into clcx gate 2 bit 4 lcxg3d3n: gate 2 data 3 negated (inverted) bit 1 = clcin2 (inverted) is gated into clcx gate 2 0 = clcin2 (inverted) is not gated into clcx gate 2 bit 3 lcxg3d2t: gate 2 data 2 true (non-inverted) bit 1 = clcin1 (true) is gated into clcx gate 2 0 = clcin1 (true) is not gated into clcx gate 2 bit 2 lcxg3d2n: gate 2 data 2 negated (inverted) bit 1 = clcin1 (inverted) is gated into clcx gate 2 0 = clcin1 (inverted) is not gated into clcx gate 2 bit 1 lcxg3d1t: gate 2 data 1 true (non-inverted) bit 1 = clcin0 (true) is gated into clcx gate 2 0 = clcin0 (true) is not gated into clcx gate 2 bit 0 lcxg3d1n: gate 2 data 1 negated (inverted) bit 1 = clcin0 (inverted) is gated into clcx gate 2 0 = clcin0 (inverted) is not gated into clcx gate 2 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 231 pic16(l)f18326/18346 register 20-10: clcxgls3: gate 3 logic select register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxg4d4t lcxg4d4n lcxg4d3t lcxg4d3n lcxg4d2t lcxg4d2n lcxg4d1t lcxg4d1n bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 lcxg4d4t: gate 3 data 4 true (non-inverted) bit 1 = clcin3 (true) is gated into clcx gate 3 0 = clcin3 (true) is not gated into clcx gate 3 bit 6 lcxg4d4n: gate 3 data 4 negated (inverted) bit 1 = clcin3 (inverted) is gated into clcx gate 3 0 = clcin3 (inverted) is not gated into clcx gate 3 bit 5 lcxg4d3t: gate 3 data 3 true (non-inverted) bit 1 = clcin2 (true) is gated into clcx gate 3 0 = clcin2 (true) is not gated into clcx gate 3 bit 4 lcxg4d3n: gate 3 data 3 negated (inverted) bit 1 = clcin2 (inverted) is gated into clcx gate 3 0 = clcin2 (inverted) is not gated into clcx gate 3 bit 3 lcxg4d2t: gate 3 data 2 true (non-inverted) bit 1 = clcin1 (true) is gated into clcx gate 3 0 = clcin1 (true) is not gated into clcx gate 3 bit 2 lcxg4d2n: gate 3 data 2 negated (inverted) bit 1 = clcin1 (inverted) is gated into clcx gate 3 0 = clcin1 (inverted) is not gated into clcx gate 3 bit 1 lcxg4d1t: gate 3 data 1 true (non-inverted) bit 1 = clcin0 (true) is gated into clcx gate 3 0 = clcin0 (true) is not gated into clcx gate 3 bit 0 lcxg4d1n: gate 3 data 1 negated (inverted) bit 1 = clcin0 (inverted) is gated into clcx gate 3 0 = clcin0 (inverted) is not gated into clcx gate 3 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 232 preliminary ? 2016 microchip technology inc. register 20-11: clcdata: clc data output u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 mlc4out mlc3out mlc2out mlc1out bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 unimplemented: read as 0 bit 3 mlc4out: mirror copy of lc4out bit bit 2 mlc3out: mirror copy of lc3out bit bit 1 mlc2out: mirror copy of lc2out bit bit 0 mlc1out: mirror copy of lc1out bit table 20-3: summary of registers associated with clcx name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 register on page ansela D D ansa5 ansa4 D ansa2 ansa1 ansa0 142 trisa D D trisa5 trisa4 D (2) trisa2 trisa1 trisa0 141 anselb (1) ansb7 ansb6 ansb5 ansb4 D D D D 148 trisb (1) trisb7 trisb6 trisb5 trisb4 D D D D 147 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 intcon gie peie D D D D D intedg 98 pir3 osfif cswif tmr3gif tmr3if clc4if clc3if clc2if clc1if 107 pie3 osfie cswie tmr3gie tmr3ie clc4ie clc3ie clc2ie clc1ie 102 clc1con lc1en D lc1out lc1intp lc1intn lc1mode<2:0> 225 clc1pol lc1pol D D D lc1g4pol lc1g3pol lc1g2pol lc1g1pol 226 clc1sel0 D D lc1d1s<5:0> 227 clc1sel1 D D lc1d2s<5:0> 227 clc1sel2 D D lc1d3s<5:0> 227 clc1sel3 D D lc1d4s<5:0> 228 clc1gls0 lc1g1d4t lc1g1d4n lc1g1d3t lc1g1d3n lc1g1d2t lc1g1d2n lc1g1d1t lc1g1d1n 228 clc1gls1 lc1g2d4t lc1g2d4n lc1g2d3t lc1g2d3n lc1g2d2t lc1g2d2n lc1g2d1t lc1g2d1n 229 clc1gls2 lc1g3d4t lc1g3d4n lc1g3d3t lc1g3d3n lc1g3d2t lc1g3d2n lc1g3d1t lc1g3d1n 230 clc1gls3 lc1g4d4t lc1g4d4n lc1g4d3t lc1g4d3n lc1g4d2t lc1g4d2n lc1g4d1t lc1g4d1n 231 clc2con lc2en D lc2out lc2intp lc2intn lc2mode<2:0> 225 clc2pol lc2pol D D D lc2g4pol lc2g3pol lc2g2pol lc2g1pol 226 clc2sel0 D D lc2d1s<5:0> 227 clc2sel1 D D lc2d2s<5:0> 227 clc2sel2 D D lc2d3s<5:0> 227 clc2sel3 D D lc2d4s<5:0> 228 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 233 pic16(l)f18326/18346 clc2gls0 lc2g1d4t lc2g1d4n lc2g1d3t lc2g1d3n lc2g1d2t lc2g1d2n lc2g1d1t lc2g1d1n 228 clc2gls1 lc2g2d4t lc2g2d4n lc2g2d3t lc2g2d3n lc2g2d2t lc2g2d2n lc2g2d1t lc2g2d1n 229 clc2gls2 lc2g3d4t lc2g3d4n lc2g3d3t lc2g3d3n lc2g3d2t lc2g3d2n lc2g3d1t lc2g3d1n 230 clc2gls3 lc2g4d4t lc2g4d4n lc2g4d3t lc2g4d3n lc2g4d2t lc2g4d2n lc2g4d1t lc2g4d1n 231 clc3con lc3en D lc3out lc3intp lc3intn lc3mode<2:0> 225 clc3pol lc3pol D D D lc3g4pol lc3g3pol lc3g2pol lc3g1pol 226 clc3sel0 D D lc3d1s<5:0> 227 clc3sel1 D D lc3d2s<5:0> 227 clc3sel2 D D lc3d3s<5:0> 227 clc3sel3 D D lc3d4s<5:0> 228 clc3gls0 lc3g1d4t lc3g1d4n lc3g1d3t lc3g1d3n lc3g1d2t lc3g1d2n lc3g1d1t lc3g1d1n 228 clc3gls1 lc3g2d4t lc3g2d4n lc3g2d3t lc3g2d3n lc3g2d2t lc3g2d2n lc3g2d1t lc3g2d1n 229 clc3gls2 lc3g3d4t lc3g3d4n lc3g3d3t lc3g3d3n lc3g3d2t lc3g3d2n lc3g3d1t lc3g3d1n 230 clc3gls3 lc3g4d4t lc3g4d4n lc3g4d3t lc3g4d3n lc3g4d2t lc3g4d2n lc3g4d1t lc3g4d1n 231 clc4con lc4en D lc4out lc4intp lc4intn lc4mode<2:0> 225 clc4pol lc4pol D D D lc4g4pol lc4g3pol lc4g2pol lc4g1pol 226 clc4sel0 D D lc4d1s<5:0> 227 clc4sel1 D D lc4d2s<5:0> 227 clc4sel2 D D lc4d3s<5:0> 227 clc4sel3 D D lc4d4s<5:0> 228 clc4gls0 lc4g1d4t lc4g1d4n lc4g1d3t lc4g1d3n lc4g1d2t lc4g1d2n lc4g1d1t lc4g1d1n 228 clc4gls1 lc4g2d4t lc4g2d4n lc4g2d3t lc4g2d3n lc4g2d2t lc4g2d2n lc4g2d1t lc4g2d1n 229 clc4gls2 lc4g3d4t lc4g3d4n lc4g3d3t lc4g3d3n lc4g3d2t lc4g3d2n lc4g3d1t lc4g3d1n 230 clc4gls3 lc4g4d4t lc4g4d4n lc4g4d3t lc4g4d3n lc4g4d2t lc4g4d2n lc4g4d1t lc4g4d1n 231 clcdata D D D D mlc4out mlc3out mlc2out mlc1out 232 clcin0pps D D D clcin0pps<4:0> 160 clcin1pps D D D clcin1pps<4:0> 160 clcin2pps D D D clcin2pps<4:0> 160 clcin3pps D D D clcin3pps<4:0> 160 clc1outpps D D D clc1outpps<4:0> 160 clc2outpps D D D clc2outpps<4:0> 160 clc3outpps D D D clc3outpps<4:0> 160 clc4outpps D D D clc4outpps<4:0> 160 table 20-3: summary of registers as sociated with clcx (continued) name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 register on page downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 234 preliminary ? 2016 microchip technology inc. 21.0 analog-to-digital converter (adc) module the analog-to-digital converter (adc) allows conversion of an analog input signal to a 10-bit binary representation of that signal. this device uses analog inputs, which are multiplexed into a single sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a 10-bit binary result via successive approximation and stores the conversion result into the adc result registers (adresh:adresl register pair). figure 21-1 shows the block diagram of the adc. the adc voltage reference is software selectable to be either internally generated or externally supplied. the adc can generate an interrupt upon completion of a conversion. this interrupt can be used to wake-up the device from sleep. figure 21-1: adc block diagram v rpos v rneg enable dacx_output fvr_buffer1 temp indicator chs<4:0> external channel inputs go/done complete start adc sample circuit write to bit go/done v ss v dd v ref + pin v dd adpref 10-bit result adresh adresl 16 adfm 10 internal channel inputs .. . an0ana anz set bit adif v ss adon sampled input q1 q2 q4 fosc divider f osc f osc /n f rc adc clock select adc_clk adcs<2:0> f rc adc clock source trigger select trigger sources ... trigsel<3:0> auto conversion trigger positive reference select rev. 10-000033a 7/30/2013 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 235 pic16(l)f18326/18346 21.1 adc configuration when configuring and using the adc the following functions must be considered: port configuration channel selection adc voltage reference selection adc conversion clock source interrupt control result formatting 21.1.1 port configuration the adc can be used to convert both analog and digital signals. when converting analog signals, the i/o pin will be configured for analog by setting the associated tris and ansel bits. refer to section 11.0 ?i/o ports? for more information. 21.1.2 channel selection there are several channel selections available: five porta pins (ra0-ra2, ra4-ra5) four portb pins (rb4-rb7, pic16(l)f18346 only) six portc pins (rc0-rc5, pic16(l)f18326) eight portc pins (rc0-rc7, pic16(l)f18346 only) temperature indicator dac output fixed voltage reference (fvr) av ss (ground) the chs<5:0> bits of the adcon0 register ( register 21-1 ) determine which channel is connected to the sample and hold circuit. when changing channels, a delay is required before starting the next conversion. refer to section 21.2 ?adc operation? for more information. 21.1.3 adc voltage reference the adpref<1:0> bits of the adcon1 register provides control of the positive voltage reference. the positive voltage reference can be: v ref + pin v dd fvr 2.048v fvr 4.096v (not available on lf devices) the adnref bit of the adcon1 register provides control of the negative voltage reference. the negative voltage reference can be: v ref - pin v ss see section 21.0 ?analog-to-digital converter (adc) module? for more details on the fixed voltage reference. 21.1.4 conversion clock the source of the conversion clock is software selectable via the adcs<2:0> bits of the adcon1 register. there are seven possible clock options: f osc /2 f osc /4 f osc /8 f osc /16 f osc /32 f osc /64 adcrc (dedicated rc oscillator) the time to complete one bit conversion is defined as t ad . one full 10-bit conversion requires 11.5 t ad periods as shown in figure 21-2 . for correct conversion, the appropriate t ad specification must be met. refer to table 34-13 for more information. table 21-1 gives examples of appropriate adc clock selections. note: analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. note: unless using the adcrc, any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 236 preliminary ? 2016 microchip technology inc. figure 21-2: analog-to-dig ital conversion t ad cycles table 21-1: adc clock period (t ad ) v s . device operating frequencies adc clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0> 32 mhz 20 mhz 16 mhz 8 mhz 4 mhz 1 mhz f osc /2 000 62.5ns (2) 100 ns (2) 125 ns (2) 250 ns (2) 500 ns (2) 2.0 ? s f osc /4 100 125 ns (2) 200 ns (2) 250 ns (2) 500 ns (2) 1.0 ? s4 . 0 ? s f osc /8 001 0.5 ? s (2) 400 ns (2) 0.5 ? s (2) 1.0 ? s2 . 0 ? s 8.0 ? s (3) f osc /16 101 800 ns 800 ns 1.0 ? s2 . 0 ? s4 . 0 ? s 16.0 ? s (3) f osc /32 010 1.0 ? s1 . 6 ? s2 . 0 ? s4 . 0 ? s 8.0 ? s (3) 32.0 ? s (2) f osc /64 110 2.0 ? s3 . 2 ? s4 . 0 ? s 8.0 ? s (3) 16.0 ? s (2) 64.0 ? s (2) adcrc x11 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) legend: shaded cells are outside of recommended range. note 1: see t ad parameter for adcrc source typical t ad value. 2: these values violate the required t ad time. 3: outside the recommended t ad time. 4: the adc clock period (t ad ) and total adc conversion time can be minimized when the adc clock is de rived from the system clock f osc . however, the adcrc oscillator source must be used when conversions are t o be performed with the device in sleep mode. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 9 t ad 10 t ad 11 set go bit conversion starts holding capacitor disconnected from analog input (thcd). on the following cycle: adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is reconnected to analog input. b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 enable adc (adon bit) and select channel (acs bits) t hcd t acq downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 237 pic16(l)f18326/18346 21.1.5 interrupts the adc module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. the adc interrupt flag is the adif bit in the pir1 register. the adc interrupt enable is the adie bit in the pie1 register. the adif bit must be cleared in software. this interrupt can be generated while the device is operating or while in sleep. if the device is in sleep, the interrupt will wake-up the device. upon waking from sleep, the next instruction following the sleep instruction is always executed. if the user is attempting to wake-up from sleep and resume in-line code execution, the adie bit of the pie1 register and the peie bit of the intcon register must both be set and the gie bit of the intcon register must be cleared. if all three of these bits are set, the execution will switch to the interrupt service routine (isr). 21.1.6 result formatting the 10-bit adc conversion result can be supplied in two formats, left justified or right justified. the adfm bit of the adcon1 register controls the output format. figure 21-3 shows the two output formats. note 1: the adif bit is set at the completion of every conversion, regardless of whether or not the adc interrupt is enabled. 2: the adc operates during sleep only when the adcrc oscillator is selected. figure 21-3: 10-bit adc conversion result format adresh adresl (adfm = 0 )m s b l s b bit 7 bit 0 bit 7 bit 0 10-bit adc result unimplemented: read as 0 (adfm = 1 ) msb lsb bit 7 bit 0 bit 7 bit 0 unimplemented: read as 0 10-bit adc result downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 238 preliminary ? 2016 microchip technology inc. 21.2 adc operation 21.2.1 starting a conversion to enable the adc module, the adon bit of the adcon0 register must be set to a 1 . setting the go/done bit of the adcon0 register to a 1 will start the analog-to-digital conversion. 21.2.2 completion of a conversion when the conversion is complete, the adc module will: clear the go/done bit set the adif interrupt flag bit update the adresh and adresl registers with new conversion result 21.2.3 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared in software. the adresh and adresl registers will be updated with the partially complete analog-to-digital conversion sample. incomplete bits will match the last bit converted. 21.2.4 adc operation during sleep the adc module can operate during sleep. this requires the adc clock source to be set to the adcrc option. when the adcrc oscillator source is selected, the adc waits one additional instruction before starting the conversion. this allows the sleep instruction to be executed, which can reduce system noise during the conversion. if the adc interrupt is enabled, the device will wake-up from sleep when the conversion completes. if the adc interrupt is disabled, the adc module is turned off after the conversion completes, although the adon bit remains set. when the adc clock source is something other than adcrc, a sleep instruction causes the present conversion to be aborted and the adc module is turned off, although the adon bit remains set. 21.2.5 auto-conversion trigger the auto-conversion trigger allows periodic adc measurements without software intervention. when a rising edge of the selected source occurs, the go/done bit is set by hardware. the auto-conversion trigger source is selected with the adact<3:0> bits of the adact register. using the auto-conversion trigger does not assure proper adc timing. it is the users responsibility to ensure that the adc timing requirements are met. see table 21-2 for auto-conversion sources. note: the go/done bit will not be set in the same instruction that turns on the adc. refer to section 21.2.6 ?adc conver- sion procedure? . note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated. table 21-2: adc auto-conversion table source peripheral description tmr0 timer0 overflow condition tmr1 timer1 overflow condition tmr3 timer3 overflow condition tmr5 timer5 overflow condition tmr2 match between timer2 and pr2 tmr4 match between timer4 and pr4 tmr6 match between timer6 and pr6 c1 comparator c1 output c2 comparator c2 output clc1 clc1 output clc2 clc2 output clc3 clc3 output clc4 clc4 output ccp1 ccp1 output ccp2 ccp2 output ccp3 ccp3 output ccp4 ccp4 output downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 239 pic16(l)f18326/18346 21.2.6 adc conversion procedure this is an example procedure for using the adc to perform an analog-to-digital conversion: 1. configure port: disable pin output driver (refer to the tris register) configure pin as analog (refer to the ansel register) 2. configure the adc module: select adc conversion clock configure voltage reference select adc input channel turn on adc module 3. configure adc interrupt (optional): clear adc interrupt flag enable adc interrupt enable peripheral interrupt enable global interrupt (1) 4. wait the required acquisition time (2) . 5. start conversion by setting the go/done bit. 6. wait for adc conversion to complete by one of the following: polling the go/done bit waiting for the adc interrupt (interrupts enabled) 7. read adc result. 8. clear the adc interrupt flag (required if interrupt is enabled). example 21-1: adc conversion note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: refer to section 21.3 ?adc acquisi- tion requirements? . ;this code block configures the adc ;for polling, vdd and vss references, adcrc ;oscillator and an0 input. ; ;conversion start & polling for completion ; are included. ; banksel adcon1 ; movlw b11110000 ;right justify, adcrc ;oscillator movwf adcon1 ;vdd and vss vref banksel trisa ; bsf trisa,0 ;set ra0 to input banksel ansel ; bsf ansel,0 ;set ra0 to analog banksel adcon0 ; movlw b00000001 ;select channel an0 movwf adcon0 ;turn adc on call sampletime ;acquisiton delay bsf adcon0,adgo ;start conversion btfsc adcon0,adgo ;is conversion done? goto $-1 ;no, test again banksel adresh ; movf adresh,w ;read upper 2 bits movwf resulthi ;store in gpr space banksel adresl ; movf adresl,w ;read lower 8 bits movwf resultlo ;store in gpr space downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 240 preliminary ? 2016 microchip technology inc. 21.3 adc acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 21-4 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), refer to figure 21-4 . the maximum recommended impedance for analog sources is 10 k ? . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an adc acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 21-1 may be used. this equation assumes that 1/2 lsb error is used (1,024 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 21-1: acquisition time example note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification. t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 2s t c temperature - 25c ?? 0.05s/c ?? ?? ++ = t c c hold r ic r ss r s ++ ?? ln(1/2047) ? = 10pf 1k ? 7k ? 10k ? ++ ?? ? ln(0.0004885) = 1.37 = s v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? = v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ;[2] v chold charge response to v applied ;combining [1] and [2] the value for t c can be approximated with the following equations: solving for t c : therefore: temperature 50c and external impedance of 10k ? 5.0v v dd = assumptions: note: where n = number of bits of the adc. t acq 2s 892ns 50c- 25c ?? 0.05 s/c ?? ?? ++ = 4.62s = downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 241 pic16(l)f18326/18346 figure 21-4: analog input model figure 21-5: adc transfer function c pin va rs analog 5 pf v dd v t ? 0.6v v t ? 0.6v i leakage (1) r ic ? 1k sampling switch ss rss c hold = 10 pf ref- 6v sampling switch 5v4v 3v 2v 567891011 (k ? ) v dd legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance various junctions r ss note 1: refer to table 34-4 (parameter d060). r ss = resistance of sampling switch input pin 3ffh 3feh adc output code 3fdh 3fch 03h02h 01h 00h full-scale 3fbh 0.5 lsb ref- zero-scale transition ref+ transition 1.5 lsb full-scale range analog input voltage downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 242 preliminary ? 2016 microchip technology inc. 21.4 register definitions: adc control register 21-1: adcon0: ad c control register 0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 chs<5:0> go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-2 chs<5:0>: analog channel select bits 111111 = fvr (fixed voltage reference) (2) 111110 = dac1 output (1) 111101 = temperature indicator (3) 111100 =av ss (analog ground) 111011 = reserved. no channel connected. 010111 =anc7 (4) 010110 =anc6 (4) 010101 =anc5 010100 =anc4 010011 =anc3 010010 =anc2 010001 =anc1 010000 =anc0 001111 =anb7 (4) 001110 =anb6 (4) 001101 =anb5 (4) 001100 =anb4 (4) 001011 = reserved. no channel connected. 000101 =ana5 000100 =ana4 000011 = reserved. no channel connected. 000010 =ana2 000001 =ana1 000000 =ana0 bit 1 go/done : adc conversion status bit 1 = adc conversion cycle in progress. setting this bit starts an adc conversion cycle. this bit is automatically cleared by hardware when the adc conversion has completed. 0 = adc conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current note 1: see section 23.0 ?5-bit digital-to-analog converter (dac1) module? for more information. 2: see section 15.0 ?fixed voltage reference (fvr)? for more information. 3: see section 16.0 ?temperature indicator module? for more information. 4: pic16(l)f18346 only. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 243 pic16(l)f18326/18346 register 21-2: adcon1: ad c control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 adfm adcs<2:0> adnref adpref<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 adfm: adc result format select bit 1 = right justified. six most significant bits of adresh are set to 0 when the conversion result is loaded. 0 = left justified. six least significant bits of adresl are set to 0 when the conversion result is loaded. bit 6-4 adcs<2:0>: adc conversion clock select bits 111 = adcrc (dedicated rc oscillator) 110 =f osc /64 101 =f osc /16 100 =f osc /4 011 = adcrc (dedicated rc oscillator) 010 =f osc /32 001 =f osc /8 000 =f osc /2 bit 3 unimplemented: read as 0 bit 2 adnref: a/d negative voltage reference configuration bit when adon = 0 , all multiplexer inputs are disconnected. 0 =v ref - is connected to av ss 1 =v ref - is connected to external v ref - bit 1-0 adpref<1:0>: adc positive voltage reference configuration bits 11 =v ref + is connected to internal fixed voltage reference (fvr) module (1) 10 =v ref + is connected to external v ref + pin (1) 01 = reserved 00 =v ref + is connected to v dd note 1: when selecting the v ref + pin as the source of the positive reference, be aware that a minimum voltage specification exists. see table 34-13 for details. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 244 preliminary ? 2016 microchip technology inc. register 21-3: adact: a/d auto-conversion trigger u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 adact<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 unimplemented: read as 0 bit 3-0 adact<3:0>: auto-conversion trigger selection bits (1) 1111 = ccp4 1110 = ccp3 1101 = ccp2 1100 = ccp1 1011 =clc4 1010 =clc3 1001 =clc2 1000 =clc1 0111 = comparator c2 0110 = comparator c1 0101 = timer2-pr2 match 0100 = timer1 overflow (2) 0011 = timer0 overflow (2) 0010 = timer6-pr6 match 0001 = timer4-pr4 match 0000 = no auto-conversion trigger selected note 1: this is a rising edge sensitive input for all sources. 2: trigger corresponds to when the peripherals interrupt flag is set. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 245 pic16(l)f18326/18346 register 21-4: adresh: adc result register high (adresh) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<9:2> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 adres<9:2> : adc result register bits upper eight bits of 10-bit conversion result register 21-5: adresl: adc result register low (adresl) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 adres<1:0> : adc result register bits lower two bits of 10-bit conversion result bit 5-0 reserved : do not use. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 246 preliminary ? 2016 microchip technology inc. register 21-6: adresh: adc result register high (adresh) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<9:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-2 reserved : do not use. bit 1-0 adres<9:8> : adc result register bits upper two bits of 10-bit conversion result register 21-7: adresl: adc result register low (adresl) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 adres<7:0> : adc result register bits lower eight bits of 10-bit conversion result downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 247 pic16(l)f18326/18346 table 21-3: summary of registers associated with adc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie i n t e d g 98 pie1 tmr1gie adie rcie txie ssp1ie bcl1ie tmr2ie tmr1ie 100 pir1 tmr1gif adif rcif txif ssp1if bcl1if tmr2if tmr1if 105 trisa trisa5 trisa4 (2) trisa2 trisa1 trisa0 141 trisb (1) trisb7 trisb6 trisb5 trisb4 147 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 ansela ansa5 ansa4 ansa2 ansa1 ansa0 142 anselb (1) ansb7 ansb6 ansb5 ansb4 148 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 adcon0 chs<5:0> go/done adon 242 adcon1 adfm adcs<2:0> adnref adpref<1:0> 243 adact adact<3:0> 244 adresh adresh<7:0> 245 adresl adresl<7:0> 245 fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 178 dac1con1 d a c 1 r < 4 : 0 > 262 oscstat1 extor hfor lfor sor ador pllr 88 legend: = unimplemented read as 0 . shaded cells are not used for the adc module. note 1: pic16(l)f18346 only. 2: unimplemented, read as 1 . downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 248 preliminary ? 2016 microchip technology inc. 22.0 numerically controlled oscillator (nco1) module the numerically controlled oscillator (nco1) module is a timer that uses the overflow from the addition of an increment value to divide the input frequency. the advantage of the addition method over simple counter-driven timer is that the output frequency resolution does not vary with the divider value. the nco1 is most useful for applications that require frequency accuracy and fine resolution at a fixed duty cycle. features of the nco1 include: 20-bit increment function fixed duty cycle (fdc) mode pulse frequency (pf) mode output pulse-width control multiple clock input sources output polarity control interrupt capability figure 22-1 is a simplified block diagram of the nco1 module. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 249 pic16(l)f18326/18346 figure 22-1: numerically controlled oscilla tor module simplified block diagram 0011 10 01 000011 010 001100 101 110 111 1 0 r s qq d qq 1 & 2 incu 1 & 2 inch 1 & 2 incl incbufu (1) incbufh (1) incbufl (1) 1 & 2 accu 1 & 2 acch 1 & 2 accl hfintosc f osc lc1 b r x w 5 h v h u y h g 1 cks<1:0> 1 pws<2:0> ripple counter 1 & 2 b f o n 1 & 2 b f o n overflow overflow reset 1 en 1 3 ) 0 1 & 2 pol 1 & 2 pps adder 1 & 2 b l nterrupt 1 & 2 if 1 & 2 b r x w bit peripherals note 1: the increment registers are double-buffered to allow for value changes to be made without first disabling the nco1 m odule. they are shown for reference only and are not user accessible. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 250 preliminary ? 2016 microchip technology inc. 22.1 nco1 operation the nco1 operates by repeatedly adding a fixed value to an accumulator. additions occur at the input clock rate. the accumulator will overflow with a carry periodically, which is the raw nco1 output (nco_overflow). this effectively reduces the input clock by the ratio of the addition value to the maximum accumulator value. see equation 22-1 . the nco1 output can be further modified by stretching the pulse or toggling a flip-flop. the modified nco1 output is then distributed internally to other peripherals and can optionally be output to a pin. the accumulator overflow also generates an interrupt (nco_interrupt). the nco1 period changes in discrete steps to create an average frequency. this output depends on the ability of the receiving circuit (i.e., cwg or external resonant converter circuitry) to average the nco1 output to reduce uncertainty. equation 22-1: nco1 operation 22.1.1 nco1 clock sources clock sources available to the nco1 include: hfintosc f osc lc1_out the nco1 clock source is selected by configuring the n1cks<1:0> bits in the nco1clk register. 22.1.2 accumulator the accumulator is a 20-bit register. read and write access to the accumulator is available through three registers: nco1accl nco1acch nco1accu 22.1.3 adder the nco1 adder is a full adder, which operates independently from the system clock. the addition of the previous result and the increment value replaces the accumulator value on the rising edge of each input clock. 22.1.4 increment registers the increment value is stored in three registers making up a 20-bit increment. in order of lsb to msb they are: nco1incl nco1inch nco1incu when the nco1 module is enabled, the nco1incu and nco1inch registers should be written first, then the nco1incl register. writing to the nco1incl register initiates the increment buffer registers to be loaded simultaneously on the second rising edge of the nco_clk signal. the registers are readable and writable. the increment registers are double-buffered to allow value changes to be made without first disabling the nco1 module. when the nco1 module is disabled, the increment buffers are loaded immediately after a write to the increment registers. f overflow nco1 clock frequency increment value ? 2 20 ------------------------------------------------------------------------------------------------------------ ------- = note: the increment buffer registers are not user-accessible. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 251 pic16(l)f18326/18346 22.2 fixed duty cycle (fdc) mode in fixed duty cycle (fdc) mode, every time the accumulator overflows (nco_overflow), the output is toggled. this provides a 50% duty cycle, provided that the increment value remains constant. for more information, see figure 22-2 . the fdc mode is selected by clearing the n1pfm bit in the nco1con register. 22.3 pulse frequency (pf) mode in pulse frequency (pf) mode, every time the accumulator overflows (nco_overflow), the output becomes active for one or more clock periods. once the clock period expires, the output returns to an inactive state. this provides a pulsed output. the output becomes active on the rising clock edge immediately following the overflow event. for more information, see figure 22-2 . the value of the active and inactive states depends on the polarity bit, n1pol, in the nco1con register. the pf mode is selected by setting the n1pfm bit in the nco1con register. 22.3.1 output pulse-width control when operating in pf mode, the active state of the output can vary in width by multiple clock periods. various pulse widths are selected with the n1pws<2:0> bits in the nco1clk register. when the selected pulse width is greater than the accumulator overflow time frame, the output of the nco1 operation is indeterminate. 22.4 output polarity control the last stage in the nco1 module is the output polarity. the n1pol bit in the nco1con register selects the output polarity. changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. the nco1 output can be used internally by source code or other peripherals. accomplish this by reading the n1out (read-only) bit of the nco1con register. the nco1 output signal is available to the following peripherals: cwg downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 252 preliminary ? 2016 microchip technology inc. figure 22-2: fdc output mode operation diagram rev. 10-000029a 11/7/2013 00000h 04000h 08000h fc000h 00000h 04000h 08000h fc000h 00000h 04000h 08000h 4000h 4000h 4000h nco_interrupt ncox output fdc mode ncox output pf mode ncoxpws = ncox output pf mode ncoxpws = ncox accumulator value ncox increment value ncox clock source 000 001 nco_overflow downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 253 pic16(l)f18326/18346 22.5 interrupts when the accumulator overflows (nco_overflow), the nco1 interrupt flag bit, nco1if, of the pir2 register is set. to enable the interrupt event (nco_interrupt), the following bits must be set: n1en bit of the nco1con register nco1ie bit of the pie2 register peie bit of the intcon register gie bit of the intcon register the interrupt must be cleared by software by clearing the nco1if bit in the interrupt service routine. 22.6 effects of a reset all of the nco1 registers are cleared to zero as the result of a reset. 22.7 operation in sleep the nco1 module operates independently from the system clock and will continue to run during sleep, provided that the clock source selected remains active. the hfintosc remains active during sleep when the nco1 module is enabled and the hfintosc is selected as the clock source, regardless of the system clock source selected. in other words, if the hfintosc is simultaneously selected as the system clock and the nco1 clock source, when the nco1 is enabled, the cpu will go idle during sleep, but the nco1 will continue to operate and the hfintosc will remain active. this will have a direct effect on the sleep mode current. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 254 preliminary ? 2016 microchip technology inc. 22.8 nco1 control registers register 22-1: nco1con: nco1 control register r/w-0/0 u-0 r-0/0 r/w-0/0 u-0 u-0 u-0 r/w-0/0 n1en n1out n1pol n 1 p f m bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 n1en: nco1 enable bit 1 = nco1 module is enabled 0 = nco1 module is disabled bit 6 unimplemented : read as 0 bit 5 n1out: nco1 output bit displays the current output value of the nco1 module bit 4 n1pol: nco1 polarity bit 1 = nco1 output signal is inverted 0 = nco1 output signal is not inverted bit 3-1 unimplemented : read as 0 bit 0 n1pfm: nco1 output divider mode bit 1 = nco1 operates in pulse frequency mode 0 = nco1 operates in fixed duty cycle mode, divide by 2 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 255 pic16(l)f18326/18346 register 22-2: nco1clk: nco1 input clock control register r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 n1pws<2:0> n1cks<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-5 n1pws<2:0>: nco1 output pulse width select bits (1, 2) 111 = nco1 output is active for 128 input clock periods 110 = nco1 output is active for 64 input clock periods 101 = nco1 output is active for 32 input clock periods 100 = nco1 output is active for 16 input clock periods 011 = nco1 output is active for 8 input clock periods 010 = nco1 output is active for 4 input clock periods 001 = nco1 output is active for 2 input clock periods 000 = nco1 output is active for 1 input clock period bit 4-2 unimplemented: read as 0 bit 1-0 n1cks<1:0>: nco1 clock source select bits 11 =reserved 10 = clc1out 01 = f osc 00 = hfintosc (16 mhz) note 1: n1pws applies only when operating in pulse frequency mode. 2: if nco1 pulse width is greater than nco1 overflow period, operation is undefined. register 22-3: nco1accl: nco1 accumulator register ? low byte r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 nco1acc<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 nco1acc<7:0>: nco1 accumulator, low byte downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 256 preliminary ? 2016 microchip technology inc. register 22-4: nco1acch: nco1 accum ulator register ? high byte r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 nco1acc<15:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other res ets 1 = bit is set 0 = bit is cleared bit 7-0 nco1acc<15:8>: nco1 accumulator, high byte register 22-5: nco1accu: nco1 accum ulator register ? upper byte (1) u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 nco1acc<19:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 unimplemented: read as 0 bit 3-0 nco1acc<19:16>: nco1 accumulator, upper byte note 1: the accumulator spans registers nco1accu:nco1acch:nco1accl. the 24 bits are reserved but not all are used.this register updates in real-time, asynchronously to the cpu; there is no provision to ensu re atomic access to this 24-bit space using an 8-bit bus. writing to this register whil e the module is operating will produce undefined results. register 22-6: nco1incl (1,2) : nco1 increment register ? low byte r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-1/1 nco1inc<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 nco1inc<7:0>: nco1 increment, low byte note 1: the logical increment spans nco1incu:nco1inch:nco1incl. 2: nco1inc is double-buffered as incbuf; incbuf is updated on the next falling edge of ncoclk after writing to nco1incl;nco1incu and nco1inch should be written prior to writing nco1incl . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 257 pic16(l)f18326/18346 register 22-7: nco1inch (1) : nco1 increment register ? high byte r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 nco1inc<15:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 nco1inc<15:8>: nco1 increment, high byte note 1: the logical increment spans nco1incu:nco1inch:nco1incl. register 22-8: nco1incu (1) : nco1 increment register ? upper byte u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 nco1inc<19:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 unimplemented: read as 0 bit 3-0 nco1inc<19:16>: nco1 increment, upper byte note 1: the logical increment spans nco1incu:nco1inch:nco1incl. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 258 preliminary ? 2016 microchip technology inc. table 22-1: summary of regi sters associated with nco1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page trisa trisa5 trisa4 (2) trisa2 trisa1 trisa0 141 ansela ansa5 ansa4 ansa2 ansa1 ansa0 142 trisb (1) trisb7 trisb6 trisb5 trisb4 147 anselb (1) ansb7 ansb6 ansb5 ansb4 148 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 pir2 tmr6if c2if c1if nvmif ssp2if bcl2if tmr4if nco1if 106 pie2 tmr6ie c2ie c1ie nvmie ssp2ie bcl2ie tmr4ie nco1ie 101 intcon gie peie intedg 98 nco1con n1en n1out n1pol n 1 p f m 254 nco1clk n1pws<2:0> n1cks<1:0> 255 nco1accl nco1acc <7:0> 255 nco1acch nco1acc <15:8> 256 nco1accu nco1acc <19:16> 256 nco1incl nco1inc<7:0> 256 nco1inch nco1inc<15:8> 257 nco1incu nco1inc<19:16> 257 rxypps rxypps<4:0> 161 cwg1dat d a t < 3 : 0 > 213 mdsrc mdms<3:0> 270 mdcarh mdchpol mdchsync mdch<3:0> 271 mdcarl mdclpol mdclsync mdcl<3:0> 272 ccpxcap ccpxcts<3:0> 308 legend: = unimplemented read as 0 . shaded cells are not used for nco1 module. note 1: pic16(l)f18346 only. 2: unimplemented, read as 1 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 259 pic16(l)f18326/18346 23.0 5-bit digital-to-analog converter (dac1) module the digital-to-analog converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. the input of the dac can be connected to: external v ref pins v dd supply voltage fvr (fixed voltage reference) the output of the dac can be configured to supply a reference voltage to the following: comparator positive input adc input channel dac1out pin the digital-to-analog converter (dac) is enabled by setting the dac1en bit of the dac1con0 register. 23.1 output voltage selection the dac has 32 voltage level ranges. the 32 levels are set with the dac1r<4:0> bits of the dac1con1 register. the dac output voltage is determined by equation 23-1 : equation 23-1: dac output voltage 23.2 ratiometric output level the dac output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. if the voltage of either input source fluctuates, a similar fluctuation will result in the dac output value. the value of the individual resistors within the ladder can be found in table 34-15 . 23.3 dac voltage reference output the dac voltage can be output to the dac1out pin by setting the dac1oe bit of the dac1con0 register. selecting the dac reference voltage for output on the dac1out pin automatically overrides the digital output buffer and digital input threshold detector functions, it disables the weak pull-up and the constant-current drive function of that pin. reading the dac1out pin when it has been configured for dac reference voltage output will always return a 0 . due to the limited current drive capability, a buffer must be used on the dac voltage reference output for external connections to the dac1out pin. figure 23-2 shows an example buffering technique. v out v source + ?? v source - ?? dac 1 r 4:0 ?? 2 5 --------------------------------- - ? ? ?? ?? ?? v source - ?? + = v source + v dd or = v source - v ss or = v ref + or fvr v ref - downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 260 preliminary ? 2016 microchip technology inc. figure 23-1: digital-to-analog co nverter block diagram figure 23-2: voltage reference ou tput buffer example note 1: the unbuffered dac1_output is provided on the dac1out pin(s). v ref + v dd v source + v source - v ss r 32 steps rr r r r r 32-to-1 mux to peripherals dac1out (1) dac1oe dac1_output dac1en dac1r<4:0> 5 0011 10 01 fvr_buffer2 reserved dac1pss 10 v ref - dac1nss dac1out buffered dac output +C dac module voltage reference output impedance r pic ? mcu downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 261 pic16(l)f18326/18346 23.4 operation during sleep the dac continues to function during sleep. when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the dac1con0 register are not affected. 23.5 effects of a reset a device reset affects the following: dac is disabled. dac output voltage is removed from the dac1out pin. the dac1r<4:0> range select bits are cleared. 23.6 register definitions: dac control register 23-1: daccon0: voltage re ference control register 0 r/w-0/0 u-0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 dac1en d a c 1 o e dac1pss<1:0> dac1nss bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 dac1en: dac1 enable bit 1 = dac is enabled 0 = dac is disabled bit 6 unimplemented: read as 0 bit 5 dac1oe: dac1 voltage output 1 enable bit 1 = dac voltage level is also an output on the dac1out pin 0 = dac voltage level is disconnected from the dac1out pin bit 4 unimplemented: read as 0 bit 3-2 dac1pss<1:0>: dac1 positive source select bits 11 = reserved, do not use 10 = fvr output 01 =v ref + pin 00 =v dd bit 1 unimplemented: read as 0 bit 0 dac1nss: dac1 negative source select bits 1 =v ref - pin 0 =v ss downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 262 preliminary ? 2016 microchip technology inc. register 23-2: daccon1: voltage re ference control register 1 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 d a c 1 r < 4 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-5 unimplemented: read as 0 bit 4-0 dac1r<4:0>: dac1 voltage output select bits v out = (v src + - v src -)*(dac1r<4:0>/32) + v src table 23-1: summary of registers associated with the dac1 module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page daccon0 dac1en d a c 1 o e dac1pss<1:0> d a c 1 n s s 261 daccon1 d a c 1 r < 4 : 0 > 262 cmxcon1 cxintp cxintn cxpch<2:0> cxnch<2:0> 189 adcon0 chs<5:0> go/done adon 242 legend: = unimplemented location, read as 0 . shaded cells are not used with the dac module. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 263 pic16(l)f18326/18346 24.0 data signal modulator (dsm) module the data signal modulator (dsm) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. both the carrier and the modulator signals are supplied to the dsm module either internally, from the output of a peripheral, or externally through an input pin. the modulated output signal is generated by performing a logical and operation of both the carrier and modulator signals and then provided to the mdout pin. the carrier signal is comprised of two distinct and separate signals. a carrier high (carh) signal and a carrier low (carl) signal. during the time in which the modulator (mod) signal is in a logic high state, the dsm mixes the carrier high signal with the modulator signal. when the modulator signal is in a logic low state, the dsm mixes the carrier low signal with the modulator signal. using this method, the dsm can generate the following types of key modulation schemes: frequency-shift keying (fsk) phase-shift keying (psk) on-off keying (ook) additionally, the following features are provided within the dsm module: carrier synchronization carrier source polarity select carrier source pin disable programmable modulator data modulator source pin disable modulated output polarity select slew rate control figure 24-1 shows a simplified block diagram of the data signal modulator peripheral. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 264 preliminary ? 2016 microchip technology inc. figure 24-1: simplified block diagram of the data signal modulator 00000001 0010 0011 0100 0101 0110 0111 1011 1100 10001001 1010 1101 1110 1111 00000001 0010 0011 0100 0101 0110 0111 1011 1100 10001001 1010 1101 1110 1111 00000001 0010 0011 0100 0101 0110 0111 1011 1100 10001001 1010 1101 1110 1111 d q d q sync sync dsm mdopol mdchpol mdclpol mdclsync mdchsync carl carh mod mdch<3:0> mdms<3:0> mdcl<3:0> v ss mdcin1mdcin2 clkr pwm5 pwm6 1 & 2 r h v h u y h g f osc hfintosc clc1 clc2 clc3clc4 ccp1ccp2 v ss mdcin1 mdcin2 clkrccp1 ccp2 pwm5pwm6 1 & 2 r h v h u y h g clc4 clc3 f osc hfintosc clc1 clc2 mdbit mdmin ccp1 ccp2 pwm5pwm6 c1c2 sdo1 sdo2 eusar t tx 1 & 2 clc1clc2 clc3 clc4 data signal modulator 10 10 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 265 pic16(l)f18326/18346 24.1 dsm operation the dsm module can be enabled by setting the mden bit in the mdcon register. clearing the mden bit in the mdcon register, disables the dsm module by auto- matically switching the carrier high and carrier low sig- nals to the v ss signal source. the modulator signal source is also switched to the mdbit in the mdcon register. this not only assures that the dsm module is inactive, but that it is also consuming the least amount of current. the values used to select the carrier high, carrier low, and modulator sources held by the modulation source, modulation high carrier, and modulation low carrier control registers are not affected when the mden bit is cleared and the dsm module is disabled. the values inside these registers remain unchanged while the dsm is inactive. the sources for the carrier high, car- rier low and modulator signals will once again be selected when the mden bit is set and the dsm module is again enabled and active. the modulated output signal can be disabled without shutting down the dsm module. the dsm module will remain active and continue to mix signals, but the out- put value will not be sent to the dsm pin. during the time that the output is disabled, the dsm pin will remain low. the modulated output can be disabled by clearing the mden bit in the mdcon register. 24.2 modulator signal sources the modulator signal can be supplied from the following sources: ccp1 signal ccp2 signal pwm5 output pwm6 output mssp1 sdo1 signal (spi mode only) mssp2 sdo2 signal (spi mode only) comparator c1 signal comparator c2 signal eusart1 tx signal external signal on mdmin pin nco1 output clc1 output clc2 output clc3 output clc4 output mdbit bit in the mdcon register the modulator signal is selected by configuring the mdms <3:0> bits in the mdsrc register. 24.3 carrier signal sources the carrier high signal and carrier low signal can be supplied from the following sources: ccp1 signal ccp2 signal pwm5 output pwm6 output nco1 output f osc (system clock) hfintosc clc1 output clc2 output clc3 output clc4 output reference clock module signal external signal on mdcin1 pin external signal on mdcin2 pin v ss the carrier high signal is selected by configuring the mdch <3:0> bits in the mdcarh register. the carrier low signal is selected by configuring the mdcl <3:0> bits in the mdcarl register. 24.4 carrier synchronization during the time when the dsm switches between carrier high and carrier low signal sources, the carrier data in the modulated output signal can become truncated. to prevent this, the carrier signal can be synchronized to the modulator signal. when the modulator signal transitions away from the synchronized carrier, the unsynchronized carrier source is immediately active, while the synchronized carrier remains active until its next falling edge. when the modulator signal transitions back to the synchronized carrier, the unsynchronized carrier is immediately disabled, and the modulator waits until the next falling edge of the synchronized carrier before the synchronized carrier becomes active. synchronization is enabled separately for the carrier high and carrier low signal sources. synchronization for the carrier high signal is enabled by setting the mdchsync bit in the mdcarh register. synchronization for the carrier low signal is enabled by setting the mdclsync bit in the mdcarl register. figure 24-1 through figure 24-6 show timing diagrams of using various synchronization methods. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 266 preliminary ? 2016 microchip technology inc. figure 24-2: on off keyi ng (ook) synchronization figure 24-3: no synchron ization (mdshsync = 0 , mdclsync = 0 ) figure 24-4: carrier high synchronization (mdshsync = 1 , mdclsync = 0 ) carrier low (carl) mdchsync = 1 mdclsync = 0 mdchsync = 1 mdclsync = 1 mdchsync = 0 mdclsync = 0 mdchsync = 0 mdclsync = 1 carrier high (carh) modulator (mod) mdchsync = 0 mdclsync = 0 modulator (mod) carrier high (carh) carrier low (carl) active carrier carh carl carl carh state mdchsync = 1 mdclsync = 0 modulator (mod) carrier high (carh) carrier low (carl) active carrier carh carl carl carh state both both downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 267 pic16(l)f18326/18346 figure 24-5: carrier low synchronization (mdshsync = 0 , mdclsync = 1 ) figure 24-6: full synchronization (mdshsync = 1 , mdclsync = 1 ) mdchsync = 0 mdclsync = 1 modulator (mod) carrier high (carh) carrier low (carl) active carrier carh carl carl carh state mdchsync = 1 mdclsync = 1 modulator (mod) carrier high (carh) carrier low (carl) active carrier carh carl carl carh state falling edges used to sync downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 268 preliminary ? 2016 microchip technology inc. 24.5 carrier source polarity select the signal provided from any selected input source for the carrier high and carrier low signals can be inverted. inverting the signal for the carrier high source is enabled by setting the mdchpol bit of the mdcarh register. inverting the signal for the carrier low source is enabled by setting the mdclpol bit of the mdcarl register. 24.6 programmable modulator data the mdbit of the mdcon register can be selected as the source for the modulator signal. this gives the user the ability to program the value used for modulation. 24.7 modulated output polarity the modulated output signal provided on the dsm pin can also be inverted. inverting the modulated output signal is enabled by setting the mdopol bit of the mdcon register. 24.8 slew rate control the slew rate limitation on the output port pin can be disabled. the slew rate limitation can be removed by clearing the slr bit of the slrcon register associated with that pin. for example, clearing the slew rate limitation for pin ra5 would require clearing the slra5 bit of the slrcona register. 24.9 operation in sleep mode the dsm module is not affected by sleep mode. the dsm can still operate during sleep, if the carrier and modulator input sources are also still operable during sleep. 24.10 effects of a reset upon any device reset, the dsm module is disabled. the users firmware is responsible for initializing the module before enabling the output. the registers are reset to their default values. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 269 pic16(l)f18326/18346 24.11 register definitions: modulation control register 24-1: mdcon: modu lation control register r/w-0/0 u-0 u-0 r/w-0/0 r-0/0 u-0 u-0 r/w-0/0 mden mdopol mdout m d b i t (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 mden: modulator module enable bit 1 = modulator module is enabled and mixing input signals 0 = modulator module is disabled and has no output bit 6-5 unimplemented: read as 0 bit 4 mdopol: modulator output polarity select bit 1 = modulator output signal is inverted; idle high output 0 = modulator output signal is not inverted; idle low output bit 3 mdout: modulator output bit displays the current output value of the modulator module (1) bit 2-1 unimplemented: read as 0 bit 0 mdbit: allows software to manually set modulation source input to module (2) note 1: the modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. 2: mdbit must be selected as the modulation source in the mdsrc register for this operation. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 270 preliminary ? 2016 microchip technology inc. register 24-2: mdsrc: modulat ion source control register u-0 u-0 u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u m d m s < 3 : 0 > bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-4 unimplemented: read as 0 bit 3-0 mdms<3:0> modulation source selection bits 1111 = clc4 output 1110 = clc3 output 1101 = clc2 output 1100 = clc1 output 1011 = nco1 output 1010 = eusart1 tx output 1001 = mssp2 sdo2 output 1000 = mssp1 sdo1 output 0111 = c2 (comparator 2) output 0110 = c1 (comparator 1) output 0101 = pwm6 output 0100 = pwm5 output 0011 = ccp2 output (pwm output mode only) 0010 = ccp1 output (pwm output mode only) 0001 = mdminpps 0000 = mdbit bit of mdcon register is modulation source downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 271 pic16(l)f18326/18346 register 24-3: mdcarh: modulation high carri er control register u-0 r/w-x/u r/w-x/u u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u mdchpol mdchsync mdch<3:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6 mdchpol: modulator high carrier polarity select bit 1 = selected high carrier signal is inverted 0 = selected high carrier signal is not inverted bit 5 mdchsync: modulator high carrier synchronization enable bit 1 = modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier 0 = modulator output is not synchronized to the high time carrier signal (1) bit 4 unimplemented: read as 0 bit 3-0 mdch<3:0> modulator data high carrier selection bits (1) 1111 = clc4 output 1110 = clc3 output 1101 = clc2 output 1100 = clc1 output 1011 =hfintosc 1010 = f osc 1001 = reserved. no channel connected. 1000 = nco1 output 0111 = pwm6 output 0110 = pwm5 output 0101 = ccp2 output (pwm output mode only) 0100 = ccp1 output (pwm output mode only) 0011 = reference clock module signal (clkr) 0010 = mdcin2pps 0001 = mdcin1pps 0000 =v ss note 1: narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized . downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 272 preliminary ? 2016 microchip technology inc. register 24-4: mdcarl: modulatio n low carrier control register u-0 r/w-x/u r/w-x/u u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u mdclpol mdclsync mdcl<3:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6 mdclpol: modulator low carrier polarity select bit 1 = selected low carrier signal is inverted 0 = selected low carrier signal is not inverted bit 5 mdclsync: modulator low carrier synchronization enable bit 1 = modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier 0 = modulator output is not synchronized to the low time carrier signal (1) bit 4 unimplemented: read as 0 bit 3-0 mdcl<3:0> modulator data high carrier selection bits (1) 1111 = clc4 output 1110 = clc3 output 1101 = clc2 output 1100 = clc1 output 1011 =hfintosc 1010 = f osc 1001 = reserved. no channel connected. 1000 = nco1 output 0111 = pwm6 output 0110 = pwm5 output 0101 = ccp2 output (pwm output mode only) 0100 = ccp1 output (pwm output mode only) 0011 = reference clock module signal (clkr) 0010 = mdcin2pps 0001 = mdcin1pps 0000 =v ss note 1: narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 273 pic16(l)f18326/18346 table 24-1: summary of registers associ ated with data signal modulator mode name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page trisa D D trisa5 trisa4 D (2) trisa2 trisa1 trisa0 141 ansela D D ansa5 ansa4 D ansa2 ansa1 ansa0 142 slrcona D D slra5 slra4 D slra2 slra1 slra0 144 inlvla D D inlvla5 inlvla4 inlvla3 inlvla2 inlvla1 inlvla0 144 trisb (1) trisb7 trisb6 trisb5 trisb4 D D D D 147 anselb (1) ansb7 ansb6 ansb5 ansb4 D D D D 148 slrconb (1) slrb7 slrb6 slrb5 slrb4 D D D D 150 inlvlb (1) inlvlb7 inlvlb6 inlvlb5 inlvlb4 D D D D 150 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 slrconc slrc7 (1) slrc6 (1) slrc5 slrc4 slrc3 slrc2 slrc1 slrc0 156 inlvlc inlvlc7 (1) inlvlc6 (1) inlvlc5 inlvlc4 inlvlc3 inlvlc2 inlvlc1 inlvlc0 157 mdcon mden D D mdopol mdout D D mdbit 269 mdsrc D D D D mdms<3:0> 270 mdcarh D mdchpol mdchsync D mdch<3:0> 271 mdcarl D mdclpol mdclsync D mdcl<3:0> 272 mdcin1pps D D D mdcin1pps<4:0> 160 mdcin2pps D D D mdcin2pps<4:0> 160 mdminpps D D D mdminpps<4:0> 160 legend: = unimplemented, read as 0 . shaded cells are not used in the data signal modulator mode. note 1: pic16(l)f18346 only. 2: unimplemented. read as 1 . downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 274 preliminary ? 2016 microchip technology inc. 25.0 timer0 module the timer0 module is an 8/16-bit timer/counter with the following features: 16-bit timer/counter 8-bit timer/counter with programmable period synchronous or asynchronous operation selectable clock sources programmable prescaler (independent of watchdog timer) programmable postscaler operation during sleep mode interrupt on match or overflow output on i/o pin (via pps) or to other peripherals 25.1 timer0 operation timer0 can operate as either an 8-bit timer/counter or a 16-bit timer/counter. the mode is selected with the t016bit bit of the t0con register. when used with an internal clock source, the module is a timer and increments on every instruction cycle. when used with an external clock source, the module can be used as either a timer or a counter and increments on every rising edge of the external source. 25.1.1 16-bit mode in normal operation, tmr0 increments on the rising edge of the clock source. a 15-bit prescaler on the clock input gives several prescale options (see prescaler control bits, t0ckps<3:0> in the t0con1 register). 25.1.1.1 timer0 reads and writes in 16-bit mode tmr0h is not the actual high byte of timer0 in 16-bit mode. it is actually a buffered version of the real high byte of timer0, which is neither directly readable nor writable (see figure 25-1 ). tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this provides the ability to read all 16 bits of timer0 without having to verify that the read of the high and low byte was valid, due to a rollover between successive reads of the high and low byte. similarly, a write to the high byte of timer0 must also take place through the tmr0h buffer register. the high byte is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. 25.1.2 8-bit mode in normal operation, tmr0 increments on the rising edge of the clock source. a 15-bit prescaler on the clock input gives several prescale options (see prescaler control bits, t0ckps<3:0> in the t0con1 register). the value of tmr0l is compared to that of the period buffer, a copy of tmr0h, on each clock cycle. when the two values match, the following events happen: tmr0_out goes high for one prescaled clock period tmr0l is reset the contents of tmr0h are copied to the period buffer in 8-bit mode, the tmr0l and tmr0h registers are both directly readable and writable. the tmr0l register is cleared on any device reset, while the tmr0h register initializes at ffh. both the prescaler and postscaler counters are cleared on the following events: a write to the tmr0l register a write to either the t0con0 or t0con1 registers. any device reset C power-on reset (por), mclr reset, watchdog timer reset (wdtr) or brown-out reset (bor) 25.1.3 counter mode in counter mode, the prescaler is normally disabled by setting the t0ckps bits of the t0con1 register to 0000 . each rising edge of the clock input (or the output of the prescaler if the prescaler is used) increments the counter by 1 . 25.1.4 timer mode in timer mode, the timer0 module will increment every instruction cycle as long as there is a valid clock signal and the t0ckps bits of the t0con1 register ( register 25-4 ) are set to 0000 . when a prescaler is added, the timer will increment at the rate based on the prescaler value. 25.1.5 asynchronous mode when the t0async bit of the t0con1 register is set (t0async = 1 ), the counter increments with each rising edge of the input source (or output of the prescaler, if used). asynchronous mode allows the counter to continue operation during sleep mode provided that the clock also continues to operate during sleep. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 275 pic16(l)f18326/18346 25.1.6 synchronous mode when the t0async bit of the t0con1 register is clear (t0async = 0 ), the counter clock is synchronized to the system oscillator (f osc /4). when operating in synchronous mode, the counter clock frequency cannot exceed f osc /4. 25.2 clock source selection the t0cs<2:0> bits of the t0con1 register are used to select the clock source for timer0. register 25-4 displays the clock source selections. 25.2.1 internal clock source when the internal clock source is selected, timer0 operates as a timer and will increment on multiples of the clock source, as determined by the timer0 prescaler. 25.2.2 external clock source when an external clock source is selected, timer0 can operate as either a timer or a counter. timer0 will increment on multiples of the rising edge of the external clock source, as determined by the timer0 prescaler. 25.3 programmable prescaler a software programmable prescaler is available for exclusive use with timer0. there are 16 prescaler options for timer0 ranging in powers of two from 1:1 to 1:32768. the prescaler values are selected using the t0ckps<3:0> bits of the t0con1 register. the prescaler is not directly readable or writable. clearing the prescaler register can be done by writing to the tmr0l register or the t0con1 register. 25.4 programmable postscaler a software programmable postscaler (output divider) is available for exclusive use with timer0. there are 16 postscaler options for timer0 ranging from 1:1 to 1:16. the postscaler values are selected using the t0outps<3:0> bits of the t0con0 register. the postscaler is not directly readable or writable. clearing the postscaler register can be done by writing to the tmr0l register or the t0con0 register. 25.5 operation during sleep when operating synchronously, timer0 will halt. when operating asynchronously, timer0 will continue to increment and wake the device from sleep (if timer0 interrupts are enabled) provided that the input clock source is active. 25.6 timer0 interrupts the timer0 interrupt flag bit (tmr0if) is set when either of the following conditions occur: 8-bit tmr0l matches the tmr0h value 16-bit tmr0 rolls over from ffffh when the postscaler bits (t0outps<3:0>) are set to 1:1 operation (no division), the t0if flag bit will be set with every tmr0 match or rollover. in general, the tmr0if flag bit will be set every t0outps +1 matches or rollovers. if timer0 interrupts are enabled (tmr0ie bit of the pie0 register = 1 ), the cpu will be interrupted and the device may wake from sleep (see section 25.5 ?operation during sleep? for more details). 25.7 timer0 output the timer0 output can be routed to any i/o pin via the rxypps output selection register (see section 12.0 ?peripheral pin select (pps) module? for additional information). the timer0 output can also be used by other peripherals, such as the auto-conversion trigger of the analog-to-digital converter. finally, the timer0 output can be monitored through software via the timer0 output bit (t0out) of the t0con0 register ( register 25-3 ). tmr0_out will be one postscaled clock period when a match occurs between tmr0l and tmr0h in 8-bit mode, or when tmr0 rolls over in 16-bit mode. the timer0 output is a 50% duty cycle that toggles on each tmr0_out rising clock edge. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 276 preliminary ? 2016 microchip technology inc. figure 25-1: block diagram of timer0 rev. 10-000017b 2/27/2014 000 011010 001 100 101 110 111 t0ckipps f osc /4 hfintosc lfintosc reserved sosc clc1 t0ckipps (inverted) t0cs<2:0> t0ckps<3:0> prescaler f osc /4 t0async t016bit t0outps<3:0> t0if t0_out peripherals tmr0 10 postscaler t0_match tmr0l comparator tmr0 high byte (1) tmr0h t0_match clear latch enable 8-bit tmr0 bod diagram (t016bit = 0) tmr0l tmr0h internal data bus 16-bit tmr0 bod diagram (t016bit = 1) sync in out tmr0 body qq d ck pps rxypps r in out tmr0 high byte (1) in out read tmr0l write tmr0l 8 8 8 8 8 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 277 pic16(l)f18326/18346 25.8 register definitions: timer0 register register 25-1: tmr0l: timer0 count register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tmr0l<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 tmr0l<7:0>: tmr0 counter bits 7..0 register 25-2: tmr0h: timer0 period register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 tmr0h<7:0> or tmr0<15:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 when t016bit = 0 tmr0h<7:0>: tmr0 period register bits 7..0 when t016bit = 1 tmr0<15:8>: tmr0 counter bits 15..8 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 278 preliminary ? 2016 microchip technology inc. register 25-3: t0con0: time r0 control register 0 r/w-0/0 u-0 r-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 t0en t0out t016bit t0outps<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 t0en: tmr0 enable bit 1 = the module is enabled and operating 0 = the module is disabled and in the lowest power mode bit 6 unimplemented: read as 0 bit 5 t0out: tmr0 output (read-only) tmr0 output bit bit 4 t016bit: tmr0 operating as 16-bit timer select bit 1 = tmr0 is a 16-bit timer 0 = tmr0 is an 8-bit timer bit 3-0 t0outps<3:0>: tmr0 output postscaler (divider) select bits 1111 = 1:16 postscaler 1110 = 1:15 postscaler 1101 = 1:14 postscaler 1100 = 1:13 postscaler 1011 = 1:12 postscaler 1010 = 1:11 postscaler 1001 = 1:10 postscaler 1000 = 1:9 postscaler 0111 = 1:8 postscaler 0110 = 1:7 postscaler 0101 = 1:6 postscaler 0100 = 1:5 postscaler 0011 = 1:4 postscaler 0010 = 1:3 postscaler 0001 = 1:2 postscaler 0000 = 1:1 postscaler downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 279 pic16(l)f18326/18346 register 25-4: t0con1: time r0 control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 t0cs<2:0> t0async t0ckps<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-5 t0cs<2:0>: timer0 clock source select bits 111 = clc1 110 = sosc 101 = reserved 100 = lfintosc 011 = hfintosc 010 = f osc /4 001 = t0ckipps (inverted) 000 = t0ckipps (true) bit 4 t0async: tmr0 input asynchronization enable bit 1 = the input to the tmr0 counter is not synchronized to system clocks 0 = the input to the tmr0 counter is synchronized to f osc /4 bit 3-0 t0ckps<3:0>: prescaler rate select bit 1111 = 1:32768 1110 = 1:16384 1101 = 1:8192 1100 = 1:4096 1011 = 1:2048 1010 = 1:1024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 280 preliminary ? 2016 microchip technology inc. table 25-1: summary of registers associated with timer0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page trisa D D trisa5 trisa4 D (2) trisa2 trisa1 trisa0 141 ansela D D ansa5 ansa4 D ansa2 ansa1 ansa0 142 trisb (1) trisb7 trisb6 trisb5 trisb4 D D D D 147 anselb (1) ansb7 ansb6 ansb5 ansb4 D D D D 148 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 tmr0l tmr0l<7:0> 277 tmr0h tmr0h<7:0> or tmr0<15:8> 277 t0con0 t0en D t0out t016bit t0outps<3:0> 278 t0con1 t0cs<2:0> t0async t0ckps<3:0> 279 t0ckipps D D D t0ckipps<4:0> 160 tmr0pps D D D tmr0pps<4:0> 160 adact D D D D adact<3:0> 244 clcxsely D D lcxdys<5:0> 227 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/done t1gval t1gss<1:0> 291 intcon gie peie D D D D D intedg 98 pir0 D D tmr0if iocif D D D intf 104 pie0 D D tmr0ie iocie D D D inte 99 legend: = unimplemented location, read as 0 . shaded cells are not used by the timer0 module. note 1: pic16(l)f18346 only. 2: unimplemented, read as 1 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 281 pic16(l)f18326/18346 26.0 timer1/3/5 module with gate control timer1/3/5 modules are 16-bit timers/counters, each with the following features: 16-bit timer/counter register pair (tmr1h:tmr1l) programmable internal or external clock source 2-bit prescaler optionally synchronized comparator out multiple timer1 gate (count enable) sources interrupt on overflow wake-up on overflow (external clock, asynchronous mode only) time base for the capture/compare function auto-conversion trigger (with ccp) selectable gate source polarity gate toggle mode gate single-pulse mode gate value status gate event interrupt figure 26-1 is a block diagram of the timer1 module. note 1: in devices with more than one timer module, it is very important to pay close attention to the register names used. a number placed after the module acronym is used to distinguish between separate modules. for example, the t1con and t3con control the same operational aspects of two completely different timer modules. 2: throughout this section, generic references to timer1 module in any of its operating modes may be interpreted as being equally applicable to timerx module. register names, module signals, i/o pins and bit names may use the generic designator x to indicate the use of a numeral to distinguish a particular module, when required. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 282 preliminary ? 2016 microchip technology inc. figure 26-1: timer1 block diagram note 1: st buffer is high speed type when using t1cki. 2: timer1 register increments on rising edge. 3: synchronize does not operate while in sleep. note 1: st buffer is high speed type when using t1cki. 2: timer1 register increments on rising edge. 3: synchronize does not operate while in sleep 0011 10 01 t1g t0_overflow c1out_sync c2out_sync t1gss<1:0> t1gpol 01 single pulse acq. control 10 t1gspm tmr1on t1gtm tmr1ge tmr1on d q en tmr1l tmr1h t1_overflow set flag bit tmr1if tmr1 (2) 1 0 fosc internal clock fosc/4 internal clock lfintosc tmr1cs<1:0> 00 11 1001 prescaler 1,2,4,8 t1sync sleep input fosc/2 internal clock t1ckps<1:0> synchronized clock input 2 det synchronize (3) (1) d q ck r q t1ggo/done t1clk t1cki dq set bit tmr1gif t1gval q1 det interrupt sosc_clk 10 t1sosc downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 283 pic16(l)f18326/18346 26.1 timer1 operation the timer1 module is a 16-bit incrementing counter which is accessed through the tmr1h:tmr1l register pair. writes to tmr1h or tmr1l directly update the counter. when used with an internal clock source, the module is a timer and increments on every instruction cycle. when used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source. timer1 is enabled by configuring the tmr1on and tmr1ge bits in the t1con and t1gcon registers, respectively. table 26-1 displays the timer1 enable selections. 26.2 clock source selection the tmr1cs<1:0> and t1sosc bits of the t1con register are used to select the clock source for timer1. table 26-2 displays the clock source selections. 26.2.1 internal clock source when the internal clock source is selected, the tmr1h:tmr1l register pair will increment on multiples of f osc as determined by the timer1 prescaler. when the f osc internal clock source is selected, the timer1 register value will in crement by four counts every instruction clock cycle. due to this condition, a 2 lsb error in resolution will occur when reading the timer1 value. to utilize the full resolution of timer1, an asynchronous input signal must be used to gate the timer1 clock input. the following asynchronous sources may be used: asynchronous event on the t1g pin to timer1 gate c1 or c2 comparator input to timer1 gate 26.2.2 external clock source when the external clock source is selected, the timer1 module may work as a timer or a counter. when enabled to count, timer1 is incremented on the rising edge of the external clock input, t1cki, which can be either synchronized to the microcontroller system clock or run asynchronously. when used as a timer with a clock oscillator, an external 32.768 khz crystal can be connected to the sosci/sosco pins. table 26-1: timer1 enable selections tmr1on tmr1ge timer1 operation 00 off 01 off 10 always on 11 count enabled note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: timer1 enabled after por write to tmr1h or tmr1l timer1 is disabled timer1 is disabled (tmr1on = 0 ) when t1cki is high then timer1 is enabled (tmr1on= 1 ) when t1cki is low. table 26-2: clock source selections tmr1cs<1:0> clock source 11 lfintosc 10 external clocking on t1cki pin 01 system clock (f osc ) 00 instruction clock (f osc /4) downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 284 preliminary ? 2016 microchip technology inc. 26.3 timer1 prescaler timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. the t1ckps bits of the t1con register control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmr1h or tmr1l. 26.4 timer1 (secondary) oscillator a dedicated low-power 32.768 khz oscillator circuit is built-in between pins sosci (input) and sosco (amplifier output). this internal circuit is designed to be used in conjunction with an external 32.768 khz crystal. the oscillator circuit is enabled by setting the t1sosc bit of the t1con register. the oscillator will continue to run during sleep. 26.5 timer1 operation in asynchronous counter mode if the control bit t1sync of the t1con register is set, the external clock input is not synchronized. the timer increments asynchronously to the internal phase clocks. if the external clock source is selected then the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in software are needed to read/write the timer (see section 26.5.1 ?reading and writing timer1 in asynchronous counter mode? ). 26.5.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write contention may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the tmr1h:tmr1l register pair. 26.6 timer1 gate timer1 can be configured to count freely or the count can be enabled and disabled using timer1 gate circuitry. this is also referred to as timer1 gate enable. timer1 gate can also be driven by multiple selectable sources. 26.6.1 timer1 gate enable the timer1 gate enable mode is enabled by setting the tmr1ge bit of the t1gcon register. the polarity of the timer1 gate enable mode is configured using the t1gpol bit of the t1gcon register. when timer1 gate enable mode is enabled, timer1 will increment on the rising edge of the timer1 clock source. when timer1 gate enable mode is disabled, no incrementing will occur and timer1 will hold the current count. see figure 26-3 for timing details. note: the oscillator requires a start-up and stabilization time before use. thus, t1sosc should be set and a suitable delay observed prior to using timer1. a suitable delay similar to the ost delay can be implemented in software by clearing the tmr1if bit then presetting the tmr1h:tmr1l register pair to fc00h. the tmr1if flag will be set when 1024 clock cycles have elapsed, thereby indicating that the oscillator is running and reasonably stable. note: when switching from synchronous to asynchronous operation, it is possible to skip an increment. when switching from asynchronous to synchronous operation, it is possible to produce an additional increment. table 26-3: timer1 gate enable selections t1clk t1gpol t1g timer1 operation ? 00 counts ? 01 holds count ? 10 holds count ? 11 counts downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 285 pic16(l)f18326/18346 26.6.2 timer1 gate source selection timer1 gate source selections are shown in table 26-4 . source selection is controlled by the t1gss bits of the t1gcon register. the polarity for each available source is also selectable. polarity selection is controlled by the t1gpol bit of the t1gcon register. 26.6.2.1 t1g pin gate operation the t1g pin is one source for timer1 gate control. it can be used to supply an external source to the timer1 gate circuitry. 26.6.2.2 timer0 overflow gate operation when timer0 increments from ffh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the timer1 gate circuitry. 26.6.2.3 comparator c1 gate operation the output resulting from a comparator 1 operation can be selected as a source for timer1 gate control. the comparator 1 output can be synchronized to the timer1 clock or left asynchronous. for more information see section 17.4.1 ?comparator output synchronization? . 26.6.2.4 comparator c2 gate operation the output resulting from a comparator 2 operation can be selected as a source for timer1 gate control. the comparator 2 output can be synchronized to the timer1 clock or left asynchronous. for more information see section 17.4.1 ?comparator output synchronization? . 26.6.3 timer1 gate toggle mode when timer1 gate toggle mode is enabled, it is possible to measure the full-cycle length of a timer1 gate signal, as opposed to the duration of a single level pulse. the timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. see figure 26-4 for timing details. timer1 gate toggle mode is enabled by setting the t1gtm bit of the t1gcon register. when the t1gtm bit is cleared, the flip-flop is cleared and held clear. this is necessary in order to control which edge is measured. 26.6.4 timer1 gate single-pulse mode when timer1 gate single-pulse mode is enabled, it is possible to capture a single-pulse gate event. timer1 gate single-pulse mode is first enabled by setting the t1gspm bit in the t1gcon register. next, the t1ggo/done bit in the t1gcon register must be set. the timer1 will be fully enabled on the next incrementing edge. on the next trailing edge of the pulse, the t1ggo/done bit will automatically be cleared. no other gate events will be allowed to increment timer1 until the t1ggo/done bit is once again set in software. see figure 26-5 for timing details. if the single-pulse gate mode is disabled by clearing the t1gspm bit in the t1gcon register, the t1ggo/done bit should also be cleared. enabling the toggle mode and the single-pulse mode simultaneously will permit both sections to work together. this allows the cycle times on the timer1 gate source to be measured. see figure 26-6 for timing details. 26.6.5 timer1 gate value status when timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. the value is stored in the t1gval bit in the t1gcon register. the t1gval bit is valid even when the timer1 gate is not enabled (tmr1ge bit is cleared). 26.6.6 timer1 gate event interrupt when timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. when the falling edge of t1gval occurs, the tmr1gif flag bit in the pir1 register will be set. if the tmr1gie bit in the pie1 register is set, then an interrupt will be recognized. the tmr1gif flag bit operates even when the timer1 gate is not enabled (tmr1ge bit is cleared). table 26-4: timer1 gate sources t1gss timer1 gate source 00 timer1 gate pin 01 overflow of timer0 (tmr0 increments from ffh to 00h) 10 comparator 1 output (optionally timer1 synchronized output) 11 comparator 2 output (optionally timer1 synchronized output) note: enabling toggle mode at the same time as changing the gate polarity may result in indeterminate operation. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 286 preliminary ? 2016 microchip technology inc. 26.7 timer1 interrupt the timer1 register pair (tmr1h:tmr1l) increments to ffffh and rolls over to 0000h. when timer1 rolls over, the timer1 interrupt flag bit of the pir1 register is set. to enable the interrupt on rollover, you must set these bits: tmr1on bit of the t1con register tmr1ie bit of the pie1 register peie bit of the intcon register gie bit of the intcon register the interrupt is cleared by clearing the tmr1if bit in the interrupt service routine. 26.8 timer1 operation during sleep timer1 can only operate during sleep when setup in asynchronous counter mode. in this mode, an external crystal or clock source can be used to increment the counter. to set up the timer to wake the device: tmr1on bit of the t1con register must be set tmr1ie bit of the pie1 register must be set peie bit of the intcon register must be set t1sync bit of the t1con register must be set tmr1cs bits of the t1con register must be configured t1sosc bit of the t1con register must be configured the device will wake-up on an overflow and execute the next instructions. if the gie bit of the intcon register is set, the device will call the interrupt service routine. secondary oscillator will continue to operate in sleep regardless of the t1sync bit setting. 26.9 ccp capture/compare time base the ccp modules use the tmr1h:tmr1l register pair as the time base when operating in capture or compare mode. in capture mode, the value in the tmr1h:tmr1l register pair is copied into the ccpr1h:ccpr1l register pair on a configured event. in compare mode, an event is triggered when the value ccpr1h:ccpr1l register pair matches the value in the tmr1h:tmr1l register pair. this event can be an auto-conversion trigger. for more information, see section 28.0 ?capture/compare/pwm modules? . 26.10 ccp auto-conversion trigger when any of the ccps are configured to trigger an auto-conversion, the trigger will clear the tmr1h:tmr1l register pair. this auto-conversion does not cause a timer1 interrupt. the ccp module may still be configured to generate a ccp interrupt. in this mode of operation, the ccpr1h:ccpr1l register pair becomes the period register for timer1. timer1 should be synchronized and f osc /4 should be selected as the clock source in order to utilize the auto-conversion trigger. asynchronous operation of timer1 can cause an auto-conversion trigger to be missed. in the event that a write to tmr1h or tmr1l coincides with an auto-conversion trigger from the ccp, the write will take precedence. for more information, see section 28.3.3 ?auto-conversion trigger? . figure 26-2: timer1 incrementing edge note: the tmr1h:tmr1l register pair and the tmr1if bit should be cleared before enabling interrupts. t1cki = 1 when tmr1 enabled t1cki = 0 when tmr1 enabled note 1: arrows indicate counter increments. 2: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 287 pic16(l)f18326/18346 figure 26-3: timer1 gate enable mode figure 26-4: timer1 gate toggle mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 n n + 1 n + 2 n + 3 n + 4 tmr1ge t1gpol t1gtm t1g_in t1cki t1gval timer1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 288 preliminary ? 2016 microchip technology inc. figure 26-5: timer1 gate single-pulse mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 n n + 1 n + 2 t1gspm t1ggo/ done set by software cleared by hardware on falling edge of t1gval set by hardware on falling edge of t1gval cleared by software cleared by software tmr1gif counting enabled on rising edge of t1g downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 289 pic16(l)f18326/18346 figure 26-6: timer1 gate single-pulse and toggle combined mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 nn + 1 n + 2 t1gspm t1ggo/ done set by software cleared by hardware on falling edge of t1gval set by hardware on falling edge of t1gval cleared by software cleared by software tmr1gif t1gtm counting enabled on rising edge of t1g n + 4 n + 3 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 290 preliminary ? 2016 microchip technology inc. 26.11 register definitions: timer1/3/5 control register 26-1: txcon (1) : timerx control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u u-0 r/w-0/u tmrxcs<1:0> txckps<1:0> txsosc t xs ync t m r x o n bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-6 tmrxcs<1:0>: timerx clock source select bits 11 = timerx clock source is lfintosc 10 = timerx clock source is pin or oscillator: if t xs osc = 0 : external clock from txckipps pin (on the rising edge) if t xs osc = 1 : clock from sosc, either crystal oscillator on txsosci/txsosco pins, or soscin input 01 = timerx clock source is system clock (f osc ) 00 = timerx clock source is instruction clock (f osc /4) bit 5-4 txckps<1:0>: timerx input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 txsosc: lp oscillator enable control bit 1 = sosc requested as the clock source 0 = txcki enabled as the clock source bit 2 t xs ync : timer1 synchronization control bit tmrxcs<1:0> = 1x 1 = do not synchronize external clock input 0 = synchronize external clock input with system clock tmrxcs<1:0> = 0x this bit is ignored. timer1 uses the internal clock and no additional synchronization is performed. bit 1 unimplemented: read as 0 bit 0 tmrxon: timer1 on bit 1 = enables timerx 0 = stops timerx and clears timerx gate flip-flop note 1: x refers to either 1, 3 or 5 for the respective timer1/3/5 registers. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 291 pic16(l)f18326/18346 register 26-2: txgcon (1) : timerx gate control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w/hc-0/u r-x/x r/w-0/u r/w-0/u tmrxge txgpol txgtm txgspm txggo/d one txgval txgss<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hc = bit is cleared by hardware bit 7 tmrxge: timer1 gate enable bit if tmr xo n = 0 : this bit is ignored if tmr xo n = 1 : 1 = timerx counting is controlled by the timer1 gate function 0 = timerx is always counting bit 6 txgpol: timerx gate polarity bit 1 = timerx gate is active-high (timerx counts when gate is high) 0 = timerx gate is active-low (timerx counts when gate is low) bit 5 txgtm: timerx gate toggle mode bit 1 = timerx gate toggle mode is enabled 0 = timerx gate toggle mode is disabled and toggle flip-flop is cleared timerx gate flip-flop toggles on every rising edge. bit 4 txgspm: timerx gate single-pulse mode bit 1 = timerx gate single-pulse mode is enabled and is controlling timerx gate 0 = timerx gate single-pulse mode is disabled bit 3 txggo/done : timerx gate single-pulse acquisition status bit 1 = timerx gate single-pulse acquisition is ready, waiting for an edge 0 = timerx gate single-pulse acquisition has completed or has not been started this bit is automatically cleared when txgspm is cleared bit 2 txgval: timerx gate value status bit indicates the current state of the timerx gate that could be provided to tmrxh:tmrxl unaffected by timerx gate enable (tmrxge) bit 1-0 txgss<1:0>: timerx gate source select bits 11 = comparator 2 optionally synchronized output 10 = comparator 1 optionally synchronized output 01 = timer0 overflow output 00 = timerx gate pin note 1: x refers to either 1, 3 or 5 for the respective timer1/3/5 registers. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 292 preliminary ? 2016 microchip technology inc. register 26-3: tmrxl (1) : timerx low byte register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u tmrxl<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 tmrxl<7:0>: tmrx low byte bits note 1: x refers to either 1, 3 or 5 for the respective timer1/3/5 registers. register 26-4: tmrxh (1) : timerx high byte register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u tmrxh<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 tmrxh<7:0>: tmrx high byte bits note 1: x refers to either 1, 3 or 5 for the respective timer1/3/5 registers. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 293 pic16(l)f18326/18346 table 26-5: summary of registers associated with timer1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page trisa D D trisa5 trisa4 D (2) trisa2 trisa1 trisa0 141 ansela D D ansa5 ansa4 D ansa2 ansa1 ansa0 142 trisb (1) trisb7 trisb6 trisb5 trisb4 D D D D 147 anselb (1) ansb7 ansb6 ansb5 ansb4 D D D D 148 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 intcon gie peie D D D D D intedg 98 pir1 tmr1gif adif rcif txif ssp1if bcl1if tmr2if tmr1if 105 pie1 tmr1gie adie rcie txie ssp1ie bcl1ie tmr2ie tmr1ie 100 pir3 osfif cswif tmr3gif tmr3if clc4if clc3if clc2if clc1if 107 pie3 osfie cswie tmr3gie tmr3ie clc4ie clc3ie clc2ie clc1ie 102 pir4 cwg2if cwg1if tmr5gif tmr5if ccp4if ccp3if ccp2if ccp1if 108 pie4 cwg2ie cwg1ie tmr5gie tmr5ie ccp4ie ccp3ie ccp2ie ccp1ie 103 t1con tmr1cs<1:0> t1ckps<1:0> t1sosc t1sync D tmr1on 290 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/done t1gval t1gss<1:0> 291 tmr1l tmr1l<7:0> 292 tmr1h tmr1h<7:0> 292 t1ckipps D D D t1ckipps<4:0> 160 t1gpps D D D t1gpps<4:0> 160 t3con tmr3cs<1:0> t3ckps<1:0> t3sosc t3sync D tmr3on 290 t3gcon tmr3ge t3gpol t3gtm t3gspm t3ggo/done t3gval t3gss<1:0> 291 tmr3l tmr3l<7:0> 292 tmr3h tmr3h<7:0> 292 t3ckipps D D D t3ckipps<4:0> 160 t3gpps D D D t3gpps<4:0> 160 t5con tmr5cs<1:0> t5ckps<1:0> t5sosc t5sync D tmr5on 290 t5gcon tmr5ge t5gpol t5gtm t5gspm t5ggo/done t5gval t5gss<1:0> 291 tmr5l tmr5l<7:0> 292 tmr5h tmr5h<7:0> 292 t5ckipps D D D t5ckipps<4:0> 160 t5gpps D D D t5gpps<4:0> 160 t0con0 t0en D t0out t016bit t0outps<3:0> 278 cmxcon0 cxon cxout D cxpol D cxsp cxhys cxsync 188 ccptmrs c4tsel<1:0> c3tsel<1:0> c2tsel<1:0> c1tsel<1:0> 310 ccpxcon ccpxen D ccpxout ccpxfmt ccpxmode<3:0> 307 clcxsely D D lcxdys<5:0> 227 adact D D D D adact<3:0> 244 legend: = unimplemented location, read as 0 . shaded cells are not used by the timer1 module. note 1: pic16(l)f18346 only. 2: unimplemented, read as 1 . downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 294 preliminary ? 2016 microchip technology inc. 27.0 timer 2/4/6 module timer2/4/6 modules are 8-bit timers that incorporate the following features: 8-bit timer and period registers (tmr2/4/6 and pr2/4/6, respectively) readable and writable (both registers) software programmable prescaler (1:1, 1:4, 1:16, and 1:64) software programmable postscaler (1:1 to 1:16) interrupt on tmr2/4/6 match with pr2/4/6 optional use as the shift clock for the msspx module see figure 27-1 for a block diagram of timer2/4/6. figure 27-1: timer2/4 /6 block diagram note 1: in devices with more than one timer module, it is very important to pay close attention to the register names used. a number placed after the module acronym is used to distinguish between separate modules. for example, the t2con and t4con control the same operational aspects of two completely different timer modules. 2: throughout this section, generic references to timer2 module in any of its operating modes may be interpreted as being equally applicable to timerx module. register names, module signals, i/o pins and bit names may use the generic designator x to indicate the use of a numeral to distinguish a particular module, when required. prescaler 1:1, 1:4, 1:16, 1:64 fosc/4 2 t [ ckps<1:0> comparator postscaler 1:1 to 1:16 4 t [ outps<3:0> set bit tmr [ if tmr2 r pr2 t [ _match to peripherals downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 295 pic16(l)f18326/18346 27.1 timer2 operation the clock input to the timer2 modules is the system instruction clock (f osc /4). a 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. these options are selected by the prescaler control bits, t2ckps<1:0> of the t2con register. the value of tmr2 is compared to that of the period register, pr2, on each clock cycle. when the two values match, the comparator generates a match signal as the timer output. this signal also resets the value of tmr2 to 00h on the next cycle and drives the output counter/postscaler (see section 27.2 ?timer2 interrupt? ). the tmr2 and pr2 registers are both directly readable and writable. the tmr2 register is cleared on any device reset, whereas the pr2 register initializes to ffh. both the prescaler and postscaler counters are cleared on the following events: a write to the tmr2 register a write to the t2con register power-on reset (por) brown-out reset (bor) mclr reset watchdog timer (wdt) reset stack overflow reset stack underflow reset reset instruction 27.2 timer2 interrupt timer2 can also generate an optional device interrupt. the timer2 output signal (tmr2-to-pr2 match) provides the input for the 4-bit counter/postscaler. this counter generates the tmr2 match interrupt flag which is latched in tmr2if of the pir1 register. the interrupt is enabled by setting the tmr2 match interrupt enable bit, tmr2ie, of the pie1 register. a range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, t2outps<3:0>, of the t2con register. 27.3 timer2 output the unscaled output of tmr2 is available primarily to the ccp modules, where it is used as a time base for operations in pwm mode. timer2 can be optionally used as the shift clock source for the msspx module operating in spi mode. additional information is provided in section 29.0 ?master synchronous serial port (msspx) module? 27.4 timer2 operation during sleep the timer2 timers cannot be operated while the processor is in sleep mode. the contents of the tmr2 and pr2 registers will remain unchanged while the processor is in sleep mode. note: tmr2 is not cleared when t2con is written. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 296 preliminary ? 2016 microchip technology inc. 27.5 register definitions: timer2/4/6 control register 27-1: txcon (1) : timerx control register u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 txoutps<3:0> tmrxon txckps<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 unimplemented: read as 0 bit 6-3 txoutps<3:0>: timerx output postscaler select bits 1111 = 1:16 postscaler 1110 = 1:15 postscaler 1101 = 1:14 postscaler 1100 = 1:13 postscaler 1011 = 1:12 postscaler 1010 = 1:11 postscaler 1001 = 1:10 postscaler 1000 = 1:9 postscaler 0111 = 1:8 postscaler 0110 = 1:7 postscaler 0101 = 1:6 postscaler 0100 = 1:5 postscaler 0011 = 1:4 postscaler 0010 = 1:3 postscaler 0001 = 1:2 postscaler 0000 = 1:1 postscaler bit 2 tmrxon: timer2 on bit 1 =timerx is on 0 =timerx is off bit 1-0 txckps<1:0>: timerx clock prescale select bits 11 = prescaler is 64 10 = prescaler is 16 01 =prescaler is 4 00 =prescaler is 1 note 1: x refers to either 2, 4 or 6 for the respective timer2/4/6 registers. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 297 pic16(l)f18326/18346 register 27-3: prx: timerx period register (1) register 27-2: tmrx (1) : timerx count register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tmrx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 tmrx<7:0>: tmrx counter bits 7..0 note 1: x refers to either 2, 4 or 6 for the respective timer2/4/6 registers. r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 prx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 prx<7:0>: tmrx counter bits 7..0 when tmrx = prx, the next clock will reset the counter; counter period is (prx+1) note 1: x refers to either 2, 4 or 6 for the respective timer2/4/6 registers. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 298 preliminary ? 2016 microchip technology inc. table 27-1: summary of registers associated with timer2/4/6 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie D D D D D intedg 98 pir1 tmr1gif adif rcif txif ssp1if bcl1if tmr2if tmr1if 105 pie1 tmr1gie adie rcie txie ssp1ie bcl1ie tmr2ie tmr1ie 100 pir2 tmr6if c2if c1if nvmif ssp2if bcl2if tmr4if nco1if 106 pie2 tmr6ie c2ie c1ie nvmie ssp2ie bcl2ie tmr4ie nco1ie 101 t2con D t2outps<3:0> tmr2on t2ckps<1:0> 296 tmr2 tmr2<7:0> 297 pr2 pr2<7:0> 297 t4con D t4outps<3:0> tmr4on t4ckps<1:0> 296 tmr4 tmr4<7:0> 297 pr4 pr4<7:0> 297 t6con D t6outps<3:0> tmr6on t6ckps<1:0> 296 tmr6 tmr6<7:0> 297 pr6 pr6<7:0> 297 adact D D D D adact<3:0> 244 pwmtmrs D D D D p6tsel<1:0> p5tsel<1:0> 195 clcxsely D D lcxdys<5:0> 227 legend: = unimplemented location, read as 0 . shaded cells are not used for timer2/4/6 module. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 299 pic16(l)f18326/18346 28.0 capture/compare/pwm modules the capture/compare/pwm module is a peripheral that allows the user to time and control different events and to generate pulse-width modulation (pwm) signals. in capture mode, the peripheral allows the timing of the duration of an event. the compare mode allows the user to trigger an external event when a predetermined amount of time has expired. the pwm mode can generate pulse-width modulated signals of varying frequency and duty cycle. this family of devices contains four standard capture/compare/pwm modules (ccp1, ccp2, ccp3 and ccp4). the capture and compare functions are identical for all ccp modules. 28.1 ccp/pwm clock selection the pic16(l)f18326/18346 devices allow each individual ccp and pwm module to select the timer source that controls the module. each module has an independent selection. as there are up to three 8-bit timers with auto-reload (timer2, timer4, and timer6), pwm mode on the ccp and pwm modules can use any of these timers. the ccptmrs register is used to select which timer is used. 28.2 capture mode the capture mode function described in this section is available and identical for all ccp modules. capture mode makes use of either the 16-bit timer0 or timer1 resource. when an event occurs on the capture source, the 16-bit ccprxh:ccprxl register pair captures and stores the 16-bit value of the tmr0h:tmr0l or tmr1h:tmr1l register pair, respectively. an event is defined as one of the following and is configured by the ccpxmode<3:0> bits of the ccpxcon register: every falling edge every rising edge every 4th rising edge every 16th rising edge when a capture is made, the interrupt request flag bit ccpxif of the pir4 register is set. the interrupt flag must be cleared in software. if another capture occurs before the value in the ccprxh, ccprxl register pair is read, the old captured value is overwritten by the new captured value. figure 28-1 shows a simplified diagram of the capture operation. 28.2.1 capture sources in capture mode, the ccpx pin should be configured as an input by setting the associated tris control bit. the capture source is selected by configuring the ccpxcts<3:0> bits of the ccpxcap register. the following sources can be selected: ccpxpps input c1_output c2_output nco_output ioc_interrupt lc1_output lc2_output lc3_output lc4_output note 1: in devices with more than one ccp module, it is very important to pay close attention to the register names used. a number placed after the module acronym is used to distinguish between separate modules. for example, the ccp1con and ccp2con control the same operational aspects of two completely different ccp modules. 2: throughout this section, generic references to a ccp module in any of its operating modes may be interpreted as being equally applicable to ccpx module. register names, module signals, i/o pins, and bit names may use the generic designator x to indicate the use of a numeral to distinguish a particular module, when required. note: when the ccp is configured in compare mode using the toggle output on match setting (ccpxmode<3:0> bits = 0010 ) and the reference timer is set for an input clock prescale other than 1:1, the output of the ccp will toggle multiple times until finally settling a 0 logic level. to avoid this, the timer input clock prescale select bits must be set to a 1:1 ratio (txckps = 00 ). note: if the ccpx pin is configured as an output, a write to the port can cause a capture condition. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 300 preliminary ? 2016 microchip technology inc. figure 28-1: capture mode operation block diagram rev. 10-000158c 5/2/2014 ccprxh ccprxl tmr1h tmr1l 1616 prescaler 1,4,16 ccpx tris control set ccpxif ccpx mode <3:0> and edge detect c1out_sync c2out_sync ioc_interrupt rxypps ccpxcts<3:0> nco lc1_output lc2_output reserved 0000 00000 000 000 00 00 0 000 00- lc3_output lc4_output downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 301 pic16(l)f18326/18346 28.2.2 timer1/3/5 mode resource timer1/3/5 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in a synchronous counter mode, the capture operation may not work. see section 26.0 ?timer1/3/5 module with gate control? for more information on configuring timer1/3/5. 28.2.3 software interrupt mode when the capture mode is changed, a false capture interrupt may be generated. the user should keep the ccpxie interrupt enable bit of the pie4 register clear to avoid false interrupts. additionally, the user should clear the ccpxif interrupt flag bit of the pir4 register following any change in operating mode. 28.2.4 ccp prescaler there are four prescaler settings specified by the ccpxmode<3:0> bits of the ccpxcon register. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. to avoid this unexpected operation, turn the module off by clearing the ccpxcon register before changing the prescaler. example 28-1 demonstrates the code to perform this function. example 28-1: changing between capture prescalers 28.2.5 capture during sleep capture mode depends upon the timer1/3/5 module for proper operation. there are two options for driving the timer1/3/5 module in capture mode. it can be driven by the instruction clock (f osc /4), or by an external clock source. when timer1/3/5 is clocked by f osc /4, timer1/3/5 will not increment during sleep. when the device wakes from sleep, timer1/3/5 will continue from its previous state. capture mode will operate during sleep when timer1/3/5 is clocked by an external clock source. note: clocking timer1/3/5 from the system clock (f osc ) should not be used in capture mode. in order for capture mode to recognize the trigger event on the ccpx pin, timer1/3/5 must be clocked from the instruction clock (f osc /4) or from an external clock source. banksel ccpxcon ;set bank bits to point ;to ccpxcon clrf ccpxcon ;turn ccp module off movlw new_capt_ps ;load the w reg with ;the new prescaler ;move value and ccp on movwf ccpxcon ;load ccpxcon with this ;value downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 302 preliminary ? 2016 microchip technology inc. 28.3 compare mode the compare mode function described in this section is available and identical for all ccp modules. compare mode makes use of the 16-bit timer1/3/5 resource. the 16-bit value of the ccprxh:ccprxl register pair is constantly compared against the 16-bit value of the tmr1/3/5h:tmr1/3/5l register pair. when a match occurs, one of the following events can occur: toggle the ccpx output set the ccpx output clear the ccpx output generate an auto-conversion trigger generate a software interrupt the action on the pin is based on the value of the ccpxmode<3:0> control bits of the ccpxcon regis- ter. at the same time, the interrupt flag ccpxif bit is set, and an adc conversion can be triggered, if selected. all compare modes can generate an interrupt and trigger an adc conversion. figure 28-2 shows a simplified diagram of the compare operation. figure 28-2: compare mode operation block diagram 28.3.1 ccpx pin configuration the user must configure the ccpx pin as an output by clearing the associated tris bit and defining the appropriate output pin through the rxypps registers. see section 12.0 ?peripheral pin select (pps) module? for more details. the ccp output can also be used as an input for other peripherals. 28.3.2 timer1/3/5 mode resource in compare mode, timer1/3/5 must be running in either timer mode or synchronized counter mode. the compare operation may not work in asynchronous counter mode. see section 26.0 ?timer1/3/5 module with gate control? for more information on configuring timer1/3/5. 28.3.3 auto-conversion trigger all ccpx modes set the ccp interrupt flag (ccpxif). when this flag is set as a match occurs, an auto-conversion trigger can occur if the ccp module is selected as the conversion trigger source. refer to section 21.2.5 ?auto-conversion trigger? for more information. 28.3.4 compare during sleep since f osc is shut down during sleep mode, the compare mode will not function properly during sleep, unless the timer is running. the device will wake on interrupt (if enabled). note: clearing the ccpxcon register will force the ccpx compare output latch to the default low level. this is not the port i/o data latch. ccprxh ccprxl tmr1h tmr1l comparator qs r output logic auto-conversion trigger set ccpxif interrupt flag (pirx) match tris ccpxmode<3:0> mode select output enable pin ccpx 4 note: clocking timer1/3/5 from the system clock (f osc ) should not be used in compare mode. in order for compare mode to recognize the trigger event on the ccpx pin, timer1/3/5 must be clocked from the instruction clock (f osc /4) or from an external clock source. note: removing the match condition by changing the contents of the ccprxh and ccprxl register pair, between the clock edge that generates the auto-conversion trigger and the clock edge that generates the timer reset, will preclude the reset from occurring. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 303 pic16(l)f18326/18346 28.4 pwm overview pulse-width modulation (pwm) is a scheme that provides power to a load by switching quickly between fully on and fully off states. the pwm signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. the high portion, also known as the pulse width, can vary in time and is defined in steps. a larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. lowering the number of steps applied, which shortens the pulse width, supplies less power. the pwm period is defined as the duration of one complete cycle or the total amount of on and off time combined. pwm resolution defines the maximum number of steps that can be present in a single pwm period. a higher resolution allows for more precise control of the pulse-width time and in turn the power that is applied to the load. the term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. a lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. figure 28-3 shows a typical waveform of the pwm signal. 28.4.1 standard pwm operation the standard pwm function described in this section is available and identical for all ccp modules. the standard pwm mode generates a pulse-width modulation (pwm) signal on the ccpx pin with up to 10 bits of resolution. the period, duty cycle, and resolution are controlled by the following registers: pr2/4/6 registers t2/4/6con registers ccprxl registers ccpxcon registers figure 28-4 shows a simplified block diagram of pwm operation. figure 28-3: ccp pwm output signal note: the corresponding tris bit must be cleared to enable the pwm output on the ccpx pin. period pulse width tmr2/4/6 = 0 tmr2/4/6 = ccprxh:ccprxl tmr2 = pr2 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 304 preliminary ? 2016 microchip technology inc. figure 28-4: simplified pw m block diagram rev. 10-000157b 2/27/2014 ccprxh duty cycle registers 10-bit latch (2) (not accessible by user) comparator comparator pr2 (1) tmr2 tmr2 module ccpx ccpx_out to peripherals r tris control r s q ccprxl set ccpif ccpx_pset ers logic notes: 1. 8-bit timer is concatenated with two bits generated by fosc or two bits of the internal prescaler to create 10-bit time-base. 2. the alignment of the 10 bits from the ccpr register is determined by the ccpxfmt bit. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 305 pic16(l)f18326/18346 28.4.2 setup for pwm operation the following steps should be taken when configuring the ccp module for standard pwm operation: 1. use the desired output pin rxypps control to select ccpx as the source and disable the ccpx pin output driver by setting the associated tris bit. 2. load the pr2 register with the pwm period value. 3. configure the ccp module for the pwm mode by loading the ccpxcon register with the appropriate values. 4. load the ccprxl register and the ccprxh register bits, with the pwm duty cycle value and configure the ccpxfmt bit of the ccpxcon register to set the proper register alignment. 5. configure and start timer2, 4 or 6. clear the tmr2/4/6if interrupt flag bits of the pir4 register. see note below. configure the t2/4/6ckps bits of the t2/4/6con register with the timer prescale value. enable the timer by setting the tmr2/4/6on bit of the t2/4/6con register. 6. enable pwm output pin: wait until the timer overflows and the tmr2/4/6if bits of the pir4 register is set. see note below. enable the ccpx pin output driver by clearing the associated tris bit. 28.4.3 timer2/4/6 timer resource the pwm standard mode makes use of the 8-bit timer2/4/6 timer resources to specify the pwm period. 28.4.4 pwm period the pwm period is specified by the prx register of timer2/4/6. the pwm period can be calculated using the formula of equation 28-1 . equation 28-1: pwm period when tmr2/4/6 is equal to pr2/4/6, the following three events occur on the next increment cycle: tmr2/4/6 is cleared the ccpx pin is set. (exception: if the pwm duty cycle = 0%, the pin will not be set.) the pwm duty cycle is transferred from the ccprxl/h register pair into a 10-bit buffer. 28.4.5 pwm duty cycle the pwm duty cycle is specified by writing a 10-bit value to the ccprxh:ccprxl register pair. the alignment of the 10-bit value is determined by the ccprxfmt bit of the ccpxcon register (see figure 28-5 ). the ccprxh:ccprxl register pair can be written to at any time; however, the duty cycle value is not latched into the 10-bit buffer until after a match between pr2/4/6 and tmr2/4/6. equation 28-2 is used to calculate the pwm pulse width. equation 28-3 is used to calculate the pwm duty cycle ratio. figure 28-5: pwm 10-bit alignment block diagram note: in order to send a complete duty cycle and period on the first pwm output, the above steps must be included in the setup sequence. if it is not critical to start with a complete pwm signal on the first output, then step 6 may be ignored. note: the timer postscaler (see section 27.1 ?timer2 operation? ) is not used in the determination of the pwm frequency. pwm period pr 2 x ?? 1+ ?? 4t osc ? ? ? = (tmr2/4/6 prescale value) note: t osc = 1/f osc rev. 10 -000 160a 12 /9/201 3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ccprxh ccprxl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ccprxh ccprxl fmt = 0 fmt = 1 7 6 5 4 3 2 1 0 9 8 10-bit duty cycle downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 306 preliminary ? 2016 microchip technology inc. equation 28-2: pulse width equation 28-3: duty cycle ratio the ccprxh:ccprxl register pair and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. the 8-bit timer tmr2/4/6 register is concatenated with either the 2-bit internal system clock (f osc ), or two bits of the prescaler, to create the 10-bit time base. the system clock is used if the timer2/4/6 prescaler is set to 1:1. when the 10-bit time base matches the ccprxh:ccprxl register pair, then the ccpx pin is cleared (see figure 28-4 ). 28.4.6 pwm resolution the resolution determines the number of available duty cycles for a given period. for example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. the maximum pwm resolution is ten bits when prx is 255. the resolution is a function of the prx register value as shown by equation 28-4 . equation 28-4: pwm resolution 28.4.7 operation in sleep mode in sleep mode, the tmr2/4/6 register will not incre- ment and the state of the module will not change. if the ccpx pin is driving a value, it will continue to drive that value. when the device wakes up, tmr2/4/6 will continue from its previous state. 28.4.8 changes in system clock frequency the pwm frequency is derived from the system clock frequency. any changes in the system clock frequency will result in changes to the pwm frequency. see section 6.0 ?oscillator module (with fail-safe clock monitor)? for additional details. 28.4.9 effects of reset any reset will force all ports to input mode and the ccp registers to their reset states. pulse width ccprxh:ccprxl register pair ?? ? = t osc ? (tmr2 prescale value) duty cycle ratio ccprxh:ccprxl register pair ?? 4pr 2 1+ ?? --------------------------------------------------------------------------------- - = note: if the pulse-width value is greater than the period the assigned pwm pin(s) will remain unchanged. resolution 4prx 1 + ?? ?? log 2 ?? log ----------------------------------------- - bits = table 28-1: example pwm frequencies and resolutions (f osc = 20 mhz) pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale 16 4 1 1 1 1 prx value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 table 28-2: example pwm frequencies and resolutions (f osc = 8 mhz) pwm frequency 1.22 khz 4.90 khz 19.61 khz 76.92 khz 153.85 khz 200.0 khz timer prescale 16 4 1 1 1 1 prx value 0x65 0x65 0x65 0x19 0x0c 0x09 maximum resolution (bits) 8 8 8 6 5 5 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 307 pic16(l)f18326/18346 28.5 register definitions: ccp control register 28-1: ccpxcon: ccpx control register r/w-0/0 u-0 r-x/x r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ccpxen ccpxout ccpxfmt ccpxmode<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other reset 1 = bit is set 0 = bit is cleared bit 7 ccpxen: ccp module enable bit 1 = ccp is enabled 0 = ccp is disabled bit 6 unimplemented: read as 0 bit 5 ccpxout: ccpx output data (read-only) bit bit 4 ccpxfmt: ccpw (pulse width) alignment bit ccp x m ode = capture mode unused ccpxmode = compare mode unused ccpxmode = pwm mode 1 = left-aligned format 0 = right-aligned format bit 3-0 ccpxmode<3:0>: ccpx mode select bits (1) 1111 = pwm mode 1110 = reserved 1101 = reserved 1100 = reserved 1011 = compare mode: output will pulse 0 - 1 - 0 ; clears tmr1/3/5 1010 = compare mode: output will pulse 0 - 1 - 0 1001 = compare mode: clear output on compare match 1000 = compare mode: set output on compare match 0111 = capture mode: every 16th rising edge of ccpx input 0110 = capture mode: every 4th rising edge of ccpx input 0101 = capture mode: every rising edge of ccpx input 0100 = capture mode: every falling edge of ccpx input 0011 = capture mode: every edge of ccpx input 0010 = compare mode: toggle output on match 0001 = compare mode: toggle output on match; clear tmr1/3/5 0000 = capture/compare/pwm off (resets ccpx module) note 1: all modes will set the ccpxif bit and will trigger an adc conversion if ccpx is selected as the adc trigger source. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 308 preliminary ? 2016 microchip technology inc. register 28-2: ccpxcap: capture input selection register u-0 u-0 u-0 u-0 r/w-0/x r/w-0/x r/w-0/x r/w-0/x ccpxcts<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other reset 1 = bit is set 0 = bit is cleared bit 7-4 unimplemented: read as 0 bit 3-0 ccpxcts<3:0>: ccpx capture mode data select bits ccap<3:0> ccp1cap capture input ccp2cap capture input ccp3cap capture input ccp4cap capture input 0000 ccp1pps ccp2pps ccp3pps ccp4pps 0001 c1out 0010 c2out 0011 nco1 0100 ioc_interrupt 0101 lc1_output 0110 lc2_output 0111 lc3_output 1000 lc4_output 1001 1111 reserved downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 309 pic16(l)f18326/18346 register 28-3: ccprxl register: ccpx register low byte r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x ccprxl<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other reset 1 = bit is set 0 = bit is cleared bit 7-0 ccp x m ode = capture mode ccprxl<7:0>: captured value of tmr1/3/5l ccpxmode = compare mode ccprxl<7:0>: ls byte compared to tmr1/3/5l ccpxmode = pwm modes when ccpxfmt = 0 ccprxl<7:0>: ccpw<7:0> C pulse-width least significant eight bits ccpxmode = pwm modes when ccpxfmt = 1 ccprxl<7:6>: ccpw<1:0> C pulse-width least significant two bits ccprxl<5:0>: not used. register 28-4: ccprxh register: ccpx register high byte r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x ccprxh<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other reset 1 = bit is set 0 = bit is cleared bit 7-0 ccpxmode = capture mode ccprxh<7:0>: captured value of tmr1/3/5h ccpxmode = compare mode ccprxh<7:0>: ms byte compared to tmr1/3/5h ccpxmode = pwm modes when ccpxfmt = 0 ccprxh<7:2>: not used ccprxh<1:0>: ccpw<9:8> C pulse-width most significant two bits ccpxmode = pwm modes when ccpxfmt = 1 ccprxh<7:0>: ccpw<9:2> C pulse-width most significant eight bits downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 310 preliminary ? 2016 microchip technology inc. register 28-5: ccptmrs: ccp timers control register r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 c4tsel<1:0> c3tsel<1:0> c2tsel<1:0> c1tsel<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other reset 1 = bit is set 0 = bit is cleared bit 7-6 c4tsel<1:0>: ccp4 capture, compare and pwm mode timer selection bits selection as show in tab le 2 8- 4 . bit 5-4 c3tsel<1:0>: ccp3 capture, compare and pwm mode timer selection bits selection as show in tab le 2 8- 4 . bit 3-2 c2tsel<1:0>: ccp2 capture, compare and pwm mode timer selection bits selection as show in tab le 2 8- 4 . bit 1-0 c1tsel<1:0>: ccp1 capture, compare and pwm mode timer selection bits selection as show in tab le 2 8- 4 . table 28-3: timer selections cxtsel<1:0> operating mode based on ccpxmode<3:0> capture compare pwm 00 tmr0 tmr2 01 tmr1 10 tmr3 tmr4 11 tmr5 tmr6 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 311 pic16(l)f18326/18346 table 28-4: summary of registers associated with ccpx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page trisa D D trisa5 trisa4 D (2) trisa2 trisa1 trisa0 141 ansela D D ansa5 ansa4 D ansa2 ansa1 ansa0 142 trisb (1) trisb7 trisb6 trisb5 trisb4 D D D D 147 anselb (1) ansb7 ansb6 ansb5 ansb4 D D D D 148 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 anselc ansc7 (1) ansc6 (1) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 intcon gie peie D D D D D intedg 98 pir4 cwg2if cwg1if tmr5gif tmr5if ccp4if ccp3if ccp2if ccp1if 108 pie4 cwg2ie cwgie tmr5gie tmr5ie ccp4ie ccp3ie ccp2ie ccp1ie 103 ccpxcon ccpxen D ccpxout ccpxfmt ccpxmode<3:0> 307 ccpxcap D D D D ccpxcts<3:0> 308 ccprxl ccprx<7:0> 309 ccprxh ccprx<15:8> 309 ccptmrs c4tsel<1:0> c3tsel<1:0> c2tsel<1:0> c1tsel<1:0> 310 ccp1pps D D D ccp1pps<4:0> 160 ccp2pps D D D ccp2pps<4:0> 160 ccp3pps D D D ccp3pps<4:0> 160 ccp4pps D D D ccp4pps<4:0> 160 rxypps D D D rxypps<4:0> 161 adact D D D D adact<3:0> 244 clcxsely D D lcxdys<5:0> 227 cwgxdat D D D D dat<3:0> 213 mdsrc D D D D mdms<3:0> 270 mdcarh D mdchpol mdchsync D mdch<3:0> 271 mdcarl D mdclpol mdclsync D mdcl<3:0> 272 legend: = unimplemented location, read as 0 . shaded cells are not used by the ccp module. note 1: pic16(l)f18346 only. 2: unimplemented, read as 1 . downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 312 preliminary ? 2016 microchip technology inc. 29.0 master synchronous serial port (msspx) module 29.1 msspx module overview the master synchronous serial port (msspx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the msspx module can operate in one of two modes: serial peripheral interface (spi) inter-integrated circuit (i 2 c) the spi interface supports the following modes and features: master mode slave mode clock parity slave select synchronization (slave mode only) daisy-chain connection of slave devices figure 29-1 is a block diagram of the spi interface module. figure 29-1: mssp block diagram (spi mode) note 1: in devices with more than one mssp module, it is very important to pay close attention to the register names used. a number placed after the module acronym is used to distinguish between separate modules. for example, the ssp1stat and ssp2stat control the same operational aspects of two completely different mssp modules. 2: throughout this section, generic references to the mssp1 module in any of its operating modes may be interpreted as being equally applicable to msspx module. register names, module signals, i/o pins, and bit names may use the generic designator x to indicate the use of a numeral to distinguish a particular module, when required. ( ) read write data bus sspxsr reg sspm<3:0> bit 0 shift clock ss control enable edge select clock select t2_match 2 edge select 2 (ckp, cke) 4 tris bit sdo sspxbuf reg sdi ss sck t osc prescaler 4, 16, 64 baud rate generator (sspxadd) downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 313 pic16(l)f18326/18346 the i 2 c interface supports the following modes and features: master mode slave mode byte nacking (slave mode) limited multi-master support 7-bit and 10-bit addressing start and stop interrupts interrupt masking clock stretching bus collision detection general call address matching address masking address hold and data hold modes selectable sda hold times figure 29-2 is a block diagram of the i 2 c interface module in master mode. figure 29-3 is a diagram of the i 2 c interface module in slave mode. figure 29-2: mssp block diagram (i 2 c master mode) read write sspxsr start bit, stop bit, start bit detect, sspxbuf internal data bus set/reset: s, p, sspxstat, wcol, sspov shift clock msb lsb sda acknowledge generate (sspxcon2) stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable (rcen) clock cntl clock arbitrate/bcol detect (hold off clock source) [sspm<3:0>] baud rate reset sen, pen (sspxcon2) generator (sspxadd) address match detect set sspxif, bclxif downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 314 preliminary ? 2016 microchip technology inc. figure 29-3: mssp block diagram (i 2 c slave mode) read write sspxsr reg match detect sspxadd reg start and stop bit detect sspxbuf reg internal data bus addr match set, reset s, p bits (sspxstat reg) scl sda shift clock msb lsb sspxmsk reg downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 315 pic16(l)f18326/18346 29.2 spi mode overview the serial peripheral interface (spi) bus is a synchronous serial data communication bus that operates in full-duplex mode. devices communicate in a master/slave environment where the master device initiates the communication. a slave device is controlled through a chip select known as slave select. the spi bus specifies four signal connections: serial clock (sck) serial data out (sdo) serial data in (sdi) slave select (ss ) figure 29-1 shows the block diagram of the msspx module when operating in spi mode. the spi bus operates with a single master device and one or more slave devices. when multiple slave devices are used, an independent slave select connection is required from the master device to each slave device. figure 29-4 shows a typical connection between a master device and multiple slave devices. the master selects only one slave at a time. most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. with either the master or the slave device, data is always shifted out one bit at a time, with the most significant bit (msb) shifted out first. at the same time, a new least significant bit (lsb) is shifted into the same register. figure 29-5 shows a typical connection between two processors configured as master and slave devices. data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. the master device transmits information out on its sdo output pin which is connected to, and received by, the slaves sdi input pin. the slave device transmits infor- mation out on its sdo output pin, which is connected to, and received by, the masters sdi input pin. to begin communication, the master device first sends out the clock signal. both the master and the slave devices should be configured for the same clock polar- ity. the master device starts a transmission by sending out the msb from its shift register. the slave device reads this bit from that same line and saves it into the lsb position of its shift register. during each spi clock cycle, a full-duplex data transmission occurs. this means that while the master device is sending out the msb from its shift register (on its sdo pin) and the slave device is reading this bit and saving it as the lsb of its shift register, that the slave device is also sending out the msb from its shift register (on its sdo pin) and the master device is reading this bit and saving it as the lsb of its shift register. after eight bits have been shifted out, the master and slave have exchanged register values. if there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. whether the data is meaningful or not (dummy data), depends on the application software. this leads to three scenarios for data transmission: master sends useful data and slave sends dummy data. master sends useful data and slave sends useful data. master sends dummy data and slave sends useful data. transmissions may involve any number of clock cycles. when there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. every slave device connected to the bus that has not been selected through its slave select line must disre- gard the clock and transmission signals and must not transmit out any data of its own. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 316 preliminary ? 2016 microchip technology inc. figure 29-4: spi master and multiple slave connection 29.2.1 spi mode registers the msspx module has five registers for spi mode operation. these are: msspx status register (sspxstat) msspx control register 1 (sspxcon1) msspx control register 3 (sspxcon3) msspx data buffer register (sspxbuf) msspx address register (sspxadd) msspx shift register (sspxsr) (not directly accessible) sspxcon1 and sspstat are the control and status registers in spi mode operation. the sspxcon1 register is readable and writable. the lower six bits of the sspxstat are read-only. the upper two bits of the sspxstat are read/write. in one spi master mode, sspxadd can be loaded with a value used in the baud rate generator. more information on the baud rate generator is available in section 29.7 ?baud rate generator? . sspxsr is the shift register used for shifting data in and out. sspxbuf provides indirect access to the sspxsr register. sspxbuf is the buffer register to which data bytes are written, and from which data bytes are read. in receive operations, sspxsr and sspxbuf together create a buffered receiver. when sspxsr receives a complete byte, it is transferred to sspxbuf and the sspxif interrupt is set. during transmission, the sspxbuf is not buffered. a write to sspxbuf will write to both sspxbuf and sspxsr. 29.2.2 spi mode operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspxcon1<5:0> and sspxstat<7:6>). these control bits allow the following to be specified: master mode (sck is the clock output) slave mode (sck is the clock input) clock polarity (idle state of sck) data input sample phase (middle or end of data output time) clock edge (output data on rising/falling edge of sck) clock rate (master mode only) slave select mode (slave mode only) to enable the serial port, ssp enable bit, sspen of the sspxcon1 register, must be set. to reset or reconfig- ure spi mode, clear the sspen bit, re-initialize the sspxcony registers and then set the sspen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed as follows: sdi must have corresponding tris bit set sdo must have corresponding tris bit cleared sck (master mode) must have corresponding tris bit cleared sck (slave mode) must have corresponding tris bit set ss must have corresponding tris bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. spi master sck sdo sdi general i/o general i/o general i/o scksdi sdo ss spi slave #1 scksdi sdo ss spi slave #2 scksdi sdo ss spi slave #3 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 317 pic16(l)f18326/18346 the msspx consists of a transmit/receive shift register (sspxsr) and a buffer register (sspxbuf). the sspxsr shifts the data in and out of the device, msb first. the sspxbuf holds the data that was written to the sspxsr until the received data is ready. once the eight bits of data have been received, that byte is moved to the sspxbuf register. then, the buffer full detect bit, bf of the sspxstat register, and the interrupt flag bit, sspxif, are set. this double-buffering of the received data (sspxbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspxbuf register during transmission/reception of data will be ignored and the write collision detect bit, wcol, of the sspxcon1 register, will be set. user software must clear the wcol bit to allow the following write(s) to the sspxbuf register to complete successfully. when the application software is expecting to receive valid data, the sspxbuf should be read before the next byte of data to transfer is written to the sspxbuf. the buffer full bit, bf of the sspxstat register, indicates when sspxbuf has been loaded with the received data (transmission is complete). when the sspxbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has completed. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. the sspxsr is not directly readable or writable and can only be accessed by addressing the sspxbuf register. additionally, the sspxstat register indicates the various status conditions. figure 29-5: spi mast er/slave connection serial input buffer (sspxbuf) shift register (sspxsr) msb lsb sdo sdi processor 1 sck spi master sspm<3:0> = 00xx serial input buffer (sspxbuf) shift register (sspxsr) lsb msb sdi sdo processor 2 sck spi slave sspm<3:0> = 010x serial clock ss slave select general i/o (optional) = 1010 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 318 preliminary ? 2016 microchip technology inc. 29.2.3 spi master mode the master can initiate the data transfer at any time because it controls the sck line. the master determines when the slave (processor 2, figure 29-5 ) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspxbuf register is written to. if the spi is only going to receive, the sdo output could be disabled (programmed as an input). the sspxsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspxbuf register as if a normal received byte (interrupts and status bits appropriately set). the clock polarity is selected by appropriately programming the ckp bit of the sspxcon1 register and the cke bit of the sspxstat register. this then, would give waveforms for spi communication as shown in figure 29-6 , figure 29-8 , figure 29-9 and figure 29-10 , where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: f osc /4 (or t cy ) f osc /16 (or 4 * t cy ) f osc /64 (or 16 * t cy ) timer2 output/2 f osc /(4 * (sppxadd + 1)) figure 29-6 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspxbuf is loaded with the received data is shown. figure 29-6: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdi sspxif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sppxbuf sspxsr to sspxbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) bit 0 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 319 pic16(l)f18326/18346 29.2.4 spi slave mode in slave mode, the data is transmitted and received as external clock pulses appear on sck. when the last bit is latched, the sspxif interrupt flag bit is set. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sck pin. the idle state is determined by the ckp bit of the sspxcon1 register. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. the shift register is clocked from the sck pin input and when a byte is received, the device will generate an interrupt. if enabled, the device will wake-up from sleep. 29.2.4.1 daisy-chain configuration the spi bus can sometimes be connected in a daisy-chain configuration. the first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. the final slave output is connected to the master input. each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. the whole chain acts as one large communication shift register. the daisy-chain feature only requires a single slave select line from the master device. figure 29-7 shows the block diagram of a typical daisy-chain connection when operating in spi mode. in a daisy-chain configuration, only the most recent byte on the bus is required by the slave. setting the boen bit of the sspxcon3 register will enable writes to the sspxbuf register, even if the previous byte has not been read. this allows the software to ignore data that may not apply to it. 29.2.5 slave select synchronization the slave select can also be used to synchronize communication. the slave select line is held high until the master device is ready to communicate. when the slave select line is pulled low, the slave knows that a new transmission is starting. if the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the slave select line returns to a high state. the slave is then ready to receive a new transmission when the slave select line is pulled low again. if the slave select line is not used, there is a risk that the slave will eventually become out of sync with the master. if the slave misses a bit, it will always be one bit off in future transmissions. use of the slave select line allows the slave and master to align themselves at the beginning of each transmission. the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspxcon1<3:0> = 0100 ). when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the applica- tion. when the spi module resets, the bit counter is forced to 0 . this can be done by either forcing the ss pin to a high level or clearing the sspen bit. note 1: when the spi is in slave mode with ss pin control enabled (sspxcon1<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: when the spi is used in slave mode with cke set; the user must enable ss pin control. 3: while operated in spi slave mode the smp bit of the sspxstat register must remain clear. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 320 preliminary ? 2016 microchip technology inc. figure 29-7: spi daisy-chain connection figure 29-8: slave select synchronous waveform spi master sck sdo sdi general i/o scksdi sdo ss spi slave #1 scksdi sdo ss spi slave #2 scksdi sdo ss spi slave #3 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspxif interrupt cke = 0 ) cke = 0 ) write to sspxbuf sspxsr to sspxbuf ss flag bit 0 bit 7 bit 0 bit 6 sspxbuf to sspxsr shift register sspxsr and bit count are reset downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 321 pic16(l)f18326/18346 figure 29-9: spi mode wavefo rm (slave mode with cke = 0 ) figure 29-10: spi mode waveform (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspxif interrupt cke = 0 ) cke = 0 ) write to sspxbuf sspxsr to sspxbuf ss flag optional bit 0 detection active write collision valid sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspxif interrupt cke = 1 ) cke = 1 ) write to sspxbuf sspxsr to sspxbuf ss flag not optional write collision detection active valid downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 322 preliminary ? 2016 microchip technology inc. 29.2.6 spi operation in sleep mode in spi master mode, module clocks may be operating at a different speed than when in full-power mode; in the case of the sleep mode, all clocks are halted. special care must be taken by the user when the mssp clock is much faster than the system clock. in slave mode, when mssp interrupts are enabled, after the master completes sending data, an mssp interrupt will wake the controller from sleep. if an exit from sleep mode is not desired, mssp interrupts should be disabled. in spi master mode, when the sleep mode is selected, all module clocks are halted and the transmis- sion/reception will remain in that state until the device wakes. after the device returns to run mode, the module will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all eight bits have been received, the mssp interrupt flag bit will be set and if enabled, will wake the device. 29.3 i 2 c mode overview the inter-integrated circuit (i 2 c) bus is a multi-master serial data communication bus. devices communicate in a master/slave environment where the master devices initiate the communication. a slave device is controlled through addressing. the i 2 c bus specifies two signal connections: serial clock (scl) serial data (sda) figure 29-11 shows the block diagram of the msspx module when operating in i 2 c mode. both the scl and sda connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. figure 29-11 shows a typical connection between two processors configured as master and slave devices. the i 2 c bus can operate with one or more master devices and one or more slave devices. there are four potential modes of operation for a given device: master transmit mode (master is transmitting data to a slave) master receive mode (master is receiving data from a slave) slave transmit mode (slave is transmitting data to a master) slave receive mode (slave is receiving data from the master) to begin communication, a master device starts out in master transmit mode. the master device sends out a start bit followed by the address byte of the slave it intends to communicate with. this is followed by a single read/write bit, which determines whether the master intends to transmit to or receive data from the slave device. if the requested slave exists on the bus, it will respond with an acknowledge bit, otherwise known as an ack . the master then continues in either transmit mode or receive mode and the slave continues in the comple- ment, either in receive mode or transmit mode, respectively. a start bit is indicated by a high-to-low transition of the sda line while the scl line is held high. address and data bytes are sent out, most significant bit (msb) first. the read/write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. figure 29-11: i 2 c master/ slave connection the acknowledge bit (ack ) is an active-low signal, which holds the sda line low to indicate to the transmit- ter that the slave device has received the transmitted data and is ready to receive more. the transition of a data bit is always performed while the scl line is held low. transitions that occur while the scl line is held high are used to indicate start and stop bits. if the master intends to write to the slave, then it repeat- edly sends out a byte of data, with the slave responding after each byte with an ack bit. in this example, the master device is in master transmit mode and the slave is in slave receive mode. if the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ack bit. in this exam- ple, the master device is in master receive mode and the slave is slave transmit mode. master scl sda sclsda slave v dd v dd downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 323 pic16(l)f18326/18346 on the last byte of data communicated, the master device may end the transmission by sending a stop bit. if the master device is in receive mode, it sends the stop bit in place of the last ack bit. a stop bit is indicated by a low-to-high transition of the sda line while the scl line is held high. in some cases, the master may want to maintain control of the bus and re-initiate another transmission. if so, the master device may send another start bit in place of the stop bit or last ack bit when it is in receive mode. the i 2 c bus specifies three message protocols; single message where a master writes data to a slave. single message where a master reads data from a slave. combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. when one device is transmitting a logical one, or letting the line float, and a second device is transmitting a log- ical zero, or holding the line low, the first device can detect that the line is not a logical one. this detection, when used on the scl line, is called clock stretching. clock stretching gives slave devices a mechanism to control the flow of data. when this detection is used on the sda line, it is called arbitration. arbitration ensures that there is only one master device communicating at any single time. 29.3.1 clock stretching when a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. an addressed slave device may hold the scl clock line low after receiving or send- ing a bit, indicating that it is not yet ready to continue. the master that is communicating with the slave will attempt to raise the scl line in order to transfer the next bit, but will detect that the clock line has not yet been released. because the scl connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 29.3.2 arbitration each master device must monitor the bus for start and stop bits. if the device detects that the bus is busy, it cannot begin a new message until the bus returns to an idle state. however, two master devices may try to initiate a transmission on or about the same time. when this occurs, the process of arbitration begins. each transmitter checks the level of the sda data line and compares it to the level that it expects to find. the first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the sda line. for example, if one transmitter holds the sda line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the sda line will be low. the first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. the first transmitter to notice this difference is the one that loses arbitration and must stop driving the sda line. if this transmitter is also a master device, it also must stop driving the scl line. it then can monitor the lines for a stop condition before trying to reissue its transmission. in the meantime, the other device that has not noticed any difference between the expected and actual levels on the sda line continues with its original transmission. it can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. if two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitra- tion. when two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 324 preliminary ? 2016 microchip technology inc. 29.4 i 2 c mode operation all mssp i 2 c communication is byte oriented and shifted out msb first. six sfr registers and two interrupt flags interface the module with the pic ? microcontroller and user software. two pins, sda and scl, are exercised by the module to communicate with other external i 2 c devices. 29.4.1 byte format all communication in i 2 c is done in 9-bit segments. a byte is sent from a master to a slave or vice-versa, followed by an acknowledge bit sent back. after the eighth falling edge of the scl line, the device output- ting data on the sda changes that pin to an input and reads in an acknowledge value on the next clock pulse. the clock signal, scl, is provided by the master. data is valid to change while the scl signal is low, and sampled on the rising edge of the clock. changes on the sda line while the scl line is high define special conditions on the bus, explained below. 29.4.2 definition of i 2 c terminology there is language and terminology in the description of i 2 c communication that have definitions specific to i 2 c. that word usage is defined below and may be used in the rest of this document without explanation. this table was adapted from the philips i 2 c specification. 29.4.3 sda and scl pins selection of any i 2 c mode with the sspen bit set, forces the scl and sda pins to be open-drain. these pins should be set by the user to inputs by setting the appropriate tris bits. 29.4.4 sda hold time the hold time of the sda pin is selected by the sdaht bit of the sspxcon3 register. hold time is the time sda is held valid after the falling edge of scl. setting the sdaht bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. note 1: data is tied to output zero when an i 2 c mode is enabled. 2: any device pin can be selected for sda and scl functions with the pps peripheral. these functions are bidirectional. the sda input is selected with the sspdatpps registers. the scl input is selected with the sspclkpps registers. outputs are selected with the rxypps registers. it is the users responsibility to make the selections so that both the input and the output for each function is on the same pin. table 29-1: i 2 c bus terms term description transmitter the device which shifts data out onto the bus. receiver the device which shifts data in from the bus. master the device that initiates a transfer, generates clock signals and terminates a transfer. slave the device addressed by the master. multi-master a bus with more than one device that can initiate data transfers. arbitration procedure to ensure that only one master at a time controls the bus. winning arbitration ensures that the message is not corrupted. synchronization procedure to synchronize the clocks of two or more devices on the bus. idle no master is controlling the bus, and both sda and scl lines are high. active any time one or more master devices are controlling the bus. addressed slave slave device that has received a matching address and is actively being clocked by a master. matching address address byte that is clocked into a slave that matches the value stored in sppxadd. write request slave receives a matching address with r/w bit clear, and is ready to clock in data. read request master sends an address byte with the r/w bit set, indicating that it wishes to clock data out of the slave. this data is the next and all following bytes until a restart or stop. clock stretching when a device on the bus hold scl low to stall communication. bus collision any time the sda line is sampled low by the module while it is out- putting and expected high state. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 325 pic16(l)f18326/18346 29.4.5 start condition the i 2 c specification defines a start condition as a transition of sda from a high to a low state while scl line is high. a start condition is always generated by the master and signifies the transition of the bus from an idle to an active state. figure 29-12 shows wave forms for start and stop conditions. a bus collision can occur on a start condition if the module samples the sda line low before asserting it low. this does not conform to the i 2 c specification that states no bus collision can occur on a start. 29.4.6 stop condition a stop condition is a transition of the sda line from low-to-high state while the scl line is high. 29.4.7 restart condition a restart is valid any time that a stop would be valid. a master can issue a restart if it wishes to hold the bus after terminating the current transfer. a restart has the same effect on the slave that a start would, resetting all slave logic and preparing it to clock in an address. the master may want to address the same or another slave. figure 29-13 shows the wave form for a restart condition. in 10-bit addressing slave mode a restart is required for the master to clock data out of the addressed slave. once a slave has been fully addressed, match- ing both high and low address bytes, the master can issue a restart and the high address byte with the r/w bit set. the slave logic will then hold the clock and prepare to clock out data. after a full match with r/w clear in 10-bit mode, a prior match flag is set and maintained until a stop condition, a high address with r/w clear, or high address match fails. 29.4.8 start/stop condition interrupt masking the scie and pcie bits of the sspxcon3 register can enable the generation of an interrupt in slave modes that do not typically support this function. slave modes where interrupt on start and stop detect are already enabled, these bits will have no effect. figure 29-12: i 2 c start and stop conditions figure 29-13: i 2 c restart condition note: at least one scl low time must appear before a stop is valid, therefore, if the sda line goes low then high again while the scl line stays high, only the start condition is detected. sda scl p stop condition s start condition change of data allowed change of data allowed restart condition sr change of data allowed change of data allowed downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 326 preliminary ? 2016 microchip technology inc. 29.4.9 acknowledge sequence the ninth scl pulse for any transferred byte in i 2 c is dedicated as an acknowledge. it allows receiving devices to respond back to the transmitter by pulling the sda line low. the transmitter must release control of the line during this time to shift in the response. the acknowledge (ack ) is an active-low signal, pulling the sda line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more. the result of an ack is placed in the ackstat bit of the sspxcon2 register. slave software, when the ahen and dhen bits are set, allow the user to set the ack value sent back to the transmitter. the ackdt bit of the sspxcon2 register is set/cleared to determine the response. slave hardware will generate an ack response if the ahen and dhen bits of the sspxcon3 register are clear. there are certain conditions where an ack will not be sent by the slave. if the bf bit of the sspxstat register or the sspov bit of the sspxcon1 register are set when a byte is received. when the module is addressed, after the eighth falling edge of scl on the bus, the acktim bit of the sspxcon3 register is set. the acktim bit indicates the acknowledge time of the active bus. the acktim status bit is only active when the ahen bit or dhen bit is enabled. 29.5 i 2 c slave mode operation the mssp slave mode operates in one of four modes selected by the sspm bits of sspxcon1 register. the modes can be divided into 7-bit and 10-bit addressing mode. 10-bit addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. modes with start and stop bit interrupts operate the same as the other modes with sspxif additionally getting set upon detection of a start, restart, or stop condition. 29.5.1 slave mode addresses the sspxadd register ( register 29-6 ) contains the slave mode address. the first byte received after a start or restart condition is compared against the value stored in this register. if the byte matches, the value is loaded into the sspxbuf register and an interrupt is generated. if the value does not match, the module goes idle and no indication is given to the software that anything happened. the ssp mask register ( register 29-5 ) affects the address matching process. see section 29.5.9 ?ssp mask register? for more information. 29.5.1.1 i 2 c slave 7-bit addressing mode in 7-bit addressing mode, the lsb of the received data byte is ignored when determining if there is an address match. 29.5.1.2 i 2 c slave 10-bit addressing mode in 10-bit addressing mode, the first received byte is compared to the binary value of 1 1 1 1 0 a9 a8 0. a9 and a8 are the two msbs of the 10-bit address and stored in bits 2 and 1 of the sspxadd register. after the acknowledge of the high byte the ua bit is set and scl is held low until the user updates sspxadd with the low address. the low address byte is clocked in and all eight bits are compared to the low address value in sspxadd. even if there is not an address match; sspif and ua are set, and scl is held low until sspxadd is updated to receive a high byte again. when sspxadd is updated the ua bit is cleared. this ensures the module is ready to receive the high address byte on the next communication. a high and low address match as a write request is required at the start of all 10-bit addressing communi- cation. a transmission can be initiated by issuing a restart once the slave is addressed, and clocking in the high address with the r/w bit set. the slave hardware will then acknowledge the read request and prepare to clock out data. this is only valid for a slave after it has received a complete high and low address byte match. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 327 pic16(l)f18326/18346 29.5.2 slave reception when the r/w bit of a matching received address byte is clear, the r/w bit of the sspxstat register is cleared. the received address is loaded into the sspxbuf register and acknowledged. when the overflow condition exists for a received address, then not acknowledge is given. an overflow condition is defined as either bit bf of the sspxstat register is set, or bit sspov of the sspxcon1 register is set. the boen bit of the sspxcon3 register modi- fies this operation. for more information see register 29-4 . an mssp interrupt is generated for each transferred data byte. flag bit, sspxif, must be cleared by software. when the sen bit of the sspxcon2 register is set, scl will be held low (clock stretch) following each received byte. the clock must be released by setting the ckp bit of the sspxcon1 register, except sometimes in 10-bit mode. see section 29.5.6.2 ?10-bit addressing mode? for more detail. 29.5.2.1 7-bit addressing reception this section describes a standard sequence of events for the msspx module configured as an i 2 c slave in 7-bit addressing mode. figure 29-14 and figure 29-15 is used as a visual reference for this description. this is a step-by-step process of what typically must be done to accomplish i 2 c communication. 1. start bit detected. 2. s bit of sspxstat is set; sspxif is set if inter- rupt on start detect is enabled. 3. matching address with r/w bit clear is received. 4. the slave pulls sda low sending an ack to the master, and sets sspxif bit. 5. software clears the sspxif bit. 6. software reads received address from sspxbuf clearing the bf flag. 7. if sen = 1 ; slave software sets ckp bit to release the scl line. 8. the master clocks out a data byte. 9. slave drives sda low sending an ack to the master, and sets sspxif bit. 10. software clears sspxif. 11. software reads the received byte from sspxbuf clearing bf. 12. steps 8-12 are repeated for all received bytes from the master. 13. master sends stop condition, setting p bit of sspxstat, and the bus goes idle. 29.5.2.2 7-bit reception with ahen and dhen slave device reception with ahen and dhen set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of scl. these additional interrupts allow the slave software to decide whether it wants to ack the receive address or data byte, rather than the hard- ware. this functionality adds support for pmbus that was not present on previous versions of this module. this list describes the steps that need to be taken by slave software to use these options for i 2 c communi- cation. figure 29-16 displays a module using both address and data holding. figure 29-17 includes the operation with the sen bit of the sspxcon2 register set. 1. s bit of sspxstat is set; sspxif is set if interrupt on start detect is enabled. 2. matching address with r/w bit clear is clocked in. sspxif is set and ckp cleared after the eighth falling edge of scl. 3. slave clears the sspxif. 4. slave can look at the acktim bit of the sspxcon3 register to determine if the sspxif was after or before the ack. 5. slave reads the address value from sspxbuf, clearing the bf flag. 6. slave sets ack value clocked out to the master by setting ackdt. 7. slave releases the clock by setting ckp. 8. sspxif is set after an ack , not after a nack. 9. if sen = 1 the slave hardware will stretch the clock after the ack. 10. slave clears sspxif. 11. sspxif set and ckp cleared after eighth falling edge of scl for a received data byte. 12. slave looks at acktim bit of sspxcon3 to determine the source of the interrupt. 13. slave reads the received data from sspxbuf clearing bf. 14. steps 7-14 are the same for each received data byte. 15. communication is ended by either the slave sending an ack = 1 , or the master sending a stop condition. if a stop is sent and interrupt on stop detect is disabled, the slave will only know by polling the p bit of the sspxstat register. note: sspxif is still set after the ninth falling edge of scl even if there is no clock stretching and bf has been cleared. only if nack is sent to master is sspif not set downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 328 preliminary ? 2016 microchip technology inc. figure 29-14: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving data ack receiving data ack = 1 a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspxif bf sspov 12345678 12345678 12345678 9 9 9 ack is not sent. sspov set because sspxbuf is still full. cleared by software first byte of data is available in sspxbuf sspxbuf is read sspxif set on 9th falling edge of scl cleared by software p bus master sends stop condition s from slave to master downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 329 pic16(l)f18326/18346 figure 29-15: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sen sen a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl 123456789 123456789 123456789 p sspxif set on 9th scl is not held ckp is written to 1 in software, ckp is written to 1 in software, ack low because falling edge of scl releasing scl ack is not sent. bus master sends ckp sspov bf sspxif sspov set because sspxbuf is still full. cleared by software first byte of data is available in sspxbuf ack = 1 cleared by software sspxbuf is read clock is held low until ckp is set to 1 releasing scl stop condition s ack ack receive address receive data receive data r/w= 0 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 330 preliminary ? 2016 microchip technology inc. figure 29-16: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 1 , dhen = 1 ) receiving address receiving data received data p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl bf ckp s p 12 3 4 56 7 8 9 12345678 9 12345678 master sends stop condition s data is read from sspxbuf cleared by software sspxif is set on 9th falling edge of scl, after ack ckp set by software, scl is released slave software 9 acktim cleared by hardware in 9th rising edge of scl sets ackdt to not ack when dhen = 1 : ckp is cleared by hardware on 8th falling edge of scl slave software clears ackdt to ack the received byte acktim set by hardware on 8th falling edge of scl when ahen= 1 : ckp is cleared by hardware and scl is stretched address is read from sspxbuf acktim set by hardware on 8th falling edge of scl ack master releases sda to slave for ack sequence no interrupt after not ack from slave ack = 1 ack ackdt acktim sspxif if ahen = 1 : sspif is set downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 331 pic16(l)f18326/18346 figure 29-17: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 1 , dhen = 1 ) receiving address receive data receive data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspxif bf ackdt ckp sp ack s 12 34 5678 9 12 3 4567 8 9 12 345 67 8 9 ack ack cleared by software acktim is cleared by hardware sspxbuf can be set by software, read any time before next byte is loaded release scl on 9th rising edge of scl received address is loaded into sspxbuf slave software clears ackdt to ack r/w = 0 master releases sda to slave for ack sequence the received byte when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl when dhen = 1 ; on the 8th falling edge of scl of a received data byte, ckp is cleared received data is available on sspxbuf slave sends not ack ckp is not cleared if not ack p master sends stop condition no interrupt after if not ack from slave acktim downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 332 preliminary ? 2016 microchip technology inc. 29.5.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspxstat register is set. the received address is loaded into the sspxbuf register, and an ack pulse is sent by the slave on the ninth bit. following the ack , slave hardware clears the ckp bit and the scl pin is held low (see section 29.5.6 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspxbuf register which also loads the sspxsr register. then the scl pin should be released by setting the ckp bit of the sspxcon1 register. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time. the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. this ack value is copied to the ackstat bit of the sspxcon2 register. if ackstat is set (not ack ), then the data transfer is complete. in this case, when the not ack is latched by the slave, the slave goes idle and waits for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspxbuf register. again, the scl pin must be released by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspxif bit must be cleared by software and the sspxstat register is used to determine the status of the byte. the sspxif bit is set on the falling edge of the ninth clock pulse. 29.5.3.1 slave mode bus collision a slave receives a read request and begins shifting data out on the sda line. if a bus collision is detected and the sbcde bit of the sspxcon3 register is set, the bclif bit of the pir register is set. once a bus col- lision is detected, the slave goes idle and waits to be addressed again. user software can use the bclif bit to handle a slave bus collision. 29.5.3.2 7-bit transmission a master device can transmit a read request to a slave, and then clock data out of the slave. the list below outlines what software for a slave will need to do to accomplish a standard transmission. figure 29-18 can be used as a reference to this list. 1. master sends a start condition on sda and scl. 2. s bit of sspxstat is set; sspxif is set if interrupt on start detect is enabled. 3. matching address with r/w bit set is received by the slave setting sspxif bit. 4. slave hardware generates an ack and sets sspxif. 5. sspxif bit is cleared by user. 6. software reads the received address from sspxbuf, clearing bf. 7. r/w is set so ckp was automatically cleared after the ack. 8. the slave software loads the transmit data into sspxbuf. 9. ckp bit is set releasing scl, allowing the master to clock the data out of the slave. 10. sspxif is set after the ack response from the master is loaded into the ackstat register. 11. sspxif bit is cleared. 12. the slave software checks the ackstat bit to see if the master wants to clock out more data. 13. steps 9-13 are repeated for each transmitted byte. 14. if the master sends a not ack ; the clock is not held, but sspxif is still set. 15. the master sends a restart condition or a stop. 16. the slave is no longer addressed. note 1: if the master ack s the clock will be stretched. 2: ackstat is the only bit updated on the rising edge of scl (9th) rather than the falling. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 333 pic16(l)f18326/18346 figure 29-18: i 2 c slave, 7-bit address, transmission (ahen = 0 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspxif bf ckp ackstat r/w d/a sp received address when r/w is set r/w is copied from the indicates an address is read from sspxbuf scl is always held low after 9th scl falling edge matching address byte has been received masters not ack is copied to ackstat ckp is not held for not ack bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into sspxbuf set by software cleared by software ack ack ack r/w = 1 s p master sends stop condition downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 334 preliminary ? 2016 microchip technology inc. 29.5.3.3 7-bit transmission with address hold enabled setting the ahen bit of the sspxcon3 register enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. once a matching address has been clocked in, ckp is cleared and the sspxif interrupt is set. figure 29-19 displays a standard waveform of a 7-bit address slave transmission with ahen enabled. 1. bus starts idle. 2. master sends start condition; the s bit of sspxstat is set; sspxif is set if interrupt on start detect is enabled. 3. master sends matching address with r/w bit set. after the eighth falling edge of the scl line the ckp bit is cleared and sspxif interrupt is generated. 4. slave software clears sspxif. 5. slave software reads acktim bit of sspxcon3 register, and r/w and d/a of the sspxstat register to determine the source of the interrupt. 6. slave reads the address value from the sspxbuf register clearing the bf bit. 7. slave software decides from this information if it wishes to ack or not ack and sets the ackdt bit of the sspxcon2 register accordingly. 8. slave sets the ckp bit releasing scl. 9. master clocks in the ack value from the slave. 10. slave hardware automatically clears the ckp bit and sets sspxif after the ack if the r/w bit is set. 11. slave software clears sspxif. 12. slave loads value to transmit to the master into sspxbuf setting the bf bit. 13. slave sets the ckp bit releasing the clock. 14. master clocks out the data from the slave and sends an ack value on the ninth scl pulse. 15. slave hardware copies the ack value into the ackstat bit of the sspxcon2 register. 16. steps 10-15 are repeated for each byte transmit- ted to the master from the slave. 17. if the master sends a not ack the slave releases the bus allowing the master to send a stop and end the communication. note: sspxbuf cannot be loaded until after the ack. note: master must send a not ack on the last byte to ensure that the slave releases the scl line to receive a stop. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 335 pic16(l)f18326/18346 figure 29-19: i 2 c slave, 7-bit address, transmission (ahen = 1 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspxif bf ackdt ackstat ckp r/w d/a received address is read from sspxbuf bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into sspxbuf cleared by software slave clears ackdt to ack address masters ack response is copied to sspxstat ckp not cleared after not ack set by software, releases scl acktim is cleared on 9th rising edge of scl acktim is set on 8th falling edge of scl when ahen = 1 ; ckp is cleared by hardware after receiving matching address. when r/w = 1 ; ckp is always cleared after ack s p master sends stop condition ack r/w = 1 master releases sda to slave for ack sequence ack ack acktim downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 336 preliminary ? 2016 microchip technology inc. 29.5.4 slave mode 10-bit address reception this section describes a standard sequence of events for the msspx module configured as an i 2 c slave in 10-bit addressing mode. figure 29-20 is used as a visual reference for this description. this is a step-by-step process of what must be done by slave software to accomplish i 2 c communication. 1. bus starts idle. 2. master sends start condition; s bit of sspxstat is set; sspxif is set if interrupt on start detect is enabled. 3. master sends matching high address with r/w bit clear; ua bit of the sspxstat register is set. 4. slave sends ack and sspxif is set. 5. software clears the sspxif bit. 6. software reads received address from sspxbuf clearing the bf flag. 7. slave loads low address into sspxadd, releasing scl. 8. master sends matching low address byte to the slave; ua bit is set. 9. slave sends ack and sspxif is set. 10. slave clears sspxif. 11. slave reads the received matching address from sspxbuf clearing bf. 12. slave loads high address into sspxadd. 13. master clocks a data byte to the slave and clocks out the slaves ack on the ninth scl pulse; sspxif is set. 14. if sen bit of sspxcon2 is set, ckp is cleared by hardware and the clock is stretched. 15. slave clears sspxif. 16. slave reads the received byte from sspxbuf clearing bf. 17. if sen is set the slave sets ckp to release the scl. 18. steps 13-17 repeat for each received byte. 19. master sends stop to end the transmission. 29.5.5 10-bit addressing with address or data hold reception using 10-bit addressing with ahen or dhen set is the same as with 7-bit modes. the only difference is the need to update the sspxadd register using the ua bit. all functionality, specifically when the ckp bit is cleared and scl line is held low are the same. figure 29-21 can be used as a reference of a slave in 10-bit addressing with ahen set. figure 29-22 shows a standard waveform for a slave transmitter in 10-bit addressing mode. note: updates to the sspxadd register are not allowed until after the ack sequence. note: if the low address does not match, sspxif and ua are still set so that the slave software can set sspxadd back to the high address. bf is not set because there is no match. ckp is unaffected. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 337 pic16(l)f18326/18346 figure 29-20: i 2 c slave, 10-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sspxif receive first address byte ack receive second address byte ack receive data ack receive data ack 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl ua ckp 1 2345678 912345678 912345678 9 12345678 9 p master sends stop condition cleared by software receive address is software updates sspxadd data is read scl is held low set by software, while ckp = 0 from sspxbuf releasing scl when sen = 1 ; ckp is cleared after 9th falling edge of received byte read from sspxbuf and releases scl when ua = 1 ; if address matches set by hardware on 9th falling edge sspxadd it is loaded into sspxbuf scl is held low s bf downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 338 preliminary ? 2016 microchip technology inc. figure 29-21: i 2 c slave, 10-bit address, reception (sen = 0 , ahen = 1 , dhen = 0 ) receive first address byte ua receive second address byte ua receive data ack receive data 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 sda scl sspxif bf ackdt ua ckp acktim 12345678 9 s ack ack 12 345678 9 12345678 91 2 sspxbuf is read from received data sspxbuf can be read anytime before the next received byte cleared by software falling edge of scl not allowed until 9th update to sspxadd is set ckp with software releases scl scl clears ua and releases update of sspxadd, set by hardware on 9th falling edge slave software clears ackdt to ack the received byte if when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl cleared by software r/w = 0 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 339 pic16(l)f18326/18346 figure 29-22: i 2 c slave, 10-bit address, transmission (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving second address byte sr receive first address byte ack transmitting data byte 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 1 1 0 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspxif bf ua ckp r/w d/a 1 2345 6789 1 2345 6789 1 23 4 5 6789 1 23456 789 ack = 1 p master sends stop condition master sends not ack master sends restart event ack r/w = 0 s cleared by software after sspxadd is updated, ua is cleared and scl is released high address is loaded received address is data to transmit is set by software indicates an address when r/w = 1 ; r/w is copied from the set by hardware ua indicates sspxadd sspxbuf loaded with received address must be updated has been received loaded into sspxbuf releases scl masters not ack is copied matching address byte ckp is cleared on 9th falling edge of scl read from sspxbuf back into sspxadd ackstat set by hardware downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 340 preliminary ? 2016 microchip technology inc. 29.5.6 clock stretching clock stretching occurs when a device on the bus holds the scl line low, effectively pausing communi- cation. the slave may stretch the clock to allow more time to handle data or prepare a response for the master device. a master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. any stretching done by a slave is invisible to the master software and handled by the hardware that generates scl. the ckp bit of the sspxcon1 register is used to control stretching in software. any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. setting ckp will release scl and allow more communication. 29.5.6.1 normal clock stretching following an ack if the r/w bit of sspxstat is set, a read request, the slave hardware will clear ckp. this allows the slave time to update sspxbuf with data to transfer to the master. if the sen bit of sspxcon2 is set, the slave hardware will always stretch the clock after the ack sequence. once the slave is ready; ckp is set by software and communication resumes. 29.5.6.2 10-bit addressing mode in 10-bit addressing mode, when the ua bit is set, the clock is always stretched. this is the only time the scl is stretched without ckp being cleared. scl is released immediately after a write to sspxadd. 29.5.6.3 byte nacking when the ahen bit of sspxcon3 is set; ckp is cleared by hardware after the eighth falling edge of scl for a received matching address byte. when the dhen bit of sspxcon3 is set; ckp is cleared after the eighth falling edge of scl for received data. stretching after the eighth falling edge of scl allows the slave to look at the received address or data and decide if it wants to ack the received data. 29.5.7 clock synchronization and the ckp bit any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. however, clearing the ckp bit will not assert the scl output low until the scl output is already sampled low. there- fore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have released scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 29-23 ). figure 29-23: clock synchronization timing note 1: the bf bit has no effect on if the clock will be stretched or not. this is different than previous versions of the module that would not stretch the clock, clear ckp, if sspxbuf was read before the ninth falling edge of scl. 2: previous versions of the module did not stretch the clock for a transmission if sspxbuf was loaded before the ninth falling edge of scl. it is now always cleared for read requests. note: previous versions of the module did not stretch the clock if the second address byte did not match. sda scl dx ? C 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspxcon1 ckp master device releases clock master device asserts clock downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 341 pic16(l)f18326/18346 29.5.8 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master device. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is a reserved address in the i 2 c protocol, defined as address 0x00. when the gcen bit of the sspxcon2 register is set, the slave module will automatically ack the reception of this address regardless of the value stored in sspxadd. after the slave clocks in an address of all zeros with the r/w bit clear, an interrupt is generated and slave software can read sspxbuf and respond. figure 29-24 shows a general call reception sequence. in 10-bit address mode, the ua bit will not be set on the reception of the general call address. the slave will prepare to receive the second byte as data, just as it would in 7-bit mode. if the ahen bit of the sspxcon3 register is set, just as with any other address reception, the slave hard- ware will stretch the clock after the eighth falling edge of scl. the slave must then set its ackdt value and release the clock with communication progressing as it would normally. figure 29-24: slave mode general call address sequence 29.5.9 ssp mask register an ssp mask (sppxmsk) register ( register 29-5 ) is available in i 2 c slave mode as a mask for the value held in the sspxsr register during an address comparison operation. a zero ( 0 ) bit in the sspxmsk register has the effect of making the corresponding bit of the received address a dont care. this register is reset to all 1 s upon any reset condition and, therefore, has no effect on standard ssp operation until written with a mask value. the ssp mask register is active during: 7-bit address mode: address compare of a<7:1>. 10-bit address mode: address compare of a<7:0> only. the ssp mask has no effect during the reception of the first (high) byte of the address. sda scl s sspxif bf (sspxstat<0>) cleared by software sspxbuf is read r/w = 0 ack general call address address is compared to general call address receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt gcen (sspxcon2<7>) 1 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 342 preliminary ? 2016 microchip technology inc. 29.6 i 2 c master mode master mode is enabled by setting and clearing the appropriate sspm<3:0> bits in the sspxcon1 register and by setting the sspen bit. in master mode, the sda and sck pins must be configured as inputs. the mssp peripheral hardware will override the output driver tris controls when necessary to drive the pins low. master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the msspx module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit condition detection. start and stop condition detection is the only active circuitry in this mode. all other communication is done by the user software directly manipulating the sda and scl lines. the following events will cause the ssp interrupt flag bit, sspxif, to be set (ssp interrupt, if enabled): start condition detected stop condition detected data transfer byte transmitted/received acknowledge transmitted/received repeated start generated 29.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic 0 . serial data is transmitted eight bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic 1 . thus, the first byte transmitted is a 7-bit slave address followed by a 1 to indicate the receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received eight bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. a baud rate generator is used to set the clock frequency output on scl. see section 29.7 ?baud rate generator? for more detail. note 1: the msspx module, when configured in i 2 c master mode, does not allow queuing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspxbuf register to initiate transmission before the start condition is complete. in this case, the sspxbuf will not be written to and the wcol bit will be set, indicating that a write to the sspxbuf did not occur 2: when in master mode, start/stop detection is masked and an interrupt is generated when the sen/pen bit is cleared and the generation is complete. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 343 pic16(l)f18326/18346 29.6.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, releases the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspxadd<7:0> and begins count- ing. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 29-25 ). figure 29-25: baud rate generator timing with clock arbitration 29.6.3 wcol status flag if the user writes the sspxbuf when a start, restart, stop, receive or transmit sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write does not occur). any time the wcol bit is set it indicates that an action on sspxbuf was attempted while the module was not idle. sda scl scl deasserted but slave holds dx ? C 1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles note: because queuing of events is not allowed, writing to the lower five bits of sspxcon2 is disabled until the start condition is complete. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 344 preliminary ? 2016 microchip technology inc. 29.6.4 i 2 c master mode start condition timing to initiate a start condition ( figure 29-26 ), the user sets the start enable bit, sen bit of the sspxcon2 register. if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of sspxadd<7:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit of the sspxstat register to be set. following this, the baud rate generator is reloaded with the contents of sspxadd<7:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit of the sspxcon2 register will be automatically cleared by hardware; the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. figure 29-26: first start bit timing note 1: if at the beginning of the start condition, the sda and scl pins are already sampled low, or if during the start condi- tion, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. 2: the philips i 2 c specification states that a bus collision cannot occur on a start. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspxbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspxstat<3>) and sets sspxif bit downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 345 pic16(l)f18326/18346 29.6.5 i 2 c master mode repeated start condition timing a repeated start condition ( figure 29-27 ) occurs when the rsen bit of the sspxcon2 register is programmed high and the master state machine is no longer active. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. scl is asserted low. following this, the rsen bit of the sspxcon2 register will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit of the sspxstat register will be set. the sspxif bit will not be set until the baud rate generator has timed out. figure 29-27: repeated start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: sda is sampled low when scl goes from low-to-high. scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data 1 . sdascl repeated start write to sspxcon2 write to sspxbuf occurs here at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sda = 1 , sda = 1 , scl (no change) scl = 1 occurs here t brg t brg t brg and sets sspxif sr downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 346 preliminary ? 2016 microchip technology inc. 29.6.6 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspxbuf register. this action will set the buffer full flag bit, bf, and allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted. scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high. when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received properly. the status of ack is written into the ackstat bit on the rising edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspxbuf, leaving scl low and sda unchanged ( figure 29-28 ). after the write to the sspxbuf, each bit of the address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will release the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit of the sspxcon2 register. following the falling edge of the ninth clock transmission of the address, the sspxif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspxbuf takes place, holding scl low and allowing sda to float. 29.6.6.1 bf status flag in transmit mode, the bf bit of the sspxstat register is set when the cpu writes to sspxbuf and is cleared when all eight bits are shifted out. 29.6.6.2 wcol status flag if the user writes the sspxbuf when a transmit is already in progress (i.e., sspxsr is still shifting out a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). wcol must be cleared by software before the next transmission. 29.6.6.3 ackstat status flag in transmit mode, the ackstat bit of the sspxcon2 register is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowledge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 29.6.6.4 typical transmit sequence 1. the user generates a start condition by setting the sen bit of the sspxcon2 register. 2. sspxif is set by hardware on completion of the start. 3. sspxif is cleared by software. 4. the msspx module will wait the required start time before any other operation takes place. 5. the user loads the sspxbuf with the slave address to transmit. 6. address is shifted out the sda pin until all eight bits are transmitted. transmission begins as soon as sspxbuf is written to. 7. the msspx module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 8. the msspx module generates an interrupt at the end of the ninth clock cycle by setting the sspxif bit. 9. the user loads the sspxbuf with eight bits of data. 10. data is shifted out the sda pin until all eight bits are transmitted. 11. the msspx module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 12. steps 8-11 are repeated for all transmitted data bytes. 13. the user generates a stop or restart condition by setting the pen or rsen bits of the sspxcon2 register. interrupt is generated once the stop/restart condition is complete. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 347 pic16(l)f18326/18346 figure 29-28: i 2 c master mode waveform (transmission, 7 or 10-bit address) sdascl sspxif bf (sspxstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared by software service routine sspxbuf is written by software from ssp interrupt after start condition, sen cleared by hardware s sspxbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspxif sen = 0 of 10-bit address write sspxcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspxcon2<6> ackstat in sspxcon2 = 1 cleared by software sspxbuf written pen r/w cleared by software downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 348 preliminary ? 2016 microchip technology inc. 29.6.7 i 2 c master mode reception master mode reception ( figure 29-29 ) is enabled by programming the receive enable bit, rcen bit of the sspxcon2 register. the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high-to-low/low-to-high) and data is shifted into the sspxsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspxsr are loaded into the sspxbuf, the bf flag bit is set, the sspxif flag bit is set and the baud rate generator is suspended from counting, holding scl low. the msspx is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable, acken bit of the sspxcon2 register. 29.6.7.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspxbuf from sspxsr. it is cleared when the sspxbuf register is read. 29.6.7.2 sspov status flag in receive operation, the sspov bit is set when eight bits are received into the sspxsr and the bf flag bit is already set from a previous reception. 29.6.7.3 wcol status flag if the user writes the sspxbuf when a receive is already in progress (i.e., sspxsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 29.6.7.4 typical receive sequence: 1. the user generates a start condition by setting the sen bit of the sspxcon2 register. 2. sspxif is set by hardware on completion of the start. 3. sspxif is cleared by software. 4. user writes sspxbuf with the slave address to transmit and the r/w bit set. 5. address is shifted out the sda pin until all eight bits are transmitted. transmission begins as soon as sspxbuf is written to. 6. the msspx module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 7. the msspx module generates an interrupt at the end of the ninth clock cycle by setting the sspxif bit. 8. user sets the rcen bit of the sspxcon2 regis- ter and the master clocks in a byte from the slave. 9. after the eighth falling edge of scl, sspxif and bf are set. 10. master clears sspxif and reads the received byte from sspxbuf, clears bf. 11. master sets ack value sent to slave in ackdt bit of the sspxcon2 register and initiates the ack by setting the acken bit. 12. masters ack is clocked out to the slave and sspxif is set. 13. user clears sspif. 14. steps 8-13 are repeated for each received byte from the slave. 15. master sends a not ack or stop to end communication. note: the msspx module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 349 pic16(l)f18326/18346 figure 29-29: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sdascl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w transmit address to slave sspxif bf ack is not sent write to sspxcon2<0>(sen = 1 ), write to sppxbuf occurs here, ack from slave master configured as a receiver by programming sspxcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared by software start xmit sen = 0 sspov sda = 0 , scl = 1 while cpu (sspxstat<0>) ack cleared by software cleared by software set sspxif interrupt at end of receive set p bit (sspxstat<4>) and sspxif cleared in software ack from master set sspif at end set sspxif interrupt at end of acknowledge sequence set sspxif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sspov is set because sspxbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspxcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared by software sda = ackdt = 0 last bit is shifted into sspxsr and contents are unloaded into sspxbuf rcen master configured as a receiver by programming sspxcon2<3> (rcen = 1 ) rcen cleared automatically ack from master sda = ackdt = 0 rcen cleared automatically downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 350 preliminary ? 2016 microchip technology inc. 29.6.8 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken bit of the sspxcon2 register. when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to generate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is auto- matically cleared, the baud rate generator is turned off and the msspx module then goes into idle mode ( figure 29-30 ). 29.6.8.1 wcol status flag if the user writes the sspxbuf when an acknowledge sequence is in progress, then wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 29.6.9 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen bit of the sspxcon2 register. at the end of a receive/transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to 0 . when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sampled high while scl is high, the p bit of the sspxstat register is set. a t brg later, the pen bit is cleared and the sspxif bit is set ( figure 29-31 ). 29.6.9.1 wcol status flag if the user writes the sspxbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). figure 29-30: acknowledge sequen ce waveform figure 29-31: stop cond ition receive or transmit mode note: t brg = one baud rate generator period. sda scl sspxif set at acknowledge sequence starts here, write to sspxcon2 acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 sspxif software sspxif set at the end of acknowledge sequence cleared in software ack sclsda sda asserted low before rising edge of clock write to sspxcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspxstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspxcon2<2>) is cleared by hardware and the sspxif bit is set downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 351 pic16(l)f18326/18346 29.6.10 sleep operation while in sleep mode, the i 2 c slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 29.6.11 effects of a reset a reset disables the msspx module and terminates the current transfer. 29.6.12 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the msspx module is disabled. control of the i 2 c bus may be taken when the p bit of the sspxstat register is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed by hardware with the result placed in the bcl1if bit. the states where arbitration can be lost are: address transfer data transfer a start condition a repeated start condition an acknowledge condition 29.6.13 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a 1 on sda, by letting sda float high and another master asserts a 0 . when the scl pin floats high, data should be stable. if the expected data on sda is a 1 and the data sampled on the sda pin is 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif and reset the i 2 c port to its idle state ( figure 29-32 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspxbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deasserted and the respective control bits in the sspxcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspxif bit will be set. a write to the sspxbuf will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspxstat register, or the bus is idle and the s and p bits are cleared. figure 29-32: bus collision timing for transmit and acknowledge sda scl bcl1if sda released sda line pulled low by another source sample sda. while scl is high, data does not match what is driven bus collision has occurred. set bus collision interrupt (bcl1if) by the master. by master data changes while scl = 0 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 352 preliminary ? 2016 microchip technology inc. 29.6.13.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition ( figure 29-33 ). b) scl is sampled low before sda is asserted low ( figure 29-34 ). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: the start condition is aborted, the bcl1if flag is set and the msspx module is reset to its idle state ( figure 29-33 ). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded and counts down. if the scl pin is sampled low while sda is high, a bus collision occurs because it is assumed that another master is attempting to drive a data 1 during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early ( figure 29-35 ). if, however, a 1 is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to zero; if the scl pin is sampled as 0 during this time, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 29-33: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condi- tion at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspxif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspxif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bcl1if s sspxif sda = 0 , scl = 1 . sspxif and bcl1if are cleared by software sspxif and bcl1if are cleared by software set bcl1if, start condition. set bcl1if. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 353 pic16(l)f18326/18346 figure 29-34: bus collision d uring start condition (scl = 0 ) figure 29-35: brg reset due to sda arbitration during start condition sdascl sen bus collision occurs. set bcl1if. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bcl1if s sspxif interrupt cleared by software bus collision occurs. set bcl1if. scl = 0 before brg time-out, 0 0 0 0 sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bcl1if s sspxif s interrupts cleared by software set sspxif sda = 0 , scl = 1 , scl pulled low after brg time-out set sspxif 0 sda pulled low by other master. reset brg and assert sda. set sen, enable start sequence if sda = 1 , scl = 1 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 354 preliminary ? 2016 microchip technology inc. 29.6.13.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level (case 1). b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data 1 (case 2). when the user releases sda and the pin is allowed to float high, the brg is loaded with sspxadd and counts down to zero. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data 0 , figure 29-36 ). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data 1 during the repeated start condition, see figure 29-37 . if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 29-36: bus collision during a repeat ed start condition (case 1) figure 29-37: bus collision during repeated start condition (case 2) sda scl rsen bcl1if s sspxif sample sda when scl goes high. if sda = 0 , set bcl1if and release sda and scl. cleared by software 0 0 sda scl bcl1if rsen s sspxif interrupt cleared by software scl goes low before sda, set bcl1if. release sda and scl. t brg t brg 0 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 355 pic16(l)f18326/18346 29.6.13.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out (case 1). b) after the scl pin is deasserted, scl is sampled low before sda goes high (case 2). the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspxadd and counts down to zero. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data 0 ( figure 29-38 ). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data 0 ( figure 29-39 ). figure 29-38: bus collision during a stop condition (case 1) figure 29-39: bus collision during a stop condition (case 2) sda scl bcl1if pen p sspxif t brg t brg t brg sda asserted low sda sampled low after t brg , set bcl1if 0 0 sda scl bcl1if pen p sspxif t brg t brg t brg assert sda scl goes low before sda goes high, set bcl1if 0 0 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 356 preliminary ? 2016 microchip technology inc. 29.7 baud rate generator the msspx module has a baud rate generator avail- able for clock generation in both i 2 c and spi master modes. the baud rate generator (brg) reload value is placed in the sspxadd register ( register 29-6 ). when a write occurs to sspxbuf, the baud rate generator will automatically begin counting down. once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. an internal signal reload in figure 29-40 triggers the value from sspxadd to be loaded into the brg counter. this occurs twice for each oscillation of the module clock line. the logic dictating when the reload signal is asserted depends on the mode the msspx is being operated in. table 29-4 demonstrates clock rates based on instruction cycles and the brg value loaded into sppxadd. equation 29-1: baud rate generator figure 29-40: baud rate genera tor block diagram f clock f osc sspxadd 1 + ?? 4 ?? ------------------------------------------------- = note: values of 0x00, 0x01 and 0x02 are not valid for sspxadd when used as a baud rate generator for i 2 c. this is an implementation limitation. sspm<3:0> brg down counter sspxclk f osc /2 sspxadd<7:0> sspm<3:0> scl reload control reload downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 357 pic16(l)f18326/18346 table 29-2: mssp clock rate w/brg f osc f cy brg value f clock (2 rollovers of brg) 32 mhz 8 mhz 13h 400 khz 32 mhz 8 mhz 19h 308 khz 32 mhz 8 mhz 4fh 100 khz 16 mhz 4 mhz 09h 400 khz 16 mhz 4 mhz 0ch 308 khz 16 mhz 4 mhz 27h 100 khz 4 mhz 1 mhz 09h 100 khz note: refer to the i/o port electrical specifications in tab l e 3 4- 4 to ensure the system is designed to support i ol requirements. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 358 preliminary ? 2016 microchip technology inc. 29.8 register definitions: mssp control register 29-1: sspxstat: ssp status register r/w-0/0 r/w-0/0 r/hs/hc-0/0 r/hs/hc-0/0 r/hs/hc-0/0 r/hs/hc-0/0 r/hs/hc-0/0 r/hs/hc-0/0 smp cke (1) d/a p (2) s (2) r/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs/hc = hardware set/clear bit 7 smp: spi data input sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high-speed mode (400 khz) bit 6 cke: spi clock edge select bit (spi mode only) (1) in spi master or slave mode: 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state in i 2 c mode only: 1 = enable input logic so that thresholds are compliant with smbus specification 0 = disable smbus specific inputs bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (2) (i 2 c mode only. this bit is cleared when the ms sp module is disabled, sspen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is 0 on reset) 0 = stop bit was not detected last bit 3 s: start bit (2) (i 2 c mode only. this bit is cleared when the ms sp module is disabled, sspen is cleared.) 1 = indicates that a start bit has been detected last (this bit is 0 on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address matc h. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress or-ing this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1 ua: update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sppxadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspxbuf is full 0 = receive not complete, sspxbuf is empty transmit (i 2 c mode only): 1 = data transmit in progress (does not include the ack and stop bits), sppxbuf is full 0 = data transmit complete (does not include the ack and stop bits), sppxbuf is empty note 1: polarity of clock state is set by the ckp bit of the sspcon register. 2: this bit is cleared on reset and when sspen is cleared. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 359 pic16(l)f18326/18346 register 29-2: sspxcon1: ssp control register 1 r/c/hs-0/0 r/c/hs-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 wcol sspov (1) sspen ckp sspm<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hs = bit is set by hardware c = user cleared bit 7 wcol: write collision detect bit (transmit mode only) 1 = the sppxbuf register is written while it is still transmitting the previous word (must be cl eared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit (1) in spi mode: 1 = a new byte is received while the sppxbuf register is still holding the previous data. in case of overflow, the data in sspsr is lost. overflow can only occur in slave mode. in slave mode, the user must read the sppxbuf, even if only transmitting data, to avoi d setting overflow. in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sppxbuf register (must be cleared in software). 0 = no overflow in i 2 c mode: 1 = a byte is received while the sppxbuf register is still holding the previous byte. sspov is a dont care in transmit mode (must be cleared in software). 0 = no overflow bit 5 sspen: synchronous serial port enable bit in both modes, when enabled, the following pins must be properly configured as input or output in spi mode: 1 = enables serial port and configures sck, sdo, sdi and ss as the source of the serial port pins (2) 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins (3) 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode: scl release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in i 2 c master mode: unused in this mode downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 360 preliminary ? 2016 microchip technology inc. bit 3-0 sspm<3:0>: synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1101 = reserved 1100 = reserved 1011 = i 2 c firmware controlled master mode (slave idle) 1010 = spi master mode, clock = f osc /(4 * (sppxadd+1)) (5) 1001 = reserved 1000 = i 2 c master mode, clock = f osc / (4 * (sppxadd+1)) (4) 0111 = i 2 c slave mode, 10-bit address 0110 = i 2 c slave mode, 7-bit address 0101 = spi slave mode, clock = sck pin, ss pin control disabled, ss can be used as i/o pin 0100 = spi slave mode, clock = sck pin, ss pin control enabled 0011 = spi master mode, clock = t2_match/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note 1: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sppxbuf register. 2: when enabled, these pins must be properly configured as input or output. use ssp1sspps, ssp1clkpps, ssp1datpps, and rxypps to select the pins. 3: when enabled, the sda and scl pins must be configured as inputs. use sspxclkpps, sspxdatpps, and rxypps to select the pins. 4: sppxadd values of 0, 1 or 2 are not supported for i 2 c mode. 5: sppxadd value of 0 is not supported. use sspm = 0000 instead. register 29-2: sspxcon1: ssp co ntrol register 1 (continued) downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 361 pic16(l)f18326/18346 register 29-3: sspxcon2: ss px control register 2 (i 2 c mode only) (1) r/w-0/0 r/hs/hc-0 r/w-0/0 r/s/hc-0/0 r/s/hc-0/0 r/s/hc-0/0 r/s/hc-0/0 r/s/hc-0/0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared hc = cleared by hardware s = user set bit 7 gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0x00 or 00h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (in i 2 c mode only) 1 = acknowledge was not received 0 = acknowledge was received bit 5 ackdt: acknowledge data bit (in i 2 c mode only) in receive mode: value transmitted when the user initiates an acknowledge sequence at the end of a receive 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (in i 2 c master mode only) in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (in i 2 c master mode only) sckmssp release control: 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enable bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable/stretch enable bit in master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sppxbuf may not be written (or writes to the sppxbuf are disabled). downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 362 preliminary ? 2016 microchip technology inc. register 29-4: sspxcon3: ssp control register 3 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 acktim (3) pcie scie boen sdaht sbcde ahen dhen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 acktim: acknowledge time status bit (i 2 c mode only) (3) 1 = indicates the i 2 c bus is in an acknowledge sequence, set on eighth falling edge of scl clock 0 = not an acknowledge sequence, cleared on ninth rising edge of scl clock bit 6 pcie : stop condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of stop condition 0 = stop detection interrupts are disabled (2) bit 5 scie : start condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of start or restart conditions 0 = start detection interrupts are disabled (2) bit 4 boen: buffer overwrite enable bit in spi slave mode: (1) 1 = sppxbuf updates every time that a new data byte is shifted in ignoring the bf bit 0 = if new byte is received with bf bit of the sspstat register already set, sspov bit of the sspcon1 register is set, and the buffer is not updated in i 2 c master mode and spi master mode: this bit is ignored. in i 2 c slave mode: 1 = sppxbuf is updated and ack is generated for a received address/data byte, ignoring the state of the sspov bit only if the bf bit = 0 . 0 = sppxbuf is only updated when sspov is clear bit 3 sdaht: sda hold time selection bit (i 2 c mode only) 1 = minimum of 300 ns hold time on sda after the falling edge of scl 0 = minimum of 100 ns hold time on sda after the falling edge of scl bit 2 sbcde: slave mode bus collision detect enable bit (i 2 c slave mode only) if, on the rising edge of scl, sda is sampled low when the module is outputting a high state, the bcl1if bit of the pir1 register is set, and bus goes idle 1 = enable slave bus collision interrupts 0 = slave bus collision interrupts are disabled bit 1 ahen: address hold enable bit (i 2 c slave mode only) 1 = following the eighth falling edge of scl for a matching received address byte; ckp bit of the sspcon1 register will be cleared and the scl will be held low. 0 = address holding is disabled bit 0 dhen: data hold enable bit (i 2 c slave mode only) 1 = following the eighth falling edge of scl for a received data byte; slave hardware clears the c kp bit of the sspcon1 register and scl is held low. 0 = data holding is disabled note 1: for daisy-chained spi operation; allows the user to ignore all but the last received byte. sspov is still set when a new byte is received and bf = 1 , but hardware continues to write the most recent byte to sppxbuf. 2: this bit has no effect in slave modes that start and stop condition detection is explicitly listed as enabled. 3: the acktim status bit is only active when the ahen bit or dhen bit is set. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 363 pic16(l)f18326/18346 register 29-5: sspxmsk: ssp mask register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 sspxmsk<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-1 sspxmsk<7:1>: mask bits 1 = the received address bit n is compared to sppxadd pic16(l)f18326/18346 ds40001839a-page 364 preliminary ? 2016 microchip technology inc. register 29-7: sspxbuf: mssp buffer register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u sspxbuf<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 sspxbuf<7:0>: mssp buffer bits table 29-3: summary of registers associated with msspx name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page trisa D D trisa5 trisa4 D (3) trisa2 trisa1 trisa0 141 ansela D D ansa5 ansa4 D ansa2 ansa1 ansa0 142 inlvla (1) D D inlvla5 inlvla4 inlvla3 inlvla2 inlvla1 inlvla0 144 trisb (2) trisb7 trisb6 trisb5 trisb4 D D D D 147 anselb (2) ansb7 ansb6 ansb5 ansb4 D D D D 148 inlvlb (2) inlvlb7 inlvlb6 inlvlb5 inlvlb4 D D D D 150 trisc trisc7 (2) trisc6 (2) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 anselc ansc7 (2) ansc6 (2) ansc5 ansc4 ansc3 ansc2 ansc1 ansc0 155 inlvlc (1) inlvlc7 (2) inlvlc6 (2) inlvlc5 inlvlc4 inlvlc3 inlvlc2 inlvlc1 inlvlc0 157 intcon gie peie D D D D D intedg 98 pir1 tmr1gif adif rcif txif ssp1if bcl1if tmr2if tmr1if 105 pie1 tmr1gie adie rcie txie ssp1ie bcl1ie tmr2ie tmr1ie 100 pir2 tmr6if c2if c1if nvmif ssp2if bcl2if tmr4if nco1if 106 pie2 tmr6ie c2ie c1ie nvmie ssp2ie bcl2ie tmr4ie nco1ie 101 sspxstat smp cke d/a psr / w ua bf 358 sspxcon1 wcol sspov sspen ckp sspm<3:0> 359 sspxcon2 gcen ackstat ackdt acken rcen pen rsen sen 361 sspxcon3 acktim pcie scie boen sdaht sbcde ahen dhen 362 sspxmsk sspxmsk<7:0> 363 sspxadd sspxadd<7:0> 363 sspxbuf sspxbuf<7:0> 364 sspxclkpps D D D sspxclkpps<4:0> 160 sspxdatpps D D D sspxdatpps<4:0> 160 sspxsspps D D D sspxsspps<4:0> 160 rxypps D D D rxypps<4:0> 161 legend: = unimplemented location, read as 0 . shaded cells are not used by the mssp module note 1: when using designated i 2 c pins, the associated pin values in inlvlx will be ignored. 2: pic16(l)f18346 only. 3: unimplemented, read as 1 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 365 pic16(l)f18326/18346 30.0 enhanced universal synchronous asynchronous receiver transmitter (eusart1) the enhanced universal synchronous asynchronous receiver transmitter (eusart1) module is a serial i/o communications peripheral. it contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. the eusart1, also known as a serial communications interface (sci), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. full-duplex mode is useful for communications with peripheral systems, such as crt terminals and personal computers. half-duplex synchronous mode is intended for communications with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms or other microcontrollers. these devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. the eusart1 module includes the following capabilities: full-duplex asynchronous transmit and receive two-character input buffer one-character output buffer programmable 8-bit or 9-bit character length address detection in 9-bit mode input buffer overrun error detection received character framing error detection half-duplex synchronous master half-duplex synchronous slave programmable clock polarity in synchronous modes sleep operation the eusart1 module implements the following additional features, making it ideally suited for use in local interconnect network (lin) bus systems: automatic detection and calibration of the baud rate wake-up on break reception 13-bit break character transmit block diagrams of the eusart1 transmitter and receiver are shown in figure 30-1 and figure 30-2 . the eusart1 transmit output (tx_out) is available to the tx/ck pin and internally to the following peripherals: configurable logic cell (clc) figure 30-1: eusart1 transmit block diagram txif txie interrupt txen tx9d msb lsb data bus tx1reg register transmit shift register (tsr) (8) 0 tx9 trmt tx/ck pin pin buffer and control 8 sp1brgl sp1brgh brg16 f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator tx_out downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 366 preliminary ? 2016 microchip technology inc. figure 30-2: eusart1 receive block diagram the operation of the eusart1 module is controlled through three registers: transmit status and control (tx1sta) receive status and control (rc1sta) baud rate control (baud1con) these registers are detailed in register 30-1 , register 30-2 and register 30-3 , respectively. the rx and ck input pins are selected with the rxpps and ckpps registers, respectively. tx, ck, and dt output pins are selected with each pins rxypps register. since the rx input is coupled with the dt output in synchronous mode, it is the users responsibility to select the same pin for both of these functions when operating in synchronous mode. the eusart1 control logic will control the data direction drivers automatically. rx/dt pin pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rc1reg register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9 sp1brgl sp1brgh brg16 rcidl f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 367 pic16(l)f18326/18346 30.1 eusart1 asynchronous mode the eusart1 transmits and receives data using the standard non-return-to-zero (nrz) format. nrz is implemented with two levels: a v oh mark state which represents a 1 data bit, and a v ol space state which represents a 0 data bit. nrz refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. an nrz transmission port idles in the mark state. each character transmission consists of one start bit followed by eight or nine data bits and is always terminated by one or more stop bits. the start bit is always a space and the stop bits are always marks. the most common data format is eight bits. each transmitted bit persists for a period of 1/(baud rate). an on-chip dedicated 8-bit/16-bit baud rate generator is used to derive standard baud rate frequencies from the system oscillator. see tab l e 3 0- 3 for examples of baud rate configurations. the eusart1 transmits and receives the lsb first. the eusart1s transmitter and receiver are function- ally independent, but share the same data format and baud rate. parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 30.1.1 eusart1 asynchronous transmitter the eusart1 transmitter block diagram is shown in figure 30-1 . the heart of the transmitter is the serial transmit shift register (tsr), which is not directly accessible by software. the tsr obtains its data from the transmit buffer, which is the tx1reg register. 30.1.1.1 enabling the transmitter the eusart1 transmitter is enabled for asynchronous operations by configuring the following three control bits: txen = 1 sync = 0 spen = 1 all other eusart1 control bits are assumed to be in their default state. setting the txen bit of the tx1sta register enables the transmitter circuitry of the eusart1. clearing the sync bit of the tx1sta register configures the eusart1 for asynchronous operation. setting the spen bit of the rc1sta register enables the eusart1 and automatically configures the tx/ck i/o pin as an output. if the tx/ck pin is shared with an analog peripheral, the analog i/o function must be disabled by clearing the corresponding ansel bit. 30.1.1.2 transmitting data a transmission is initiated by writing a character to the tx1reg register. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the tx1reg is immediately transferred to the tsr register. if the tsr still contains all or part of a previous character, the new character data is held in the tx1reg until the stop bit of the previous character has been transmitted. the pending character in the tx1reg is then transferred to the tsr in one t cy immediately following the stop bit transmission. the transmission of the start bit, data bits and stop bit sequence commences immediately following the transfer of the data to the tsr from the tx1reg. 30.1.1.3 transmit data polarity the polarity of the transmit data can be controlled with the sckp bit of the baud1con register. the default state of this bit is 0 which selects high true transmit idle and data bits. setting the sckp bit to 1 will invert the transmit data resulting in low true idle and data bits. the sckp bit controls transmit data polarity in asynchronous mode only. in synchronous mode, the sckp bit has a different function. see section 30.4.1.2 ?clock polarity? . 30.1.1.4 transmit interrupt flag the txif interrupt flag bit of the pir1 register is set whenever the eusart1 transmitter is enabled and no character is being held for transmission in the tx1reg. in other words, the txif bit is only clear when the tsr is busy with a character and a new character has been queued for transmission in the tx1reg. the txif flag bit is not cleared immediately upon writing tx1reg. txif becomes valid in the second instruction cycle following the write execution. polling txif immediately following the tx1reg write will return invalid results. the txif bit is read-only, it cannot be set or cleared by software. the txif interrupt can be enabled by setting the txie interrupt enable bit of the pie1 register. however, the txif flag bit will be set whenever the tx1reg is empty, regardless of the state of txie enable bit. to use interrupts when transmitting data, set the txie bit only when there is more data to send. clear the txie interrupt enable bit upon writing the last character of the transmission to the tx1reg. note: the txif transmitter interrupt flag is set when the txen enable bit is set. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 368 preliminary ? 2016 microchip technology inc. 30.1.1.5 tsr status the trmt bit of the tx1sta register indicates the status of the tsr register. this is a read-only bit. the trmt bit is set when the tsr register is empty and is cleared when a character is transferred to the tsr register from the tx1reg. the trmt bit remains clear until all bits have been shifted out of the tsr register. no interrupt logic is tied to this bit, so the user has to poll this bit to determine the tsr status. 30.1.1.6 transmitting 9-bit characters the eusart1 supports 9-bit character transmissions. when the tx9 bit of the tx1sta register is set, the eusart1 will shift nine bits out for each character transmitted. the tx9d bit of the tx1sta register is the ninth, and most significant data bit. when transmitting 9-bit data, the tx9d data bit must be written before writing the eight least significant bits into the tx1reg. all nine bits of data will be transferred to the tsr shift register immediately after the tx1reg is written. a special 9-bit address mode is available for use with multiple receivers. see section 30.1.2.7 ?address detection? for more information on the address mode. 30.1.1.7 asynchronous transmission setup 1. initialize the sp1brgh, sp1brgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 30.3 ?eusart1 baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if 9-bit transmission is desired, set the tx9 control bit. a set ninth data bit will indicate that the eight least significant data bits are an address when the receiver is set for address detection. 4. set sckp bit if inverted transmit is desired. 5. enable the transmission by setting the txen control bit. this will cause the txif interrupt bit to be set. 6. if interrupts are desired, set the txie interrupt enable bit of the pie1 register. an interrupt will occur immediately provided that the gie and peie bits of the intcon register are also set. 7. if 9-bit transmission is selected, the ninth bit should be loaded into the tx9d data bit. 8. load 8-bit data into the tx1reg register. this will start the transmission. figure 30-3: asynchronous transmission note: the tsr register is not mapped in data memory, so it is not available to the user. word 1 stop bit word 1 transmit shift reg. start bit bit 0 bit 1 bit 7/8 write to tx1reg word 1 brg output (shift clock) tx/ck txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy pin downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 369 pic16(l)f18326/18346 figure 30-4: asynchronous transmiss ion (back-to-back) 30.1.2 eusart1 asynchronous receiver the asynchronous mode is typically used in rs-232 systems. the receiver block diagram is shown in figure 30-2 . the data is received on the rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial receive shift register (rsr) operates at the bit rate. when all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character first-in-first-out (fifo) memory. the fifo buffering allows reception of two complete characters and the start of a third character before software must start servicing the eusart1 receiver. the fifo and rsr registers are not directly accessible by software. access to the received data is via the rc1reg register. 30.1.2.1 enabling the receiver the eusart1 receiver is enabled for asynchronous operation by configuring the following three control bits: cren = 1 sync = 0 spen = 1 all other eusart1 control bits are assumed to be in their default state. setting the cren bit of the rc1sta register enables the receiver circuitry of the eusart1. clearing the sync bit of the tx1sta register configures the eusart1 for asynchronous operation. setting the spen bit of the rc1sta register enables the eusart1. the programmer must set the corresponding tris bit to configure the rx/dt i/o pin as an input. 30.1.2.2 receiving data the receiver data recovery circuit initiates character reception on the falling edge of the first bit. the first bit, also known as the start bit, is always a zero. the data recovery circuit counts one-half bit time to the center of the start bit and verifies that the bit is still a zero. if it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the start bit. if the start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. the bit is then sampled by a majority detect circuit and the resulting 0 or 1 is shifted into the rsr. this repeats until all data bits have been sampled and shifted into the rsr. one final bit time is measured and the level sampled. this is the stop bit, which is always a 1 . if the data recovery circuit samples a 0 in the stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. see section 30.1.2.4 ?receive framing error? for more information on framing errors. immediately after all data bits and the stop bit have been received, the character in the rsr is transferred to the eusart1 receive fifo and the rcif interrupt flag bit of the pir1 register is set. the top character in the fifo is transferred out of the fifo by reading the rc1reg register. transmit shift reg. write to tx1reg spr1brg output (shift clock) tx/ck trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy pin txif bit (transmit buffer reg. empty flag) note: if the rx/dt function is on an analog pin, the corresponding ansel bit must be cleared for the receiver to function. note: if the receive fifo is overrun, no additional characters will be received until the overrun condition is cleared. see section 30.1.2.5 ?receive overrun error? for more information on overrun errors. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 370 preliminary ? 2016 microchip technology inc. 30.1.2.3 receive interrupts the rcif interrupt flag bit of the pir1 register is set whenever the eusart1 receiver is enabled and there is an unread character in the receive fifo. the rcif interrupt flag bit is read-only, it cannot be set or cleared by software. rcif interrupts are enabled by setting all of the following bits: rcie, interrupt enable bit of the pie1 register peie, peripheral interrupt enable bit of the intcon register gie, global interrupt enable bit of the intcon register the rcif interrupt flag bit will be set when there is an unread character in the fifo, regardless of the state of interrupt enable bits. 30.1.2.4 receive framing error each character in the receive fifo buffer has a corresponding framing error status bit. a framing error indicates that a stop bit was not seen at the expected time. the framing error status is accessed via the ferr bit of the rc1sta register. the ferr bit represents the status of the top unread character in the receive fifo. therefore, the ferr bit must be read before reading the rc1reg. the ferr bit is read-only and only applies to the top unread character in the receive fifo. a framing error (ferr = 1 ) does not preclude reception of additional characters. it is not necessary to clear the ferr bit. reading the next character from the fifo buffer will advance the fifo to the next character and the next corresponding framing error. the ferr bit can be forced clear by clearing the spen bit of the rc1sta register which resets the eusart1. clearing the cren bit of the rc1sta register does not affect the ferr bit. a framing error by itself does not generate an interrupt. 30.1.2.5 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before the fifo is accessed. when this happens the oerr bit of the rc1sta register is set. the characters already in the fifo buffer can be read but no additional characters will be received until the error is cleared. the error must be cleared by either clearing the cren bit of the rc1sta register or by resetting the eusart1 by clearing the spen bit of the rc1sta register. 30.1.2.6 receiving 9-bit characters the eusart1 supports 9-bit character reception. when the rx9 bit of the rc1sta register is set the eusart1 will shift nine bits into the rsr for each character received. the rx9d bit of the rc1sta reg- ister is the ninth and most significant data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the eight least signifi- cant bits from the rc1reg. 30.1.2.7 address detection a special address detection mode is available for use when multiple receivers share the same transmission line, such as in rs-485 systems. address detection is enabled by setting the adden bit of the rc1sta register. address detection requires 9-bit character reception. when address detection is enabled, only characters with the ninth data bit set will be transferred to the receive fifo buffer, thereby setting the rcif interrupt bit. all other characters will be ignored. upon receiving an address character, user software determines if the address matches its own. upon address match, user software must disable address detection by clearing the adden bit before the next stop bit occurs. when user software detects the end of the message, determined by the message protocol used, software places the receiver back into the address detection mode by setting the adden bit. note: if all receive characters in the receive fifo have framing errors, repeated reads of the rc1reg will not clear the ferr bit. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 371 pic16(l)f18326/18346 30.1.2.8 asynchronous reception setup 1. initialize the sp1brgh, sp1brgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 30.3 ?eusart1 baud rate generator (brg)? ). 2. clear the ansel bit for the rx pin (if applicable). 3. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 5. if 9-bit reception is desired, set the rx9 bit. 6. enable reception by setting the cren bit. 7. the rcif interrupt flag bit will be set when a character is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 8. read the rc1sta register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. get the received eight least significant data bits from the receive buffer by reading the rc1reg register. 10. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 30.1.2.9 9-bit address detection mode setup this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the sp1brgh, sp1brgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 30.3 ?eusart1 baud rate generator (brg)? ). 2. clear the ansel bit for the rx pin (if applicable). 3. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 5. enable 9-bit reception by setting the rx9 bit. 6. enable address detection by setting the adden bit. 7. enable reception by setting the cren bit. 8. the rcif interrupt flag bit will be set when a character with the ninth bit set is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 9. read the rc1sta register to get the error flags. the ninth data bit will always be set. 10. get the received eight least significant data bits from the receive buffer by reading the rc1reg register. software determines if this is the devices address. 11. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 12. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and generate interrupts. figure 30-5: asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx/dt pin reg rcv buffer reg. rcv shift read rcv buffer reg. rc1reg rcif (interrupt flag) oerr bit cren word 1 rc1reg word 2 rc1reg stop bit note: this timing diagram shows three words appearing on the rx input. the rc1reg (receive bu ffer) is read after the third word, causing the oerr (overrun) bit to be set. rcidl downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 372 preliminary ? 2016 microchip technology inc. 30.2 clock accuracy with asynchronous operation the factory calibrates the internal oscillator block output (intosc). however, the intosc frequency may drift as v dd or temperature changes, and this directly affects the asynchronous baud rate. two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. the first (preferred) method uses the osctune register to adjust the intosc output. adjusting the value in the osctune register allows for fine resolution changes to the system clock source. see section 6.2.2.3 ?internal oscillator frequency adjustment? for more information. the other method adjusts the value in the baud rate generator. this can be done automatically with the auto-baud detect feature (see section 30.3.1 ?auto-baud detect? ). there may not be fine enough resolution when adjusting the baud rate generator to compensate for a gradual change in the peripheral clock frequency. 30.3 eusart1 baud rate generator (brg) the baud rate generator (brg) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous eusart1 operation. by default, the brg operates in 8-bit mode. setting the brg16 bit of the baud1con register selects 16-bit mode. the sp1brgh, sp1brgl register pair determines the period of the free running baud rate timer. in asynchronous mode the multiplier of the baud rate period is determined by both the brgh bit of the tx1sta register and the brg16 bit of the baud1con register. in synchronous mode, the brgh bit is ignored. table 30-1 contains the formulas for determining the baud rate. example 30-1 provides a sample calculation for determining the baud rate and baud rate error. typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in table 30-3 . it may be advantageous to use the high baud rate (brgh = 1 ), or the 16-bit brg (brg16 = 1 ) to reduce the baud rate error. the 16-bit brg mode is used to achieve slow baud rates for fast oscillator frequencies. writing a new value to the sp1brgh, sp1brgl reg- ister pair causes the brg timer to be reset (or cleared). this ensures that the brg does not wait for a timer overflow before outputting the new baud rate. if the system clock is changed during an active receive operation, a receive error or data loss may result. to avoid this problem, check the status of the rcidl bit to make sure that the receive operation is idle before changing the system clock. example 30-1: calculating baud rate error for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit spr1brg: solving for sp1brgh:sp1brgl: x f osc desired baud rate --------------------------------------------- 64 --------------------------------------------- 1 ? = desired baud rate f osc 64 [spbrgh:spbrgl] 1 + ?? ----------------------------------------------------------------------- - = 16000000 9600 ----------------------- - 64 ----------------------- -1 ? = 25.042 ?? 25 == calculated baud rate 16000000 64 25 1+ ?? -------------------------- - = 9615 = error calc. baud rate desired baud rate ? desired baud rate -------------------------------------------------------------------------------------------- = 9615 9600 ? ?? 9600 ---------------------------------- 0 . 1 6 % == downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 373 pic16(l)f18326/18346 30.3.1 a uto-baud detect the eusart1 module supports automatic detection and calibration of the baud rate. in the auto-baud detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rx signal, the rx signal is timing the brg. the baud rate generator is used to time the period of a received 55h (ascii u) which is the sync character for the lin bus. the unique feature of this character is that it has five rising edges including the stop bit edge. setting the abden bit of the baud1con register starts the auto-baud calibration sequence. while the abd sequence takes place, the eusart1 state machine is held in idle. on the first rising edge of the receive line, after the start bit, the spbrg begins counting up using the brg counter clock as shown in figure 30-6 . the fifth rising edge will occur on the rx pin at the end of the eighth bit period. at that time, an accumulated value totaling the proper brg period is left in the sp1brgh, sp1brgl register pair, the abden bit is automatically cleared and the rcif interrupt flag is set. the value in the rc1reg needs to be read to clear the rcif interrupt. rc1reg content should be discarded. when calibrating for modes that do not use the sp1brgh register the user can verify that the sp1brgl register did not overflow by checking for 00h in the sp1brgh register. the brg auto-baud clock is determined by the brg16 and brgh bits as shown in tab le 3 0- 1 . during abd, both the sp1brgh and sp1brgl registers are used as a 16-bit counter, independent of the brg16 bit set- ting. while calibrating the baud rate period, the sp1brgh and sp1brgl registers are clocked at 1/8th the brg base clock rate. the resulting byte mea- surement is the average bit time when clocked at full speed. figure 30-6: automatic baud rate calibration note 1: if the wue bit is set with the abden bit, auto-baud detection will occur on the byte following the break character (see section 30.3.3 ?auto-wake-up on break? ). 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart1 baud rates are not possible. 3: during the auto-baud process, the auto-baud counter starts counting at one. upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the sp1brgh:sp1brgl register pair. table 30-1: brg counter clock rates brg16 brgh brg base clock brg abd clock 00 f osc /64 f osc /512 01 f osc /16 f osc /128 10 f osc /16 f osc /128 11 f osc /4 f osc /32 note: during the abd sequence, sp1brgl and sp1brgh registers are both used as a 16-bit counter, independent of the brg16 setting. spr1brg value rx pin abden bit rcif bit bit 0 bit 1 (interrupt) read rc1reg spr1brg clock start auto cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 stop bit edge #5 001ch note 1: the abd sequence requires the eusart1 module to be configured in asynchronous mode. sp1brgl xxh 1ch sp1brgh xxh 00h rcidl downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 374 preliminary ? 2016 microchip technology inc. 30.3.2 auto-baud overflow during the course of automatic-baud detection, the abdovf bit of the baudxcon register will be set if the baud rate counter overflows before the fifth rising edge is detected on the rx pin. the abdovf bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the spxbrgh:spxbrgl register pair. the overflow condition will set the rcif flag. the counter continues to count until the fifth rising edge is detected on the rx pin. the rcidl bit will remain false ( 0 ) until the fifth rising edge at which time the rcidl bit will be set. if the rcreg is read after the overflow occurs but before the fifth rising edge, then the fifth rising edge will set the rcif again. terminating the auto-baud process early to clear an overflow condition will prevent proper detection of the sync character fifth rising edge. if any falling edges of the sync character have not yet occurred when the abden bit is cleared, then those will be falsely detected as start bits. the following steps are recommended to clear the overflow condition: 1. read rcreg to clear rcif 2. if rcidl is zero, then wait for rcif and repeat step 1 3. clear the abdovf bit 30.3.3 auto-wake-up on break during sleep mode, all clocks to the eusart1 are suspended. because of this, the baud rate generator is inactive and a proper character reception cannot be performed. the auto-wake-up feature allows the controller to wake-up due to activity on the rx/dt line. this feature is available only in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit of the baud1con register. once set, the normal receive sequence on rx/dt is disabled, and the eusart1 remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event consists of a high-to-low transition on the rx/dt line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) the eusart1 module generates an rcif interrupt coincident with the wake-up event. the interrupt is generated synchronously to the q clocks in normal cpu operating modes ( figure 30-7 ), and asynchronously if the device is in sleep mode ( figure 30-8 ). the interrupt condition is cleared by reading the rc1reg register. the wue bit is automatically cleared by the low-to-high transition on the rx line at the end of the break. this signals to the user that the break event is over. at this point, the eusart1 module is in idle mode waiting to receive the next character. 30.3.3.1 special considerations break character to avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. when the wake-up is enabled the function works independent of the low time on the data stream. if the wue bit is set and a valid non-zero character is received, the low time from the start bit to the first rising edge will be interpreted as the wake-up event. the remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. therefore, the initial character in the transmission must be all 0 s. this must be ten or more bit times, 13-bit times recommended for lin bus, or any number of bit times for standard rs-232 devices. oscillator start-up time oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., lp, xt or hs/pll mode). the sync break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the eusart1. wue bit the wake-up event causes a receive interrupt by setting the rcif bit. the wue bit is cleared in hardware by a rising edge on rx/dt. the interrupt condition is then cleared in software by reading the rc1reg register and discarding its contents. to ensure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process before setting the wue bit. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 375 pic16(l)f18326/18346 figure 30-7: auto-wake-up bit (wue) timing during normal operation figure 30-8: auto-wake-up bit (wue) timings during sleep 30.3.4 break character sequence the eusart1 module has the capability of sending the special break character sequences that are required by the lin bus standard. a break character consists of a start bit, followed by 12 0 bits and a stop bit. to send a break character, set the sendb and txen bits of the tx1sta register. the break character trans- mission is then initiated by a write to the tx1reg. the value of data written to tx1reg will be ignored and all 0 s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). the trmt bit of the tx1sta register indicates when the transmit operation is active or idle, just as it does during normal transmission. see figure 30-9 for the timing of the break character sequence. 30.3.4.1 break and sync transmit sequence the following sequence will start a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart1 for the desired mode. 2. set the txen and sendb bits to enable the break sequence. 3. load the tx1reg with a dummy character to initiate transmission (the value is ignored). 4. write 55h to tx1reg to load the sync charac- ter into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware and the sync character is then transmitted. when the tx1reg becomes empty, as indicated by the txif, the next data byte can be written to tx1reg. q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rc1reg note 1: the eusart1 remains in idle while the wue bit is set. q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rc1reg sleep command executed note 1 note 1: if the wake-up event requires long oscillator warm-up time, the automatic clearin g of the wue bit can occur while the stposc signal is still active. this sequence should not depend on the presence of q clocks. 2: the eusart1 remains in idle while the wue bit is set. sleep ends downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 376 preliminary ? 2016 microchip technology inc. 30.3.5 receiving a break character the enhanced eusart1 module can receive a break character in two ways. the first method to detect a break character uses the ferr bit of the rc1sta register and the received data as indicated by rc1reg. the baud rate generator is assumed to have been initialized to the expected baud rate. a break character has been received when: rcif bit is set ferr bit is set rc1reg = 00h the second method uses the auto-wake-up feature described in section 30.3.3 ?auto-wake-up on break? . by enabling this feature, the eusart1 will sample the next two transitions on rx/dt, cause an rcif interrupt, and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud detect feature. for both methods, the user can set the abden bit of the baud1con register before placing the eusart1 in sleep mode. figure 30-9: send break character sequence write to tx1reg dummy write spr1brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break txif bit (transmit interrupt flag) tx (pin) trmt bit (transmit shift empty flag) sendb (send break control bit) sendb sampled here auto cleared downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 377 pic16(l)f18326/18346 30.4 eusart1 synchronous mode synchronous serial communications are typically used in systems with a single master and one or more slaves. the master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. there are two signal lines in synchronous mode: a bidirectional data line and a clock line. slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and trans- mit shift registers. since the data line is bidirectional, synchronous operation is half-duplex only. half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. the eusart1 can operate as either a master or slave device. start and stop bits are not used in synchronous transmissions. 30.4.1 synchronous master mode the following bits are used to configure the eusart1 for synchronous master operation: sync = 1 csrc = 1 sren = 0 (for transmit); sren = 1 (for receive) cren = 0 (for transmit); cren = 1 (for receive) spen = 1 setting the sync bit of the tx1sta register configures the device for synchronous operation. setting the csrc bit of the tx1sta register configures the device as a master. clearing the sren and cren bits of the rc1sta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rc1sta register enables the eusart1. 30.4.1.1 master clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device config- ured as a master transmits the clock on the tx/ck line. the tx/ck pin output driver is automatically enabled when the eusart1 is configured for synchronous transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one clock cycle is gener- ated for each data bit. only as many clock cycles are generated as there are data bits. 30.4.1.2 clock polarity a clock polarity option is provided for microwire compatibility. clock polarity is selected with the sckp bit of the baud1con register. setting the sckp bit sets the clock idle state as high. when the sckp bit is set, the data changes on the falling edge of each clock. clearing the sckp bit sets the idle state as low. when the sckp bit is cleared, the data changes on the rising edge of each clock. 30.4.1.3 synchronous master transmission data is transferred out of the device on the rx/dt pin. the rx/dt and tx/ck pin output drivers are automat- ically enabled when the eusart1 is configured for synchronous master transmit operation. a transmission is initiated by writing a character to the tx1reg register. if the tsr still contains all or part of a previous character the new character data is held in the tx1reg until the last bit of the previous character has been transmitted. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the tx1reg is immediately trans- ferred to the tsr. the transmission of the character commences immediately following the transfer of the data to the tsr from the tx1reg. each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. 30.4.1.4 synchronous master transmission setup 1. initialize the sp1brgh, sp1brgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 30.3 ?eusart1 baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. disable receive mode by clearing bits sren and cren. 4. enable transmit mode by setting the txen bit. 5. if 9-bit transmission is desired, set the tx9 bit. 6. if interrupts are desired, set the txie bit of the pie1 register and the gie and peie bits of the intcon register. 7. if 9-bit transmission is selected, the ninth bit should be loaded in the tx9d bit. 8. start transmission by loading data to the tx1reg register. note: the tsr register is not mapped in data memory, so it is not available to the user. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 378 preliminary ? 2016 microchip technology inc. figure 30-10: synchronous transmission figure 30-11: synchronous transmissi on (through txen) 30.4.1.5 synchronous master reception data is received at the rx/dt pin. the rx/dt pin output driver is automatically disabled when the eusart1 is configured for synchronous master receive operation. in synchronous mode, reception is enabled by setting either the single receive enable bit (sren of the rc1sta register) or the continuous receive enable bit (cren of the rc1sta register). when sren is set and cren is clear, only as many clock cycles are generated as there are data bits in a single character. the sren bit is automatically cleared at the completion of one character. when cren is set, clocks are continuously generated until cren is cleared. if cren is cleared in the middle of a character the ck clock stops immediately and the partial charac- ter is discarded. if sren and cren are both set, then sren is cleared at the completion of the first character and cren takes precedence. to initiate reception, set either sren or cren. data is sampled at the rx/dt pin on the trailing edge of the tx/ck clock pin and is shifted into the receive shift register (rsr). when a complete character is received into the rsr, the rcif bit is set and the char- acter is automatically transferred to the two character receive fifo. the least significant eight bits of the top character in the receive fifo are available in rc1reg. the rcif bit remains set as long as there are unread characters in the receive fifo. bit 0 bit 1 bit 7 word 1 bit 2 bit 0 bit 1 bit 7 rx/dt write to tx1reg reg txif bit (interrupt flag) txen bit 1 1 word 2 trmt bit write word 1 write word 2 note: sync master mode, sp1brgl = 0 , continuous transmission of two 8-bit words. pin tx/ck pin tx/ck pin (sckp = 0 ) (sckp = 1 ) rx/dt pin tx/ck pin write to tx1reg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit note: if the rx/dt function is on an analog pin, the corresponding ansel bit must be cleared for the receiver to function. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 379 pic16(l)f18326/18346 30.4.1.6 slave clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device configured as a slave receives the clock on the tx/ck line. the tx/ck pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one data bit is transferred for each clock cycle. only as many clock cycles should be received as there are data bits. 30.4.1.7 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before rc1reg is read to access the fifo. when this happens the oerr bit of the rc1sta register is set. previous data in the fifo will not be overwritten. the two characters in the fifo buffer can be read, however, no additional characters will be received until the error is cleared. the oerr bit can only be cleared by clearing the overrun condition. if the overrun error occurred when the sren bit is set and cren is clear then the error is cleared by reading rc1reg. if the overrun occurred when the cren bit is set then the error condition is cleared by either clearing the cren bit of the rc1sta register or by clearing the spen bit which resets the eusart1. 30.4.1.8 receiving 9-bit characters the eusart1 supports 9-bit character reception. when the rx9 bit of the rc1sta register is set the eusart1 will shift nine bits into the rsr for each character received. the rx9d bit of the rc1sta register is the ninth, and most significant, data bit of the top unread character in the receive fifo. when read- ing 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the eight least significant bits from the rc1reg. 30.4.1.9 synchronous master reception setup 1. initialize the sp1brgh, sp1brgl register pair for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. clear the ansel bit for the rx pin (if applicable). 3. enable the synchronous master serial port by setting bits sync, spen and csrc. 4. ensure bits cren and sren are clear. 5. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 6. if 9-bit reception is desired, set bit rx9. 7. start reception by setting the sren bit or for continuous reception, set the cren bit. 8. interrupt flag bit rcif will be set when reception of a character is complete. an interrupt will be generated if the enable bit rcie was set. 9. read the rc1sta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. read the 8-bit received data by reading the rc1reg register. 11. if an overrun error occurs, clear the error by either clearing the cren bit of the rc1sta register or by clearing the spen bit which resets the eusart1. figure 30-12: synchronous reception (master mode, sren) note: if the device is configured as a slave and the tx/ck function is on an analog pin, the corresponding ansel bit must be cleared. cren bit rx/dt write to bit sren sren bit rcif bit (interrupt) read rc1reg 0 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . tx/ck pin tx/ck pin pin (sckp = 0 ) (sckp = 1 ) downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 380 preliminary ? 2016 microchip technology inc. 30.4.2 synchronous slave mode the following bits are used to configure the eusart1 for synchronous slave operation: sync = 1 csrc = 0 sren = 0 (for transmit); sren = 1 (for receive) cren = 0 (for transmit); cren = 1 (for receive) spen = 1 setting the sync bit of the tx1sta register configures the device for synchronous operation. clearing the csrc bit of the tx1sta register configures the device as a slave. clearing the sren and cren bits of the rc1sta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rc1sta register enables the eusart1. 30.4.2.1 eusart1 synchronous slave transmit the operation of the synchronous master and slave modes are identical (see section 30.4.1.3 ?synchronous master transmission? ) , except in the case of the sleep mode. if two words are written to the tx1reg and then the sleep instruction is executed, the following will occur: 1. the first character will immediately transfer to the tsr register and transmit. 2. the second word will remain in the tx1reg register. 3. the txif bit will not be set. 4. after the first character has been shifted out of tsr, the tx1reg register will transfer the second character to the tsr and the txif bit will now be set. 5. if the peie and txie bits are set, the interrupt will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will call the interrupt service routine. 30.4.2.2 synchronous slave transmission setup 1. set the sync and spen bits and clear the csrc bit. 2. clear the ansel bit for the ck pin (if applicable). 3. clear the cren and sren bits. 4. if interrupts are desired, set the txie bit of the pie1 register and the gie and peie bits of the intcon register. 5. if 9-bit transmission is desired, set the tx9 bit. 6. enable transmission by setting the txen bit. 7. if 9-bit transmission is selected, insert the most significant bit into the tx9d bit. 8. start transmission by writing the least significant eight bits to the tx1reg register. 30.4.2.3 eusart1 synchronous slave reception the operation of the synchronous master and slave modes is identical ( section 30.4.1.5 ?synchronous master reception? ), with the following exceptions: sleep cren bit is always set, therefore the receiver is never idle sren bit, which is a dont care in slave mode a character may be received while in sleep mode by setting the cren bit prior to entering sleep. once the word is received, the rsr register will transfer the data to the rc1reg register. if the rcie enable bit is set, the interrupt generated will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will branch to the interrupt vector. 30.4.2.4 synchronous slave reception setup 1. set the sync and spen bits and clear the csrc bit. 2. clear the ansel bit for both the ck and dt pins (if applicable). 3. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 4. if 9-bit reception is desired, set the rx9 bit. 5. set the cren bit to enable reception. 6. the rcif bit will be set when reception is complete. an interrupt will be generated if the rcie bit was set. 7. if 9-bit mode is enabled, retrieve the most significant bit from the rx9d bit of the rc1sta register. 8. retrieve the eight least significant bits from the receive fifo by reading the rc1reg register. 9. if an overrun error occurs, clear the error by either clearing the cren bit of the rc1sta register or by clearing the spen bit which resets the eusart1. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 381 pic16(l)f18326/18346 30.5 eusart1 operation during sleep the eusart1 will remain active during sleep only in the synchronous slave mode. all other modes require the system clock and therefore cannot generate the necessary signals to run the transmit or receive shift registers during sleep. synchronous slave mode uses an externally generated clock to run the transmit and receive shift registers. 30.5.1 synchronous receive during sleep to receive during sleep, all the following conditions must be met before entering sleep mode: rc1sta and tx1sta control registers must be configured for synchronous slave reception (see section 30.4.2.4 ?synchronous slave reception setup? ). if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. the rcif interrupt flag must be cleared by read- ing rc1reg to unload any pending characters in the receive buffer. upon entering sleep mode, the device will be ready to accept data and clocks on the rx/dt and tx/ck pins, respectively. when the data word has been completely clocked in by the external device, the rcif interrupt flag bit of the pir1 register will be set. thereby, waking the processor from sleep. upon waking from sleep, the instruction following the sleep instruction will be executed. if the global interrupt enable (gie) bit of the intcon register is also set, then the interrupt service routine at address 004h will be called. 30.5.2 synchronous transmit during sleep to transmit during sleep, all the following conditions must be met before entering sleep mode: the rc1sta and tx1sta control registers must be configured for synchronous slave transmission (see section 30.4.2.2 ?synchronous slave transmission setup? ). the txif interrupt flag must be cleared by writing the output data to the tx1reg, thereby filling the tsr and transmit buffer. if interrupts are desired, set the txie bit of the pie1 register and the peie bit of the intcon register. interrupt enable bits txie of the pie1 register and peie of the intcon register must set. upon entering sleep mode, the device will be ready to accept clocks on tx/ck pin and transmit data on the rx/dt pin. when the data word in the tsr has been completely clocked out by the external device, the pending byte in the tx1reg will transfer to the tsr and the txif flag will be set. thereby, waking the pro- cessor from sleep. at this point, the tx1reg is avail- able to accept another character for transmission, which will clear the txif flag. upon waking from sleep, the instruction following the sleep instruction will be executed. if the global interrupt enable (gie) bit is also set then the interrupt service routine at address 0004h will be called. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 382 preliminary ? 2016 microchip technology inc. 30.6 register definitions: eusart1 control register 30-1: tx1sta: transmit status and control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-1/1 r/w-0/0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 csrc: clock source select bit asynchronous mode : unused in this mode C value ignored synchronous mode : 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: eusart1 mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode : 1 = send synch break on next transmission C start bit, followed by 12 0 bits, followed by stop bit; cleared by hardware upon completion 0 = synch break transmission disabled or completed synchronous mode : unused in this mode C value ignored bit 2 brgh: high baud rate select bit asynchronous mode : 1 = high speed 0 = low speed synchronous mode: unused in this mode C value ignored bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: ninth bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 383 pic16(l)f18326/18346 register 30-2: rc1sta: receiv e status and control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 r-0/0 r-x/x spen (1) rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 spen: serial port enable bit (1) 1 = serial port enabled 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : unused in this mode C value ignored synchronous mode C master : 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode C slave unused in this mode C value ignored bit 4 cren: continuous receive enable bit asynchronous mode : 1 = enables continuous receive until enable bit cren is cleared 0 = disables continuous receive synchronous mode : 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection C enable interrupt and load of the receive buffer when the ninth bit in the receive buffer is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 8-bit (rx9 = 0 ) : unused in this mode C value ignored bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rc1reg register and receive next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: ninth bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware. note 1: the eusart1 module automatically changes the pin from tri-state to drive as needed. configure the associated tris bits for tx/ck and rx/dt to 1 . downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 384 preliminary ? 2016 microchip technology inc. register 30-3: baud1con: baud rate control register r-0/0 r-1/1 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 abdovf rcidl sckp brg16 wue abden bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 abdovf: auto-baud detect overflow bit asynchronous mode : 1 = auto-baud timer overflowed 0 = auto-baud timer did not overflow synchronous mode : dont care bit 6 rcidl: receive idle flag bit asynchronous mode : 1 = receiver is idle 0 = start bit has been received and the receiver is receiving synchronous mode : dont care bit 5 unimplemented: read as 0 bit 4 sckp: clock/transmit polarity select bit asynchronous mode : 1 = idle state for transmit (tx) is a low level 0 = idle state for transmit (tx) is a high level synchronous mode : 1 = idle state for clock (ck) is a high level 0 = idle state for clock (ck) is a low level bit 3 brg16: 16-bit baud rate generator bit 1 = 16-bit baud rate generator is used 0 = 8-bit baud rate generator is used bit 2 unimplemented: read as 0 bit 1 wue: wake-up enable bit asynchronous mode : 1 = eusart will continue to sample the rx pin C interrupt generated on falling edge; bit cleared in hardware on following rising edge. 0 = rx pin not monitored nor rising edge detected synchronous mode : unused in this mode C value ignored bit 0 abden : auto-baud detect enable bit asynchronous mode : 1 = enable baud rate measurement on the next character C requires recep tion of a synch field (55h);cleared in hardware upon completion 0 = baud rate measurement disabled or completed synchronous mode : unused in this mode C value ignored downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 385 pic16(l)f18326/18346 register 30-4: rc1reg (1) : receive data register r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 rc1reg<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 rc1reg<7:0>: lower eight bits of the received data; read-only; see also rx9d ( register 30-2 ) note 1: rc1reg (including the ninth bit) is double buffered, and data is available while new data is being received. register 30-5: tx1reg (1) : transmit data register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 tx1reg<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 tx1reg<7:0>: lower eight bits of the received data; read-only; see also rx9d ( register 30-1 ) note 1: tx1reg (including the ninth bit) is double buffered, and can be written when previous data has started shifting. register 30-6: sp1brgl (1) : baud rate generator register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sp1brg<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7-0 sp1brg<7:0>: lower eight bits of the baud rate generator note 1: writing to sp1brg resets the brg counter. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 386 preliminary ? 2016 microchip technology inc. register 30-7: sp1brgh (1, 2) : baud rate generator high register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 sp1brg<15:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 sp1brg<15:8>: upper eight bits of the baud rate generator note 1: sp1brgh value is ignored for all modes unless baud1con ? 2016 microchip technology inc. preliminary ds40001839a-page 387 pic16(l)f18326/18346 table 30-3: baud rate formulas configuration bits brg/eusart1 mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n+1)] 001 8-bit/asynchronous f osc /[16 (n+1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n+1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = dont care, n = value of sp1brgh, sp1brgl register pair. table 30-4: baud rate fo r asynchronous modes baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 32.000 mhz f osc = 20.000 mhz f osc = 18.432 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 3 0 0 1200 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 57.60k 0.00 7 57.60k 0.00 2 115.2k baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 9600 9615 0.16 12 9600 0.00 5 10417 10417 0.00 11 10417 0.00 5 19.2k 19.20k 0.00 2 57.6k 57.60k 0.00 0 115.2k downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 388 preliminary ? 2016 microchip technology inc. baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 32.000 mhz f osc = 20.000 mhz f osc = 18.432 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 1200 2400 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300 0.16 207 1200 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 57.6k 55556 -3.55 8 57.60k 0.00 3 115.2k 115.2k 0.00 1 baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 32.000 mhz f osc = 20.000 mhz f osc = 18.432 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 table 30-4: baud rate for a synchronous modes (continued) downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 389 pic16(l)f18326/18346 baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 57.6k 55556 -3.55 8 57.60k 0.00 3 115.2k 115.2k 0.00 1 baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 32.000 mhz f osc = 20.000 mhz f osc = 18.432 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 table 30-4: baud rate for asy nchronous modes (continued) downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 390 preliminary ? 2016 microchip technology inc. 31.0 reference clock output module the reference clock output module provides the ability to send a clock signal to the clock reference output pin (clkr). the reference clock output can also be used as a signal for other peripherals, such as the data signal modulator (dsm). the reference clock output module has the following features: system clock is the module source clock programmable clock divider selectable duty cycle 31.1 clock source the reference clock output module uses the system clock (f osc ) as the clock source. any device clock switching will be reflected in the clock output. 31.1.1 clock synchronization once the reference clock enable (clkren) is set, the module is ensured to be glitch-free at start-up. when the reference clock output is disabled, the output signal will be disabled immediately. clock dividers and clock duty cycles can be changed while the module is enabled, but glitches may occur on the output. to avoid possible glitches, clock dividers and clock duty cycles should be changed only when the clkren is clear. 31.2 programmable clock divider the module takes the system clock input and divides it based on the value of the clkrdiv<2:0> bits of the clkrcon register ( register 31-1 ). the following configurations can be made based on the clkrdiv<2:0> bits: base f osc value f osc divided by 2 f osc divided by 4 f osc divided by 8 f osc divided by 16 f osc divided by 32 f osc divided by 64 f osc divided by 128 the clock divider values can be changed while the module is enabled; however, in order to prevent glitches on the output, the clkrdiv<2:0> bits should only be changed when the module is disabled (clkren = 0 ). 31.3 selectable duty cycle the clkrdc<1:0> bits of the clkrcon register can be used to modify the duty cycle of the output clock. a duty cycle of 25%, 50%, or 75% can be selected for all clock rates, with the exception of the undivided base f osc value. the duty cycle can be changed while the module is enabled; however, in order to prevent glitches on the output, the clkrdc<1:0> bits should only be changed when the module is disabled (clkren = 0 ). 31.4 operation in sleep mode the reference clock output module clock is based on the system clock. when the device goes to sleep, the module outputs will remain in their current state. this will have a direct effect on peripherals using the reference clock output as an input signal. note: the clkrdc1 bit is reset to 1 . this makes the default duty cycle 50% and not 0%. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 391 pic16(l)f18326/18346 figure 31-1: clock refe rence block diagram figure 31-2: clock reference timing d en q f osc clkren freeze enabled (1) icd freeze mode (1) clkrdiv<2:0> duty cycle clkrdc<1:0> clkr to peripherals note 1: freeze is used in debug mode only; otherwise read as 0 0000 00 0000 0 0 f osc /2 f osc /4 f osc /8 f osc /16 f osc /32 f osc /64 f osc /128 clkren counter reset clock counter f osc clkren clkr div[2:0] = 001 clkrdc[1:0] = 10 clkrdc[1:0] = 01 clkr div[2:0] = 001 clkr output duty cycle (25%) duty cycle (50%) f osc /2 p1 p2 clkr output downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 392 preliminary ? 2016 microchip technology inc. register 31-1: clkrcon: refere nce clock control register r/w-0/0 u-0 u-0 r/w-1/1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 clkren clkrdc<1:0> clkrdiv<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as 0 u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets 1 = bit is set 0 = bit is cleared bit 7 clkren: reference clock module enable bit 1 = reference clock module enabled 0 = reference clock module is disabled bit 6-5 unimplemented: read as 0 bit 4-3 clkrdc<1:0>: reference clock duty cycle bits (1) 11 = clock outputs duty cycle of 75% 10 = clock outputs duty cycle of 50% 01 = clock outputs duty cycle of 25% 00 = clock outputs duty cycle of 0% bit 2-0 clkrdiv<2:0>: reference clock divider bits 111 = f osc divided by 128 110 = f osc divided by 64 101 = f osc divided by 32 100 = f osc divided by 16 011 = f osc divided by 8 010 = f osc divided by 4 001 = f osc divided by 2 000 = f osc note 1: bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided . table 31-1: summary of registers asso ciated with clock reference output name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page trisa D D trisa5 trisa4 D (2) trisa2 trisa1 trisa0 141 trisb (1) trisb7 trisb6 trisb5 trisb4 D D D D 147 trisc trisc7 (1) trisc6 (1) trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 153 clkrcon clkren D D clkrdc<1:0> clkrdiv<2:0> 225 clcxsely D D lcxdys<5:0> 227 mdcarh D mdchpol mdchsync D mdch<3:0> 271 mdcarl D mdclpol mdclsync D mdcl<3:0> 272 rxypps D D D rxypps<4:0> 161 legend: = unimplemented, read as 0 . shaded cells are not used by the clkr module. note 1: pic16(l)f18346 only. 2: unimplemented, read as 1 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 393 pic16(l)f18326/18346 32.0 in-circuit serial programming? (icsp?) icsp? programming allows customers to manufacture circuit boards with unprogrammed devices. programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. five pins are needed for icsp programming: icspclk icspdat mclr /v pp v dd v ss in program/verify mode the program memory, user ids and the configuration words are programmed through serial communications. the icspdat pin is a bidirectional i/o used for transferring the serial data and the icspclk pin is the clock input. for more information on icsp, refer to the ? pic16(l)f183xx memory programming specification ? (ds40001738). 32.1 high-voltage programming entry mode the device is placed into high-voltage programming entry mode by holding the icspclk and icspdat pins low then raising the voltage on mclr /v pp to v ihh . 32.2 low-voltage programming entry mode the low-voltage programming entry mode allows the pic ? flash mcus to be programmed using v dd only, without high voltage. when the lvp bit of configuration words is set to 1 , the low-voltage icsp programming entry is enabled. to disable the low-voltage icsp mode, the lvp bit must be programmed to 0 . entry into the low-voltage programming entry mode requires the following steps: 1. mclr is brought to v il . 2. a 32-bit key sequence is presented on icspdat, while clocking icspclk. once the key sequence is complete, mclr must be held at v il for as long as program/verify mode is to be maintained. if low-voltage programming is enabled (lvp = 1 ), the mclr reset function is automatically enabled and cannot be disabled. see section 5.4 ?mclr for more information. the lvp bit can only be reprogrammed to 0 by using the high-voltage programming mode. 32.3 common programming interfaces connection to a target device is typically done through an icsp? header. a commonly found connector on development tools is the rj-11 in the 6p6c (6-pin, 6-connector) configuration. see figure 32-1 . figure 32-1: icd rj-11 style connector interface another connector often found in use with the pickit? programmers is a standard 6-pin header with 0.1 inch spacing. refer to figure 32-2 . for additional interface recommendations, refer to your specific device programmer manual prior to pcb design. it is recommended that isolation devices be used to separate the programming pins from other circuitry. the type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. see figure 32-3 for more information. 1 2 3 4 5 6 target bottom side pc board v pp /mclr v ss icspclk v dd icspdat nc pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 394 preliminary ? 2016 microchip technology inc. figure 32-2: pickit? programme r style connector interface figure 32-3: typical connect ion for icsp? programming 12 3 4 5 6 * the 6-pin header (0.100" spacing) accepts 0.025" square pins. pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect pin 1 indicator v dd v pp v ss external device to be data clock v dd mclr /v pp v ss icspdat icspclk * * * to normal connections * isolation devices (as required). programming signals programmed v dd downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 395 pic16(l)f18326/18346 33.0 instruction set summary each instruction is a 14-bit word containing the opera- tion code (opcode) and all required operands. the opcodes are broken into three broad categories. byte oriented bit oriented literal and control the literal and control category contains the most varied instruction word format. table 33-3 lists the instructions recognized by the mpasm ? assembler. all instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: subroutine takes two cycles ( call , callw ) returns from interrupts or subroutines take two cycles ( return , retlw , retfie ) program branching takes two cycles ( goto , bra , brw , btfss , btfsc , decfsz , incsfz ) one additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. one instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 mhz, this gives a nominal instruction execution rate of 1 mhz. all instruction examples use the format 0xhh to represent a hexadecimal number, where h signifies a hexadecimal digit. 33.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator d. a read operation is performed on a register even if the instruction writes to that register. table 33-1: opcode field descriptions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x dont care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w, d = 1 : store result in file register f. default is d = 1 . n fsr or indf number. (0-1) mm pre-post increment-decrement mode selection table 33-2: abbreviation descriptions field description pc program counter to time-out bit c carry bit dc digit carry bit z zero bit pd power-down bit downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 396 preliminary ? 2016 microchip technology inc. figure 33-1: general format for instructions byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only movlp instruction only 13 5 4 0 opcode k (literal) k = 5-bit immediate value movlb instruction only 13 9 8 0 opcode k (literal) k = 9-bit immediate value bra instruction only fsr offset instructions 13 7 6 5 0 opcode n k (literal) n = appropriate fsr fsr increment instructions 13 7 6 0 opcode k (literal) k = 7-bit immediate value 13 3 2 1 0 opcode n m (mode) n = appropriate fsr m = 2-bit mode value k = 6-bit immediate value 13 0 opcode opcode only downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 397 pic16(l)f18326/18346 table 33-3: pic16(l)f1832 6/18346 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf asrf lslf lsrf clrf clrw comf decf incf iorwf movf movwf rlf rrf subwf subwfb swapf xorwf f, d f, d f, d f, d f, d f, d f C f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d add w and f add with carry w and f and w with f arithmetic right shift logical left shift logical right shift clear f clear w complement f decrement f increment f inclusive or w with f move f move w to f rotate left f through carry rotate right f through carry subtract w from f subtract with borrow w from f swap nibbles in f exclusive or w with f 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0011 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 01111101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffffffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z c, dc, z z c, z c, z c, z z z z z z z z c c c, dc, z c, dc, z z 22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 byte oriented skip operations decfsz incfsz f, d f, d decrement f, skip if 0 increment f, skip if 0 1(2)1(2) 0000 10111111 dfffdfff ffffffff 1, 2 1, 2 bit-oriented file register operations bcf bsf f, b f, b bit clear f bit set f 11 0101 00bb01bb bfffbfff ffffffff 22 bit-oriented skip operations btfsc btfss f, b f, b bit test f, skip if clear bit test f, skip if set 1 (2)1 (2) 0101 10bb11bb bfff bfff ffffffff 1, 2 1, 2 literal operations addlw andlw iorlw movlb movlp movlw sublw xorlw kk k k k k k k add literal and w and literal with w inclusive or literal with w move literal to bsr move literal to pclath move literal to w subtract w from literal exclusive or literal with w 11 1 1 1 1 1 1 1111 11 00 11 11 11 11 11101001 1000 0000 0001 0000 1100 1010 kkkkkkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkkkkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z z z c, dc, z z control operations bra brw call callw goto retfie retlw return kC k C k k k C relative branch relative branch with w call subroutine call subroutine with w go to address return from interrupt return with literal in w return from subroutine 22 2 2 2 2 2 2 1100 10 00 10 00 11 00 001k0000 0kkk 0000 1kkk 0000 0100 0000 kkkk0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk1011 kkkk 1010 kkkk 1001 kkkk 1000 note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle. 3: see table in the moviw and movwi instruction descriptions. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 398 preliminary ? 2016 microchip technology inc. inherent operations clrwdt nop option reset sleep tris CC C C C f clear watchdog timer no operation load option_reg register with w software device reset go into standby mode load tris register with w 11 1 1 1 1 0000 00 00 00 00 00000000 0000 0000 0000 0000 01100000 0110 0000 0110 0110 01000000 0010 0001 0011 0fff to , pd to , pd c-compiler optimized addfsr moviw movwi n, k n mm k[n] n mm k[n] add literal k to fsrn move indirect fsrn to w with pre/post inc/dec modifier, mm move indfn to w, indexed indirect. move w to indirect fsrn with pre/post inc/dec modifier, mm move w to indfn, indexed indirect. 11 1 1 1 1100 11 00 11 00010000 1111 0000 1111 0nkk 0001 0nkk 0001 1nkk kkkk 0nmmkkkk 1nmm kkkk zz 2, 3 2 2, 3 2 table 33-3: pic16(l)f18326/18346 instruction set (continued) mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle. 3: see table in the moviw and movwi instruction descriptions. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 399 pic16(l)f18326/18346 33.2 instruction descriptions addfsr add literal to fsrn syntax: [ label ] addfsr fsrn, k operands: -32 ? k ? 31 n ? [ 0, 1] operation: fsr(n) + k ? fsr(n) status affected: none description: the signed 6-bit literal k is added to the contents of the fsrnh:fsrnl register pair. fsrn is limited to the range 0000h-ffffh. moving beyond these bounds will cause the fsr to wrap-around. addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the 8-bit literal k and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register f. if d is 0 , the result is stored in the w register. if d is 1 , the result is stored back in register f. addwfc add w and carry bit to f syntax: [ label ] addwfc f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (w) + (f) + (c) ? dest status affected: c, dc, z description: add w, the carry flag and data mem- ory location f. if d is 0 , the result is placed in w. if d is 1 , the result is placed in data memory location f. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are anded with the 8-bit literal k. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register f. if d is 0 , the result is stored in the w register. if d is 1 , the result is stored back in register f. asrf arithmetic right shift syntax: [ label ] asrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register f are shifted one bit to the right through the carry flag. the msb remains unchanged. if d is 0 , the result is placed in w. if d is 1 , the result is stored back in register f. register f c downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 400 preliminary ? 2016 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit b in register f is cleared. bra relative branch syntax: [ label ] bra label [ label ] bra $+k operands: -256 ? label - pc + 1 ? 255 -256 ? k ? 255 operation: (pc) + 1 + k ? pc status affected: none description: add the signed 9-bit literal k to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 1 + k. this instruction is a 2-cycle instruction. this branch has a limited range. brw relative branch with w syntax: [ label ] brw operands: none operation: (pc) + (w) ? pc status affected: none description: add the contents of w (unsigned) to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 1 + (w). this instruction is a 2-cycle instruction. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit b in register f is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit b in register f is 1 , the next instruction is executed. if bit b, in register f, is 0 , the next instruction is discarded, and a nop is executed instead, making this a 2-cycle instruction. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit b in register f is 0 , the next instruction is executed. if bit b is 1 , then the next instruction is discarded and a nop is executed instead, making this a 2-cycle instruction. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 401 pic16(l)f18326/18346 call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<6:3>) ? pc<14:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the 11-bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a 2-cycle instruction. callw subroutine call with w syntax: [ label ] callw operands: none operation: (pc) +1 ? tos, (w) ? pc<7:0>, (pclath<6:0>) ?? pc<14:8> status affected: none description: subroutine call with w. first, the return address (pc + 1) is pushed onto the return stack. then, the contents of w is loaded into pc<7:0>, and the contents of pclath into pc<14:8>. callw is a 2-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register f are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f ) ? (destination) status affected: z description: the contents of register f are complemented. if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination) status affected: z description: decrement register f. if d is 0 , the result is stored in the w register. if d is 1 , the result is stored back in register f. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 402 preliminary ? 2016 microchip technology inc. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register f are decre- mented. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed back in register f. if the result is 1 , the next instruction is executed. if the result is 0 , then a nop is executed instead, making it a 2-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<6:3> ? pc<14:11> status affected: none description: goto is an unconditional branch. the 11-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a 2-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination) status affected: z description: the contents of register f are incre- mented. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed back in register f. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register f are incre- mented. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed back in register f. if the result is 1 , the next instruction is executed. if the result is 0 , a nop is executed instead, making it a 2-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are ored with the 8-bit literal k. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with regis- ter f. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed back in register f. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 403 pic16(l)f18326/18346 lslf logical left shift syntax: [ label ] lslf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? c (f<6:0>) ? dest<7:1> 0 ? dest<0> status affected: c, z description: the contents of register f are shifted one bit to the left through the carry flag. a 0 is shifted into the lsb. if d is 0 , the result is placed in w. if d is 1 , the result is stored back in register f. lsrf logical right shift syntax: [ label ] lsrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: 0 ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register f are shifted one bit to the right through the carry flag. a 0 is shifted into the msb. if d is 0 , the result is placed in w. if d is 1 , the result is stored back in register f. register f 0 c register f c 0 movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) ? (dest) status affected: z description: the contents of register f is moved to a destination dependent upon the status of d. if d = 0 , destination is w register. if d = 1 , the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register z= 1 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 404 preliminary ? 2016 microchip technology inc. moviw move indfn to w syntax: [ label ] moviw ++fsrn [ label ] moviw --fsrn [ label ] moviw fsrn++ [ label ] moviw fsrn-- [ label ] moviw k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: indfn ? w effective address is determined by fsr + 1 (preincrement) fsr - 1 (predecrement) fsr + k (relative offset) after the move, the fsr value will be either: fsr + 1 (all increments) fsr - 1 (all decrements) unchanged status affected: z mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h - ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. movlb move literal to bsr syntax: [ label ] movlb k operands: 0 ? k ? 31 operation: k ? bsr status affected: none description: the 5-bit literal k is loaded into the bank select register (bsr). movlp move literal to pclath syntax: [ label ] movlp k operands: 0 ? k ? 127 operation: k ? pclath status affected: none description: the 7-bit literal k is loaded into the pclath register. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the 8-bit literal k is loaded into w reg- ister. the dont cares will assemble as 0 s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none description: move data from w register to register f. words: 1 cycles: 1 example: movwf option_reg before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 405 pic16(l)f18326/18346 movwi move w to indfn syntax: [ label ] movwi ++fsrn [ label ] movwi --fsrn [ label ] movwi fsrn++ [ label ] movwi fsrn-- [ label ] movwi k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: w ? indfn effective address is determined by fsr + 1 (preincrement) fsr - 1 (predecrement) fsr + k (relative offset) after the move, the fsr value will be either: fsr + 1 (all increments) fsr - 1 (all decrements) unchanged status affected: none mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h-ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. the increment/decrement operation on fsrn will not affect any status bits. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. words: 1 cycles: 1 example: nop option load option_reg register with w syntax: [ label ] option operands: none operation: (w) ? option_reg status affected: none description: move data from w register to option_reg register. words: 1 cycles: 1 example: option before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f reset software reset syntax: [ label ] reset operands: none operation: execute a device reset. resets the ri flag of the pcon register. status affected: none description: this instruction provides a way to execute a hardware reset by software. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 406 preliminary ? 2016 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie k operands: none operation: tos ? pc, 1 ? gie status affected: none description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a 2-cycle instruction. words: 1 cycles: 2 example: retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the 8-bit literal k. the program counter is loaded from the top of the stack (the return address). this is a 2-cycle instruction. words: 1 cycles: 2 example: table call table;w contains table ;offset value ;w now has table value addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a 2-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register f are rotated one bit to the left through the carry flag. if d is 0 , the result is placed in the w register. if d is 1 , the result is stored back in register f. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w = 1100 1100 c= 1 register f c downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 407 pic16(l)f18326/18346 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register f are rotated one bit to the right through the carry flag. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed back in register f. sleep enter sleep mode syntax: [ label ]sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. see section 8.2 ?sleep mode? for more information. register f c sublw subtract w from literal syntax: [ label ]sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z description: the w register is subtracted (2s complement method) from the 8-bit literal k. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [ 0 , 1 ] operation: (f) - (w) ??? destination) status affected: c, dc, z description: subtract (2s complement method) w register from register f. if d is 0 , the result is stored in the w register. if d is 1 , the result is stored back in register f. subwfb subtract w from f with borrow syntax: subwfb f {,d} operands: 0 ? f ? 127 d ? [0,1] operation: (f) C (w) C (b ) ?? dest status affected: c, dc, z description: subtract w and the borrow flag (carry) from register f (2s complement method). if d is 0 , the result is stored in w. if d is 1 , the result is stored back in register f. c = 0 w ? k c = 1 w ? k dc = 0 w<3:0> ? k<3:0> dc = 1 w<3:0> ? k<3:0> c = 0 w ? f c = 1 w ? f dc = 0 w<3:0> ? f<3:0> dc = 1 w<3:0> ? f<3:0> downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 408 preliminary ? 2016 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of register f are exchanged. if d is 0 , the result is placed in the w register. if d is 1 , the result is placed in register f. tris load tris register with w syntax: [ label ] tris f operands: 5 ? f ? 7 operation: (w) ? tris register f status affected: none description: move data from w register to tris register. when f = 5, trisa is loaded. when f = 6, trisb is loaded. when f = 7, trisc is loaded. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xored with the 8-bit literal k. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .xor. (f) ??? destination) status affected: z description: exclusive or the contents of the w register with register f. if d is 0 , the result is stored in the w register. if d is 1 , the result is stored back in register f. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 409 pic16(l)f18326/18346 34.0 electrical specifications 34.1 absolute maximum ratings (?) ambient temperature under bias................................................................................................. ..... -40c to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on pins with respect to v ss on v dd pin pic16f18326/18346 ................................................................................................. -0.3v to +6 .5v pic16lf18326/18346 ............................................................................................... -0.3v to +4. 0v on mclr pin .......................................................................................................................... . -0.3v to +9.0v on all other pins ............................................................................................................ -0.3v to (v dd + 0.3v) maximum current on v ss pin (1) -40c ? t a ? +85c .............................................................................................................. 250 ma +85c ? t a ? +125c ............................................................................................................. 85 ma on v dd pin (1) -40c ? t a ? +85c .............................................................................................................. 250 ma +85c ? t a ? +125c ............................................................................................................. 85 ma on any i/o pin ................................................................................................................ ..................... ? 50 ma clamp current, i k (v pin < 0 or v pin > v dd ) ................................................................................................... ? 20 ma total power dissipation (2) .............................................................................................................................. 800 mw note 1: maximum current rating requires even load distribution across i/o pins. maximu m current rating may be limited by the device package power dissipation characterizations, see tab le 3 4- 3 to calculate device specifications. 2: power dissipation is calculated as follows: p dis = v dd x {i dd C i oh } + {(v dd C v oh ) x i oh } + (v ol x i ol ). ? notice: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions abov e those indicated in the operation listings of this specification is not implied. exposure above maximum rating conditions for extended periods may affect device reliability. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 410 preliminary ? 2016 microchip technology inc. 34.2 standard operating conditions the standard operating conditions for any device are defined as: operating voltage: v ddmin ?? v dd ?? v ddmax operating temperature: t a _ min ?? t a ?? t a _ max v dd ? operating supply voltage (1) pic16lf18326/18346 v ddmin (fosc ? 16 mhz).......................................................................................................... +1.8v v ddmin (fosc ? 32 mhz).......................................................................................................... +2.5v v ddmax ............................................................................................................................... ..... +3.6v pic16f18326/18346 v ddmin (fosc ? 16 mhz).......................................................................................................... +2.3v v ddmin (fosc ? 32 mhz).......................................................................................................... +2.5v v ddmax ............................................................................................................................... ..... +5.5v t a ? operating ambient temperature range industrial temperature t a _ min ............................................................................................................................... ....... -40c t a _ max ............................................................................................................................... ..... +85c extended temperature t a _ min ............................................................................................................................... ....... -40c t a _ max ............................................................................................................................... ... +125c note 1: see parameter d002 , dc characteristics: supply voltage. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 411 pic16(l)f18326/18346 figure 34-1: voltage frequency graph, -40c ? t a ?? +125c, pic16f18326/18346 only figure 34-2: voltage frequency graph, -40c ? t a ?? +125c, pic16lf18326/18346 only 0 2.5 frequency (mhz) v dd (v) 43 2 10 16 5.5 2.3 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 34-7 for each oscillator modes supported frequencies. 1.8 0 2.5 frequency (mhz) v dd (v) 43 2 10 16 3.6 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 34-7 for each oscillator modes supported frequencies. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 412 preliminary ? 2016 microchip technology inc. 34.3 dc characteristics table 34-1: supply voltage pic16lf18326/18346 standard operating conditions (unless otherwise stated) pic16f18326/18346 standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions supply voltage d002 v dd 1.8 2.5 3.63.6 vv f osc ? 16 mhz f osc > 16 mhz d002 v dd 2.3 2.5 5.55.5 vv f osc ? 16 mhz: f osc > 16 mhz ram data retention (1) d003 v dr 1.5 v device in sleep mode d003 v dr 1.7 v device in sleep mode power-on reset release voltage (2) d004 v por 1.6 v bor and lpbor disabled (3) d004 v por 1.6 v bor and lpbor disabled (3) power-on reset rearm voltage (2) d005 v porr 0.8 v bor and lpbor disabled (3) d005 v porr 1.5 v bor and lpbor disabled (3) v dd rise rate to ensure internal power-on reset signal (2) d006 s vdd 0.05 v/ms bor and lpbor disabled (3) d006 s vdd 0.05 v/ms bor and lpbor disabled (3) ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode or during a device reset, without losing ram data. 2: see figure 34-3 . 3: please see tab le 3 4- 11 for bor and lpbor trip point information. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 413 pic16(l)f18326/18346 figure 34-3: por and por rearm with slow rising v dd v dd v por v porr v ss v ss npor (1) t por (3) por rearm t vlow (2) s vdd note 1: when npor is low, the device is held in reset. 2: t por 1 ? s typical. 3: t vlow 2.7 ? s typical. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 414 preliminary ? 2016 microchip technology inc. table 34-2: supply current (i dd ) (1,2) pic16lf18326/18346 standard operating conditions (unless otherwise stated) pic16f18326/18346 standard operating conditions (unless otherwise stated) param. no. symbol device characteristics min. typ.? max. units conditions v dd note d100 idd xt 4 xt = 4 mhz 321 455 ua 3.0v d100 idd xt 4 xt = 4 mhz 332 479 ua 3.0v d101 idd hfo 16 hfintosc = 16 mhz 1.3 1.8 ma 3.0v d101 idd hfo 16 hfintosc = 16 mhz 1.4 1.9 ma 3.0v d102 idd hfopll hfintosc = 32 mhz 2.2 2.8 ma 3.0v d102 idd hfopll hfintosc = 32 mhz 2.3 2.9 ma 3.0v d103 idd hspll 32 hs+pll = 32 mhz 2.2 2.8 ma 3.0v d103 idd hspll 32 hs+pll = 32 mhz 2.3 2.9 ma 3.0v d104 idd idle idle mode, hfintosc = 16 mhz 804 1283 ua 3.0v d104 idd idle idle mode, hfintosc = 16 mhz 816 1284 ua 3.0v d105 idd doze (3) doze mode, hfintosc = 16 mhz, doze ratio = 16 863 ua 3.0v d105 idd doze (3) doze mode, hfintosc = 16 mhz, doze ratio = 16 875 ua 3.0v ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: idd doze = [idd idle *(n-1)/n] + idd hfo 16/n where n = doze ration (see register 8-2 ). downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 415 pic16(l)f18326/18346 table 34-3: power-down currents (i pd ) (1,2,3) pic16lf18326/18346 standard operating conditions (unless otherwise stated) pic16f18326/18346 standard operating conditions (unless otherwise stated) vregpm = 1 param. no. symbol device characteristics min. typ.? max. +85c max. +125c units conditions v dd note d200 i pd i pd base 0.05 2 9 ? a3.0v d200 i pd i pd base 0.8 4 12 ? a 3.0v 13 22 27 ? a 3.0v vregpm = 0 d201 i pd _ wdt low-frequency internal oscillator/wdt 0 . 8 5 1 3 ? a3.0v d201 i pd _ wdt low-frequency internal oscillator/wdt 0.9 5 13 ? a 3.0v d202 i pd _ sosc secondary oscillator (sosc) 0.6 5 13 ? a3.0v d202 i pd _ sosc secondary oscillator (sosc) 0.8 9 15 ? a 3.0v d203 i pd _ fvr fvr 40 47 47 ? a3.0v d203 i pd _ fvr fvr 33 44 44 ? a 3.0v d204 i pd _ bor brown-out reset (bor) 12 17 19 ? a3.0v d204 i pd _ bor brown-out reset (bor) 12 18 20 ? a 3.0v d205 i pd _ lpbor low power brown-out reset (lpbor) 3 5 1 3 ? a3.0v d205 i pd _ lpbor low power brown-out reset (lpbor) 4 5 13 ? a 3.0v d207 i pd _ adca adc - active 0.9 5 13 ? a 3.0v adc is converting (4) d207 i pd _ adca adc - active 0.9 5 13 ? a 3.0v adc is converting (4) d208 i pd _ cmp comparator 32 43 45 ? a3.0v d208 i pd _ cmp comparator 31 42 44 ? a 3.0v * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v ss . 3: all peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. 4: adc clock source is adcrc. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 416 preliminary ? 2016 microchip technology inc. table 34-4: i/o ports (1) dc characteristics standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions v il input low voltage i/o port: d300 with ttl buffer 0.8 v 4.5v ? v dd ? 5.5v d301 0.15 v dd v1.8v ? v dd ? 4.5v d302 with schmitt trigger buffer 0.2 v dd v2.0v ? v dd ? 5.5v d303 with i 2 c levels 0.3 v dd v d304 with smbus levels 0.8 v 2.7v ? v dd ? 5.5v d305 mclr 0 . 2 v dd v v ih input high voltage i/o port: d320 with ttl buffer 2.0 v 4.5v ? v dd ?? 5.5v d321 0.25 v dd + 0.8 v 1.8v ? v dd ? 4.5v d322 with schmitt trigger buffer 0.8 v dd v2 . 0 v ? v dd ? 5.5v d323 with i 2 c levels 0.7 v dd v d324 with smbus levels 2.1 v 2.7v ? v dd ? 5.5v d325 mclr 0.7 v dd v i il input leakage current (2) d340 i/o ports 5 125 na v ss ? v pin ? v dd , pin at high-impedance, 85c d341 5 1000 na v ss ? v pin ? v dd , pin at high-impedance, 125c d342 mclr (2) 50 200 na v ss ? v pin ? v dd , pin at high-impedance, 85c i pur weak pull-up current d350 25 120 200 ? av dd = 3.0v, v pin = v ss v ol output low voltage (3) d360 i/o ports 0.6 v i ol = 10.0 ma, v dd = 3.0v v oh output high voltage (3) d370 i/o ports v dd - 0.7 v i oh = 6.0 ma, v dd = 3.0v d380 c io all i/o pins 55 0p f * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: negative current is defined as current sourced by the pin. 2: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 3: excluding osc2 in clkout mode. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 417 pic16(l)f18326/18346 table 34-5: i/o and clock timing specifications standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions high voltage entry programming mode specifications mem01 v ihh voltage on mclr /v pp pin to enter programming mode 8 9 v note 2 mem02 i ppgm current on mclr /v pp pin during programming mode 6 0 0u a note 2 programming mode specifications mem10 v be v dd for bulk erase 2.7 v mem11 i ddpgm supply current during programming operation 3m a data eeprom memory specifications mem20 e d dataee byte endurance 100k e/w -40c ? t a ?? 85c mem21 t d _ ret characteristic retention 40 year provided no other specifications are violated mem22 n d _ ref total erase/write cycles before refresh 100k e/w mem23 v d _ rw v dd for read or erase/write operation v ddmin v ddmax v mem24 t d _ bew byte erase and write cycle time 4.0 5.0 ms program flash memory specifications mem30 e p flash memory cell endurance 10k e/w -40c ? t a ? 85c (note 1) mem31 e phef high-endurance flash memory cell endurance 100k e/w tbd mem32 t p _ ret characteristic retention 40 year provided no other specifications are violated mem33 v p _ rd v dd for read operation v ddmin v ddmax v mem34 v p _ rew v dd for row erase or write operation v ddmin v ddmax v mem35 t p _ rew self-timed row erase or self-timed write 2 . 02 . 5m s ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: flash memory cell endurance for the flash memory is defined as: one row erase operation and one self-timed write. 2: required only if config3.lvp is disabled. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 418 preliminary ? 2016 microchip technology inc. table 34-6: thermal characteristics standard operating conditions (unless otherwise stated) param. no. sym. characteristic typ. units conditions th01 ? ja thermal resistance junction to ambient 70.0 ? c/w 14-pin pdip package 95.3 ? c/w 14-pin soic package 100.0 ? c/w 14-pin tssop package 51.5 ? c/w 16-pin uqfn 4x4mm package 62.2 ? c/w 20-pin pdip package 87.3 ? c/w 20-pin ssop package 77.7 ? c/w 20-pin soic package 43.0 ? c/w 20-pin uqfn 4x4mm package th02 ? jc thermal resistance junction to case 32.75 ? c/w 14-pin pdip package 31.0 ? c/w 14-pin soic package 24.4 ? c/w 14-pin tssop package 5.4 ? c/w 16-pin uqfn 4x4mm package 27.5 ? c/w 20-pin pdip package 31.1 ? c/w 20-pin ssop package 23.1 ? c/w 20-pin soic package 5.3 ? c/w 20-pin uqfn 4x4mm package th03 t jmax maximum junction temperature 150 ? c th04 pd power dissipation 0.800 w pd = p internal + p i / o th05 p internal internal power dissipation w p internal = i dd x v dd (1) th06 p i / o i/o power dissipation w p i / o = ? (i ol * v ol ) + ? (i oh * (v dd - v oh )) th07 p der derated power w p der = pd max (t j - t a )/ ? ja (2) note 1: i dd is current to run the chip alone without driving any load on the output pins. 2: t a = ambient temperature, t j = junction temperature downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 419 pic16(l)f18326/18346 34.4 ac characteristics figure 34-4: load conditions figure 34-5: clock timing v ss c l load condition pin note: c l = 50 pf for all pins. clkin clkout q4 q1 q2 q3 q4 q1 os1 os20 (clkout mode) os2 os2 note: see table 34-10 . downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 420 preliminary ? 2016 microchip technology inc. table 34-7: external clock/oscillator timing requirements (1) standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions ecl oscillator os1 f ecl clock frequency 500 khz os2 t ecl _ dc clock duty cycle 40 60 % ecm oscillator os3 f ecm clock frequency 4 mhz note 4 os4 t ecm _ dc clock duty cycle 40 60 % ech oscillator os5 f ech clock frequency 32 mhz os6 t ech _ dc clock duty cycle 40 60 % lp oscillator os7 f lp clock frequency 100 khz note 4 xt oscillator os8 f xt clock frequency 4 mhz note 4 hs oscillator os9 f hs clock frequency 20 mhz note 4 system clock os20 f osc system clock frequency 32 mhz note 2, note 3 os21 f cy instruction frequency f osc /4 mhz os22 t cy instruction period 125 1/f cy n s * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at min values with an external clock applied to osc1 pin. when an external clock input is used, the max cycle time limit is dc (no clock) for all devices. 2: the system clock frequency (f osc ) is selected by the main clock switch controls as described in section 6.3 ?clock switching? . 3: the system clock frequency (f osc ) must meet the voltage requirements defined in the section 34.2 ?standard operating conditions? . lp, xt and hs oscillator modes require an appropriate crystal or resonator to be connected to the device. 4: for clocking the device with an external square wave, one of the ec mode selections must be used. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 421 pic16(l)f18326/18346 figure 34-6: precision cal ibrated hfintosc frequency accuracy over device v dd and temperature table 34-8: oscillator parameters (1) standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions os20 f hfosc precision calibrated hfintosc frequency 3.92 4 4.08 mhz 25c os20 f hfosc precision calibrated hfintosc frequency 4 8 1216 32 mhz -40c to 125c (2) os21 f hfosclp low-power optimized hfintosc frequency 0.931.86 12 1.07 2.14 mhzmhz os23 f lfosc internal lfintosc frequency 31 khz os24 t hfoscst hfintosc wake-up from sleep start-up time 1 1 50 20 ? s ? s vregpm = 0 vregpm = 1 os26 t lfoscst lfintosc wake-up from sleep start-up time 0 . 2 m s * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended. 2: see figure 34-6 . 125 2.0 0 60 85 v dd (v) 4.0 5.0 4.5 temperature ( c ) 2.3 3.0 3.5 5.5 1.8 -40 5% 2% 5% 3% downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 422 preliminary ? 2016 microchip technology inc. figure 34-7: clkout and i/o timing table 34-9: pll clock timing specifications standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions pll01 f pllin pll input frequency range 4 8 mhz pll02 f pllout pll output frequency range 16 32 mhz pll03 t pllst pll lock time from start-up 200 ? s pll04 f plljit pll output frequency stability (jitter) -0.25 0.25 % * these parameters are characterized but not tested. ? data in typ. column is at 5v, 25 ? c unless otherwise stated. these parameters are for design guidance only and are not tested. f osc clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 io1 io8 io3 io7, io8 io10 io12 io5 io4 io2 io7 old value new value write fetch read execute cycle downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 423 pic16(l)f18326/18346 table 34-10: clkout and i/o timing specifications standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions io1 t clkouth clkout rising edge delay (rising edge f osc (q1 cycle) to falling edge clkout n s io2 t clkoutl clkout falling edge delay (rising edge f osc (q3 cycle) to rising edge clkout n s io3 t io _ valid port output valid time (rising edge f osc (q1 cycle) to port valid) n s io4 t io _ setup port input setup time (setup time before rising edge f osc - q2 cycle) n s io5 t io _ hold port input hold time (hold time after rising edge f osc - q2 cycle) n s io6 t ior _ slren port i/o rise time, slew rate enabled n s v dd = 3.0v, load conditions io7 t ior _ slrdis port i/o rise time, slew rate disabled n s v dd = 3.0v, load conditions io8 t iof _ slren port i/o fall time, slew rate enabled n s v dd = 3.0v, load conditions io9 t iof _ slrdis port i/o fall time, slew rate disabled n s v dd = 3.0v, load conditions io10 t int int pin high or low time to trigger an interrupt n s io11 t ioc interrupt-on-change minimum high or low time to trigger interrupt n s * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25 ? c unless otherwise stated. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 424 preliminary ? 2016 microchip technology inc. figure 34-8: reset, watchdog timer, osci llator, start-up timer and power-up timer timing figure 34-9: brown-out rese t timing and characteristics v dd mclr internal por pwrt time-out osc start-up time internal reset (1) watchdog timer rst01 i/o pins reset (1) note 1: asserted low. rst04 rst05 rst03 rst02 rst02 v bor v dd (device in brown-out reset) (device not in brown-out reset) 33 (1) reset (due to bor) v bor and v hyst 37 note 1: 64 ms delay only if pwrte bit in the configuration word register is programmed to 0 . 2 ms delay if pwrte = 0 . downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 425 pic16(l)f18326/18346 table 34-11: reset, watchdog timer, oscillator, start-up timer, power-up timer, brown-out reset and low power brown-out reset specifications standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions rst01 t mclr mclr pulse width low to ensure reset 2 ? s rst02 t ioz i/o high-impedance from reset detection 2 ? s rst03 t wdt watchdog timer time-out period 10 16 27 ms 16 ms nominal reset time rst04* t pwrt power-up timer period 40 65 140 ms rst05 t ost oscillator start-up timer period (1,2) 1024t osc (note3) rst06 v bor brown-out reset voltage (4) 2.552.30 1.80 2.70 2.45 1.90 2.85 2.60 2.10 vv v borv = 0 borv = 1 (pic16f18326/18346) borv = 1 (pic16lf18326/18346) rst07 v borhys brown-out reset hysteresis 0 25 75 mv rst08 t bordc brown-out reset response time 133 5 ? s rst09 v lpbor low-power brown-out reset voltage 1.8 2.1 2.5 v pic16lf18326/18346 * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator o pera- tion and/or higher than expected current consumption. all devices are tested to operate at min values with an external clock applied to the osc1 pin. when an external clock input is used, the max cycle time limit is dc (no clock) for all devices. 2: by design. 3: period of the slower clock. 4: to ensure these voltage tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 426 preliminary ? 2016 microchip technology inc. table 34-12: a nalog-to-digital converter (adc) characteristics (1,2) standard operating conditions (unless otherwise stated) v dd = 3.0v, t a = 25c param. no. sym. characteristic min. typ.? max. units conditions ad01 n r resolution 10 bit ad02 e il integral error 0.1 1.0 lsb adc ref + = 3.0v, adc ref -= 0v ad03 e dl differential error 0.1 1.0 lsb adc ref + = 3.0v, adc ref -= 0v ad04 e off offset error 0.5 2 lsb adc ref + = 3.0v, adc ref -= 0v ad05 e gn gain error 0.2 1.0 lsb adc ref + = 3.0v, adc ref -= 0v ad06 v adref adc reference voltage (ad ref +) (3) 1.8 v dd v ad07 v ain full-scale range v ss ad ref +v ad06 v adref adc reference voltage (ad ref + - ad ref -) (3) 1.8 v dd v ad07 v ain full-scale range ad ref -ad ref +v ad08 z ain recommended impedance of analog voltage source 1 0 k ? ad09 r vref adc voltage reference ladder impedance k ? * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: total absolute error is the sum of the offset, gain and integral non-linearity (inl) errors. 2: the adc conversion result never decreases with an increase in the input and has no missing codes. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 427 pic16(l)f18326/18346 figure 34-10: adc conversi on timing (adc clock f osc -based) table 34-13: analog-to digital converter (adc) conversion timing specifications standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions ad20 tad adc clock period 1 9 us using f osc as the adc clock source; adcs ! = x11 ad21 1 2 6 us using adcrc as the adc clock source; adcs = x11 ad22 tcnv conversion time 11 tad set of go/done bit to clear of go/done bit ad23 tacq acquisition time 2 us ad24 thcd sample and hold capacitor disconnect time u s f osc based clock source us adcrc based clock source * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ad131 ad130 bsf adcon0, go q4 adc_clk adc data adres adif go sample old_data sampling stopped done new_data 987 3210 1 t cy 6 ad133 1 t cy ad132 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 428 preliminary ? 2016 microchip technology inc. figure 34-11: adc conversion timing (adc clock from adcrc) ad132 ad131 ad130 bsf adcon0, go q4 adc_clk adc data adres adif go sample old_data sampling stopped done new_data 9 7 3210 ad133 6 8 1 t cy 1 t cy note: if the adc clock source is selected as adcrc, a time of t cy is added before the adc clock starts. this allows the sleep instruction to be executed. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 429 pic16(l)f18326/18346 table 34-14: comparator specifications standard operating conditions (unless otherwise stated) v dd = 3.0v, t a = 25c see section 35.0 ?dc and ac characteristics graphs and charts? for operating characterization. param no. sym. characteristics min. typ. max. units comments cm01 v ioff input offset voltage 40 mv v icm = v dd /2 cm02 v icm input common mode voltage gnd v dd v cm03 cmrr common mode input rejection ratio 5 0d b cm04 c hyst comparator hysteresis 15 25 35 mv cm05 t resp (1) response time, rising edge 300 600 ns response time, falling edge 220 500 ns cm06* t mcv 2 vo (2) mode change to valid output 10 us * these parameters are characterized but not tested. note 1: response time measured with one comparator input at v dd /2, while the other input transitions from v ss to v dd . 2: a mode change includes changing any of the control register values, including module enable. table 34-15: digital-to-analog co nverter (dac) specifications standard operating conditions (unless otherwise stated) v dd = 3.0v, t a = 25c param no. sym. characteristics min. typ.? max. units comments dsb01 v lsb step size v dd /32 v dsb01 v acc absolute accuracy ? 0.5 lsb dsb03* r unit unit resistor value 6000 ? dsb04* t st settling time (1) 1 0 ? s * these parameters are characterized but not tested. ? data in typ column is at 3.0v, 25c unless otherwise stated. these parameters are for desi gn guidance only and are not tested. note 1: settling time measured while dacr<4:0> transitions from 00000 to 01111 . table 34-16: fixed voltage re ference (fvr) specifications standard operating conditions (unless otherwise stated) param. no. symbol characteristic min. typ. max. units conditions fvr01 v fvr 1 1x gain (1.024v nominal) -4 4% v dd ? 2.5v, -40c to 85c fvr02 v fvr 2 2x gain (2.048v nominal) -4 4 % v dd ? 2.5v, -40c to 85c fvr03 v fvr 4 4x gain (4.096v nominal) -5 5 % v dd ? 4.75v, -40c to 85c fvr04 t fvrst fvr start-up time ? s downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 430 preliminary ? 2016 microchip technology inc. figure 34-12: timer0 and time r1 external clock timings table 34-17: timer0 and timer1 external clock requirements standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ns with prescaler 10 ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ns with prescaler 10 ns 42* t t 0p t0cki period greater of: 20 or t cy + 40 n ns n = prescale value 45* t t 1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ns synchronous, with prescaler 15 ns asynchronous 30 ns 46* t t 1l t1cki low time synchronous, no prescaler 0.5 t cy + 20 ns synchronous, with prescaler 15 ns asynchronous 30 ns 47* t t 1p t1cki input period synchronous greater of: 30 or t cy + 40 n ns n = prescale value asynchronous 60 ns 48 f t 1 secondary oscillator input frequency range (oscillator enabled by setting bit t1oscen) 32.4 32.768 33.1 khz 49* tckez tmr 1 delay from external clock edge to timer increment 2 t osc 7 t osc timers in sync mode * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki t1cki 40 41 42 45 46 47 49 tmr0 or tmr1 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 431 pic16(l)f18326/18346 figure 34-13: capture/com pare/pwm timings (ccp) table 34-18: capture/compare/pwm requirements (ccp) standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions cc01* tccl ccpx input low time no prescaler 0.5t cy + 20 n s with prescaler 20 ns cc02* tcch ccpx input high time no prescaler 0.5t cy + 20 n s with prescaler 20 ns cc03* tccp ccpx input period 3t cy + 40 n ns n = prescale value * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. (capture mode) cc01 cc02 cc03 ccpx note: refer to figure 34-4 for load conditions. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 432 preliminary ? 2016 microchip technology inc. figure 34-14: clc pr opagation timing figure 34-15: eusart synchrono us transmission (master/slave) timing lcx_in[n] (1) clc output time clc input time lcx_out (1) clcx clcxinn clc module clc01 clc02 clc03 lcx_in[n] (1) clc output time clc input time lcx_out (1) clcx clcxinn clc module note 1: see figure 20-1, "clcx simplified block diagram" to identify specific clc signals. table 34-19: config urable logic cell (clc) characteristics standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ.? max. units conditions clc01* t clcin clc input time 7 os17 ns (note 1) clc02* t clc clc module input to output propagation time 2412 nsns v dd = 1.8v v dd > 3.6v clc03* t clcout clc output time rise time os18 (note 1) fall time os19 (note 1) clc04* f clcmax clc maximum switching frequency 32 f osc mhz * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: see table 34-10 for os17, os18 and os19 rise and fall times. us121 us121 us120 us122 ck dt note: refer to figure 34-4 for load conditions. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 433 pic16(l)f18326/18346 figure 34-16: eusart synchrono us receive (master/slave) timing table 34-20: eusart synchronous transmission requirements standard operating conditions (unless otherwise stated) param. no. symbol characteristic min. max. units conditions us120 t ck h2 dt v sync xmit (m aster and s lave ) clock high to data-out valid 8 0n s 3 . 0 v ? v dd ? 5.5v 100 ns 1.8v ? v dd ? 5.5v us121 t ckrf clock out rise time and fall time (master mode) 4 5n s 3 . 0 v ? v dd ? 5.5v 5 0n s 1 . 8 v ? v dd ? 5.5v us122 t dtrf data-out rise time and fall time 45 ns 3.0v ? v dd ? 5.5v 5 0n s 1 . 8 v ? v dd ? 5.5v us125 us126 ck dt note: refer to figure 34-4 for load conditions. table 34-21: eusart synchro nous receive requirements standard operating conditions (unless otherwise stated) param. no. symbol characteristic min. max. units conditions us125 t dt v2 ckl sync rcv (m aster and s lave ) data-setup before ck ? (dt hold time) 10 ns us126 t ck l2 dtl data-hold after ck ? (dt hold time) 15 ns downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 434 preliminary ? 2016 microchip technology inc. figure 34-17: spi master mode timing (cke = 0 , smp = 0 ) figure 34-18: spi master mode timing (cke = 1 , smp = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdosdi sp81 sp71 sp72 sp73 sp74 sp75, sp76 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 34-4 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdosdi sp81 sp71 sp72 sp74 sp75, sp76 sp78 sp80 msb sp79 sp73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 34-4 for load conditions. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 435 pic16(l)f18326/18346 figure 34-19: spi slav e mode timing (cke = 0 ) figure 34-20: spi slav e mode timing (cke = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi sp70 sp71 sp72 sp73 sp74 sp75, sp76 sp77 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in sp83 note: refer to figure 34-4 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi sp70 sp71 sp72 sp82 sp74 sp75, sp76 msb bit 6 - - - - - -1 lsb sp77 msb in bit 6 - - - -1 lsb in sp80 sp83 note: refer to figure 34-4 for load conditions. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 436 preliminary ? 2016 microchip technology inc. table 34-22: spi mode requirements standard operating conditions (unless otherwise stated) param. no. symbol characteristic min. typ.? max. units conditions sp70* t ss l2 sc h, t ss l2 sc l ss ? to sck ? or sck ? input 2.25*t cy n s sp71* t sc h sck input high time (slave mode) t cy + 20 ns sp72* t sc l sck input low time (slave mode) t cy + 20 ns sp73* t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ns sp74* t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ns sp75* t do r sdo data output rise time 10 25 ns 3.0v ? v dd ? 5.5v 2 55 0n s 1 . 8 v ? v dd ? 5.5v sp76* t do f sdo data output fall time 10 25 ns sp77* t ss h2 do zss ? to sdo output high-impedance 10 50 ns sp78* t sc r sck output rise time (master mode) 1 02 5n s 3 . 0 v ? v dd ? 5.5v 2 55 0n s 1 . 8 v ? v dd ? 5.5v sp79* t sc f sck output fall time (master mode) 10 25 ns sp80* t sc h2 do v, t sc l2 do v sdo data output valid after sck edge 50 ns 3.0v ? v dd ? 5.5v 1 4 5 n s 1 . 8 v ? v dd ? 5.5v sp81* t do v2 sc h, t do v2 sc l sdo data output setup to sck edge 1 tcy ns sp82* t ss l2 do v sdo data output valid after ss ? edge 5 0 n s sp83* t sc h2 ss h, t sc l2 ss h ss ?? after sck edge 1.5 t cy + 40 ns * these parameters are characterized but not tested. ? data in typ. column is at 3.0v, 25c unless otherwise stated. these parameters are for design guida nce only and are not tested. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 437 pic16(l)f18326/18346 figure 34-21: i 2 c bus start/stop bits timing figure 34-22: i 2 c bus data timing sp91 sp92 sp93 sclsda start condition stop condition sp90 note: refer to figure 34-4 for load conditions. table 34-23: i 2 c bus start/stop bits requirements standard operating conditions (unless otherwise stated) param. no. symbol characteristic min. typ. max. units conditions sp90* t su : sta start condition 100 khz mode 4700 ns only relevant for repeated start condition setup time 400 khz mode 600 sp91* t hd : sta start condition 100 khz mode 4000 ns after this period, the first clock pulse is generated hold time 400 khz mode 600 sp92* t su : sto stop condition 100 khz mode 4700 ns setup time 400 khz mode 600 sp93 t hd : sto stop condition 100 khz mode 4000 ns hold time 400 khz mode 600 * these parameters are characterized but not tested. sp90 sp91 sp92 sp100 sp101 sp103 sp106 sp107 sp109 sp109 sp110 sp102 scl sda in sda out note: refer to figure 34-4 for load conditions. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 438 preliminary ? 2016 microchip technology inc. table 34-24: i 2 c bus data requirements standard operating conditions (unless otherwise stated) param. no. symbol characteristic min. max. units conditions sp100* t high clock high time 100 khz mode 4.0 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy sp101* t low clock low time 100 khz mode 4.7 ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy sp102* t r sda and scl rise time 100 khz mode 1000 ns 400 khz mode 20 + 0.1c b 300 ns c b is specified to be from 10-400 pf sp103* t f sda and scl fall time 100 khz mode 250 ns 400 khz mode 20 + 0.1c b 250 ns c b is specified to be from 10-400 pf sp106* t hd : dat data input hold time 100 khz mode 0 ns 400 khz mode 0 0.9 ? s sp107* t su : dat data input setup time 100 khz mode 250 ns (note 2) 400 khz mode 100 ns sp109* t aa output valid from clock 100 khz mode 3500 ns (note 1) 400 khz mode ns sp110* t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s sp111 c b bus capacitive loading 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su : dat ?? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 439 pic16(l)f18326/18346 35.0 dc and ac characteristics graphs and charts charts and graphs are not available at this time. downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 440 preliminary ? 2016 microchip technology inc. 36.0 development support the pic ? microcontrollers (mcu) and dspic ? digital signal controllers (dsc) are supported with a full range of software and hardware development tools: integrated development environment - mplab ? x ide software compilers/assemblers/linkers - mplab xc compiler -mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families simulators - mplab x sim software simulator emulators - mplab real ice? in-circuit emulator in-circuit debuggers/programmers - mplab icd 3 - pickit? 3 device programmers - mplab pm3 device programmer low-cost demonstration/development boards, evaluation kits and starter kits third-party development tools 36.1 mplab x integrated development environment software the mplab x ide is a single, unified graphical user interface for microchip and third-party software, and hardware development tool that runs on windows ? , linux and mac os ? x. based on the netbeans ide, mplab x ide is an entirely new ide with a host of free software components and plug-ins for high- performance application development and debugging. moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. with complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, mplab x ide is flexible and friendly enough for new users. with the ability to support multiple tools on multiple projects with simultaneous debugging, mplab x ide is also suitable for the needs of experienced users. feature-rich editor: color syntax highlighting smart code completion makes suggestions and provides hints as you type automatic code formatting based on user-defined rules live parsing user-friendly, customizable interface: fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. call graph window project-based workspaces: multiple projects multiple tools multiple configurations simultaneous debugging sessions file history and bug tracking: local file history feature built-in support for bugzilla issue tracker downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 441 pic16(l)f18326/18346 36.2 mplab xc compilers the mplab xc compilers are complete ansi c compilers for all of microchips 8, 16, and 32-bit mcu and dsc devices. these compilers provide powerful integration capabilities, superior code optimization and ease of use. mplab xc compilers run on windows, linux or mac os x. for easy source level debugging, the compilers provide debug information that is optimized to the mplab x ide. the free mplab xc compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. mplab xc compilers include an assembler, linker and utilities. the assembler generates relocatable object files that can then be archived or linked with other relo- catable object files and archives to create an execut- able file. mplab xc compiler uses the assembler to produce its object file. notable features of the assem- bler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility 36.3 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code, and coff files for debugging. the mpasm assembler features include: integration into mplab x ide projects user-defined macros to streamline assembly code conditional assembly for multipurpose source files directives that allow complete control over the assembly process 36.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 36.5 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic dsc devices. mplab xc compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire device instruction set support for fixed-point and floating-point data command-line interface rich directive set flexible macro language mplab x ide compatibility downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 442 preliminary ? 2016 microchip technology inc. 36.6 mplab x sim software simulator the mplab x sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab x sim software simulator fully supports symbolic debugging using the mplab xc compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 36.7 mplab real ice in-circuit emulator system the mplab real ice in-circuit emulator system is microchips next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs all 8, 16 and 32-bit mcu, and dsc devices with the easy-to-use, powerful graphical user interface of the mplab x ide. the emulator is connected to the design engineers pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (rj-11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradeable through future firm- ware downloads in mplab x ide. mplab real ice offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 36.8 mplab icd 3 in-circuit debugger system the mplab icd 3 in-circuit debugger system is microchips most cost-effective, high-speed hardware debugger/programmer for microchip flash dsc and mcu devices. it debugs and programs pic flash microcontrollers and dspic dscs with the powerful, yet easy-to-use graphical user interface of the mplab ide. the mplab icd 3 in-circuit debugger probe is connected to the design engineers pc using a high- speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 36.9 pickit 3 in-circuit debugger/ programmer the mplab pickit 3 allows debugging and program- ming of pic and dspic flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab ide. the mplab pickit 3 is connected to the design engineers pc using a full- speed usb interface and can be connected to the tar- get via a microchip debug (rj-11) connector (compati- ble with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial programming? (icsp?). 36.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages, and a mod- ular, detachable socket assembly to support various package types. the icsp cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an mmc card for file storage and data applications. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 443 pic16(l)f18326/18346 36.11 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully functional systems. most boards include prototyping areas for adding custom circuitry and provide applica- tion firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demonstration/development board series of circuits, microchip has a line of evaluation kits and demonstra- tion software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. 36.12 third-party development tools microchip also offers a great collection of tools from third-party vendors. these tools are carefully selected to offer good value and unique functionality. device programmers and gang programmers from companies, such as softlog and ccs software tools from companies, such as gimpel and trace systems protocol analyzers from companies, such as saleae and total phase demonstration boards from companies, such as mikroelektronika, digilent ? and olimex embedded ethernet solutions from companies, such as ez web lynx, wiznet and iplogika ? downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 444 preliminary ? 2016 microchip technology inc. 37.0 packaging information 37.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead soic (7.50 mm) example 14-lead pdip (300 mil) example 14-lead soic (3.90 mm) example 1519017 3 e pic16lf18326 p pic16f18326 sl 1519017 3 e 14-lead tssop (4.4 mm) example yyww nnn xxxxxxxx f18326st 1519 017 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 445 pic16(l)f18326/18346 package marking information (continued) 20-lead pdip (300 mil) example xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn 20-lead soic (7.50 mm) example legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e pic16lf18346 so 1519017 pic16lf18346 p 1519017 3 e 3 e example pin 1 pin 1 ml 519017 pic16 f18326 3 e 16-lead uqfn (4x4x0.5mm) downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 446 preliminary ? 2016 microchip technology inc. package marking information (continued) 20-lead uqfn (4x4x0.5 mm) example pin 1 pin 1 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e pic16 f18346ml 519017 20-lead ssop (5.30 mm) example 16f18346 ss 1405017 3 e 3 e downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 447 pic16(l)f18326/18346 37.2 package details the following sections give the technical details of the packages. n e1 d note 1 12 3 e c eb a2 l a a1 b1 be downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 448 preliminary ? 2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 449 pic16(l)f18326/18346 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 450 preliminary ? 2016 microchip technology inc. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 451 pic16(l)f18326/18346 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 452 preliminary ? 2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 453 pic16(l)f18326/18346 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 454 preliminary ? 2016 microchip technology inc. b a 0.20 c 0.20 c 0.10 c a b (datum b) (datum a) c seating plane note 1 1 2 n 2x top view side view bottom view for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: note 1 1 2 n 0.10 c a b 0.10 c a b 0.10 c 0.08 c a1 microchip technolog drawing c04-257a sheet 1 of 2 16-lead ultra thin plastic quad flat, no lead package (jq) - 4x4x0.5 mm bod [uqfn] d e a (a3) 16x b e e 2 2x d2 e2 k l 16x downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 455 pic16(l)f18326/18346 microchip technolog drawing c04-257a sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: number of pins overall height terminal width overall width overall length terminal length exposed pad width exposed pad length terminal thickness pitch standoff units dimension limits a1 a b d e2 d2 a3 e l e n 0.65 bsc 0.127 ref 2.502.50 0.30 0.25 0.45 0.00 0.30 4.00 bsc 0.40 2.60 2.60 0.500.02 4.00 bsc millimeters min nom 16 2.702.70 0.50 0.35 0.550.05 max k- 0.20 - ref: reference dimension, usuall without tolerance, for information purposes onl. bsc: basic dimension. theoreticall exact value shown without tolerances. 1.2. 3. noes: pin 1 visual index feature ma var, but must be located within the hatched area. package is saw singulated dimensioning and tolerancing per asme y14.5m terminal-to-exposed-pad 16-lead ultra thin plastic quad flat, no lead package (jq) - 4x4x0.5 mm bod [uqfn] downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 456 preliminary ? 2016 microchip technology inc. recommended land pattern for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: silk screen dimension limits units c2 optional center pad width contact pad spacing optional center pad length contact pitch y2 x2 2.70 2.70 millimeters 0.65 bsc min e max 4.00 contact pad length (x16) contact pad width (x16) y1 x1 0.80 0.35 bsc: basic dimension. theoreticall exact value shown without tolerances. notes: 1. dimensioning and tolerancing per asme y14.5m microchip technolog drawing c04-2257a nom 16-lead ultra thin plastic quad flat, no lead package (jq) - 4x4x0.5 mm bod c2 c1 x2 y2 x1 e y1 c1 4.00 contact pad spacing 12 16 [uqfn] downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 457 pic16(l)f18326/18346 n e1 note 1 d 123 a a1 a2 l e b1 b e c eb downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 458 preliminary ? 2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 459 pic16(l)f18326/18346 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 460 preliminary ? 2016 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 461 pic16(l)f18326/18346 l l1 a2 c e b a1 a 12 note 1 e1 e d n downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 462 preliminary ? 2016 microchip technology inc. recommended land pattern microchip technolog drawing no. c04-2072b 20-lead plastic shrink small outline (ss) - 5.30 mm bod [ssop] for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: c g e x1 y1 silk screen dimension limits units c contact pad spacing contact pitch millimeters 0.65 bsc min e max 7.20 contact pad length (x20) contact pad width (x20) y1 x1 1.75 0.45 bsc: basic dimension. theoreticall exact value shown without tolerances. notes: 1. dimensioning and tolerancing per asme y14.5m g distance between pads 0.20 nom 0.45 0.65 downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 463 pic16(l)f18326/18346 b a 0.20 c 0.20 c 0.10 c a b (datum b) (datum a) c seating plane 1 2 n 2x top view side view bottom view for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: note 1 1 2 n 0.10 c a b 0.10 c a b 0.10 c 0.08 c a1 microchip technolog drawing c04-255a sheet 1 of 2 20-lead ultra thin plastic quad flat, no lead package (gz) - 4x4x0.5 mm bod [uqfn] d e a (a3) 20x b e 2x d2 e2 note 1 l k 20x downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 464 preliminary ? 2016 microchip technology inc. microchip technolog drawing c04-255a sheet 2 of 2 for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: number of terminals overall height terminal width overall width overall length terminal length exposed pad width exposed pad length terminal thickness pitch standoff units dimension limits a1 a b d e2 d2 a3 e l e n 0.50 bsc 0.127 ref 2.602.60 0.30 0.20 0.45 0.00 0.25 4.00 bsc 0.40 2.70 2.70 0.500.02 4.00 bsc millimeters min nom 20 2.802.80 0.50 0.30 0.550.05 max k- 0.20 - ref: reference dimension, usuall without tolerance, for information purposes onl. bsc: basic dimension. theoreticall exact value shown without tolerances. 1.2. 3. noes: pin 1 visual index feature ma var, but must be located within the hatched area. package is saw singulated dimensioning and tolerancing per asme y14.5m terminal-to-exposed-pad 20-lead ultra thin plastic quad flat, no lead package (gz) - 4x4x0.5 mm bod [uqfn] downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 465 pic16(l)f18326/18346 recommended land pattern for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: dimension limits units c2 optional center pad width contact pad spacing optional center pad length contact pitch y2 x2 2.80 2.80 millimeters 0.50 bsc min e max 4.00 contact pad length (x20) contact pad width (x20) y1 x1 0.80 0.30 bsc: basic dimension. theoreticall exact value shown without tolerances. notes: 1. dimensioning and tolerancing per asme y14.5m microchip technolog drawing c04-2255a nom 20-lead ultra thin plastic quad flat, no lead package (gz) - 4x4x0.5 mm bod [uqfn] silk screen 12 20 c1 c2 e x1 y1 g1 y2 x2 c1 contact pad spacing 4.00 contact pad to center pad (x20) g1 0.20 downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 466 preliminary ? 2016 microchip technology inc. appendix a: data sheet revision history revision a (04/2016) initial release of the document. downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 467 pic16(l)f18326/18346 the microchip website microchip provides online support via our website at www.microchip.com . this website is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the website contains the following information: product support C data sheets and errata, application notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip website at www.microchip.com . under support, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the website at: http://www.microchip.com/support downloaded from: http:/// pic16(l)f18326/18346 ds40001839a-page 468 preliminary ? 2016 microchip technology inc. product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16f18326, pic16lf18326, pic16f18346, pic16lf18346. tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1) temperature range: i= - 4 0 ? c to +85 ? c(industrial) e= - 4 0 ? c to +125 ? c (extended) package: (2) jq = 16-lead uqfn (4x4) gz = 20-lead uqfn (4x4) p= p d i p st = tssop sl = 14-lead soic so = 20-lead soic ss = ssop pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16lf18326- e/p extended temperature pdip package b) pic16lf18346- e/so extended temperature, soic package note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. 2: small form-factor packaging options may be available. please check www.microchip.com/packaging for small-form factor package availability, or contact your loca l sales office. [x] (1) tape and reel option - downloaded from: http:/// ? 2016 microchip technology inc. preliminary ds40001839a-page 469 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0462-0 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal me thods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outsi de the operating specifications c ontained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:/// ds40001839a-page 470 preliminary ? 2016 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - dongguan tel: 86-769-8702-9880 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - karlsruhe tel: 49-721-625370 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 worldwide sales and service 07/14/15 downloaded from: http:/// |
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