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low cost, high speed, rail-to-rail amplifiers ad8051/ad8052/ad8054 rev. j information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features high speed and fast settling on 5 v 110 mhz, ?3 db bandwidth (g = +1) (ad8051/ad8052) 150 mhz, ?3 db bandwidth (g = +1) (ad8054) 145 v/s slew rate 50 ns settling time to 0.1% single-supply operation output swings to within 25 mv of either rail input voltage range: ?0.2 v to +4 v; v s = 5 v video specifications (g = +2) 0.1 db gain flatness: 20 mhz; r l = 150 differential gain/phase: 0.03%/0.03 low distortion ?80 dbc total harmonic @ 1 mhz, r l = 100 outstanding load drive capability drives 45 ma, 0.5 v from supply rails (ad8051/ad8052) drives 50 pf capacitive load (g = +1) (ad8051/ad8052) low power: 2.75 ma/amplifier (ad8054) low power: 4.4 ma/amplifier (ad8051/ad8052) applications active filters analog-to-digital drivers clock buffer consumer video professional cameras ccd imaging systems cd/dvd roms pin connections (top views) 8 7 6 5 1 2 3 4 nc ?in +in nc nc ad8051 nc = no connect +v s v out ?v s 01062-001 1 2 3 5 4 ?in +in ad8051 +? +v s v out ?v s 01062-002 figure 1. soic-8 (r) fi gure 2. sot-23-5 (rj) 8 7 6 5 1 2 3 4 + ? + ? out1 ?in1 +in1 out ?in2 ad8052 +in2 +v s ?v s 01062-003 v+ +in b out b out d +in d v? +in c out c ad8054 +in a out a 1 2 3 4 5 6 7 14 13 12 11 10 9 8 ?in a ?in b ?in d ?in c 0 1062-004 figure 3. soic (r-8) and msop (rm-8) figure 4. soic (r-14) and tssop (ru-14) frequency (mhz) 4.5 0 50 3.0 1.5 1.0 0.5 4.0 3.5 2.0 2.5 5.0 peak-to-peak output voltage swing (thd 0.5%) (v) 0.1 1 10 v s = 5v g = ?1 r f = 2k ? r l = 2k ? 0 1062-005 figure 5. low distortion rail-to-rail output swing general description the ad8051 (single), ad8052 (dual), and ad8054 (quad) are low cost, high speed, voltage feedback amplifiers. the amplifiers operate on +3 v, +5 v, or 5 v supplies at low supply current. they have true single-supply capability with an input voltage range extending 200 mv below the negative rail and within 1 v of the positive rail. despite their low cost, the ad8051/ad8052/ad8054 provide excellent overall performance and versatility. the output voltage swings to within 25 mv of each rail, providing maximum output dynamic range with excellent overdrive recovery. the ad8051/ad8052/ad8054 are well suited for video electronics, cameras, video switchers, or any high speed portable equipment. low distortion and fast settling make them ideal for active filter applications. the ad8051/ad8052 in the 8-lead soic, the ad8052 in the msop, the ad8054 in the 14-lead soic, and the 14-lead tssop packages are available in the extended temperature range of ?40c to +125c.
important links for the ad8051_8052_8054 * last content update 10/12/2013 09:18 pm similar products & parametric selection tables find similar products by operating parameters high speed amplifiers selection table documentation an-649: using the analog devices active filter design tool an-581: biasing and decoupling op amps in single supply applications an-402: replacing output clamping op amps with input clamping amps an-417: fast rail-to-rail operational amplifiers ease design constraints in low voltage high speed systems mt-060: choosing between voltage feedback and current feedback op amps mt-059: compensating for the effects of input capacitance on vfb and cfb op amps used in current-to-voltage converters mt-058: effects of feedback capacitance on vfb and cfb op amps mt-056: high speed voltage feedback op amps mt-053: op amp distortion: hd, thd, thd + n, imd, sfdr, mtpr mt-052: op amp noise figure: dont be mislead mt-050: op amp total output noise calculations for second-order system mt-049: op amp total output noise calculations for single-pole system mt-048: op amp noise relationships: 1/f noise, rms noise, and equivalent noise bandwidth mt-047: op amp noise mt-033: voltage feedback op amp gain and bandwidth mt-032: ideal voltage feedback (vfb) op amp a stress-free method for choosing high-speed op amps for the ad8051 an-356: users guide to applying and measuring operational amplifier specifications ug-127: universal evaluation board for high speed op amps in sot-23-5/sot-23-6 packages ug-101: evaluation board user guide for the ad8052 an-357: operational integrators ug-129: evaluation board user guide ug-128: universal evaluation board for dual high speed op amps in soic packages for the ad8054 ug-111: universal evaluation board for quad, high speed op amps offered in 14-lead soic packages ug-020: universal evaluation board for quad high speed op amps offered in 14-lead tssop packages design tools, models, drivers & software dbm/dbu/dbv calculator analog filter wizard 2.0 power dissipation vs die temp adisimopamp? opamp stability ad8051/ad8052/ad8054 spice macro-model evaluation kits & symbols & footprints view the evaluation boards and kits page for the ad8051 view the evaluation boards and kits page for the ad8052 view the evaluation boards and kits page for the ad8054 symbols and footprints for the ad8051 symbols and footprints for the ad8052 symbols and footprints for the ad8054 design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ad8051 ad8052 ad8054 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ad8051/ad8052/ad8054 rev. j | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? pin connections (top views) ......................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 9 ? thermal resistance ...................................................................... 9 ? maximum power dissipation ..................................................... 9 ? esd caution .................................................................................. 9 ? typical performance characteristics ........................................... 10 ? theory of operation ...................................................................... 16 ? circuit description .................................................................... 16 ? application information ................................................................ 17 ? overdrive recovery ................................................................... 17 ? driving capacitive loads .......................................................... 17 ? layout considerations ............................................................... 18 ? active filters ............................................................................... 18 ? analog-to-digital and digital-to-analog applications ........ 19 ? sync stripper ............................................................................... 20 ? single-supply composite video line driver ......................... 20 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 23 ? revision history 7/09rev. i to rev. j changes to figure 22 ...................................................................... 12 12/08rev. h to rev. i change to settling time to 0.1% parameter, table 1 ................... 3 updated outline dimensions ....................................................... 20 12/07rev. g to rev. h changes to applications .................................................................. 1 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 23 5/06rev. f to rev. g updated format .................................................................. universal changes to features, applications, and general description ..... 1 changes to figure 15 ...................................................................... 12 changes to the ordering guide .................................................... 22 9/04rev. e to rev. f changes to ordering guide ............................................................. 7 changes to figure 15 ...................................................................... 15 3/04rev. d to rev. e changes to general description ..................................................... 2 changes to specifications ................................................................. 3 changes to ordering guide ............................................................. 6 2/03rev. c to rev. d changes to general description ..................................................... 1 changes to specifications ................................................................. 3 changes to absolute maximum ratings ........................................ 6 1/03rev. b to rev. c changes to general description ..................................................... 1 changes to pin connections ............................................................ 1 changes to specifications ................................................................. 2 changes to absolute maximum ratings ........................................ 9 changes to figure 2 ........................................................................... 9 changes to ordering guide ............................................................. 9 updated outline dimensions ........................................................ 20
ad8051/ad8052/ad8054 rev. j | page 3 of 24 specifications @ t a = 25c, v s = 5 v, r l = 2 k to 2.5 v, unless otherwise noted. table 1. ad8051a/ad8052a ad8054a parameter conditions min typ max min typ max unit dynamic performance ?3 db small signal bandwidth g = +1, v out = 0.2 v p-p 70 110 80 150 mhz g = ?1, +2, v out = 0.2 v p-p 50 60 mhz bandwidth for 0.1 db flatness g = +2, v out = 0.2 v p-p, r l = 150 to 2.5 v r f = 806 (ad8051a/ ad8052a) 20 mhz r f = 200 (ad8054a) 12 mhz slew rate g = ?1, v out = 2 v step 100 145 140 170 v/s full power response g = +1, v out = 2 v p-p 35 45 mhz settling time to 0.1% g = ?1, v out = 2 v step 50 40 ns noise/distortion performance total harmonic distortion 1 f c = 5 mhz, v out = 2 v p-p, g = +2 ?67 ?68 db input voltage noise f = 10 khz 16 16 nv/hz input current noise f = 10 khz 850 850 fa/hz differential gain error (ntsc) g = +2, r l = 150 to 2.5 v 0.09 0.07 % r l = 1 k to 2.5 v 0.03 0.02 % differential phase error (ntsc) g = +2, r l = 150 to 2.5 v 0.19 0.26 degrees r l = 1 k to 2.5 v 0.03 0.05 degrees crosstalk f = 5 mhz, g = +2 ?60 ?60 db dc performance input offset voltage 1.7 10 1.7 12 mv t min ? t max 25 30 mv offset drift 10 15 v/c input bias current 1.4 2.5 2 4.5 a t min ? t max 3.25 4.5 a input offset current 0.1 0.75 0.2 1.2 a open-loop gain r l = 2 k to 2.5 v 86 98 82 98 db t min ? t max 96 96 db r l = 150 to 2.5 v 76 82 74 82 db t min ? t max 78 78 db input characteristics input resistance 290 300 k input capacitance 1.4 1.5 pf input common-mode voltage range ?0.2 to +4 ?0.2 to +4 v common-mode rejection ratio v cm = 0 v to 3.5 v 72 88 70 86 db
ad8051/ad8052/ad8054 rev. j | page 4 of 24 ad8051a/ad8052a ad8054a parameter conditions min typ max min typ max unit output characteristics output voltage swing r l = 10 k to 2.5 v 0.015 to 4.985 0.03 to 4.975 v r l = 2 k to 2.5 v 0.1 to 4.9 0.025 to 4.975 0.125 to 4.875 0.05 to 4.95 v r l = 150 to 2.5 v 0.3 to 4.625 0.2 to 4.8 0.55 to 4.4 0.25 to 4.65 v output current v out = 0.5 v to 4.5 v 45 30 ma t min ? t max 45 30 ma short-circuit current sourcing 80 45 ma sinking 130 85 ma capacitive load drive g = +1 (ad8051/ad8052) 50 pf g = +2 (ad8054) 40 pf power supply operating range 3 12 3 12 v quiescent current/amplifier 4.4 5 2.75 3.275 ma power supply rejection ratio v s = 1 v 70 80 68 80 db operating temperature range rj-5 ?40 +85 c rm-8, r-8, ru-14, r-14 ?40 +125 ?40 +125 c 1 refer to figure 19.
ad8051/ad8052/ad8054 rev. j | page 5 of 24 @ t a = 25c, v s = 3 v, r l = 2 k to 1.5 v, unless otherwise noted. table 2. ad8051a/ad8052a ad8054a parameter conditions min typ max min typ max unit dynamic performance ?3 db small signal bandwidth g = +1, v out = 0.2 v p-p 70 110 80 135 mhz g = ?1, +2, v out = 0.2 v p-p 50 65 mhz bandwidth for 0.1 db flatness g = +2, v out = 0.2 v p-p, r l = 150 to 2.5 v r f = 402 (ad8051a/ ad8052a) 17 mhz r f = 200 (ad8054a) 10 mhz slew rate g = ?1, v out = 2 v step 90 135 110 150 v/s full power response g = +1, v out = 1 v p-p 65 85 mhz settling time to 0.1% g = ?1, v out = 2 v step 55 55 ns noise/distortion performance total harmonic distortion 1 f c = 5 mhz, v out = 2 v p-p, g = ?1, r l = 100 to 1.5 v ?47 ?48 db input voltage noise f = 10 khz 16 16 nv/hz input current noise f = 10 khz 600 600 fa/hz differential gain error (ntsc) g = +2, v cm = 1 v r l = 150 to 1.5 v 0.11 0.13 % r l = 1 k to 1.5 v 0.09 0.09 % differential phase error (ntsc) g = +2, v cm = 1 v r l = 150 to 1.5 v 0.24 0.3 degrees r l = 1 k to 1.5 v 0.10 0.1 degrees crosstalk f = 5 mhz, g = +2 ?60 ?60 db dc performance input offset voltage 1.6 10 1.6 12 mv t min ? t max 25 30 mv offset drift 10 15 v/c input bias current 1.3 2.6 2 4.5 a t min ? t max 3.25 4.5 a input offset current 0.15 0.8 0.2 1.2 a open-loop gain r l = 2 k 80 96 80 96 db t min ? t max 94 94 db r l = 150 74 82 72 80 db t min ? t max 76 76 db input characteristics input resistance 290 300 k input capacitance 1.4 1.5 pf input common-mode voltage range ?0.2 to +2 ?0.2 to +2 v common-mode rejection ratio v cm = 0 v to 1.5 v 72 88 70 86 db
ad8051/ad8052/ad8054 rev. j | page 6 of 24 ad8051a/ad8052a ad8054a parameter conditions min typ max min typ max unit output characteristics output voltage swing r l = 10 k to 1.5 v 0.01 to 2.99 0.025 to 2.98 v r l = 2 k to 1.5 v 0.0.75 to 2.9 0.02 to 2.98 0.1 to 2.9 0.35 to 2.965 v r l = 150 to 1.5 v 0.2 to 2.75 0.125 to 2.875 0.35 to 2.55 0.15 to 2.75 v output current v out = 0.5 v to 2.5 v 45 25 ma t min ? t max 45 25 ma short-circuit current sourcing 60 30 ma sinking 90 50 ma capacitive load drive g = +1 (ad8051/ad8052) 45 pf g = +2 (ad8054) 35 pf power supply operating range 3 12 3 12 v quiescent current/amplifier 4.2 4.8 2.625 3.125 ma power supply rejection ratio v s = 0.5 v 68 80 68 80 db operating temperature range rj-5 ?40 +85 c rm-8, r-8, ru-14, r-14 ?40 +125 ?40 +125 c 1 refer to figure 19.
ad8051/ad8052/ad8054 rev. j | page 7 of 24 @ t a = 25c, v s = 5 v, r l = 2 k to ground, unless otherwise noted. table 3. ad8051a/ad8052a ad8054a parameter conditions min typ max min typ max unit dynamic performance ?3 db small signal bandwidth g = +1, v out = 0.2 v p-p 70 110 85 160 mhz g = ?1, +2, v out = 0.2 v p-p 50 65 mhz bandwidth for 0.1 db flatness g = +2, v out = 0.2 v p-p, r l = 150 , r f = 1.1 k (ad8051a/ ad8052a) 20 mhz r f = 200 (ad8054a) 15 mhz slew rate g = ?1, v out = 2 v step 105 170 150 190 v/s full power response g = +1, v out = 2 v p-p 40 50 mhz settling time to 0.1% g = ?1, v out = 2 v step 50 40 mhz noise/distortion performance total harmonic distortion f c = 5 mhz, v out = 2 v p-p, g = +2 ?71 ?72 db input voltage noise f = 10 khz 16 16 nv/hz input current noise f = 10 khz 900 900 fa/hz differential gain error (ntsc) g = +2, r l = 150 0.02 0.06 % r l = 1 k 0.02 0.02 % differential phase error (ntsc) g = +2, r l = 150 0.11 0.15 degrees r l = 1 k 0.02 0.03 degrees crosstalk f = 5 mhz, g = +2 ?60 ?60 db dc performance input offset voltage 1.8 11 1.8 13 mv t min ? t max 27 32 mv offset drift 10 15 v/c input bias current 1.4 2.6 2 4.5 a t min ? t max 3.5 4.5 a input offset current 0.1 0.75 0.2 1.2 a open-loop gain r l = 2 k 88 96 84 96 db t min ? t max 96 96 db r l = 150 78 82 76 82 db t min ? t max 80 80 db input characteristics input resistance 290 300 k input capacitance 1.4 1.5 pf input common-mode voltage range ?5.2 to +4 ?5.2 to +4 v common-mode rejection ratio v cm = ?5 v to +3.5 v 72 88 70 86 db output characteristics output voltage swing r l = 10 k ?4.98 to +4.98 ?4.97 to +4.97 v r l = 2 k ?4.85 to +4.85 ?4.97 to +4.97 ?4.8 to +4.8 ?4.9 to +4.9 v r l = 150 ?4.45 to +4.3 ?4.6 to +4.6 ?4.0 to +3.8 ?4.5 to +4.5 v output current v out = ?4.5 v to +4.5 v 45 30 ma t min ? t max 45 30 ma short-circuit current sourcing 100 60 ma sinking 160 100 ma capacitive load drive g = +1 (ad8051/ad8052) 50 pf g = +2 (ad8054) 40 pf
ad8051/ad8052/ad8054 rev. j | page 8 of 24 ad8051a/ad8052a ad8054a parameter conditions min typ max min typ max unit power supply operating range 3 12 3 12 v quiescent current/amplifier 4.8 5.5 2.875 3.4 ma power supply rejection ratio v s = 1 68 80 68 80 db operating temperature range rj-5 ?40 +85 c rm-8, r-8, ru-14, r-14 ?40 +125 ?40 +125 c
ad8051/ad8052/ad8054 rev. j | page 9 of 24 absolute maximum ratings table 4. parameter ratings supply voltage 12.6 v internal power dissipation 1 soic packages observe power derating curves sot-23 package observe power derating curves msop package observe power derating curves tssop package observe power derating curves input voltage (common mode) v s differential input voltage 2.5 v output short-circuit duration observe power derating curves storage temperature range (r) ?65c to +150c operating temperature range (a grade) ?40c to +125c lead temperature (soldering 10 sec) 300c 1 see table 5. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance specification is for device in free air. table 5. thermal resistance package type ja unit 8-lead soic 125 c/w 5-lead sot-23 180 c/w 8-lead msop 150 c/w 14-lead soic 90 c/w 14-lead tssop 120 c/w maximum power dissipation the maximum power that can be safely dissipated by the ad8051/ad8052/ad8054 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150c. temporarily exceeding this limit can cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175c for an extended period can result in device failure. while the ad8051/ad8052/ad8054 are internally short- circuit protected, this cannot be sufficient to guarantee that the maximum junction temperature (150c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves. ambient temperature (c) ?55 0 2.0 1.5 1.0 0.5 5 maximum power dissipation (w) 2.5 msop-8 soic-8 sot-23-5 soic-14 tssop-14 ?35 ?15 15 35 55 75 95 115 01062-006 figure 6. maximum power dissipation vs. temperature for ad8051/ad8052/ad8054 esd caution
ad8051/ad8052/ad8054 rev. j | page 10 of 24 typical performance characteristics frequency (mhz) 3 2 ?7 ?1 ?4 ?5 ?6 1 0 ?3 ?2 500 normalized gain (db) 0.1 1 10 100 g = +10 r f = 2k ? g = +2 r f = 2k ? g = +5 r f = 2k ? g = +1 r f = 0 v s = 5v gain as shown r f as shown r l = 2k ? v out = 0.2v p-p 01062-007 figure 7. ad8051/ad8052 normalized gain vs. frequency; v s = 5 v frequency (mhz) 3 2 ?7 100 ?1 ?4 ?5 ?6 1 0 ?3 ?2 gain (db) v s = +3v v s = +5v v s = 5v v s as shown g=+1 r l =2k ? v out =0.2vp-p 0.1 1 10 500 01062-008 figure 8. ad8051/ad8052 gain vs. frequency vs. supply frequency (mhz) 3 2 ?7 0.1 500 100 ?1 ?4 ?5 ?6 1 0 ?3 ?2 ?40c +25c +85c gain (db) 1 10 v s = 5v g=+1 r l =2k ? v out =0.2vp-p temperature as shown 01062-009 figure 9. ad8051/ad8052 gain vs. frequency vs. temperature 1m frequency (hz) 3 0 ?3 ?6 ?7 100k ?5 ?4 ?2 ?1 5 4 2 1 500m normalized gain (db) 10m 100m g = +1 r f = 0 g = +2 r f = 2k ? g = +10 r f = 2k ? g = +5 r f = 2k ? v s = 5v gain as shown r f as shown r l = 5k ? v out = 0.2v p-p 01062-010 figure 10. ad8054 normalized gain vs. frequency; v s = 5 v +3v +5v 5v +3v +5v 6 2 ?3 100k 5 4 3 1 0 ?1 ?2 ?4 frequency (hz) 500m gain (db) g=+1 r l =2k ? c l = 5pf v out =0.2vp-p 5v 1m 10m 100m 01062-011 figure 11. ad8054 gain vs. frequency vs. supply 4 0 ?4 3 2 1 ?1 ?2 ?3 ?5 100 frequency (mhz) ?40c +25c +85c gain (db) 500 10 1 v s = 5v r l = 2k ? to 2.5v c l = 5pf g = +1 v out = 0.2v p-p 01062-012 figure 12. ad8054 gain vs . frequency vs. temperature
ad8051/ad8052/ad8054 rev. j | page 11 of 24 frequency (mhz) 6.3 6.2 5.3 0.1 100 5.9 5.6 5.5 5.4 6.1 6.0 5.7 5.8 gain flatness (db) 1 10 01062-013 v s = 5v g = +2 r l = 150 ? r f = 806 ? v out = 0.2v p-p figure 13. ad8051/ad8052 0.1 db gain flatness vs. frequency; g = +2 frequency (mhz) 9 8 ?1 5 2 1 0 7 6 3 4 gain (db) v s = +5v v out = 2v p-p v s as shown g = +2 r f = 2k ? r l = 2k ? v out as shown v s = 5v v out = 4v p-p 0.1 1 10 100 500 01062-014 figure 14. ad8051/ad8052 large signal frequency response; g = +2 frequency (mhz) 80 70 ?20 40 10 0 ?10 60 50 20 30 0 ?45 ?90 ?135 ?180 gain phase open-loop gain (db) phase margin (degrees) 50 phase margin 0.01 0.1 1 10 100 500 v s = 5v r l = 2k ? 01062-015 figure 15. ad8051/ad8052 open-loop gain and phase vs. frequency 6.3 5.9 5.4 6.2 6.1 6.0 5.8 5.7 5.6 5.5 1100 10 frequency (mhz) gain flatness (db) 5.3 01062-016 v s = 5v r f = 200 ? r l = 150 ? g = +2 v out = 0.2v p-p figure 16. ad8054 0.1 db gain flatness vs. frequency; g = +2 frequency (mhz) 9 8 ?1 5 2 1 0 7 6 3 4 gain (db) 0.1 1 10 100 500 01062-017 v s = 5v v out = 4v p-p v s as shown g = +2 r f = 2k ? r l = 2k ? v out as shown v s = +5v v out = 2v p-p figure 17. ad8054 large signal frequency response; g = +2 gain phase 180 135 90 45 0 frequency (hz) 80 70 ?20 40 10 0 ?10 60 50 20 30 open-loop gain (db) phase margin (degrees) 45 phase margin 30k 100k 1m 10m 100m 500m v s = 5v r l = 2k ? c l = 5pf 01062-018 figure 18. ad8054 open-loop gain and phase margin vs. frequency
ad8051/ad8052/ad8054 rev. j | page 12 of 24 fundamental frequency (mhz) ? 20 ?30 ?110 ?70 ?80 ?90 ?100 ?50 ?60 ?40 total harmonic distortion (dbc) 123 4 5 6 7 8 9 1 0 v out = 2v p-p v s = 3v, g = ?1 r f = 2k ? , r l = 100 ? v s = 5v, g = +2 r f = 2k ? , r l = 100 ? v s = 5v, g = +1 r l = 100 ? v s = 5v, g = +1 r l = 2k ? v s = 5v, g = +2 r f = 2k ? , r l = 2k ? 01062-019 figure 19. total harmonic distortion output voltage (v p-p) 05.0 4.5 ? 30 ?40 ?120 ?80 ?90 ?100 ?110 ?60 ?70 ?50 ?130 ?140 worst harmonic (dbc) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 v s = 5v r l = 2k ? g = +2 10mhz 5mhz 1mhz 01062-020 figure 20. worst harmonic vs. output voltage 0.05 0.00 ?0.05 ?0.10 ?0.15 ?0.20 ?0.25 0.10 modulating ramp level (ire) 0.10 ?0.06 0.08 0.06 0.04 0.02 0.00 ?0.02 ?0.04 ntsc subscriber (3.58mhz) differential gain error (%) differential phase error (degrees) 0 102030405060708090100 0 102030405060708090100 r l = 150 ? r l = 1k ? r l = 150 ? r l = 1k ? v s = 5v, g = +2 r f = 2k ? , r l as shown v s = 5v, g = +2 r f = 2k ? , r l as shown 01062-021 figure 21. ad8051/ad8052 differential gain and phase errors 1000 100 1 10 10m 100 voltage noise (nv/ hz) 1k 10k 100k 1m 10 frequency (hz) v s = 5v 0 1062-022 figure 22. input voltage noise vs. frequency 100 10 0.1 1 10 10m 100 current noise (pa/ hz) 1k 10k 100k 1m frequency (hz) v s = 5v 01062-023 figure 23. input current noise vs. frequency 0.10 ?0.10 0.05 0.00 ?0.05 0.2 0.1 0.0 ?0.1 ?0.2 ?0.3 0.3 modulating ramp level (ire) ntsc subscriber (3.58mhz) differential gain error (%) differential phase error (degrees) r l = 150 ? r l = 1k ? r l = 150 ? r l = 1k ? v s = 5v, g = +2 r f = 2k ? , r l as shown v s = 5v, g = +2 r f = 2k ? , r l as shown 1 st 2 nd 3 rd 4 th 5 th 6 th 7 th 8 th 9 th 10 th 11 th 1 st 2 nd 3 rd 4 th 5 th 6 th 7 th 8 th 9 th 10 th 11 th 01062-024 figure 24. ad8054 differential gain and phase errors
ad8051/ad8052/ad8054 rev. j | page 13 of 24 frequency (mhz) ? 10 ?20 0.1 500 100 ?50 ?80 ?90 ?100 ?30 ?40 ?70 ?60 crosstalk (db) 11 0 01062-025 v s = 5v r f = 2k ? r l = 2k ? v out = 2v p-p figure 25. ad8052 crosstalk (o utput-to-output) vs. frequency frequency (mhz) 0 ?10 ?100 ?40 ?70 ?80 ?90 ?20 ?30 ?60 ?50 cmrr (db) v s = 5v 0.03 0.1 1 10 100 500 01062-026 figure 26. cmrr vs. frequency frequency (mhz) 100.000 3.100 0.100 0.031 0.010 31.000 10.000 0.310 1.000 output resistance ( ? ) v s =5v g = +1 0.1 1 10 100 500 01062-027 figure 27. closed-loop outp ut resistance vs. frequency ? 10 ?50 ?100 ?20 ?30 ?40 ?60 ?70 ?80 ?90 ?110 frequency (mhz) crosstalk (db) r l = 100 ? r l = 1k ? v s = 5v r f = 1k ? r l =as shown v out = 2v p-p 0.1 1 10 100 500 01062-028 figure 28. ad8054 crosstalk (o utput-to-output) vs. frequency frequency (mhz) 20 ?10 ?30 ?50 ?70 10 0 ?20 ?40 ?60 ?80 ?psrr +psrr psrr (db) v s = 5v 0.01 0.1 1 10 100 500 01062-029 figure 29. psrr vs. frequency input step (v p-p) 60 0 40 30 20 10 50 70 settling time to 0.1% (ns) ad8051/ad8052 ad8054 0.5 1.0 1.5 2.0 v s = 5v g = ?1 r l = 2k ? 01062-030 figure 30. settling time vs. input step
ad8051/ad8052/ad8054 rev. j | page 14 of 24 load current (ma) 1.0 0.3 0 0.9 0.4 0.2 0.1 0.7 0.5 0.8 0.6 output saturation voltage (v) v s = 5v v oh = +85c v oh = +25c v oh = ?40c v ol = +85c v ol = +25c v ol = ?40c 80 857570656055504540353025 20 1510 50 01062-031 figure 31. ad8051/ad8052 output saturation voltage vs. load current 100 90 60 80 70 open-loop gain (db) output voltage (v) r l = 2k ? r l = 150 ? v s = 5v 05.0 4.54.0 3.5 3.02.52.01.5 1.00.5 01062-032 figure 32. open-loop gain vs. output voltage load current (ma) 1.000 0.500 0 0.875 0.750 0.250 0.125 0.625 0.375 output saturation voltage (v) 302724 21 181512 9630 +5v ? v oh (+125c) +5v ? v oh (+25c) +5v ? v oh (?40c) v ol (+125c) v ol (+25c) v ol (?40c) 01062-033 v s = 5v figure 33. ad8054 output saturation voltage vs. load current
ad8051/ad8052/ad8054 rev. j | page 15 of 24 1.5 volts v in = 0.1v p-p g = +1 r l = 2k ? v s = 3v 20mv 20ns 0 1062-034 figure 34. 100 mv step response, g = +1 2.5 2.6 2.4 volts v s = 5v g = +1 r l = 2k ? 50mv 20ns 01062-035 figure 35. ad8051/ad8052 200 mv step response; v s = 5 v, g = +1 volts 3.5 2.5 1.5 0.5 4.5 v in = 1v p-p g = +2 r l = 2k ? v s = 5v 500mv 20ns 0 1062-036 figure 36. large signal step response; v s = 5 v, g = +2 5.0 2.5 volts v s = 5v g = ?1 r f = 2k ? r l = 2k ? 1v 2s 0 1062-037 figure 37. output swing; g = ?1, r l = 2 k 2.55 2.50 2.45 volts v s = 5v g = +1 r l = 2k ? 50mv 40ns 01062-038 figure 38. ad8054 100 mv step response; v s = 5 v, g = +1 4 3 2 1 ?1 ?2 ?3 ?4 volts v s = 5v g = +1 r l = 2k ? 20ns 1v 01062-039 figure 39. large signal step response; v s = 5 v, g = +1
ad8051/ad8052/ad8054 rev. j | page 16 of 24 theory of operation circuit description the ad8051/ad8052/ad8054 are fabricated on the analog devices, inc. proprietary extra-fast complementary bipolar (xfcb) process, which enables the construction of pnp and npn transistors with similar fts in the 2 ghz to 4 ghz region. the process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. these features allow the construction of high frequency, low distortion amplifiers with low supply currents. this design uses a differential output input stage to maximize bandwidth and headroom (see figure 40). the smaller signal swings required on the first stage outputs (nodes sip, sin) reduce the effect of nonlinear currents due to junction capacitances and improve the distortion per- formance. this design achieves harmonic distortion of ?80 dbc @ 1 mhz into 100 with v out = 2 v p-p (gain = +1) on a single 5 v supply. the inputs of the device can handle voltages from ?0.2 v below the negative rail to within 1 v of the positive rail. exceeding these values do not cause phase reversal; however, the input esd devices begin to conduct if the input voltages exceed the rails by greater than 0.5 v. during this overdrive condition, the output stays at the rail. the rail-to-rail output range of the ad8051/ad8052/ad8054 is provided by a complementary common emitter output stage. high output drive capability is provided by injecting all output stage predriver currents directly into the bases of the output devices q8 and q36. biasing of q8 and q36 is accomplished by i8 and i5, along with a common-mode feedback loop (not shown). this circuit topology allows the ad8051/ad8052 to drive 45 ma of output current and allows the ad8054 to drive 30 ma of output current with the outputs within 0.5 v of the supply rails. i10 r39 v ee i2 i3 q25 q51 r23 r27 i9 q36 i5 v ee c3 c9 i8 v cc i11 i7 r3 r21 r5 q3 sip sin c7 q4 r15 r2 r26 q50 q22 q21 q27 q7 q8 q23 q31 q39 q13 q1 q24 q47 q11 q2 q5 q40 v out v cc v in p v in n v ee 01062-045 figure 40. ad8051/ad8052 simplified schematic
ad8051/ad8052/ad8054 rev. j | page 17 of 24 application information overdrive recovery overdrive of an amplifier occurs when the output and/or input range is exceeded. the amplifier must recover from this over- drive condition. as shown in figure 41, the ad8051/ad8052/ ad8054 recover within 60 ns from negative overdrive and within 45 ns from positive overdrive. volts v s = 5v g = +5 r f = 2k ? r l = 2k ? v/div as shown 100ns input 1v/div output 2v/div 01062-040 figure 41. overdrive recovery driving capacitive loads consider the ad8051/ad8052 in a closed-loop gain of +1 with +v s = 5 v and a load of 2 k in parallel with 50 pf. figure 42 and figure 43 show their frequency and time domain responses, respectively, to a small-signal excitation. the capacitive load drive of the ad8051/ad8052/ad8054 can be increased by adding a low value resistor in series with the load. figure 44 and figure 45 show the effect of a series resistor on the capaci- tive drive for varying voltage gains. as the closed-loop gain is increased, the larger phase margin allows for larger capacitive loads with less peaking. adding a series resistor with lower closed-loop gains accomplishes the same effect. for large capacitive loads, the frequency response of the amplifier is dominated by the roll-off of the series resistor and the load capacitance. frequency (mhz) 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 gain (db) ?12 0.1 500 100 11 0 01062-041 v s = 5v g = +1 r l = 2k ? c l = 50pf v out = 200mv p-p figure 42. ad8051/ad8052 closed-loop frequency response; c l = 50 pf 2.60 2.55 2.50 2.45 2.40 volts v s = 5v g = +1 r l = 2k ? c l = 50pf 50mv 100ns 0 1062-042 figure 43. ad8051/ad8052 200 mv step response; c l = 50 pf 10000 1000 1 capacitive load (pf) 100 10 a cl (v/v) v s = 5v 30% overshoot r s = 3 ? r s = 0 ? 123456 v out c l r s r f r g 50? v in 100mv step 01062-043 figure 44. ad8051/ad8052 capacitive load drive vs. closed-loop gain 1000 100 10 capacitive load (pf) a cl (v/v) 123456 v out c l r s r f r g 50? v in 100mv step v s = 5v 30% overshoot r s = 0 ? r s = 10 ? 01062-044 figure 45. ad8054 capacitive load drive vs. closed-loop gain
ad8051/ad8052/ad8054 rev. j | page 18 of 24 layout considerations the specified high speed performance of the ad8051/ad8052/ ad8054 requires careful attention to board layout and component selection. proper rf design techniques and low parasitic component selection are necessary. the pcb should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path. the ground plane should be removed from the area near the input pins to reduce parasitic capacitance. chip capacitors should be used for supply bypassing. one end should be connected to the ground plane and the other within 3 mm of each power pin. an additional large (4.7 f to 10 f) tantalum electrolytic capacitor should be connected in parallel, but not necessarily so close, to supply current for fast, large signal changes at the output. the feedback resistor should be located close to the inverting input pin to keep the parasitic capacitance at this node to a minimum. parasitic capacitance of less than 1 pf at the inverting input can significantly affect high speed performance. stripline design techniques should be used for long signal traces (greater than about 25 mm). these should be designed with a characteristic impedance of 50 or 75 and be properly terminated at each end. active filters active filters at higher frequencies require wider bandwidth op amps to work effectively. excessive phase shift produced by lower frequency op amps can significantly affect active filter performance. figure 46 shows an example of a 2 mhz biquad bandwidth filter that uses three op amps of an ad8054. such circuits are sometimes used in medical ultrasound systems to lower the noise bandwidth of the analog signal before analog-to-digital conversion. note that the unused amplifiers inputs should be tied to ground. 12 13 14 2 1 6 5 7 9 10 8 ad8054 ad8054 3 ad8054 r6 1k ? r4 2k ? r3 2k ? r5 2k ? r2 2k ? r1 3k ? c1 50pf c2 50pf v in band-pass filter output 01062-046 figure 46. 2 mhz biquad band-pass filter using ad8054 the frequency response of the circuit is shown in figure 47. frequency (hz) 0 ?10 ?20 ?30 ?40 gain (db) 10k 100k 1m 10m 100m 01062-047 figure 47. frequency response of 2 mhz band-pass biquad filter
ad8051/ad8052/ad8054 rev. j | page 19 of 24 analog-to-digital and digital-to-analog applications figure 50 is a schematic showing the ad8051 used as a driver for an ad9201 , a 10-bit, 20 msps, dual analog-to-digital converter. this converter is designed to convert i and q signals in communications systems. in this application, only the i channel is being driven. the i channel is enabled by applying a logic high to select (pin 13). the ad8051 is running from a dual supply and is configured for a gain of +2. the input signal is terminated in 50 and the output is 2 v p-p, which is the maximum input range of the ad9201. the 22 series resistor limits the maximum current that flows and helps to lower the distortion of the adc. the ad9201 has differential inputs for each channel. these are designated the a and b inputs. the b inputs of each channel are connected to vref (pin 22), which supplies a positive reference of 2.5 v. each of the b inputs has a small low-pass filter that also helps to reduce distortion. the output of the op amp is ac-coupled into ina-i (pin 16) via two parallel capacitors to provide good high frequency and low frequency coupling. the 1 k resistor references the signal to vref that is applied to inb-i. thus, ina-i swings both positive and negative with respect to the bias voltage applied to inb-i. with the sampling clock running at 20 msps, the analog-to- digital output was analyzed with a digital analyzer. two input frequencies were used, 1 mhz and 9.5 mhz, which is just short of the nyquist frequency. these signals were well filtered to minimize any harmonics. figure 48 shows the fft response of the adc for the case of a 1 mhz analog input. the sfdr is 71.66 db, and the analog-to- digital is producing 8.8 enob (effective number of bits). when the analog frequency was raised to 9.5 mhz, the sfdr was reduced to ?60.18 db and the adc operated with 8.46 enobs as shown in figure 49. the inclusion of the ad8051 in the circuit did not worsen the distortion performance of the ad9201. part# 0 fclk fund vin thd snr sinad enob sfdr 2nd 3rd 4th 5th 6th 7th 8th 9th fftsize 8192 20.0mhz 998.5khz ?0.51db ?68.13 54.97 54.76 8.80 71.66 ?74.53 ?76.06 ?76.35 ?79.05 ?80.36 ?75.08 ?88.12 ?77.87 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 amplitude (db) frequency (mhz) 0 12 34567 8910 fund 2nd 5th 6th 7th 8th 9th 4th 3rd 01062-049 figure 48. fft plot for ad8051 driving the ad9201 at 1 mhz part# 0 fclk fund vin thd snr sinad enob sfdr 2nd 3rd 4th 5th 6th 7th 8th 9th fftsize 8192 20.0mhz 9.5mhz ?0.44db ?57.08 54.65 52.69 8.46 60.18 ?60.18 ?60.23 ?82.01 ?78.83 ?81.28 ?77.28 ?84.54 ?92.78 10 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 amplitude (db) frequency (mhz) 0 12 34567 8910 fund 2nd 5th 6th 7th 8th 4th 3rd 01062-050 figure 49. fft plot for ad8051 driving the ad9201 at 9.5 mhz ad8051 +5v vref avdd select ina-i 10pf clock sleep d9 d1 d2 d3 d4 d5 d6 d7 d0 dvdd avss refsense ad9201 dvss chip?select inb-i reft-i refb-i refb -q reft-q inb-q ina-q d8 data out 10pf ?5v 10pf 10pf 15 16 17 18 19 20 21 22 23 24 25 26 27 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0.1f 10f +5v +v dd 10f 0.1f 0.1f 0.1f 10f 0.1f 10f 0.1f 10f 0.1f 0.1f 0.1f +5v 22 ? 22? 22? 22? 22 ? 1k ? 1k ? 0.33f 0.01f 1k ? 10f 0.1f 10f 0.1f 50? 3 2 7 4 6 01062-048 figure 50. the ad8051 driving an ad9201, a 10-bit, 20 msps analog-to-digital converter
ad8051/ad8052/ad8054 rev. j | page 20 of 24 sync stripper synchronizing pulses are sometimes carried on video signals so as not to require a separate channel to carry the synchronizing information. however, for some functions, such as analog-to- digital conversion, it is not desirable to have the sync pulses on the video signal. these pulses reduce the dynamic range of the video signal and do not provide any useful information for such a function. a sync stripper removes the synchronizing pulses from a video signal while passing all the useful video information. figure 51 shows a practical single-supply circuit that uses only a single ad8051 . it is capable of directly driving a reverse terminated video line. ad8051 0.1f 10f + 100 ? to a/d 3v or 5v v blank ground 0.4v v ideo with sync ground v ideo without sync r2 1k ? r1 1k? v in 3 2 7 4 6 0.8v (or 2 v blank ) 0 1062-051 figure 51. sync stripper the video signal plus sync is applied to the noninverting input with the proper termination. the amplifier gain is set to 2 via the two 1 k resistors in the feedback circuit. a bias voltage must be applied to r1 so that the input signal has the sync pulses stripped at the proper level. the blanking level of the input video pulse is the desired place to remove the sync information. this level is multiplied by 2 by the amplifier. this level must be at ground at the output for the sync stripping action to take place. since the gain of the amplifier from the input of r1 to the output is ?1, a voltage equal to 2 v blank must be applied to make the blanking level come out at ground. single-supply composite video line driver many composite video signals have their blanking level at ground and have video information that is both positive and negative. such signals require dual-supply amplifiers to pass them. however, by ac level shifting, a single-supply amplifier can be used to pass these signals. the following complications can arise from such techniques. signals of bounded peak-to-peak amplitude that vary in duty cycle require larger dynamic swing capacity than their (bounded) peak-to-peak amplitude after they are ac-coupled. as a worst case, the dynamic signal swing will approach twice the peak-to- peak value. the two conditions that define the maximum dynamic swing requirements are a signal that is mostly low but goes high with a duty cycle that is a small fraction of a percent, and the other extreme defined by the opposite condition. the worst case of composite video is not quite this demanding. one bounding condition is a signal that is mostly black for an entire frame but has a white (full amplitude) minimum width spike at least once in a frame. the other extreme is for a full white video signal. the blanking intervals and sync tips of such a signal have negative-going excursions in compliance with the composite video specifications. the combination of horizontal and vertical blanking intervals limit such a signal to being at the highest (white) level for a maximum of about 75% of the time. as a result of the duty cycles between the two extremes previously presented, a 1 v p-p composite video signal that is multiplied by a gain of 2 requires about 3.2 v p-p of dynamic voltage swing at the output for an op amp to pass a composite video signal of arbitrarily varying duty cycle without distortion. some circuits use a sync tip clamp to hold the sync tips at a relatively constant level to lower the amount of dynamic signal swing required. however, these circuits can have artifacts, such as sync tip compression, unless they are driven by a source with a very low output impedance. the ad8051/ad8052/ad8054 have adequate signal swing when running on a single 5 v supply to handle an ac-coupled composite video signal. the input to the circuit in figure 52 is a standard composite (1 v p-p) video signal that has the blanking level at ground. the input network level shifts the video signal by means of ac coupling. the noninverting input of the op amp is biased to half of the supply voltage. the feedback circuit provides unity gain for the dc-biasing of the input and provides a gain of 2 for any signals that are in the video bandwidth. the output is ac-coupled and terminated to drive the line. the capacitor values were selected for providing minimum tilt or field time distortion of the video signal. these values would be required for video that is considered to be studio or broadcast quality. however, if a lower consumer grade of video, sometimes referred to as consumer video, is all that is desired, the values and the cost of the capacitors can be reduced by as much as a factor of five with minimum visible degradation in the picture. ad8051 5v + 10f 4.99k ? 220f + 1000f 0.1f 10k ? + 47f 4.99k ? 0.1f 10f + composite video in 3 2 7 4 6 r g 1k ? r f 1k ? r t 75 ? r l 75 ? v out r bt 75 ? 0 1062-052 figure 52. single-supply co mposite video line driver
ad8051/ad8052/ad8054 rev. j | page 21 of 24 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ab 060606-a 14 8 7 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 8.75 (0.3445) 8.55 (0.3366) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 45 figure 53. 14-lead standard small outline package [soic_n] narrow body (r-14) dimensions shown in millimeters and (inches) pin 1 1.60 bsc 2.80 bsc 1.90 bsc 0.95 bsc 5 12 3 4 0.22 0.08 10 5 0 0.50 0.30 0.15 max seating plane 1.45 max 1.30 1.15 0.90 2.90 bsc 0.60 0.45 0.30 compliant to jedec standards mo-178-a a figure 54. 5-lead small outline transistor package [sot-23] (rj-5) dimensions shown in millimeters
ad8051/ad8052/ad8054 rev. j | page 22 of 24 compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0 .95 0 .85 0 .75 figure 55. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 56. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-153-ab-1 061908-a 8 0 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 0.75 0.60 0.45 coplanarity 0.10 seating plane figure 57. 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters
ad8051/ad8052/ad8054 rev. j | page 23 of 24 ordering guide model temperature range package de scription package option branding ad8051ar ?40c to +125c 8-lead soic_n r-8 ad8051ar-reel ?40c to +125c 8-lead soic_n, 13" tape and reel r-8 ad8051ar-reel7 ?40c to +125c 8-lead soic_n, 7" tape and reel r-8 ad8051arz 1 ?40c to +85c 8-lead soic_n r-8 ad8051arz-reel 1 ?40c to +85c 8-lead soic_n, 13" tape and reel r-8 ad8051arz-reel7 1 ?40c to +85c 8-lead soic_n, 7" tape and reel r-8 ad8051art-r2 ?40c to +85c 5-lead sot-23, 7" tape and reel rj-5 h2a AD8051ART-REEL ?40c to +85c 5-lead sot-23, 13" tape and reel rj-5 h2a AD8051ART-REEL7 ?40c to +85c 5-lead sot-23, 7" tape and reel rj-5 h2a ad8051artz-r2 1 ?40c to +85c 5-lead sot-23, 7" tape and reel rj-5 h06 ad8051artz-reel 1 ?40c to +85c 5-lead sot-23, 13" tape and reel rj-5 h06 ad8051artz-reel7 1 ?40c to +85c 5-lead sot-23, 7" tape and reel rj-5 h06 ad8052ar ?40c to +125c 8-lead soic_n r-8 ad8052ar-reel ?40c to +125c 8-lead soic_n, 13" tape and reel r-8 ad8052ar-reel7 ?40c to +125c 8-lead soic_n, 7" tape and reel r-8 ad8052arz 1 ?40c to +125c 8-lead soic_n r-8 ad8052arz-reel 1 ?40c to +125c 8-lead soic_n, 13" tape and reel r-8 ad8052arz-reel7 1 ?40c to +125c 8-lead soic_n, 7" tape and reel r-8 ad8052arm ?40c to +125c 8-lead msop rm-8 h4a ad8052arm-reel ?40c to +125c 8-lead msop, 13" tape and reel rm-8 h4a ad8052arm-reel7 ?40c to +125c 8-lead msop, 7" tape and reel rm-8 h4a ad8052armz 1 ?40c to +125c 8-lead msop rm-8 h4a# ad8052armz-reel7 1 ?40c to +125c 8-lead msop, 7" tape and reel rm-8 h4a# ad8054ar ?40c to +125c 14-lead soic_n r-14 ad8054ar-reel ?40c to +125c 14-lead soic_n, 13" tape and reel r-14 ad8054ar-reel7 ?40c to +125c 14-lead soic_n, 7" tape and reel r-14 ad8054arz 1 ?40c to +125c 14-lead soic_n r-14 ad8054arz-reel 1 ?40c to +125c 14-lead soic_n, 13" tape and reel r-14 ad8054arz-reel7 1 ?40c to +125c 14-lead soic_n, 7" tape and reel r-14 ad8054aru ?40c to +125c 14-lead tssop ru-14 ad8054aru-reel ?40c to +125c 14-lead tssop, 13" tape and reel ru-14 ad8054aru-reel7 ?40c to +125c 14-lead tssop, 7" tape and reel ru-14 ad8054aruz 1 ?40c to +125c 14-lead tssop ru-14 ad8054aruz-reel 1 ?40c to +125c 14-lead tssop, 13" tape and reel ru-14 ad8054aruz-reel7 1 ?40c to +125c 14-lead tssop, 7" tape and reel ru-14 1 z = rohs compliant part. # denotes lead-free product may be top or bottom marked.
ad8051/ad8052/ad8054 rev. j | page 24 of 24 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d01062-0-7/09(j)

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