View LTC1450LCGTRPBF_8631710.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 ltc1450/ltc1450l parallel input, 12-bit rail-to-rail micropower dacs in ssop guaranteed monotonic buffered true rail-to-rail voltage output 12-bit resolution 3v operation (ltc1450l) i cc : 250 a typ 5v operation (ltc1450) i cc : 400 a typ parallel 12-bit or 8 + 4-bit double buffereddigital input internal reference output buffer configurable to gain of 1 or 2 configurable as a multiplying dac internal power-on reset maximum dnl error: 0.5lsb the ltc 1450/ltc1450l are complete single supply, rail- to-rail voltage output, 12-bit digital-to-analog converters(dacs) in a 24-pin ssop or pdip package. they include an output buffer amplifier, reference and a double buffered parallel digital interface. the ltc1450 operates from a 4.5v to 5.5v supply. the output can be pin strapped for 4.095v or 2.048v full-scale. it has a 2.048v internal reference. the ltc1450l operates from a 2.7v to 5.5v supply. the output can be pin strapped for 2.5v or 1.22v full-scale. it has a 1.22v internal reference. the ltc1450/ltc1450l offer true stand-alone perfor- mance. in addition, the reference output, high and low reference inputs and gain setting resistor are brought to pins for maximum flexibility. features descriptio n u , ltc and lt are registered trademarks of linear technology corporation. digital calibration industrial process control automatic test equipment arbitrary function generators battery-powered data conversion products feedback control loops and gain control applicatio n s u typical applicatio n u reflo gnd ltc1450: 0v to 4.095v ltc1450l: 0v to 2.5v ltc1450: 5v ltc1450l: 3v to 5v 12-bit dac refhi refout x1/x2 ltc1450 ltc1450l 1450/50l ta01 v out v cc upper 4-bit input latch d11 (msb) d8d7 data in from microprocessor data bus from microprocessor decode logic from system reset d0 (lsb) + reference ltc1450: 2.048v ltc1450l: 1.22v 12-bit dac latch power-on reset ldac clr wr csmsb cslsb lower 8-bit input latch code 0 dnl error (lsb) 0.5 0.0 0.5 1024 2048 2560 1450/50l ta02 512 1536 3072 3584 4095 differential nonlinearity vs input code downloaded from: http:///
2 ltc1450/ltc1450l absolute m axi m u m ratings w ww u package/order i n for m atio n w u u v cc to gnd .............................................. 0.5v to 7.5v logic inputs to gnd ................................ 0.5v to 7.5v v out .............................................. 0.5v to v cc + 0.5v refout, reflo, refhi, x1/x2 ..... 0.5v to v cc + 0.5v maximum junction temperature .......................... 125 c operating temperature range commercial ........................................... 0 c to 70 c industrial ......................................... 40 c to 85 c storage temperature range ................ 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c order part number consult factory for military grade parts. t jmax = 125 c, ja = 95 c/ w (g) t jmax = 125 c, ja = 58 c/ w (n) symbol parameter conditions min typ max units dac resolution 12 bits dnl differential nonlinearity guaranteed monotonic (note 1) 0.5 lsb inl integral nonlinearity t a = 25 c 3.5 lsb (note 1) 4.0 lsb v os offset error t a = 25 c 12 mv 18 mv v os tc offset error temperature coefficient 15 v/ c v fs full-scale voltage using internal reference, ltc1450, t a = 25 c 4.065 4.095 4.125 v using internal reference, ltc1450 4.045 4.095 4.145 v external 2.048v reference, ltc1450 4.075 4.095 4.115 v using internal reference, ltc1450l, t a = 25 c 2.470 2.500 2.530 v using internal reference, ltc1450l 2.460 2.500 2.540 v external 1.22v reference, ltc1450l 2.480 2.500 2.520 v v fs tc full-scale voltage temperature coefficient using internal reference, ltc1450 0.10 lsb/ c using external reference, ltc1450/ltc1450l 0.02 lsb/ c using internal reference, ltc1450l 0.10 lsb/ c reference output (refout) reference output voltage ltc1450l 1.195 1.220 1.245 v ltc1450 2.008 2.048 2.088 v reference output temperature coefficient 0.08 lsb/ c reference line regulation 0.7 2l s b / v reference load regulation 0 i out 100 a, ltc1450l 0.6 3.0 lsb ltc1450 0.2 1.5 lsb short-circuit current refout shorted to gnd 80 ma 1 2 3 4 5 6 7 8 9 10 11 12 top view g package 24-lead plastic ssop n package 24-lead plastic pdip 24 23 22 21 20 19 18 17 16 15 14 13 wr cslsb csmsb (lsb) d0 d1 d2 d3 d4 d5 d6 d7 d8 ldac clr x1/x2 v out v cc refout refhi reflo gnd d11(msb) d10 d9 ltc1450cgltc1450cn ltc1450ig ltc1450in ltc1450lcg ltc1450lcn ltc1450lig ltc1450lin v cc = 4.5v to 5.5v (ltc1450), 2.7v to 5.5v (ltc1450l), v out unloaded, refout = refhi, reflo = gnd = x1/x2, t a = t min to t max , unless otherwise noted. electrical characteristics downloaded from: http:///
3 ltc1450/ltc1450l v cc = 4.5v to 5.5v (ltc1450), 2.7v to 5.5v (ltc1450l), v out unloaded, refout = refhi, reflo = gnd = x1/x2, t a = t min to t max , unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units reference input (reflo = gnd) refhi input range v refhi v cc ?1.5v v cc /2 v refhi input resistance 81 83 0 k refhi input capacitance 15 pf power supplyv cc positive supply voltage for specified performance, ltc1450l 2.7 5.5 v ltc1450 4.5 5.5 v i cc supply current 4.5v v cc 5.5v (note 4) ltc1450 300 400 620 a 2.7v v cc 5.5v (note 4) ltc1450l 150 250 500 a op amp dc performance short-circuit current low v out shorted to gnd 100 ma short-circuit current high v out shorted to v cc 120 ma output impedance to gnd input code = 0 40 120 ac performance voltage output slew rate (note 2) 0.5 1.0 v/ s voltage output settling time (notes 2, 3) to 0.5lsb 14 s digital feedthrough ldac = 1 5 (nv)(s) ac feedthrough refhi = 1khz, 2v p? ?5 db sinad signal-to-noise + distortion refhi = 1khz, 2v p? (code: all 1?) 85 db digital inputsv ih digital input high voltage v cc = 3v, ltc1450l 2.2 v v cc = 5v, ltc1450 2.4 v v il digital input low voltage v cc = 3v, ltc1450l 0.8 v v cc = 5v, ltc1450 0.8 v v lth logic threshold voltage ltc1450l v cc /2 v i leak digital input leakage v cc = 5v, v in = gnd to v cc ?0 10 a c in digital input capacitance guaranteed by design. not subject to test 10 pf downloaded from: http:///
4 ltc1450/ltc1450l electrical characteristics v cc = 4.5v to 5.5v (ltc1450), v cc = 2.7v to 3.6v (ltc1450l), t a = t min to t max , unless otherwise noted. typical perfor m a n ce characteristics u w load current (ma) 4.4 ltc1450 minimum supply voltage (v) ltc1450l minimum supply voltage (v) 4.8 5.0 5.4 5.8 0.01 1 10 100 1450/50l g01 4.0 0.1 5.24.6 4.2 5.6 2.8 3.2 3.4 3.8 4.22.4 3.63.0 2.6 4.0 ? v out < 1lsb ltc1450 ltc1450l minimum supply voltagevs load current temperature ( c) ?5 350 supply current ( a) 360 380 390 400 450420 ?5 25 45 125 1450/50l g02 370 430 440410 ?5 5 65 85 105 v cc = 5.5v v cc = 4.5v v cc = 5v logic input voltage (v) 0 0.5 1.0 1.5 2.0 3.0 4.0 3.5 4.5 supply current (ma) 6 8 1450/50l g03 42 0 7 53 1 2.5 5.0 v cc = 5v all logic inputs tied together ltc1450 ltc1450l ltc1450 supply currentvs temperature supply currentvs logic input voltage the denotes specifications which apply over the full operating temperature range.note 1: nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to code 4095 (full-scale).note 2: load is 5k in parallel with 100pf. note 3: dac switched all 1? and the code corresponding to v os(max) for the part.note 4: digital inputs at 0v or v cc . note 5: digital inputs swing 10% to 90% of v cc , t r = t f = 5ns and timing measurements are from v cc /2. symbol parameter conditions min typ max units switching characteristics (note 5) t cs cs (msb or lsb) pulse width 40 ns t wr wr pulse width 40 ns t cws cs to wr setup 0n s t cwh cs to wr hold 0n s t dws data valid to wr setup v cc = 4.5v to 5.5v (ltc1450) 40 15 ns v cc = 2.7v to 3.6v (ltc1450l) 40 15 ns v cc = 5v (ltc1450l) 10 ns t dwh data valid to wr hold v cc = 4.5v to 5.5v (ltc1450) 0 1 0 n s v cc = 2.7v to 3.6v (ltc1450l) 0 1 0 n s v cc = 5v (ltc1450l) 5 ns t ldac ldac pulse width 40 ns t clr clr pulse width 40 ns downloaded from: http:///
5 ltc1450/ltc1450l typical perfor m a n ce characteristics u w logic input voltage (v) 0 0.3 0.6 0.9 1.2 supply current ( a) 1200 1600 1450/50l g04 800400 0 1400 1000 600200 1.5 1.8 2.1 2.4 2.7 3.0 v cc = 3v all logic inputs tied together ltc1450l supply currentvs logic input voltage ltc1450 output swingvs load resistance load resistance ( ) 10 output swing (v) 100 1k 10k 1450/50l g05 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 full scale r l tied to gnd zero scale r l tied to v cc v cc = 5v output sink current (ma) output pull-down voltage (mv) 1000 100 10 1 0.1 0.0001 0.1 1 10 100 1450/50l g06 0.001 0.01 125 c ?5 c 25 c ltc1450 pull-down voltage vsoutput sink current capability ltc1450 output offset voltagevs temperature ltc1450integral nonlinearity (inl) temperature ( c) ?5 0 output offset voltage (mv) 0.5 1.5 2.0 2.5 5.03.5 ?5 25 45 125 1450/50l g07 1.0 4.0 4.53.0 ?5 5 65 85 105 ltc1450differential nonlinearity (dnl) code 0 0.2 dnl error (lsb) 0 0.2 1024 2048 2560 1450/50l g08 512 1536 3072 3584 4095 code 0 ? error (lsb) 0 2 1024 2048 2560 1450/50l g09 512 1536 3072 3584 4095 ltc1450broadband output noise ltc1450 total harmonicdistortion + noise vs frequency frequency (hz) 20 psrr (db) 30 50 60 80 90 10 100 10k 10m 1450/50l g10 10 1 1k 7040 0 refout v out code = fff h power supply rejectionvs frequency frequency (hz) total harmonic distortion + noise (db) 40 50 60 ?0 80 90 100 100 10k 100k 1450/50l g11 1k v cc = 5v v refhi = 2v p-p v out = 4v p-p 5ms/div 1mv/div 1450/50l g12 code = fff h x1/x2 = gnd bw = 3hz to 1.2mhz total = 0.35mv rms downloaded from: http:///
6 ltc1450/ltc1450l typical perfor m a n ce characteristics u w ltc1450large-scale settling (falling) 2 s/div 0v 5v 1450/50l g15 3v2v 4v1v 0v data inputs falling edge v out no load ltc1450 digital feedthrough 2 s/div 0v 4v 1450/50l g18 all data inputs toggling v out = 5mv/div v out(dc) = 4v r l = no load 500ns/div 20mv/div 1450/50l g13 5v0v v out ldac ltc1450 midscale transitiondata = 2048 to 2047 ltc1450large-scale settling (rising) 2 s/div 0v 5v 1450/50l g14 4v3v 2v 1v 0v data inputs rising edge v out no load 5 s/div 0v 5v 1450/50l g16 data in 000 h to fff h v out 1mv/div output load 5k//10pf output voltage full-scale settling output voltage zero-scale settling 5 s/div 0v 5v 1450/50l g17 data in fff h to 000 h v out 1mv/div output load 5k//10pf downloaded from: http:///
7 ltc1450/ltc1450l pi n fu n ctio n s uuu an input code of (000 h ) will connect the positive input of the output buffer to this end. can be used to offset the zeroscale above ground. refhi (pin 18): upper input terminal of the dac? internal resistor string. typically connected to refout. an inputcode of (fff h ) will connect the positive input of the output buffer to 1lsb from this end.refout (pin 19): output of the internal 2.048v/1.22v reference. typically connected to refhi to drive internaldac resistor string. v cc (pin 20): positive power supply input. 4.5v v cc 5.5v (ltc1450) and 2.7v v cc 5.5v (ltc1450l). requires a bypass capacitor to ground.v out (pin 21): buffered dac output. x1/x2 (pin 22): gain setting resistor pin. connect to gnd for g = 2 or to v out for g = 1. should always be tied to a low impedance source, such as ground or v out , to ensure stability of the output buffer when driving capacitive loads. clr (pin 23): clear input (asynchronous active low). a low on this pin asynchronously resets all internal latchesto 0s. ldac (pin 24): load dac (asynchronous active low). used to asynchronously transfer the contents of the inputlatches to the dac latches which updates the output voltage. the rising edge latches the data into the dac latches. if held low the dac latches are transparent and data from the input latches will immediately update v out . wr (pin 1): write input (active low). used with csmsb and/or cslsb to load data into the input latches. while wrand csmsb and/or cslsb are held low the enabled input latches are transparent. the rising edge of wr will latch data into all input latches. cslsb (pin 2): chip select least significant byte (active low). used with wr to load data into the eight lsb inputlatches. while wr and cslsb are held low the eight lsb input latches are transparent. the rising edge will latch data into the eight lsb input latches. can be connected to csmsb for simultaneous loading of both sets of input latches on a 12-bit bus. csmsb (pin 3): chip select most significant byte (active low). used with wr to load data into the four msb inputlatches. while wr and csmsb are held low the four msb input latches are transparent. the rising edge will latch data into the four msb input latches. can be connected to cslsb for simultaneous loading of both sets of input latches on a 12-bit bus. d0 to d7 (pins 4 to 11): input data for the least significant byte. loaded into lsb input latch when wr = 0 andcslsb = 0. d8, d9, d10, d11 (pins 12, 13, 14, 15): input data for the most significant byte. loaded into msb input latch whenwr = 0 and csmsb = 0. can be connected to d0 to d3 for multiplexed operation on an 8-bit bus. gnd (pin 16): ground. reflo (pin 17): lower input terminal of the dac? inter- nal resistor string. typically connected to analog ground. downloaded from: http:///
8 ltc1450/ltc1450l digital i n terface truth table u clr csmsb cslsb wr ldac function h h l l h loads the eight lsbs into the input latch hhl h latches the eight lsbs into the input latch hh l h latches the eight lsbs into the input latch h l h l h loads the four msbs into the input latch hlh h latches the four msbs into the input latch h h l h latches the four msbs into the input latch h h h h l loads the input latch data into the dac latch hhhh latches the input latch data into the dac latch h l l l l loads input data into dac latches (latches transparent) hlll latches input data into dac latches l x x x x all zeros loaded into input and dac latches ti m i n g diagra m w u w block diagra m w csmsb wr ldac ltc1450/50l ?td01 t cs cslsb data t cs t wr t wr t cws t cwh t dws t ldac dac update t dwh data valid data valid + reference ltc1450: 2.048v ltc1450l: 1.22v dac 12-bit dac latch d11 (msb) d10 d9 d8 d6 d4 d2 d0 (lsb) d7 d5 d3 d1 upper 4-bit input latch power-on reset lower 8-bit input latch ldac clr csmsb wr cslsb refout v cc 20 19 18 17 22 2116 45678910 11 12 13 14 15 2423 31 2 refhi reflo x1/x 2 v out gnd ltc1450/50l ?bd downloaded from: http:///
9 ltc1450/ltc1450l dac code 1450/50l ?f01 output voltage negative offset 0v figure 1. effect of negative offset integral nonlinearity (inl): end-point inl is the maxi- mum deviation from a straight line passing through theend points of the dac transfer curve. because the part operates from a single supply and the output cannot go below zero, the linearity is measured between full scale and the code corresponding to the maximum offset specification. the inl error at a given input code is calculated as follows: inl = [v out ?v os ?(v fs ?v os )(code/4095)]/lsb v out = the output voltage of the dac measured at the given input code differential nonlinearity (dnl): dnl is the difference between the measured change and the ideal one lsbchange between any two adjacent codes. the dnl error between any two codes is calculated as follows: dnl = ( ? v out ?lsb)/lsb ? v out = the measured voltage difference between two adjacent codes digital feedthrough: the glitch that appears at the analog output caused by ac coupling from the digital inputs whenthey change state. the area of the glitch is specified in (nv) ( s). resolution (n): resolution is defined as the number of digital input bits (n). it defines the number of dac outputstates (2 n ) that divide the full-scale range. the resolution does not imply linearity.full-scale voltage (v fs ): this is the output of the dac when all bits are set to 1.voltage offset error (v os ): the theoretical voltage at the output when the dac is loaded with all zeros. the outputamplifier can have a true negative offset, but because the part is operated from a single supply, the output cannot go below zero. if the offset is negative, the output will remain near 0v resulting in the transfer curve shown in figure 1. the offset of the part is measured at the code that corre- sponds to the maximum offset specification: v os = v out ?[(code)(v fs )/(2 n ?1)] least significant bit (lsb): one lsb is the ideal voltage difference between two successive codes. lsb = (v fs ?v os )/(2 n ?1) = (v fs ?v os )/4095 nominal lsbs: ltc1450 lsb = 4.095v/4095 = 1mv ltc1450l lsb = 2.5v/4095 = 0.610mv defi itio s uu downloaded from: http:///
10 ltc1450/ltc1450l parallel interface the data on the input of the dac is loaded into the dac?input latches when chip select (cslsb and/or csmsb) and wr are at a logic low. the data that is loaded into the input latches will depend on which of the chip selects are at a logic low (see digital interface truth table). if wr and cslsb are both low and csmsb is high, then only data on the eight lsbs (d0 to d7) is loaded into the input latches. similarly if wr and csmsb are both low and cslsb is high then only data on the four msbs (d8 to d11) is loaded into the input latches. data is loaded into boththe least significant data bits (d0 to d7) and the most significant bits (d8 to d11) at the same time if wr, cslsb and csmsb are low. the input data is latched into the input latches on the risingedge of either the wr or one of the chip selects. the wr transition high will latch the data in both input latches. a rising edge on csmsb will latch data bits d8 to d11. a rising edge on cslsb will latch data bits d0 to d7. once data is loaded into the input latches, it can be loaded into the dac latch. this will update the analog voltage output of the dac. the dac latch is loaded by a logic low on ldac. the data that is loaded into the dac latch will be latched on the rising edge of ldac. when wr, cslsb, csmsb and ldac are all low the latches are transparent and data on pins d0 to d11 loads directly into the dac latch. power-on reset the ltc1450/ltc1450l have an internal power-on reset that resets all internal latches to 0? on power-up (equiva- lent to the clr pin function). reference the ltc1450 includes an internal 2.048v reference, giv- ing the ltc1450 a full-scale range of 4.095v in the gain of 2 configuration. the ltc1450l has an internal 1.22v reference with a full-scale range of 2.5v and a gain of 2.05 in the gain of 2 configuration. the onboard reference in the ltc1450 and ltc1450l is not internally connected to the dac? reference resistor string but is provided on an adjacent pin for flexibility. because the internal reference operatio n u is not internally connected to the dac resistor string, anexternal reference can be used or the resistor string can be driven with an external source in multiplying configura- tion. the external reference or source must be capable of driving the 8k minimum dac ladder resistance. the reference output noise can be reduced with a bypass capacitor to ground. (note: the reference does not require a bypass capacitor to ground for proper operation.) when bypassing the reference a small value resistor in series with the capacitor is recommended to help reduce peaking on the output. a 10 resistor in series with a 4.7 f capacitor is optimum for reducing reference generatednoise. dac ladder resistor string the high and low end of the dac ladder resistor string (refhi and reflo respectively) are not connected inter- nally on this part. typically refhi will be connected to refout and reflo will be connected to gnd. this will give the ltc1450 a full-scale range of 4.095v. the full- scale range for the ltc1450l will be 2.5v either of these pins can be driven up to v cc ?1.5v when using the buffer in the gain of 1 configuration. the resistorstring pins can be driven to v cc /2 when the buffer is in the gain of 2 configuration (2.05 for the ltc1450l). theresistance between these two pins is typically 18k (8k min). voltage output the output buffer for the ltc1450/ltc1450l can be configured for two different gain settings. by tying the x1/x2 pin to gnd the gain is set to 2 (2.05 for the ltc1450l). by tying the x1/x2 pin to v out the gain is set to one.the ltc1450 family? rail-to-rail buffered output can source or sink 5ma over the entire operating temperature range while pulling to within 300mv of the positive supply voltage or gnd. the output swings to within a few milli- volts of either supply rail when unloaded and has an equivalent output resistance of 40 when driving a load to the rails. downloaded from: http:///
11 ltc1450/ltc1450l typical applicatio n s n u filter v ref to lower output noise (0.18mv rms at v out ) ltc1450 ltc1450l v out data (0:11) cslsb csmsb wr ldac clr v cc refout gnd refhi 10 reflo x1/x2 d in from p data bus from p and decode logic from system reset 5v 0.1 f 4.7 f output ltc1450/50l ?ta03 digitally programmable noninverting amplifier ltc1450 ltc1450l v out data (0:11) cslsb csmsb wr ldac clr v cc refout gnd refhi reflo x1/x2 d in from p data bus from p and decode logic from system reset v cc 0.1 f ltc1450: v in = 0v to 2.048v (v cc = 4.5v to 5v) ltc1450l: v in = 0v to 1.22v (v cc = 2.7v to 5.5v) ltc1450l: v in = 0v to 2.048v (v cc = 4.5v to 5.5v) ltc1450/50l ?ta04 d in 4096 ltc1450: v out = v in () ?2 d in 4096 ltc1450l: v out = v in () ?2.05 downloaded from: http:///
12 ltc1450/ltc1450l typical applicatio n s n u bipolar output 12-bit dac ltc1450 v out v dac v ref data (0:11) cslsb csmsb wr ldac clr v cc refout gnd refhi r3 20k r6 20k i out 2.048ma to 2.047ma (1 a/lsb) i out = z out = r1 = r3 r2 = r4 + r5 ?4.096 ?v ref reflo x1/x2 d in from p data bus from p and decode logic from system reset v cc 0.1 f ltc1450/50l ?ta06 + r4 21.5k 15v ?5v lt1097 23 74 6 r1 20k r2 22.6k r5 1.13k (r1)(r5)(r3 + r4) (r2)(r3) ?r1(r4 + r5) d in 4096 r2 (r1)(r5) () 2.047ma 2.048ma 4095 2048 i out d in digitally programmable bilateral current source/sink ltc1450 v out v dac *reflo is tied to refout and refhi is tied to gnd tying reflo to refout and refhi to gnd in this application overcomes the need for a pull-down resistor on the refout pin. refout sees a constant load to gnd independent of v out v ref data (0:11) cslsb csmsb wr ldac clr v cc refout gnd reflo* 10k 10k v out 2.048v to 2.047v (1mv/lsb) v out = 2.048 + 4.096 refhi* x1/x2 d in from p data bus from p and decode logic from system reset 5v 0.1 f ltc1450/50l ?ta05 + 10k d in ?4096 4096 5v ?v lt 1097 32 74 6 10k () 2.047v 2.048v 4095 2048 v out d in downloaded from: http:///
13 ltc1450/ltc1450l typical applicatio n s n u 4-quadrant multiplying dac applicationthis application shows the ltc1450l configured as a single supply 4-quadrant multiplying dac. it uses a 5v supply and only one external component, a 5k resistor tied from refout to ground. (the ltc1450 can be used in a similar fashion.) the multiplying dac allows the user to digitally change the amplitude and polarity of an ac input signal whose voltage is centered around an offset signal ground provided by the 1.22v reference voltage. the transfer function is shown in the following equations. v out = (v in ?v ref ) + v ref gain + 1 ?1 () d in 4096 for the ltc1450l gain = 2.05 and v ref = 1.22v v out = (v in ?1.22v) + 1.22v 2.05 ?1.05 () d in 4096 table 1 shows the expressions for v out as a function of v in , v ref and d in . the scope photo shows a 12.5khz, 2.3v p-p triangle wave input signal and the corresponding output waveforms for zero-scale and full-scale dac codes. table 1. binary code table for 4-quadrant, multiplying dacapplication binary digital input code in dac register analog output (v out ) msb lsb 1111 1111 1111 (4094/4096)(v in ?v ref ) + v ref 1100 0001 1001 0.5(v in ?v ref ) + v ref 1000 0011 0010 v ref 0100 0100 1011 0.5(v in ?v ref ) + v ref 0000 0110 0100 1.0(v in ?v ref ) + v ref 0000 0000 0000 1.05(v in ?v ref ) + v ref 5k gnd ltc1450l 5v v out 1.22v 1.21v 12-bit dac refhi reflo refout v ref d in clr v in 1.22v 1.15v v cc r 1.05r x1/x2 1450/50l ta07 + double- buffered dac latches power-on reset reference 1.22v wr csmsb cslsb ldac clean 4-quadrant multiplying is shown in the output waveforms for zero-scale and full-scale dac settings 1v/div 2v/div 1v/div v out d in = 0 v out d in = 4095 v in 1.22v 1.15v at 12.5khz 20 s/div internal reference, reflo/refhi pins, gain adjust and wide supply voltage range allow 4-quadrant mulitplying on a 5v single supply 1450/50l ta08 downloaded from: http:///
14 ltc1450/ltc1450l package descriptio n u dimensions in inches (millimeters) unless otherwise noted. g package 24-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) g24 ssop 0595 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8 9 10 11 12 0.318 ?0.328* (8.07 ?8.33) 21 22 18 17 16 15 14 13 19 20 23 24 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** downloaded from: http:///
15 ltc1450/ltc1450l n package 24-lead pdip (narrow 0.300) (ltc dwg # 05-08-1510) dimensions in inches (millimeters) unless otherwise noted. package descriptio n u n24 0695 0.255 0.015* (6.477 0.381) 1.265* (32.131) 12 3 4 5 6 7 891 0 19 11 12 13 14 16 15 17 18 20 21 22 23 24 0.015 (0.381) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.005 (0.127) min 0.100 0.010 (2.540 0.254) 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.025 0.015 +0.635 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. downloaded from: http:///
16 ltc1450/ltc1450l linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 telex : 499-3977 lt/gp 0896 7k ? printed in usa ? linear technology corporation 1996 related parts part number description comments ltc1257 complete serial i/o v out 12-bit dac 5v to 15v single supply in 8-pin so and pdip ltc1451/ltc1452/ltc1453 complete serial i/o v out 12-bit dacs 3v/5v single supply, rail-to-rail in 8-pin so and pdip ltc1446/ltc1446l dual 12-bit v out dacs in so-8 package ltc1446: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1446l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1454/ltc1454l dual 12-bit v out dacs in a 16-pin so package ltc1454: v cc = 4.5v to 5.5v, v out = 0v to 4.095v with added functionality ltc1454l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1458/ltc1458l quad 12-bit v out dacs in 28-lead sw and ssop ltc1458: v cc = 4.5v to 5.5v, v out = 0v to 4.095v packages ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc7541a parallel i/o multiplying 12-bit dac 12-bit wide input ltc7543/ltc8143 serial multiplying 12-bit dacs daisy-chainable, flexible analog and digital interface ltc7545a parallel latched input multiplying 12-bit dac 12-bit wide latched input ltc8043 serial multiplying 12-bit dac 8-pin so and pdip downloaded from: http:///

▲Up To Search▲

Price & Availability of LTC1450LCGTRPBF

	To Download LTC1450LCGTRPBF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .