1 pi6lc48p0405 block diagram description te pi6lc48p0405 is a 4-output lvpecl synthesizer optimized to generate 125mhz clock frequencies and is a member of peri - coms hiflex family of high performance clock solutions. te pi6lc48p0405 uses pericoms proprietary low phase noise vco technology and can achieve less than 0.32ps typical rms phase jitter, it is ideal for ethernet interface in all kind of sys - tems. features ? ? four diferential lvpecl output pairs ? ? selectable crystal oscillator interface or lvcmos/lvttl single-ended clock input ? ? supports the following output frequency: 125mhz ? ? rms phase jitter @ 125mhz, using a 25mhz crystal (1.875mhz C 20mhz): 0.14ps (typical) ? ? rms phase jitter @ 125mhz, using a 25mhz crystal (12khz C 20mhz): 0.32ps (typical) ? ? full 3.3v or 2.5v supply modes ? ? -40c to 85c operating temperature ? ? available in lead-free package: 24-tssop applications ? ? networking systems phase detector vco m = 25 (fixed) 5 osc clk0 clk0# clk1 clk1# clk2 clk2# clk3 clk3# m_reset in_sel xtal_out xtal_in ref_in pll_bypass 4-output lvpecl networking clock generator www.pericom.com pi6lc48p0405 rev .a 09/01/15 15-0118
2 pinout table pin no. pin name i/o ty pe description 1, 2 clk1#, clk1 output lvpecl output clock 1 3, 22 v ddo power output supply pins 4, 5 clk0, clk0# output lvpecl output clock 0 6 m_reset input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs clkx to go low and the inverted outputs clkx# to go high. when logic low, the internal dividers and outputs are enabled. 7 pll_bypass input pulldown selects either the pll or the active input reference to be routed to the output dividers. when low, selects pll (pll enable). when high, selects the reference clock (pll bypass). 8, 10, 12 nc not connected 9 v dda power analog power supply 11, 18 v dd power core power supply 13, 14 xtal_out, xtal_in output / input parallel resonant crystal interface. xtal_out is the output, and xtal_in is the input. 15, 19 g nd power ground 16 ref_in input pulldown cmos reference clock input 17 in_sel input pulldown selects between the single-ended ref_in or crystal interface as the pll reference source. when high, selects ref_in. when low selects xtal inputs. 20, 21 clk3#, clk3 output lvpecl output clock 3 23, 24 clk2, clk2# output lvpecl output clock 2 pin confguration 1 2 3 clk0 4 clk0# 5 v ddo 6 pll_bypass 7 in_sel 8 m_reset clk2# v ddo clk3 gnd v dd nc 24 23 22 21 20 19 18 17 clk1# clk1 clk3# clk2 ref_in 9v dda 16 gnd 10nc 15 xtal_in 11v dd 14 xtal_out 12 13 nc www.pericom.com pi6lc48p0405 rev .a 09/01/15 pi6lc48p0405 4-output lvpecl networking clock generator 15-0118
3 typical crystal requirement parameter test conditions minimum ty pica l maximum units mode of oscillation fundamental frequency 25 mhz equivalent series resistance (esr) 50 shunt capacitance 7 pf 5hfrpphghg&uvwdo6shflfdwlr pericom recommends: a) fl2500047, smd 3.2x2.5(4p), 25mhz, cl=18pf, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/fl.pdf b) fy2500091, smd 5x3.2(4p), 25mhz, cl=18pf, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/fy_f9.pdf www.pericom.com pi6lc48p0405 rev .a 09/01/15 pi6lc48p0405 4-output lvpecl networking clock generator 15-0118
4 maximum ratings (over operating free-air temperature range) ote stresses greater than those listed under maximum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. storage temperature .............................................. -65oc to+155oc temperature with power applied ......................... -40oc to+85oc 3.3v supply voltage .................................................... -0.5 to +3.6v esd protection (hbm) ......................................................... 2000v dc specifcations (t a = -40 to 85oc) symbol parameter condition min ty p max units v dd core supply voltage 3.135 3.3 3.465 v v dda analog supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i gnd power supply current 130 ma i dda analog supply current included in i gnd 30 ma power supply dc characterisitcs, (t a = -40 to 85oc) symbol parameter condition min ty p max units v dd core supply voltage 2.375 2.5 2.625 v v dda analog supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 2.375 2.5 2.625 v i gnd power supply current 125 ma i dda analog supply current included in i gnd 30 ma lvcmos/lvttl dc characterisitcs, (t a = -40 to 85oc) symbol parameter condition min ty p max units v ih input high voltage v dd = 3.3v 5% 2 v dd + 0.3 v v dd = 2.5v 5% 1.7 v dd + 0.3 v v il input low voltage v dd = 3.3v 5% -0.3 0.8 v v dd = 2.5v 5% -0.3 0.7 v i ih input high current ref_in, m_reset, pll_bypass, in_sel, v dd = v in = 3.465v 150 a i il input low current ref_in, m_reset, pll_bypass, in_sel, v dd = v in = 0v -5 a c in input capacitance 4 pf r pull - down input pulldown resistor 51 k www.pericom.com pi6lc48p0405 rev .a 09/01/15 pi6lc48p0405 4-output lvpecl networking clock generator 15-0118
5 lvpecl dc characterisitcs, (v dd = v ddo = 3.3v 5%, t a = -40 to 85oc) symbol parameter condition min ty p max units v oh output high voltage (1) v dd = 3.3v 1.9 2.4 v v dd = 2.5v 1.1 1.6 v ol output low voltage (1) v dd = 3.3v 1.2 1.6 v v dd = 2.5v 0.4 0.8 note: 1. lvpecl termination: source 150ohm to gnd and 100ohm across clk and clk#. ac electrical characteristics lvpecl termination: source 150ohm to gnd and using 0.01uf ac-coupled to 50ohm to gnd ac characterisitcs, (v dd = v ddo = 3.3v 5%, v dd = v ddo = 2.5v 5% , t a = -40 to 85oc) symbol parameter condition min. ty p. max units f out output frequency range 112 125 136 mhz t sk(o) output skew (1, 2) 70 ps t jit(?) rms phase jitter, (random) (3) 125mhz, (1.875mhz - 20mhz) 0.14 ps 125mhz, (12kmhz - 20mhz) 0.32 ps t r / t f output rise/fall time 20% to 80% 400 ps odc output duty cycle 48 52 % note: electrical parameters are quaranteed over the specifed ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airfow greater than 500 lfpm. te device will meet specifcations afer thermal equilibrium has been reached under these conditions. note1: defned as skew between outputs at the same supply voltage and with equal load conditions. measured at the diferential cross points. note2: tis parameter is defned in accordance with jedec standard 65. note3: please refer to the phase noise plots. phase noise plot www.pericom.com pi6lc48p0405 rev .a 09/01/15 pi6lc48p0405 4-output lvpecl networking clock generator 15-0118
6 lvpecl test circuit power supply filtering techniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter perfor - mance, power supply isolation is required. te pi6lc48p0405 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda and v ddo should be individually connected to the power supply plane through vias, and 0.1f bypass capacitors should be used for each pin. figure below illustrates this for a generic v dd pin and also shows that v dda requires that an additional 10 resistor along with a 10f bypass capacitor be connected to the v dda pin. v dd 0.1f 0.1f 10f 10? 3.3v or 2.5v v dda www.pericom.com pi6lc48p0405 rev .a 09/01/15 pi6lc48p0405 4-output lvpecl networking clock generator 15-0118
7 recommendations for unused input and output pins inputs: crystal inputs: for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be lef foating. a 1k resistor can be tied from xtal_in to ground for additional protection. ref_in input: for applications not requiring the use of the clock, it can be lef foating. a 1k resistor tied from the ref_in to ground can provide additional protection. lvcmos control pins: all control pins have internal pulldowns; a 1k resistor tied from each control pin to ground can provide additional protection. outputs: lvpecl outputs: all unused lvpecl outputs can be lef foating. crystal input interface te clock generator has been characterized with 18pf parallel resonant crystals. te capacitor values shown in the fgure below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. c1 33pf c2 27pf xtal_in xtal_out x1 18pf parallel crystal www.pericom.com pi6lc48p0405 rev .a 09/01/15 pi6lc48p0405 4-output lvpecl networking clock generator 15-0118
8 lvcmos to xtal interface te xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in the fgure below. te xtal_out pin can be lef foating. te input edge rate can be as slow as 10ns. for lvcmos signals, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. tis confguration requires that the output impedance of the driver (ro) plus the series resis - tance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. tis can be done in one of the two ways. first, r1 and r2 in parallel should equal the transmission line empedance. for most 50 applications, r1 and r2 can be 100 . this can also be accomplished by removing r1 and making r2 50. by overdriving the crystal oscillator, the device will be functional, but note, the device performance is quaranteed by using a quartz crystal. v r2 50 dd ro rs zo = ro + rs r1 xtal_in xtal_out v dd 0.1f thermal information symbol description q ja junction-to-ambient thermal resistance 84.0 o c/w q jc junction-to-case thermal resistance 13.0 o c/w www.pericom.com pi6lc48p0405 rev .a 09/01/15 pi6lc48p0405 4-output lvpecl networking clock generator 15-0118
9 ordering information ordering code packaging type package description operating temperature PI6LC48P0405LIE l pb-free & green, 24-pin tssop industrial PI6LC48P0405LIEx l pb-free & green, 24-pin tssop, tape & reel industrial notes: ? termal characteristics can be found on the company web site at www.pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com packaging mechanical: 24-contact tssop (l) date: 05/03/12 description: 24-pin, 173mil wide tssop package code: l document control #: pd-1312 revision: f notes: 1. refer jedec: mo-153f/ad 2. controlling dimensions in millimeters 3. package outline exclusive of mold flash and metal burr 12-0374 www.pericom.com pi6lc48p0405 rev .a 09/01/15 pi6lc48p0405 4-output lvpecl networking clock generator 15-0118
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