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74lvt573, 74lvth573 ?low voltage octal transparent latch with 3-state outputs ?999 fairchild semiconductor corporation www.fairchildsemi.com 74lvt573, 74lvth573 rev. 1.7.0 ja n uary 2008 74lvt573, 74lvth573 low voltage octal transparent latch with 3-state outputs features input and output interface capability to systems at 5v v cc bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74lvth573), also available without bushold feature (74lvt573) live insertion/extraction permitted power up/down high impedance provides glitch-free bus loading outputs source/sink ?2ma/+64ma functionally compatible with the 74 series 573 latch-up performance exceeds 500ma esd performance: ? human-body model > 2000v ? machine model > 200v ? charged-device model > 1000v general description the lvt573 and lvth573 consist of eight latches with 3-state outputs for bus organized system applica- tions. the latches appear transparent to the data when latch enable (le) is high. when le is low, the data satisfying the input timing requirements is latched. data appears on the bus when the output enable (oe ) is low. when oe is high, the bus output is in the high impedance state. the lvth573 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. these octal latches are designed for low-voltage (3.3v) v cc applications, but with the capability to provide a ttl interface to a 5v environment. the lvt573 and lvth573 are fabricated with an advanced bicmos technology to achieve high speed operation similar to 5v abt while maintaining a low power dissipation. ordering information device also available in tape and reel. specify by appending suffix letter ??to the ordering number. all packages are lead free per jedec: j-std-020b standard. order number package number package description 74lvt573wm m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74lvt573sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74lvt573msa msa20 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide 74lvt573mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74lvth573wm m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74lvth573sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74lvth573msa msa20 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide 74lvth573mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide
?999 fairchild semiconductor corporation www.fairchildsemi.com 74lvt573, 74lvth573 rev. 1.7.0 2 74lvt573, 74lvth573 ?low voltage octal transparent latch with 3-state outputs connection diagram pin description functional description the lvt573 and lvth573 contain eight d-type latches with 3-state standard outputs. when the latch enable (le) input is high, data on the d n inputs enters the latches. in this condition the latches are transparent, i.e., a latch output will change state each time its d-type input changes. when le is low, the latches store the infor- mation that was present on the d-type inputs a setup time preceding the high-to-low transition of le. the 3-state standard outputs are controlled by the output enable (oe ) input. when oe is low, the standard out- puts are in the 2-state mode. when oe is high, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. logic symbols ieee/iec truth table h = high voltage level l = low voltage level z = high impedance x = immaterial o 0 = previous o 0 before high to low transition of latch enable pin names description d 0 ? 7 data inputs le latch enable input oe output enable input o 0 ? 7 3-state latch outputs inputs outputs le oe d n o n xhx z hll l hlh h llx o 0
?999 fairchild semiconductor corporation www.fairchildsemi.com 74lvt573, 74lvth573 rev. 1.7.0 3 74lvt573, 74lvth573 ?low voltage octal transparent latch with 3-state outputs logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
?999 fairchild semiconductor corporation www.fairchildsemi.com 74lvt573, 74lvth573 rev. 1.7.0 4 74lvt573, 74lvth573 ?low voltage octal transparent latch with 3-state outputs absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. note: 1. i o absolute maximum rating must be observed. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter rating v cc supply voltage ?.5v to +4.6v v i dc input voltage ?.5v to +7.0v v o dc output voltage output in 3-state ?.5v to +7.0v output in high or low state (1) ?.5v to +7.0v i ik dc input diode current, v i < gnd ?0ma i ok dc output diode current, v o < gnd ?0ma i o dc output current, v o > v cc output at high state 64ma output at low state 128ma i cc dc supply current per supply pin ?4ma i gnd dc ground current per ground pin ?28ma t stg storage temperature ?5? to +150? symbol parameter min max units v cc supply voltage 2.7 3.6 v v i input voltage 0 5.5 v i oh high-level output current ?2 ma i ol low-level output current 64 ma t a f ree-air operating temperature ?0 85 ? ? t / ? v input edge rate, v in = 0.8v?.0v, v cc = 3.0v 0 10 ns/v
?999 fairchild semiconductor corporation www.fairchildsemi.com 74lvt573, 74lvth573 rev. 1.7.0 5 74lvt573, 74lvth573 ?low voltage octal transparent latch with 3-state outputs dc electrical characteristics notes: 2. all typical values are at v cc = 3.3v, t a = 25?. 3. applies to bushold versions only (74lvth573). 4. an external driver must source at least the specified current to switch from low-to-high. 5. an external driver must sink at least the specified current to switch from high-to-low. 6. this is the increase in supply current for each input that is at the specified voltage level rather than v cc or gnd. symbol parameter v cc (v) conditions t a = ?0? to +85? units min. typ. (2) max. v ik input clamp diode voltage 2.7 i i = ?8ma ?.2 v v ih input high voltage 2.7?.6 v o 0.1v or v o v cc ?0.1v 2.0 v v il input low voltage 2.7?.6 0.8 v v oh output high voltage 2.7?.6 i oh = ?00? v cc ?0.2 v 2.7 i oh = ?ma 2.4 3.0 i oh = ?2ma 2.0 v ol output low voltage 2.7 i ol = 100? 0.2 v i ol = 24ma 0.5 3.0 i ol = 16ma 0.4 i ol = 32ma 0.5 i ol = 64ma 0.55 i i(hold) (3) bushold input minimum drive 3.0 v i = 0.8v 75 ? v i = 2.0v ?5 i i(od) (3) bushold input over-drive current to change state 3.0 (4) 500 ? (5) ?00 i i input current 3.6 v i = 5.5v 10 ? control pins 3.6 v i = 0v or v cc ? data pins 3.6 v i = 0v ? v i = v cc 1 i off po w er off leakage current 0 0v v i or v o 5.5v ?00 ? i pu/pd po w er up/down 3-state output current 0?.5 v o = 0.5v to 3.0v, v i = gnd or v cc ?00 ? i ozl 3-state output leakage current 3.6 v o = 0.5v ? ? i ozh 3-state output leakage current 3.6 v o = 3.0v 5 a i ozh + 3-state output leakage current 3.6 v cc < v o 5.5v 10 ? i cch po w er supply current 3.6 outputs high 0.19 ma i ccl po w er supply current 3.6 outputs low 5 ma i ccz po w er supply current 3.6 outputs disabled 0.19 ma i ccz +p ow er supply current 3.6 v cc v o 5.5v, outputs disabled 0.19 ma ? i cc increase in power supply current (6) 3.6 one input at v cc ?0.6v, other inputs at v cc or gnd 0.2 ma
?999 fairchild semiconductor corporation www.fairchildsemi.com 74lvt573, 74lvth573 rev. 1.7.0 6 74lvt573, 74lvth573 ?low voltage octal transparent latch with 3-state outputs dynamic switching characteristics (7) notes: 7. characterized in soic package. guaranteed parameter, but not tested. 8. max number of outputs defined as (n). n? data inputs are driven 0v to 3v. output under test held low. ac electrical characteristics notes: 9. all typical values are at v cc = 3.3v, t a = 25?. 10. skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. the specification applies to any outputs switching in the same direction, either high-to-low (t oshl ) or low-to-high (t oslh ). capacitance (11) note: 11. capacitance is measured at frequency f = 1mhz, per mil-std-883, method 3012. symbol parameter v cc (v) conditions t a = 25? units c l = 50pf, r l = 500 ? min. typ. max. v olp quiet output maximum dynamic v ol 3.3 (8) 0.8 v v olv quiet output minimum dynamic v ol 3.3 (8) ?.8 v symbol parameter t a = ?0? to +85? c l = 50pf, r l = 500 ? units v cc = 3.3v ?0.3v v cc = 2.7v min. typ. (9) max. min. max. t phl propagation delay, d n to o n 1.5 4.4 1.5 4.9 ns t plh 1.5 4.1 1.5 4.7 t phl propagation delay, le to o n 1.9 4.4 1.9 4.9 ns t plh 1.9 4.4 1.9 5.0 t pzl output enable time 1.5 5.1 1.5 6.6 ns t pzh 1.5 5.1 1.5 5.9 t plz output disable time 2.0 4.6 2.0 4.9 ns t phz 2.0 4.9 2.0 5.5 t s setup time, d n to le 0.7 0.6 ns t h hold time, d n to le 1.5 1.7 ns t w le pulse width 3.0 3.0 ns t oshl , t oslh output to output skew (10) 1.0 1.0 ns symbol parameter conditions typical units c in input capacitance v cc = open, v i = 0v or v cc 4pf c out output capacitance v cc = 3.0v, v o = 0v or v cc 6 pf
?999 fairchild semiconductor corporation www.fairchildsemi.com 74lvt573, 74lvth573 rev. 1.7.0 7 74lvt573, 74lvth573 ?low voltage octal transparent latch with 3-state outputs physical dimensions figure 1. 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ 0.10 c c a see detail a notes: unless otherwise specified a) this package conforms to jedec ms-013, variation ac, issue e b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. e) landpattern standard: soic127p1030x265-20l pin one indicator 0.25 1 10 b c a m 20 11 b x45 8 0 seating plane gage plane detail a scale: 2:1 seating plane land pattern recommendation f) drawing filename: mkt-m20brev3 0.65 1.27 2.25 9.50 13.00 12.60 11.43 7.60 7.40 10.65 10.00 0.51 0.35 1.27 2.65 max 0.30 0.10 0.33 0.20 0.75 0.25 (r0.10) (r0.10) 1.27 0.40 (1.40) 0.25 d) conforms to asme y14.5m-1994
?999 fairchild semiconductor corporation www.fairchildsemi.com 74lvt573, 74lvth573 rev. 1.7.0 8 74lvt573, 74lvth573 ?low voltage octal transparent latch with 3-state outputs physical dimensions (continued) figure 2. 20-lead small outline package (sop), eiaj type ii, 5.3mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/
?999 fairchild semiconductor corporation www.fairchildsemi.com 74lvt573, 74lvth573 rev. 1.7.0 9 74lvt573, 74lvth573 ?low voltage octal transparent latch with 3-state outputs physical dimensions (continued) figure 3. 20-lead shrink small outline package (ssop), jedec mo-150, 5.3mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/
?999 fairchild semiconductor corporation www.fairchildsemi.com 74lvt573, 74lvth573 rev. 1.7.0 10 74lvt573, 74lvth573 ?low voltage octal transparent latch with 3-state outputs physical dimensions (continued) figure 4. 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/
?999 fairchild semiconductor corporation www.fairchildsemi.com 74lvt573, 74lvth573 rev. 1.7.0 11 trademarks th ef ollowing includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global s ubsidiaries, and is not intended to be an exhaustive list of all such trademarks. acex build it now coreplus crossvolt ctl current transfer logic ecospark ezswit ch * fairchild fairchild semiconductor fact quiet series fact fast fastvcore flashwriter ? fps frfet global power resource sm green fps green fpse-series gto i-lo intellimax isopla nar m egabuck mi crocoupler microfet micropak mi llerdrive mo ti on-spm optologic optopl anar pdp-spm pow er220 poweredge power-spm po we rtrench pr ogrammable active droop qfet qs qt optoelectronics quiet series rapidconfigure smart start spm stealth s uperfet su persot -3 s upersot-6 s upersot-8 s upremos syncfet the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinypwm tinywire serdes uhc ultra f rfet unifet vcx *ezswi tch and flashwriter are trademarks of system general corporation, used under license by fairchild semiconductor. disc laimer fa i rchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any pro duct or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these speci fications do not expand t he terms of fairchild? wo rl dw ide terms and conditions, specifically the warranty therein, which covers these products. life support policy fa i rchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ic h, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform wh en properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. pr oduct status definitions defi nition of terms da tasheet identification product status definition ad vance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. pr eliminary first production this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to ma ke c hanges at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve the des i gn. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. rev. i33 74lvt573, 74lvth573 ?low voltage octal transparent latch with 3-state outputs

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