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automotive power data sheet rev. 1.0, 2015-01-27 tls810d1ejv50 ultra low quiescent curren t linear voltage regulator
pg-dso-8 ep type package marking tls810d1ejv50 pg-dso-8 ep 810d1v50 data sheet 2 rev. 1.0, 2015-01-27 ultra low quiescent current linear voltage regulator tls810d1 tls810d1ejv50 1overview features ? ultra low quiescent current of 9 a ? wide input voltage range of 2.75 v to 42 v ? output current capacity up to 100 ma ? low drop out voltage of typ. 200 mv @ 100 ma ? enable ? off-mode current less than 1 a ? reset ? output current limit protection ? overtemperature shutdown ? available in pg-dso-8 ep package ? wide temperature range ? green product (rohs compliant) ? aec qualified description the tls810d1 is a linear voltage regulator featuring wide input voltage range, low drop out voltage and ultra low quiescent current. with an input voltage range of 2.75 v to 42 v and ultra low quiescent of only 9 a, the regulator is perfectly suitable for automotive or any other supply systems connected permanently to the battery. the tls810d1ejv50 is the fixed 5 v ou tput version with an accuracy of 2 % and output current capability up to 100 ma. the new regulation concept implemente d in tls810d1 combines fast regulation and very good stability while requiring only a small ceramic capacitor of 1 f at the output. the tracking region starts already at input voltages of 2.75 v (extended operating range). this makes the tls810d1 also suitable to supply automotive system s that need to operate during cranking condition. internal protection features like output current limitation and overtemperature shutdown are implemented to protect the device against immediate damage due to failu res like output short circuit to gnd, over-current and over-temperature. the device can be switched on and off by the enable fe ature. when the device is switched off, the current consumption is typically less than 1 a.
tls810d1ejv50 overview data sheet 3 rev. 1.0, 2015-01-27 the output voltage is supervised by the reset feature, including undervoltage reset and delayed reset release at power-on. choosing external components an input capacitor c i is recommended to compensate line influences. the output capacitor c q is necessary for the stability of the regulating circui t. stability is guara nteed at values c q 1 f and an esr 100 ? within the whole operating range.
tls810d1ejv50 block diagram data sheet 4 rev. 1.0, 2015-01-27 2 block diagram figure 1 block diagram tls810d1 bandgap reference gnd q i temperature shutdown en enable reset ro d current limitation
tls810d1ejv50 pin configuration data sheet 5 rev. 1.0, 2015-01-27 3 pin configuration 3.1 pin assignment in pg-dso-8 ep package figure 2 pin configuration tls810d1 in pg-dso-8 ep package 3.2 pin definitions and functi ons in pg-dso-8 ep package pin symbol function 1i input it is recommended to place a small ceramic capacitor (e.g. 100 nf) to gnd, close to the ic terminals, in order to compensate line influences. 2n.c. not connected 3en enable integrated pull-down resistor. enable the ic with high level input signal. disable the ic with low level input signal. 4gnd ground 5d reset delay timing connect a ceramic capacitor to gnd for adjusting the reset delay time. leave open if the reset function is not needed. 6ro reset output integrated pull-up resistor. open collector output. leave open if the reset function is not needed. 7n.c. not connected q n.c. ro i n.c. en gnd d 1 3 2 8 7 6 45
tls810d1ejv50 pin configuration data sheet 6 rev. 1.0, 2015-01-27 8q output connect an output capacitor c q to gnd close to the ic?s terminals, respecting the values specified for its capacitance and esr in table 2 ?functional range? on page 8 . pad ? exposed pad connect to heatsink area. connect to gnd. pin symbol function
tls810d1ejv50 general product characteristics data sheet 7 rev. 1.0, 2015-01-27 4 general product characteristics 4.1 absolute maximum ratings notes 1. stresses above the ones listed here may cause perma nent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. integrated protection func tions are designed to prevent ic destructi on under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. pr otection functi ons are not designed for continuous repetitive operation. table 1 absolute maximum ratings 1) t j = -40 c to +150 c; all voltages with respect to ground (unless otherwise specified) 1) not subject to production te sting, specified by design. parameter symbol values unit note / test condition number min. typ. max. voltage input, enable en voltage v i , v en -0.3 ? 45 v ? p_4.1.1 voltage output q voltage v q -0.3 ? 7 v ? p_4.1.2 reset output ro, reset delay d voltage v ro , v d -0.3 ? 7 v ? p_4.1.3 temperatures junction temperature t j -40 ? 150 c ? p_4.1.4 storage temperature t stg -55 ? 150 c ? p_4.1.5 esd absorption esd absorption v esd,hbm -2?2kvhbm 2) 2) esd hbm test according to aec-q100-002 - jesd22-a114 (1.5kohm, 100pf) p_4.1.6 esd absorption v esd,cdm -750 ? 750 v cdm 3) at all pins 3) esd cdm test according to esda stm5.3.1 p_4.1.7
tls810d1ejv50 general product characteristics data sheet 8 rev. 1.0, 2015-01-27 4.2 functional range note: within the functional or operating range, the ic operat es as described in the circuit description. the electrical characteristics are specif ied within the conditions given in th e electrical char acteristics table. 4.3 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . table 2 functional range parameter symbol values unit note / test condition number min. typ. max. input voltage range v i v q,nom + v dr ?42v? 1) 1) output current is limited internally and depends on the in put voltage, see electrical char acteristics for more details. p_4.2.1 extended input voltage range v i,ext 2.75 ? 42 v ? 2) 2) when v i is between v i,ext.min and v q,nom + v dr , v q = v i - v dr . when v i is below v i,ext,min , v q can drop down to 0 v. p_4.2.2 output capacitor c q 1 ? ? f ? 3) 3) the minimum output capacitance requ irement is applicable for a worst ca se capacitance tolerance of 30%. p_4.2.3 output capacitor?s esr esr( c q )? ? 100 ? ? 4) 4) relevant esr value at f = 10 khz. p_4.2.4 junction temperature t j -40 ? 150 c ? p_4.2.5 table 3 thermal resistance parameter symbol values unit note / test condition number min. typ. max. package version pg-dso-8 ep junction to case 1) 1) not subject to production test, specified by design r thjc ? 19 ? k/w ? p_4.3.1 junction to ambient 1) r thja ? 51 ? k/w 2s2p board 2) 2) specified r thja value is according to jedec jesd51-2,-5,-7 at na tural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.2 x 114.3 x 1.5 mm3 boar d with 2 inner copper layers (2 x 70m cu, 2 x 35m cu). where applicable a thermal via array under the ex posed pad contacted the first inner copper layer. p_4.3.2 junction to ambient 1) r thja ? 167 ? k/w 1s0p board, footprint only 3) 3) specified r thja value is according to jedec jesd 51-3 at natural convection on fr4 1s0p board; the product (chip+package) was simulated on a 76.2 114.3 1.5 mm 3 board with 1 copper layer (1 x 70m cu). p_4.3.3 junction to ambient 1) r thja ? 71 ? k/w 1s0p board, 300 mm 2 heatsink area on pcb 3) p_4.3.4 junction to ambient 1) r thja ? 60 ? k/w 1s0p board, 600 mm 2 heatsink area on pcb 3) p_4.3.5
tls810d1ejv50 block description and electrical characteristics data sheet 9 rev. 1.0, 2015-01-27 5 block description and el ectrical characteristics 5.1 voltage regulation the output voltage v q is divided by a resistor network. this fracti onal voltage is compared to an internal voltage reference and the pass transistor is driven accordingly. the control loop stability depen ds on the output capacitor c q , the load current, the chip temperature and the internal circuit structure. to ensure stable operation, the output capacitor?s capacitance and its equivalent series resistor esr requirements given in ?functional range? on page 8 have to be maintained. for details see the typical performance graph output capacitor series resistor esr ( c q ) versus output current i q . since the output capacitor is used to buffer load steps, it should be sized according to the application?s needs. an input capacitor c i is not required for stability, but is re commended to compensate line fluctuations. an additional reverse polarity protection di ode and a combination of several capacitors for filtering should be used, in case the input is connected directly to the battery line. connect the capacitors close to the regulator terminals. in order to prevent overshoots during start-up, a smooth ramping up function is implemented. this ensures almost no overshoots during start-up, mostly independent from load and output capacitance. whenever the load current exceeds the specified limit, e.g. in case of a short circuit, the output current is limited and the output voltage decreases. the overtemperature shutdown circuit prevents the ic from immediate destruction under fault conditions (e.g. output continuously short-circuit) by switching off the power stage. after the chip has cooled down, the regulator restarts. this oscillatory th ermal behaviour causes the junction temp erature to exceed the maximum rating of 150c and can significantly reduce the ic?s lifetime. figure 3 block diagram voltage regulation bandgap reference gnd q i temperature shutdown current limitation regulated output voltage i q v q c q supply v i load c esr c i i i
tls810d1ejv50 block description and electrical characteristics data sheet 10 rev. 1.0, 2015-01-27 table 4 electrical characteristics t j = -40 c to +150 c, v i = 13.5 v, all voltages with respect to ground (unless otherwise specified). typical values are given at t j = 25 c, v i = 13.5 v. parameter symbol values unit note / test condition number min. typ. max. output voltage precision v q 4.90 5.00 5.10 v 50 a i q 100 ma, 5.7 v v i 28 v p_5.1.2 output voltage precision v q 4.90 5.00 5.10 v 50 a i q 50 ma, 5.7 v v i 42 v p_5.1.3 output current limitation i q,lim 110 190 260 ma 0 v v q v q,nom - 0.1 v p_5.1.4 line regulation steady-state v q,line ?120mv i q = 1ma, 6v v i 32 v p_5.1.6 load regulation steady-state v q,load -20 -1 ? mv v i = 6 v, 50 a i q 100 ma p_5.1.7 dropout voltage 1) v dr = v i - v q 1) measured when the output voltage v q has dropped 100 mv from the nominal value obtained at v i = 13.5v v dr ?200550mv i q = 100 ma p_5.1.11 ripple rejection 2) 2) not subject to production test, specified by design psrr ?55? db i q =50ma, f ripple = 100 hz, v ripple = 0.5 v p-p p_5.1.12 overtemperature shutdown threshold t j,sd 151 175 ? c t j increasing p_5.1.13 overtemperature shutdown threshold hysteresis t j,sdh ?10? k t j decreasing p_5.1.14
tls810d1ejv50 block description and electrical characteristics data sheet 11 rev. 1.0, 2015-01-27 5.2 typical performance characteristics voltage regulation typical performanc e characteristics output voltage v q versus junction temperature t j output current i q versus input voltage v i dropout voltage v dr versus junction temperature t j dropout voltage v dr versus output current i q 0 50 100 150 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 t j [ c] v q [v] v i = 13.5 v i q = 50 ma 0 10 20 30 40 0 50 100 150 200 250 300 v i [v] i qmax [ma] t j = ?40 c t j = 25 c t j = 150 c 0 50 100 150 0 50 100 150 200 250 300 350 400 t j [ c] v dr [mv] i q = 10 ma i q = 50 ma i q = 100 ma 0 20 40 60 80 100 0 50 100 150 200 250 300 350 400 i q [ma] v dr [mv] t j = ?40 c t j = 25 c t j = 150 c
tls810d1ejv50 block description and electrical characteristics data sheet 12 rev. 1.0, 2015-01-27 load regulation ? v q,load versus output current i q line regulation ? v q,line versus input voltage v i output voltage v q versus input voltage v i power supply ripple rejection psrr versus ripple frequency f r 0 20 40 60 80 100 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 i q [ma] dv load [mv] v i = 6 v t j = ?40 c t j = 25 c t j = 150 c 10 15 20 25 30 35 40 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 v i [v] dv line [mv] i q = 1 ma t j = ?40 c t j = 25 c t j = 150 c 0 1 2 3 4 5 6 0 1 2 3 4 5 6 v i [v] v q [v] i q = 50 ma t j = 25 c 10 ?2 10 ?1 10 0 10 1 10 2 10 3 0 10 20 30 40 50 60 70 80 f [khz] psrr [db] i q = 10 ma c q = 1 f v i = 13.5 v v ripple = 0.5 vpp t j = 25 c
tls810d1ejv50 block description and electrical characteristics data sheet 13 rev. 1.0, 2015-01-27 output capacitor series resistor esr ( c q ) versus output current i q 0 20 40 60 80 100 10 ?2 10 ?1 10 0 10 1 10 2 10 3 i q [ma] esr(c q ) [ ] c q = 1 f v i = 3...28 v stable region unstable region
tls810d1ejv50 block description and electrical characteristics data sheet 14 rev. 1.0, 2015-01-27 5.3 current consumption table 5 electrical characteristics current consumption t j = -40 c to +150 c, v i = 13.5 v (unless otherwise specified). parameter symbol values unit note / test condition number min. typ. max. current consumption i q = i i i q,off ??1a v en 0.4 v, t j < 105 c p_5.3.1 current consumption i q = i i - i q i q ? 9 11.5 a i q = 50 a, t j = 25 c p_5.3.2 current consumption i q = i i - i q i q ? 11.5 14.5 a i q = 50 a, t j < 105 c p_5.3.3 current consumption i q = i i - i q i q ?1216a i q = 50 a, t j < 125 c p_5.3.4 current consumption i q = i i - i q i q ?1216a i q = 100 ma, t j < 125 c p_5.3.5
tls810d1ejv50 block description and electrical characteristics data sheet 15 rev. 1.0, 2015-01-27 5.4 typical performance charac teristics current consumption typical performanc e characteristics current consumption i q versus output current i q current consumption i q versus input voltage v i current consumption i q versus junction temperature t j current consumption in off mode i q,off versus junction temperature t j 0 20 40 60 80 100 0 4 8 12 16 20 24 i q [ma] i q [ a] v i = 13.5 v t j = ?40 c t j = 25 c t j = 105 c t j = 125 c 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 v i [v] i q [ a] i q = 50 a t j = ?40 c t j = 25 c t j = 105 c t j = 125 c 0 50 100 150 0 4 8 12 16 20 24 t j [ c] i q [ a] v i = 13.5 v i q = 50 a 0 50 100 150 0 0.5 1 1.5 2 2.5 3 3.5 4 t j [ c] i q,off [ a] v i = 13.5 v v en 0.4 v
tls810d1ejv50 block description and electrical characteristics data sheet 16 rev. 1.0, 2015-01-27 5.5 enable the device tls810d1 can be switched on and off by the en able feature. connect a high level as specified below (e.g. the battery voltage) to pin en to enable the devi ce; connect a low level as specified below (e.g. gnd) to switch it off. the enable function has a build-in hysteresis to avoid toggling between on /off state, if signals with slow slopes are appiled to the en input. table 6 electrical characteristics enable t j = -40 c to +150 c, v i = 13.5 v, all voltages with respect to ground (unless otherwise specified). typical values are given at t j = 25 c, v i = 13.5 v. parameter symbol values unit note / test condition number min. typ. max. high level input voltage v en,h 2?? v v q settled p_5.5.1 low level input voltage v en,l ??0.8v v q 0.1 v p_5.5.2 high level input current i en,h ??4 a v en = 5 v p_5.5.4 enable internal pull-down resistor r en 1.25 2 3.5 m ? ? p_5.5.6
tls810d1ejv50 block description and electrical characteristics data sheet 17 rev. 1.0, 2015-01-27 5.6 typical performance characteristics enable typical performanc e characteristics enable input current i en versus enable input voltage v en 0 10 20 30 40 0 5 10 15 20 25 30 35 40 v en [v] i en [ a] t j = ?40 c t j = 25 c t j = 150 c
tls810d1ejv50 block description and electrical characteristics data sheet 18 rev. 1.0, 2015-01-27 5.7 reset function the reset function provides several features: output undervoltage reset an output undervoltage condition is indi cated by setting the reset output ro to ?low?. this signal may be used to reset a microcontroller during low supply voltage. power-on reset delay time the power-on reset delay time t rd allows microcontoller and o scillator to start up. this de lay time is the time frame from exceeding the reset switching threshold v rt until the reset is released by switching the reset output ?ro? from ?low? to ?high?. the power-on reset delay time tr d is defined by an external delay capacitor c d connected to pin d charged by the delay capacitor charge current i d,ch starting from v d =0v. if the application needs a power-on reset delay time t rd different from the value given in table 7 , the delay capacitor?s value can be derived from the specif ied value and the desired power-on delay time: (5.1) with ? c d : capacitance of the delay capacitor to be chosen ? t rd,new : desired power-on reset delay time ? t rd : power-on reset delay time specified in this datasheet for a precise calculation also take the dela y capacitor?s tolerance into consideration. reset reaction time the reset reaction time avoids that short undervoltage spikes trigger an unwanted reset ?low? signal. the reset reaction rime t rr considers the internal reaction time t rr,int and the discharge time t rr,d defined by the external delay capacitor c d (see typical performance graph for details). hence, the total reset reaction time becomes: (5.2) with ? t rr : reset reaction time ? t rr,int : internal reset reaction time ? t rr,d : reset discharge optional reset output pull-up resistor r ro,ext the reset output ro is an open collector output with an integrated pull-up resistor. if needed, an external pull-up resistor to the output q can be added. in table 7 a minimum value for the external resistor r ro,ext is given. c d = t rd,new 100 nf t rd x t rr = + t rr,int t rr,d
tls810d1ejv50 block description and electrical characteristics data sheet 19 rev. 1.0, 2015-01-27 figure 4 block diagram reset function gnd q i supply ro v dst int. supply i d,ch i d,dch v radj ,t h control d c d reset optional c q vdd micro- controller gnd r ro i ro r ro ,ext
tls810d1ejv50 block description and electrical characteristics data sheet 20 rev. 1.0, 2015-01-27 figure 5 timing diagram reset table 7 electrical characteristics reset t j = -40 c to +150 c, v i = 13.5 v, all voltages with respect to ground (unless otherwise specified). typical values are given at t j = 25 c, v i = 13.5 v. parameter symbol values unit note / test condition number min. typ. max. output undervoltage reset output undervoltage reset upper switching threshold v rt,high 4.6 4.7 4.8 v v q increasing, v en 2.0 v p_5.7.1 output undervoltage reset lower switching threshold v rt,low 4.5 4.6 4.7 v v q decreasing, v en 2.0 v p_5.7.2 reset output ro reset output low voltage v ro,low 00.20.4v1v v q v rt ; r ro >4.7k ? p_5.7.4 v i t v q t v rt,high v ro timingdiagram _reset.vsd t v ro , low 1 v 1v t rr,total t rd thermal shutdown input voltage dip t rr,total t rd t rd t < t rr,t ot al t rd under- voltage spike at output over - load t rr,total v drl v du t v d v rt,low
tls810d1ejv50 block description and electrical characteristics data sheet 21 rev. 1.0, 2015-01-27 reset output internal pull-up resistor r ro,int 13 20 36 k ? internally connected to q p_5.7.5 reset output external pull-up resistor to v q r ro,ext 4.7 ? ? k ? 1v v q v rt ; v ro 0.4 v p_5.7.6 reset delay timing power on reset delay time t rd 17 25 37 ms c d = 100 nf calculated value p_5.7.8 upper delay switching threshold v du ? 0.9 ? v ? p_5.7.9 lower delay switching threshold v dl ? 0.6 ? v ? p_5.7.10 delay capacitor charge current i d,ch ?3.6?a v d = 1 v p_5.7.11 delay capacitor discharge current i d,dch ? 250 ? ma v d = 1 v p_5.7.12 delay capacitor discharge time t rr,d ?24s c d = 100 nf calculated value p_5.7.13 internal reset reaction time 1) t rr,int ?814s c d = 0 nf p_5.7.14 reset reaction time t rr,total ?1018s c d = 100 nf calculated value p_5.7.15 1) parameter not subject to produ ction test; specified by design. table 7 electrical characteristics reset t j = -40 c to +150 c, v i = 13.5 v, all voltages with respect to ground (unless otherwise specified). typical values are given at t j = 25 c, v i = 13.5 v. parameter symbol values unit note / test condition number min. typ. max.
tls810d1ejv50 block description and electrical characteristics data sheet 22 rev. 1.0, 2015-01-27 5.8 typical performance characteristics reset typical performanc e characteristics undervoltage reset threshold v rt versus junction temperature t j power on reset delay time t rd versus junction temperature t j internal reset reaction time t rr,int versus junction temperature t j 0 50 100 150 4.5 4.55 4.6 4.65 4.7 4.75 4.8 4.85 4.9 4.95 5 t j [ c] v rt [v] v rt high v rt low 0 50 100 150 0 5 10 15 20 25 30 35 40 t j [ c] t rd [ms] c d = 100 nf 0 50 100 150 0 2 4 6 8 10 12 14 16 t j [ c] t rr,int [ s]
tls810d1ejv50 application information data sheet 23 rev. 1.0, 2015-01-27 6 application information note: the following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. 6.1 application diagram figure 6 application diagram tls810d1 6.2 selection of external components 6.2.1 input pin the typical input circuitry for a linear voltage regulator is shown in the application diagram above. a ceramic capacitor at the input, in the range of 100 nf to 470 nf, is recommended to filter out the high frequency disturbances imposed by the line e.g. iso pulses 3a/b. this capacitor must be placed very close to the input pin of the linear voltage regulator on the pcb. an aluminum electrolytic capacitor in the range of 10 f to 470 f is recommended as an input buffer to smooth out high energy pulses, such as iso pulse 2a. this capaci tor should be placed close to the input pin of the linear voltage regulator on the pcb. an overvoltage suppressor diode can be used to furthe r suppress any high voltag e beyond the maximum rating of the linear voltage regulator and protect th e device against any damage due to over-voltage. the external components at the input are not mandatory for the operation of the voltage regulator, but they are recommended in case of possible external disturbances. 6.2.2 output pin an output capacitor is mandatory for th e stability of linear voltage regulators. tls810d1 q i en ro d regulated output voltage i q c q 1f c d 100nf supply 100nf 10f c i1 c i2 <45v d i2 i i gnd e.g. ignition load (e.g. micro controller) gnd (optional) r ro d i1
tls810d1ejv50 application information data sheet 24 rev. 1.0, 2015-01-27 the requirement to the output capacitor is given in ?functional range? on page 8 . the graph ?output capacitor series resistor esr ( c q ) versus output current i q ? on page 13 shows the stable operation range of the device. tls810d1 is designed to be stable with extremely low esr capacitors. according to the automotive environment, ceramic capacitors with x5r or x7r dielectrics are recommended. the output capacitor should be placed as close as possible to the regulat or?s output and gnd pins and on the same side of the pcb as the regulator itself. in case of rapid transients of input voltage or load curr ent, the capacitance should be dimensioned in accordance and verified in the re al application that t he output stability requ irements are fulfilled. 6.3 thermal considerations knowing the input voltage, the output voltage and the load profile of the application, the total power dissipation can be calculated: (6.1) with ? p d : continuous power dissipation ? v i : input voltage ? v q : output voltage ? i q : output current ? i q : quiescent current the maximum acceptable thermal resistance r thja can then be calculated: (6.2) with ? t j,max : maximum allowed junction temperature ? t a : ambient temperature based on the above calculation the proper pcb type and the necessary heat sink area can be determined with reference to the specification in ?thermal resistance? on page 8 . example application conditions: v i = 13.5 v v q = 5 v i q = 80 ma t a = 105 c calculation of r thja,max : p d =( v i ? v q ) x i q + v i x i q = (13.5v ? 5v) x 80 ma + 13.5 v x 0.016 ma =0.68w p d v i v q ? () i q v i i q + = r thja max , t jmax , t a ? p d --------------------------- - =
tls810d1ejv50 application information data sheet 25 rev. 1.0, 2015-01-27 r thja,max =( t j,max ? t a ) / p d = (150 c ? 105 c) / 0.68 w =66.2k/w as a result, the pcb design must ensure a thermal resistance r thja lower than 66.2 k/w. according to ?thermal resistance? on page 8 , at least 600 mm2 heatsink area is needed on the fr4 1s0p pcb, or the fr4 2s2p board can be used. 6.4 reverse polarity protection tls810d1 is not self protected against reverse polarity faults. to protect the device against negative supply voltage, an external reverse polarity diode is needed, as shown in figure 6 . the absolute maximum ratings of the device as specified in ?absolute maximum ratings? on page 7 must be kept. 6.5 further application information ? for further information you may contact http://www.infineon.com/
tls810d1ejv50 package outlines data sheet 26 rev. 1.0, 2015-01-27 7 package outlines figure 7 pg-dso-8 ep green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). 14 8 5 8 14 5 8 x 0.41 0.09 2) m 0.2 d c a-b 1.27 c s t a nd off +0 -0.1 0.1 (1.45) 1.7 max. 0.0 8 s e a ting pl a ne c a b 4.9 0.1 1) a-b c 0.1 2x 3 ) jedec reference m s -012 v a ri a tion ba 1) doe s not incl u de pl as tic or met a l protr us ion of 0.15 m a x. per s ide 2) d a m ba r protr us ion s h a ll b e m a xim u m 0.1 mm tot a l in exce ss of le a d width bottom view 0.2 3 0.2 2.65 0.2 0.2 d 6 m d 8 x 0.64 0.25 3 .9 0.1 1) 0.1 0. 3 5 x 45 cd2x +0.06 0.19 8 max. index m a rking for further info rmation on alternative pa ckages, please visit our website: http://www.infineon.com/packages . dimensions in mm
tls810d1ejv50 revision history data sheet 27 rev. 1.0, 2015-01-27 8 revision history revision date changes 1.0 2015-01-27 data sheet - initial version
edition 2015-01-27 published by infineon technologies ag 81726 munich, germany ? 2015 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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