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211x1-dsh-001-i mindspeed technologies ? december 2012 mindspeed proprietary and confidential m21131/m21151 72x72/144x144 3.2 gbps asynchronous crosspoint switch with amplif-eye signal conditioning applications ? large nxn cascaded switch fabrics up to 10 terabits/sec (tbps) ? dense-wavelength-division multip lexing (dwdm) telecom/datacom switcher/router ? serial digital video swit cher/router (3g/hd/sd-sdi) ? storage area network (san) switcher/router ? high-speed automated test equipment (ate) ? disaster recovery and redundancy systems the m21131/m21151 is a 3.2 gbps, 72/144 lane high-speed, low-power cmos asynchronous non-blocking crosspoint switch. it operates from dc to 3.2 gbps making it suitable for many telecom, datacom, and broadcast video applications. features ? 72/144 inputs by 72/144 outputs non-blocking crosspoint switch ? 3.2 gbps non-return to zero (nrz) raw data bandwidth ? global or individual lane programmable input equalization, output de- emphasis, and drive levels ? pinout and software compatible with the m21141/m21161 ? input signal activity monitor ? flexible interface avdd_io +1.2/1.5/1.8/2.5v ? built-in pseudo-random bit sequence (prbs) generator/checker ? smartpower? dynamically reduces power consumption ? green/rohs compliant package m21131/m21151 typical application diagram 72x72/ 144x144 crosspoint core o/e e/o phy/pointer processor o/e e/o pointer processor ser/des cdr optical optical driver driver ds3/e3 ds1/e1 vt/ framer/ mapper spe/ framer/ mapper line card/backplane sfp/xfp sfp/xfp optical optical dc~3.2 gbps dc~3.2 gbps video sd/hd video sd/hd
211x1-dsh-001-i mindspeed technologies ? 2 mindspeed proprietary and confidential ordering information 72x72 3.2 gbps crosspoint switch ordering information part number package type substrate material green/ eutectic operating temperature availability m21131-12 (1) 1156-terminal, 35 mm, bga cer amic eutectic 0c to 85 c now m21131g-12 (1) 1156-terminal, 35 mm, bga cer amic green 0c to 85 c now m21131g-13 (1,2) 1156-terminal, 35 mm, bga cer amic green 0c to 85 c now m21131-22 1156-terminal, 35 mm, bga cpcore eutectic 0c to 85 c production orders: 01/01/2011 M21131G-22 1156-terminal, 35 mm, bga cpcore green 0c to 85 c production orders: 01/01/2011 m21131g-23 (2) 1156-terminal, 35 mm, bga cpcore green 0c to 85 c production orders: 01/01/2011 (1) not recommended for new designs (2) improved input sensitivity especially for sdi applications 144x144 3.2 gbps crosspoint switch ordering information part number package type substrate material green/ eutectic operating temperature availability m21151-13 (1) 1156-terminal, 35 mm, bga cer amic eutectic 0c to 85 c now m21151g-13 (1) 1156-terminal, 35 mm, bga cer amic green 0c to 85 c now m21151g-14 (1,2) 1156-terminal, 35 mm, bga cer amic green 0c to 85 c now m21151-23 1156-terminal, 35 mm, bga cpcore eutectic 0c to 85 c production orders: 01/01/2011 m21151g-23 1156-terminal, 35 mm, bga cpcore green 0c to 85 c production orders: 01/01/2011 m21151g-24 (2) 1156-terminal, 35 mm, bga cpcore green 0c to 85 c production orders: 01/01/2011 (1) not recommended for new designs (2) improved input sensitivity especially for sdi applications note: ? mindspeed is changing the package substrate material from ceramic to cpcore. for traceability, the revision code will be changed from -1x to -2x to signify this change. the devi ce silicon will rema in unchanged during this transition. the differences between the cpcore and cera mic packaged materi al are outlined in section 2.1.3 . ? these devices are shipped in trays. ? the letter ?g? designator af ter the part number indicates that the device is rohs compliant. refer to www.minds peed.com for additional information. the rohs compliant devices are backwards compat ible with 225 c reflow profiles.
211x1-dsh-001-i mindspeed technologies ? 3 mindspeed proprietary and confidential revision history revision level date description i released december 2012 corrected an error in table 1- 1. maximum voltage on cmos inputs should be referenced to dvdd_io instead of avdd_io h released july 2010 expanded ordering matrix to include all current revisions. g released may 2010 revised part numbers to -23 and -24. corrected signal names on pin af 1 inp[117] and af2 inn[117]. updated marking diagrams. update package from ceramic to cpcore. please see section 2.1.3 for package changes f released october 2009 revised for m21131-13 part details. added marking diagrams. removed m21131-12 parameters from table 1-6 . removed bga assignments by ball name tables. corrrected global control of de-emphasis duration values in table 3-33 . e released may 2009 see prior revisions for revision history details. d released september 2008 see prior revisions for revision history details. m21131 marking diagrams m21151 marking diagrams xxxx .x yyww cc m21131 -xx m21131 - xx marking diagr am e part number lot number date and country code xxxx .x yyww cc m21131 g-xx rohs symbol m21131 g-xx marking diagram xxxx .x yyww cc m21151 -xx m21151 - xx marking diagr am e part number lot number date and country code xxxx .x yyww cc m21151 g-xx rohs symbol m21151 g-xx marking diagram
211x1-dsh-001-i mindspeed technologies ? 4 mindspeed proprietary and confidential table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 package outline drawing and pin descripti ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 package outline drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.1.1 m21131 and m2 1151 packaging drawing (-12/-13/ -14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.1.2 m21131 and m2 1151 packaging drawing (-22/-23/ -24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1.3 package changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.2 pinout diagram and pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.3 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 3.0 control registers map and descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1 control registers descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 3.1.1 even prbs registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 3.1.2 odd prbs registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 3.1.3 global registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 4.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.2 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.2.1 document conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.2.2 power supply configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.3 serial interface and switch programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 4.3.1 switch state register concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.3.2 parallel i/o overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.3.3 serial i/o overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.3.3.1 timing diagram clock set and program modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 4.3.4 switch setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4.3.5 input/output enable and output logic swing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4.3.6 programmable input equalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4.3.7 programmable output de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4.3.8 duty cycle distortion (offset) circuit on inputs to switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.3.9 input signal activity monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.3.9.1 los data rate programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.3.9.2 los signal busing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
table of contents 211x1-dsh-001-i mindspeed technologies ? 5 mindspeed proprietary and confidential 4.3.10 power-up sequence and devi ce reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.3.11 product and revision codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.3.12 core power saving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.3.13 prbs transmitter and receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.3.13.1 prbs tx pattern generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 4.3.13.2 additional test patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.3.13.3 prbs output data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.3.13.4 prbs rx control parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.3.13.5 prbs cdr control parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 4.3.14 prbs cdr data rate programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 4.3.14.1 settings for non-standard rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 4.3.14.2 prbs error detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
211x1-dsh-001-i mindspeed technologies ? 6 mindspeed proprietary and confidential 1.0 electrical characteristics unless noted otherwise, specifications in this section are valid with av dd _core = 1.2v, av dd _io = 1.8v, and dv dd _io = 2.5v power supplies, 25 c ambient temperature, 800 mvpp differential input/output data swing, prbs 2 15 ? 1 test pattern at 3.2 gbps, rl = 50 . table 1-1. absolute maximum ratings (1) symbol parameter minimum typical maximum unit dv dd _io digital logic i/o supply 0 +3.6 v av dd _io switch i/o supply 0 +2.7 v av dd _core switch core supply 0 +1.5 v v cml dc input voltage (cml) v ss - 0.5 ? av dd _io + 0.5 v v cmos dc input voltage (cmos) v ss - 0.5 ? dv dd _io + 0.5 v tst storage temperature -65 +150 c vesd human body model (low-speed) 1000 ? v vesd human body model (high-speed) 500 ? v vesd charge device model 150 ? v notes: 1. exposure to these conditions over extended pe riods of time may affect device reliability. table 1-2. recommended operating conditions symbol parameter notes minimum typical maximum unit dv dd _io digital supply voltage 2 +1.71 +1.8/2.5/3.3 +3.47 v av dd _io analog i/o supply voltage 2 +1.14 +1.2/1.5/1.8/2.5 +2.63 v av dd _core switch core supply voltage 2 +1.14 +1.2 +1.26 v tc package heat spreader temperature 1, 3 0 ? +85 c jc junction to case thermal resistance 0.3 c/w notes: 1. lower limit is ambient temperature and upper limit is case temperature. 2. power supply tolerances are 5%. 3. please refer to the 144 xps thermal application note for thermal design and bolted down heat sink recommendations for this pr oduct. the use of adhesively mounted heatsinks is prohibited.
electrical characteristics 211x1-dsh-001-i mindspeed technologies ? 7 mindspeed proprietary and confidential table 1-3. m21131 power dc electrical specifications symbol parameter notes minimum typical maximum (1) unit aidd_core core current consumption, small output swing, smartpower on 1,2 ? 4.2 4.4 a core current consumption, small output swing, smartpower off 1,2 ? 8.6 9.0 a aidd_io i/o current consumption, small ou tput swing, +1.2v i/o 2 ? 1.3 1.4 a i/o current consumption, small ou tput swing, +2.5v i/o 2 ? 2.8 3.0 a pdiss power dissipation at +1.2v core, +1. 2v i/o, smartpower on 2 ? 6.6 7.0 w power dissipation at +1.2v core, +2. 5v i/o, smartpower on 2 ? 12.1 12.8 w aidd_core core current consumption, medium output swing, smartpower on 1,2 ? 4.4 4.6 a core current consumption, medium output swing, smartpower off 1,2 ? 8.8 9.2 a aidd_io i/o current consumption, medium output swing, +1.2v i/o 2 ? 2.0 2.1 a i/o current consumption, medium output swing, +2.5v i/o 2 ? 3.1 3.2 a pdiss power dissipation at +1.2v core, +1. 2v i/o, smartpower on 2 ? 7.7 8.0 w power dissipation at +1.2v core, +2. 5v i/o, smartpower on 2 ? 12.9 13.5 w aidd_core core current consumption, high output swing, smartpower on 1,2 ? 4.5 4.7 a core current consumption, high output swing, smartpower off 1,2 ? 8.9 9.4 a aidd_io i/o current consumption, high output swing, +1.2v i/o 2 ? 2.5 2.7 a i/o current consumption, high output swing, +2.5v i/o 2 ? 3.5 3.7 a pdiss power dissipation at +1.2v core, +1. 2v i/o, smartpower on 2 ? 8.4 8.9 w power dissipation at +1.2v core, +2. 5v i/o, smartpower on 2 ? 14.2 14.9 w didd_io digital current consumption dv dd _io = +2.5v 2 ? 0.626 25 ma notes: 1. core power supply is +1.26v, (+1.20v, +5%). 2. 1-to-1 mapping (input0 to output0, input1 to output1,...).
electrical characteristics 211x1-dsh-001-i mindspeed technologies ? 8 mindspeed proprietary and confidential table 1-4. m21151 power dc electrical specifications (1) symbol parameter notes minimum typical maximum unit aidd_core core current consumption, small output swing, smartpower on 1,2 ? 8.3 8.5 a core current consumption, small output swing, smartpower off 1,2 ? 11.2 11.5 a aidd_io i/o current consumption, small output swing, +1.2v i/o 2 ? 2.5 2.6 a i/o current consumption, small output swing, +2.5v i/o 2 ? 3.6 3.7 a pdiss power dissipation at +1.2v core, +1.2v i/o, smartpower on 2 ? 12.9 13.3 w power dissipation at +1.2v core, +2.5v i/o, smartpower on 2 ? 18.9 19.5 w aidd_core core current consumption, medium out put swing, smartpower on 1,2 ? 8.4 8.7 a core current consumption, medium output swing, smartpower off 1,2 ? 11.3 11.7 a aidd_io i/o current consumption, medium output swing, +1.2v i/o 2 ? 3.6 3.8 a i/o current consumption, medium output swing, +2.5v i/o 2 ? 4.7 4.9 a pdiss power dissipation at +1.2v core, +1.2v i/o, smartpower on 2 ? 14.4 15.0 w power dissipation at +1.2v core, +2.5v i/o, smartpower on 2 ? 21.8 22.7 w aidd_core core current consumption, high output swing, smartpower on 1,2 ? 8.7 8.9 a core current consumption, high output swing, smartpower off 1,2 ? 11.6 11.9 a aidd_io i/o current consumption, high out put swing, +1.2v i/o 2 ? 4.3 4.5 a i/o current consumption, high out put swing, +2.5v i/o 2 ? 5.5 6.1 a pdiss power dissipation at +1.2v core, +1.2v i/o, smartpower on 2 ? 15.5 16.1 w power dissipation at +1.2v core, +2.5v i/o, smartpower on 2 ? 24.2 25.9 w didd_io digital current consumption dv dd _io = +2.5v 2 ? 0.626 25 ma notes: 1. core power supply is +1.26v, (+1.20v +5%). 2. 1-to-1 mapping (input0 to output0, input1 to output1,...). table 1-5. cmos dc electrical specifications symbol parameter minimum typical maximum unit v oh output logic high i oh = -100 a 0.8 x dv dd _io ? ? v v ol output logic low i ol = 100 a??0.2 x dv dd _io v v ih input logic high dv dd _io - 0.3 ? +3.6 v v il input logic low 0 ? +0.3 v
electrical characteristics 211x1-dsh-001-i mindspeed technologies ? 9 mindspeed proprietary and confidential table 1-6. pcml input elec trical specifications (1) symbol parameter notes minimum typical maximum unit v id input differential voltage (peak-to-peak) prbs sdi pseudo-pathological pattern 1 100 ? ? 350 1200 ? mv v icm input common-mode voltage ? av dd _io - 300 ? mv v ih maximum input high voltage ? ? av dd _io + 300 mv v il minimum input low voltage av dd _io - 800 ? ? mv s 11 input return loss (40 mhz to 2 ghz) ? -10.0 ? db s 11 input return loss (2 ghz to 5 ghz) ? -5.0 ? db notes: 1. input sensitivity specified @ 3.2 gbps prbs 2 23 -1 and ber 10 -12 . table 1-7. pcml output specifications symbol parameter notes minimum typical maximum unit dr out operating data rate (nrz data) ? dc ? 3.2 gbps j outrms output data broadband jitter (rms) ? ? ? 6.0 ps j outp-p output data broadband jitter (peak-to-peak) ? ? ? 36.0 ps t rise/fall rise time/fall time (20 to 80%) 2 ? ? 145 ps v od low swing: diff erential swing medium swing: di fferential swing high swing: differential swing ? ? 3 390 700 920 650 950 1225 700 1200 1600 mv s 22 output return loss (40 mhz to 2.5 ghz) output return loss (2.5 ghz to 5 ghz) 1? ? -15.0 -5.0 ? ? db t dj output deterministic jitter (isi) ? 125 ? mui t rj output random jitter ? 2 ? mui rms notes: 1. rf parameters measured into a 50 load on m21131/m21151 evm. 2. rise/fall time specificati on is for lowest output swing settings. rise/fall ti me improves with higher output swing settings. 3. package and recommended heat sink are not rated for this mode at a v dd _io = +2.5 v due to high power dissipation; improved thermal man- agement at the board level would be necessary to use this mode at a v dd _io = +2.5 v .
electrical characteristics 211x1-dsh-001-i mindspeed technologies ? 10 mindspeed proprietary and confidential figure 1-1. input equalization test setup figure 1-2. de-emphasis test setup bert hm-zd hm-zd m21131/m21151 evm m21151 sma scope/error detector copper trace bert hm-zd hm-zd m21131/m21151 evm m21151 sma scope/error detector fr-4 copper trace
211x1-dsh-001-i mindspeed technologies ? 11 mindspeed proprietary and confidential 2.0 package outline drawing and pin descriptions 2.1 package outline drawing 2.1.1 m21131 and m21151 pack aging drawing (-12/-13/-14) figure 2-1 illustrates the m21131/m21151 (-12/ -13/-14) overall package dimensio ns and a cross sectional view, figure 2-2 is a bottom view of the packag e with ball assignments. the substrate thickness is 2.03 millimeters. all dimensions are in millimeters. the ball count is 1156, the width of each ball is 0.60 m illimeters, and the ball pitch from center to center is 1.00 millimeters. figure 2-1. m21131/m21151 (-12/-13/-14) package outline top view and cross sectional view (in mm) (heat spreader)
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 12 mindspeed proprietary and confidential figure 2-2. m21131/m21151 (-12-13/-14) bottom view of package (in mm)
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 13 mindspeed proprietary and confidential 2.1.2 m21131 and m21151 pack aging drawing (-22/-23/-24) figure 2-3 illustrates the m21131/m21151 (-22/ -23/-24) overall packa ge dimensions and a cross sectional view, figure 2-4 is a bottom view of the packag e with ball assignments. the substrate thickness is 2.03 millimeters. all dimensions are in millimeters. the ball count is 1156, the width of each ball is 0.60 m illimeters, and the ball pitch from center to center is 1.00 millimeters. figure 2-3. m21131/m21151 (-22/-23/-24) package outline top view and cross sectional view (in mm)
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 14 mindspeed proprietary and confidential 2.1.3 package changes there are some differences between ceramic and cpcore in package dimension and construction. they are listed below: figure 2-4. m21131/m21151 (-22/-23/-24) bottom view of package (in mm) table 2-1. differences between ceramic and cpcore packaging dimension differences units ceramic cpcore x dimension 35 +0.15/-0.20 35 +/-0.1 mm y dimension 35 +0.15/-0.20 35 +/-0.1 mm z dimension 3.85 +/-0.26 3.16 +/-0.25 mm coplanarity 0.15 0.20 mm
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 15 mindspeed proprietary and confidential 2.2 pinout diagram and pin descriptions table 2-2. bga assignments (1 of 8) note: for the m21131, the inp/n[72:143] and ou tp/n[72:143] pins are nc (no connect). location name a1 addr9 a2 data6 a3 xrst a4 outp[134] a5 outp[122] a6 outp[138] a7 outp[132] a8 outp[126] a9 outp[120] a10 outp[114] a11 outp[108] a12 outp[102] a13 outp[96] a14 outp[90] a15 outp[84] a16 outp[78] a17 outp[72] a18 outp[66] a19 outp[60] a20 outp[54] a21 outp[48] a22 outp[42] a23 outp[36] a24 outp[30] a25 outp[24] a26 outp[18] a27 outp[12] a28 outp[6] a29 outp[0] a30 outp[20] a31 outp[8] a32 dirxp[0] a33 dotxp[0] a34 clktxref[0] b1 addr8 b2 data7 b3 r/xw b4 outn[134] b5 outn[122] b6 outn[138] b7 outn[132] b8 outn[126] b9 outn[120] b10 outn[114] b11 outn[108] b12 outn[102] b13 outn[96] b14 outn[90] b15 outn[84] b16 outn[78] b17 outn[72] b18 outn[66] b19 outn[60] b20 outn[54] b21 outn[48] b22 outn[42] b23 outn[36] b24 outn[30] b25 outn[24] b26 outn[18] b27 outn[12] b28 outn[6] b29 outn[0] b30 outn[20] b31 outn[8] b32 dirxn[0] b33 dotxn[0] b34 trig[0] c1 inp[7] c2 inn[7] c3 avss c4 data5 location name c5 xcs c6 xtest c7 av ss c8 av dd _io c9 av ss c10 av dd _io c11 av ss c12 av dd _io c13 av ss c14 av dd _io c15 av ss c16 av dd _io c17 av ss c18 av dd _io c19 av ss c20 av dd _io c21 av ss c22 av dd _io c23 av ss c24 av dd _io c25 av ss c26 av dd _io c27 av ss c28 av dd _io c29 av ss c30 mdspdtest[[3] c31 mdspdtest[2] c32 perror[0] c33 inn[0] c34 inp[0] d1 inp[17] d2 inn[17] d3 xds/sclk d4 addr7 d5 addr6 d6 data4 location name d7 outp[136] d8 outp[140] d9 outp[128] d10 outp[116] d11 outp[110] d12 outp[104] d13 outp[98] d14 outp[92] d15 outp[86] d16 outp[80] d17 outp[74] d18 outp[68] d19 outp[62] d20 outp[56] d21 outp[50] d22 outp[44] d23 outp[38] d24 outp[32] d25 outp[26] d26 outp[14] d27 outp[2] d28 outp[34] d29 outp[22] d30 outp[10] d31 xrstrx[0] d32 mdspdtest[1] d33 inn[14] d34 inp[14] e1 inp[5] e2 inn[5] e3 addr5 e4 addr1 e5 addr4 e6 xset e7 outn[136] e8 outn[140] location name
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 16 mindspeed proprietary and confidential e9 outn[128] e10 outn[116] e11 outn[110] e12 outn[104] e13 outn[98] e14 outn[92] e15 outn[86] e16 outn[80] e17 outn[74] e18 outn[68] e19 outn[62] e20 outn[56] e21 outn[50] e22 outn[44] e23 outn[38] e24 outn[32] e25 outn[26] e26 outn[14] e27 outn[2] e28 outn[34] e29 outn[22] e30 outn[10] e31 av ss e32 av dd _io e33 inn[4] e34 inp[4] f1 inp[9] f2 inn[9] f3 addr2 f4 xoutdis f5 addr0 f6 addr3 f7 data2 f8 mdspdtest[28] f9 av dd _io f10 av ss f11 av dd _io location name f12 av ss f13 av dd _io f14 av ss f15 av dd _io f16 av ss f17 av dd _io f18 av ss f19 av dd _io f20 av ss f21 av dd _io f22 av ss f23 av dd _io f24 av ss f25 av dd _io f26 av ss f27 av dd _io f28 av ss f29 av dd _io f30 inn[6] f31 inp[6] f32 av ss f33 inn[8] f34 inp[8] g1 inp[13] g2 inn[13] g3 av ss g4 inp[1] g5 inn[1] g6 xindis g7 mdspdtest[4] g8 outp[142] g9 outp[130] g10 outp[124] g11 outp[118] g12 outp[112] g13 outp[106] g14 outp[100] location name g15 outp[94] g16 outp[88] g17 outp[82] g18 outp[76] g19 outp[70] g20 outp[64] g21 outp[58] g22 outp[52] g23 outp[46] g24 outp[40] g25 outp[28] g26 outp[16] g27 outp[4] g28 clktxp[0] g29 av ss g30 inn[16] g31 inp[16] g32 av dd _io g33 inn[12] g34 inp[12] h1 inp[21] h2 inn[21] h3 av dd _io h4 inp[15] h5 inn[15] h6 data1 h7 mdspdtest[5] h8 outn[142] h9 outn[130] h10 outn[124] h11 outn[118] h12 outn[112] h13 outn[106] h14 outn[100] h15 outn[94] h16 outn[88] h17 outn[82] location name h18 outn[76] h19 outn[70] h20 outn[64] h21 outn[58] h22 outn[52] h23 outn[46] h24 outn[40] h25 outn[28] h26 outn[16] h27 outn[4] h28 clktxn[0] h29 av dd _io h30 inn[22] h31 inp[22] h32 av ss h33 inn[20] h34 inp[20] j1 inp[25] j2 inn[25] j3 av ss j4 inp[23] j5 inn[23] j6 av dd _io j7 inp[3] j8 inn[3] j9 av ss j10 mdspdtest[29] j11 av ss j12 av dd _io j13 av dd _io j14 av dd _core j15 av dd _core j16 av dd _io j17 av dd _io j18 av dd _core j19 av dd _core j20 av dd _io location name table 2-2. bga assignments (2 of 8)
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 17 mindspeed proprietary and confidential j21 av dd _io j22 av dd _core j23 av dd _core j24 av ss j25 av dd _io j26 av ss j27 inn[2] j28 inp[2] j29 av ss j30 inn[30] j31 inp[30] j32 av dd _io j33 inn[24] j34 inp[24] k1 inp[29] k2 inn[29] k3 av dd _io k4 inp[31] k5 inn[31] k6 av ss k7 inp[11] k8 inn[11] k9 n/c k10 ser/xpar k11 data3 k12 av ss k13 av ss k14 av ss k15 av ss k16 av ss k17 av ss k18 av ss k19 av ss k20 av ss k21 av ss k22 av ss k23 av ss location name k24 mdspdtest[32] k25 xenrx[0] k26 av dd _io k27 inn[10] k28 inp[10] k29 av dd _io k30 inn[32] k31 inp[32] k32 av ss k33 inn[28] k34 inp[28] l1 inp[37] l2 inn[37] l3 av ss l4 inp[33] l5 inn[33] l6 av dd _io l7 inp[19] l8 inn[19] l9 dv ss _io l10 los l11 data0 l12 av ss l13 av ss l14 av ss l15 av ss l16 av ss l17 av ss l18 av ss l19 av ss l20 av ss l21 av ss l22 av ss l23 av ss l24 mdspdtest[33] l25 xentx[0] l26 av ss location name l27 inn[18] l28 inp[18] l29 av ss l30 inn[38] l31 inp[38] l32 av dd _io l33 inn[36] l34 inp[36] m1 inp[41] m2 inn[41] m3 av dd _io m4 inp[39] m5 inn[39] m6 av ss m7 inp[27] m8 inn[27] m9 av dd _core m10 dv dd _io m11 av ss m12 av dd _io m13 av dd _io m14 av ss m15 av ss m16 av dd _core m17 av dd _core m18 av dd _core m19 av dd _core m20 av ss m21 av ss m22 av dd _io m23 av dd _io m24 av ss m25 av ss m26 av dd _core m27 inn[26] m28 inp[26] m29 av dd _io location name m30 inn[46] m31 inp[46] m32 av ss m33 inn[40] m34 inp[40] n1 inp[45] n2 inn[45] n3 av ss n4 inp[47] n5 inn[47] n6 av dd _io n7 inp[35] n8 inn[35] n9 av dd _core n10 av ss n11 av ss n12 av dd _io n13 av dd _io n14 av ss n15 av ss n16 av dd _core n17 av dd _core n18 av dd _core n19 av dd _core n20 av ss n21 av ss n22 av dd _io n23 av dd _io n24 av ss n25 av ss n26 av dd _core n27 inn[34] n28 inp[34] n29 av ss n30 inn[48] n31 inp[48] n32 av dd _io location name table 2-2. bga assignments (3 of 8)
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 18 mindspeed proprietary and confidential n33 inn[44] n34 inp[44] p1 inp[53] p2 inn[53] p3 av dd _io p4 inp[49] p5 inn[49] p6 av ss p7 inp[43] p8 inn[43] p9 av dd _io p10 av ss p11 av ss p12 av dd _io p13 av dd _io p14 av ss p15 av ss p16 av dd _core p17 av dd _core p18 av dd _core p19 av dd _core p20 av ss p21 av ss p22 av dd _io p23 av dd _io p24 av ss p25 av ss p26 av dd _io p27 inn[42] p28 inp[42] p29 av dd _io p30 inn[54] p31 inp[54] p32 av ss p33 inn[52] p34 inp[52] r1 inp[57] location name r2 inn[57] r3 av ss r4 inp[55] r5 inn[55] r6 av dd _io r7 inp[51] r8 inn[51] r9 av dd _io r10 av ss r11 av ss r12 av dd _io r13 av dd _io r14 av ss r15 av ss r16 av dd _core r17 av dd _core r18 av dd _core r19 av dd _core r20 av ss r21 av ss r22 av dd _io r23 av dd _io r24 av ss r25 av ss r26 av dd _io r27 inn[50] r28 inp[50] r29 av ss r30 inn[62] r31 inp[62] r32 av dd _io r33 inn[56] r34 inp[56] t1 inp[61] t2 inn[61] t3 av dd _io t4 inp[63] location name t5 inn[63] t6 av ss t7 inp[59] t8 inn[59] t9 av dd _core t10 av ss t11 av ss t12 av dd _io t13 av dd _io t14 av ss t15 av ss t16 av dd _core t17 av dd _core t18 av dd _core t19 av dd _core t20 av ss t21 av ss t22 av dd _io t23 av dd _io t24 av ss t25 av ss t26 av dd _core t27 inn[58] t28 inp[58] t29 av dd _io t30 inn[64] t31 inp[64] t32 av ss t33 inn[60] t34 inp[60] u1 inp[69] u2 inn[69] u3 av ss u4 inp[65] u5 inn[65] u6 av dd _io u7 inp[67] location name u8 inn[67] u9 av dd _core u10 av ss u11 av ss u12 av dd _io u13 av dd _io u14 av ss u15 av ss u16 av dd _core u17 av dd _core u18 av dd _core u19 av dd _core u20 av ss u21 av ss u22 av dd _io u23 av dd _io u24 av ss u25 av ss u26 av dd _core u27 inn[66] u28 inp[66] u29 av ss u30 inn[70] u31 inp[70] u32 av dd _io u33 inn[68] u34 inp[68] v1 inp[73] v2 inn[73] v3 av dd _io v4 inp[71] v5 inn[71] v6 av ss v7 inp[75] v8 inn[75] v9 av dd _io v10 av ss location name table 2-2. bga assignments (4 of 8)
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 19 mindspeed proprietary and confidential v11 av ss v12 av dd _io v13 av dd _io v14 av ss v15 av ss v16 av dd _core v17 av dd _core v18 av dd _core v19 av dd _core v20 av ss v21 av ss v22 av dd _io v23 av dd _io v24 av ss v25 av ss v26 av dd _io v27 inn[74] v28 inp[74] v29 av dd _io v30 inn[78] v31 inp[78] v32 av ss v33 inn[72] v34 inp[72] w1 inp[77] w2 inn[77] w3 av ss w4 inp[79] w5 inn[79] w6 av dd _io w7 inp[83] w8 inn[83] w9 av dd _io w10 av ss w11 av ss w12 av dd _io w13 av dd _io location name w14 av ss w15 av ss w16 av dd core w17 av dd _core w18 av dd _core w19 av dd _core w20 av ss w21 av ss w22 av dd _io w23 av dd _io w24 av ss w25 av ss w26 av dd _io w27 inn[82] w28 inp[82] w29 av ss w30 inn[80] w31 inp[80] w32 av dd _io w33 inn[76] w34 inp[76] y1 inp[85] y2 inn[85] y3 av dd _io y4 inp[81] y5 inn[81] y6 av ss y7 inp[91] y8 inn[91] y9 av dd _core y10 av ss y11 av ss y12 av dd _io y13 av dd _io y14 av ss y15 av ss y16 av dd _core location name y17 av dd _core y18 av dd _core y19 av dd _core y20 av ss y21 av ss y22 av dd _io y23 av dd _io y24 av ss y25 av ss y26 av dd _core y27 inn[90] y28 inp[90] y29 av dd _io y30 inn[86] y31 inp[86] y32 av ss y33 inn[84] y34 inp[84] aa1 inp[89] aa2 inn[89] aa3 av ss aa4 inp[87] aa5 inn[87] aa6 av dd _io aa7 inp[99] aa8 inn[99] aa9 av dd _core aa10 av ss aa11 av ss aa12 av dd _io aa13 av dd _io aa14 av ss aa15 av ss aa16 av dd _core aa17 av dd _core aa18 av dd _core aa19 av dd _core location name aa20 av ss aa21 av ss aa22 av dd _io aa23 av dd _io aa24 av ss aa25 av ss aa26 av dd _core aa27 inn[98] aa28 inp[98] aa29 av ss aa30 inn[94] aa31 inp[94] aa32 av dd _io aa33 inn[88] aa34 inp[88] ab1 inp[93] ab2 inn[93] ab3 av dd _io ab4 inp[95] ab5 inn[95] ab6 av ss ab7 inp[107] ab8 inn[107] ab9 av dd _io ab10 av ss ab11 av ss ab12 av dd _io ab13 av dd _io ab14 av ss ab15 av ss ab16 av dd _core ab17 av dd _core ab18 av dd _core ab19 av dd _core ab20 av ss ab21 av ss ab22 av dd _io location name table 2-2. bga assignments (5 of 8)
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 20 mindspeed proprietary and confidential ab23 av dd _io ab24 av ss ab25 av ss ab26 av dd _io ab27 inn[106] ab28 inp[106] ab29 av dd _io ab30 inn[96] ab31 inp[96] ab32 av ss ab33 inn[92] ab34 inp[92] ac1 inp[101] ac2 inn[101] ac3 av ss ac4 inp[97] ac5 inn[97] ac6 av dd _io ac7 inp[115] ac8 inn[115] ac9 av dd _io ac10 av ss ac11 av ss ac12 av dd _io ac13 av dd _io ac14 av ss ac15 av ss ac16 av dd _core ac17 av dd _core ac18 av dd _core ac19 av dd _core ac20 av ss ac21 av ss ac22 av dd _io ac23 av dd _io ac24 av ss ac25 av ss location name ac26 av dd _io ac27 inn[114] ac28 inp[114] ac29 av ss ac30 inn[102] ac31 inp[102] ac32 av dd _io ac33 inn[100] ac34 inp[100] ad1 inp[105] ad2 inn[105] ad3 av dd _io ad4 inp[103] ad5 inn[103] ad6 av ss ad7 inp[123] ad8 inn[123] ad9 av ss ad10 perror[1] ad11 mdspdtest[31] ad12 av ss ad13 av ss ad14 av ss ad15 av ss ad16 av ss ad17 av ss ad18 av ss ad19 av ss ad20 av ss ad21 av ss ad22 av ss ad23 av ss ad24 av ss ad25 av ss ad26 av dd _io ad27 inn[122] ad28 inp[122] location name ad29 av dd _io ad30 inn[110] ad31 inp[110] ad32 av ss ad33 inn[104] ad34 inp[104] ae1 inp[109] ae2 inn[109] ae3 av ss ae4 inp[111] ae5 inn[111] ae6 av dd _io ae7 inp[131] ae8 inn[131] ae9 av dd _io ae10 trig[1] ae11 mdspdtest[30] ae12 av ss ae13 av ss ae14 av ss ae15 av ss ae16 av ss ae17 av ss ae18 av ss ae19 av ss ae20 av ss ae21 av ss ae22 av ss ae23 av ss ae24 av ss ae25 av ss ae26 mdspdtest[11] ae27 inn[130] ae28 inp[130] ae29 av ss ae30 inn[112] ae31 inp[112] location name ae32 av dd _io ae33 inn[108] ae34 inp[108] af1 inp[117] af2 inn[117] af3 av dd _io af4 inp[113] af5 inn[113] af6 av ss af7 inp[139] af8 inn[139] af9 av ss af10 av dd _io af11 av ss af12 av dd _io af13 av dd _io af14 av dd _core af15 av dd _core af16 av dd _io af17 av dd _io af18 av dd _core af19 av dd _core af20 av dd _io af21 av dd _io af22 av dd _core af23 av dd _core af24 av dd _io af25 avdd_io af26 mdspdtest[12] af27 inn[138] af28 inp[138] af29 av dd _io af30 inn[118] af31 inp[118] af32 av ss af33 inn[116] af34 inp[116] location name table 2-2. bga assignments (6 of 8)
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 21 mindspeed proprietary and confidential ag1 inp[121] ag2 inn[121] ag3 av ss ag4 inp[119] ag5 inn[119] ag6 av dd _io ag7 clktxn[1] ag8 outn[143] ag9 outn[131] ag10 outn[119] ag11 outn[113] ag12 outn[107] ag13 outn[101] ag14 outn[95] ag15 outn[89] ag16 outn[83] ag17 outn[77] ag18 outn[71] ag19 outn[65] ag20 outn[59] ag21 outn[53] ag22 outn[47] ag23 outn[41] ag24 outn[35] ag25 outn[23] ag26 outn[11] ag27 outn[5] ag28 mdspdtest[17] ag29 av ss ag30 inn[126] ag31 inp[126] ag32 av dd _io ag33 inn[120] ag34 inp[120] ah1 inp[125] ah2 inn[125] ah3 av dd _io location name ah4 inp[127] ah5 inn[127] ah6 av ss ah7 clktxp[1] ah8 outp[143] ah9 outp[131] ah10 outp[119] ah11 outp[113] ah12 outp[107] ah13 outp[101] ah14 outp[95] ah15 outp[89] ah16 outp[83] ah17 outp[77] ah18 outp[71] ah19 outp[65] ah20 outp[59] ah21 outp[53] ah22 outp[47] ah23 outp[41] ah24 outp[35] ah25 outp[23] ah26 outp[11] ah27 outp[5] ah28 mdspdtest[18] ah29 mdspdtest[23] ah30 inn[128] ah31 inp[128] ah32 av ss ah33 inn[124] ah34 inp[124] aj1 inp[133] aj2 inn[133] aj3 av ss aj4 inp[135] aj5 inn[135] aj6 av dd _io location name aj7 av ss aj8 av dd _io aj9 av ss aj10 av dd _io aj11 av ss aj12 av dd _io aj13 av ss aj14 av dd _io aj15 av ss aj16 av dd _io aj17 av ss aj18 av dd _io aj19 av ss aj20 av dd _io aj21 av ss aj22 av dd _io aj23 av ss aj24 av dd _io aj25 av ss aj26 av dd _io aj27 av ss aj28 av dd _io aj29 mdspdtest[24] aj30 inn[142] aj31 inp[142] aj32 av dd _io aj33 inn[132] aj34 inp[132] ak1 inp[137] ak2 inn[137] ak3 xrstrx[1] ak4 inp[143] ak5 inn[143] ak6 outn[137] ak7 outn[125] ak8 outn[141] ak9 outn[129] location name ak10 outn[117] ak11 outn[111] ak12 outn[105] ak13 outn[99] ak14 outn[93] ak15 outn[87] ak16 outn[81] ak17 outn[75] ak18 outn[69] ak19 outn[63] ak20 outn[57] ak21 outn[51] ak22 outn[45] ak23 outn[39] ak24 outn[33] ak25 outn[27] ak26 outn[15] ak27 outn[3] ak28 outn[29] ak29 outn[17] ak30 mdspdtest[21] ak31 mdspdtest[9] ak32 mdspdtest[6] ak33 inn[136] ak34 inp[136] al1 inp[141] al2 inn[141] al3 mdspdtest[27] al4 xenrx[1] al5 mdspdtest[25] al6 outp[137] al7 outp[125] al8 outp[141] al9 outp[129] al10 outp[117] al11 outp[111] al12 outp[105] location name table 2-2. bga assignments (7 of 8)
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 22 mindspeed proprietary and confidential al13 outp[99] al14 outp[93] al15 outp[87] al16 outp[81] al17 outp[75] al18 outp[69] al19 outp[63] al20 outp[57] al21 outp[51] al22 outp[45] al23 outp[39] al24 outp[33] al25 outp[27] al26 outp[15] al27 outp[3] al28 outp[29] al29 outp[17] al30 mdspdtest[22] al31 mdspdtest[8] al32 mdspdtest[7] al33 inn[140] al34 inp[140] am1 inp[129] am2 inn[129] am3 clktxref[1] am4 xentx[1] am5 mdspdtest[26] am6 avss am7 av dd _io am8 av ss am9 av dd _io location name am10 av ss am11 av dd _io am12 av ss am13 av dd _io am14 av ss am15 av dd _io am16 av ss am17 av dd _io am18 av ss am19 av dd _io am20 av ss am21 av dd _io am22 av ss am23 av dd _io am24 av ss am25 av dd _io am26 av ss am27 av dd _io am28 av ss am29 av dd _io am30 av ss am31 mdspdtest[19] am32 mdspdtest[10] am33 inn[134] am34 inp[134] an1 dotxn[1] an2 dirxn[1] an3 outn[135] an4 outn[123] an5 outn[139] an6 outn[133] location name an7 outn[127] an8 outn[121] an9 outn[115] an10 outn[109] an11 outn[103] an12 outn[97] an13 outn[91] an14 outn[85] an15 outn[79] an16 outn[73] an17 outn[67] an18 outn[61] an19 outn[55] an20 outn[49] an21 outn[43] an22 outn[37] an23 outn[31] an24 outn[25] an25 outn[19] an26 outn[13] an27 outn[7] an28 outn[1] an29 outn[21] an30 outn[9] an31 mdspdtest[20] an32 av dd _io an33 n/c an34 mdspdtest[13] ap1 dotxp[1] ap2 dirxp[1] ap3 outp[135] location name ap4 outp[123] ap5 outp[139] ap6 outp[133] ap7 outp[127] ap8 outp[121] ap9 outp[115] ap10 outp[109] ap11 outp[103] ap12 outp[97] ap13 outp[91] ap14 outp[85] ap15 outp[79] ap16 outp[73] ap17 outp[67] ap18 outp[61] ap19 outp[55] ap20 outp[49] ap21 outp[43] ap22 outp[37] ap23 outp[31] ap24 outp[25] ap25 outp[19] ap26 outp[13] ap27 outp[7] ap28 outp[1] ap29 outp[21] ap30 outp[9] ap31 mdspdtest[16] ap32 mdspdtest[15] ap33 rxrefclk ap34 mdspdtest[14] location name table 2-2. bga assignments (8 of 8)
package outline drawing and pin descriptions 211x1-dsh-001-i mindspeed technologies ? 23 mindspeed proprietary and confidential table 2-3. digital power connections location connection l9 dv ss _io m10 dv dd _io table 2-4. bga connections to av dd _io ball location aa12 ac9 af12 aj12 am17 c22 f29 k3 p3 r32 v12 y12 aa13 ac12 af13 aj14 am19 c24 g32 l6 p9 t3 v13 y13 aa22 ac13 af16 aj16 am21 c26 h3 l32 p12 t12 v22 y22 aa23 ac22 af17 aj18 am23 c28 h29 m12 p13 t13 v23 y23 aa32 ac23 af20 aj20 am25 e32 j6 m13 p22 t22 v26 y29 aa6 ac26 af21 aj22 am27 f09 j12 m22 p23 t23 v29 ? ab3 ac32 af24 aj24 am29 f11 j13 m23 p26 t29 w6 ? ab9 ad03 af25 aj26 an32 f13 j16 m29 p29 u6 w9 ? ab12 ad26 af29 aj28 c8 f15 j17 m3 r6 u12 w12 ? ab13 ad29 ag06 aj32 c10 f17 j20 n6 r9 u13 w13 ? ab22 ae6 ag32 am07 c12 f19 j21 n12 r12 u22 w22 ? ab23 ae9 ah3 am9 c14 f21 j25 n13 r13 u23 w23 ? ab26 ae32 aj6 am11 c16 f23 j32 n22 r22 u32 w26 ? ab29 af3 aj8 am13 c18 f25 k26 n23 r23 v3 w32 ? ac6 af10 aj10 am15 c20 f27 k29 n32 r26 v9 y3 ? table 2-5. bga connections to av dd _core ball locations aa9 ac18 j22 n19 t17 v18 aa16 ac19 j23 n26 t18 v19 aa17 af14 m9 p16 t19 w16 aa18 af15 m16 p17 t26 w17 aa19 af18 m17 p18 u9 w18 aa26 af19 m18 p19 u16 w19 ab16 af22 m19 r16 u17 y9 ab17 af23 m26 r17 u18 y16 ab18 j14 n9 r18 u19 y17 ab19 j15 n16 r19 u26 y18 ac16 j18 n17 t9 v16 y19 ac17 j19 n18 t16 v17 y26
211x1-dsh-001-i mindspeed technologies ? 24 mindspeed proprietary and confidential 2.3 pin definitions table 2-6. power pins pin name function type av dd _io analog i/o positive supply power av dd _core analog core positive supply power av ss device ground power dv dd _io digital i/o positive supply power dv ss _io digital i/o negative supply power table 2-7. high-speed signal pins (1 of 2) pin name function termination type inp[71:0] / inp[143:0] positive differential input data 50 internal pull-up to av dd _io input/pcml inn[71:0] / inn[143:0] negative differential input data 50 internal pull-up to av dd _io input/pcml outp[71:0] / outp[143:0] positive differential output data 50 internal pull-up to av dd _io output/pcml outn[71:0] / outn[143:0] negative differential output data 50 internal pull-up to av dd _io output/pcml xindis hardware disable of all inputs (active low) 100 k internal pull-down input/cmos xoutdis hardware disable of all outputs (active low) 100 k internal pull-down input/cmos a[9:0] 10 bit parallel address (bit 9: msb, bit 0: lsb) 100 k internal pull-up input/cmos d[5:0] 6 low bits of 8 bit parallel data (bit 0: lsb) 100 k internal pull-up i/o/cmos d[6]/sdi 7th bit of parallel data or serial data input 100 k internal pull-up i/o/cmos d[7]/sdo 8th bit of parallel data (msb) or serial data output 100 k internal pull-up i/o/cmos dotxp[1:0] positive differential output of 2 23 -1 prbs signal generator 50 internal pull-up to av dd _io output/pcml dotxn[1:0] negative differ ential output of 2 23 -1 prbs signal generator 50 internal pull-up to av dd _io output/pcml clktxp[1:0] positive differential clock for 2 23 -1 prbs signal generator 50 internal pull-up to av dd _io input/pcml clktxn[1:0] negative differential clock for 2 23 -1 prbs signal generator 50 internal pull-up to av dd _io input/pcml clktxref[1:0] low speed reference clock for 2 23 -1 prbs signal generator (2, 3) input/cmos rxrefclk 19.44 mhz clock reference for los detection (2, 3) input/cmos xentx[1:0] enable (active low) 2 23 -1 prbs signal generator clock 100 k internal pull-up to av dd _io input/cmos dirxp[1:0] positive differential data for 2 23 -1 prbs signal receiver 50 internal pull-up to av dd _io input/pcml dirxn[1:0] negative diff erential data for 2 23 -1 prbs signal receiver 50 internal pull-up to av dd _io input/pcml xenrx[1:0] enable (active low) 2 23 -1 pseudorandom rx clock/data 100 k internal pull-up to av dd _io input/cmos
211x1-dsh-001-i mindspeed technologies ? 25 mindspeed proprietary and confidential xrstrx[1:0] reset (active low) 2 23 -1 pseudorandom rx clock/data 100 k internal pull-up to av dd _io input/cmos perror[1:0] prbs receiver bit error flag: latches high on first error (cleared on prbs reset) 100 k internal pull-up output/cmos notes: 1. in prbs mode a portion of the prbs signal will egress from the input terminal to which the prbs transmitter is connected. the device normally connected to these terminals might need to be powered down or temporarily disconnected during pr bs operation; alternatively, an y unused input can be used to route th e prbs signal to any output. 2. 100 k internal pull-ups on all cmos inputs, unless noted as pull-downs. 3. rxrefclk and clktxref[1:0] are cmos inputs that are referenced to av dd _io. table 2-8. control, interface, and alarm pins pin name function termination type r/xw parallel i/0: h = read, l = write (1) input/cmos xds/sclk parallel i/0: data latch, seria l i/0: serial clock (hysteresis) (1) input/cmos xcs serial/parallel: active low i/o enable (1) input/cmos ser/xpar serial/parallel i/o select: h = serial, l = parallel (1) input/cmos xrst hardware reset (active low) (1) input/cmos xtest mindspeed test termin al (active low) (1) input/cmos xset hardware xset terminal enables switching multiple channel configurations simult aneously (active low) (1) input/cmos mdspdtest[33:1] pins reserved for production test (should be left open) (1) n/c trig[1:0] clktx/16 for use as trigger 50 internal pull-up to av dd _io output/pcml los global loss of signal status (1) output/cmos note: 1. 100 k internal pull-ups on all cmos inputs, unless noted as pull-downs. table 2-7. high-speed signal pins (2 of 2) pin name function termination type
211x1-dsh-001-i mindspeed technologies ? 26 mindspeed proprietary and confidential 3.0 control registers map and descriptions table 3-1. control registers map (1 of 2) addr register name d7 d6 d5 d4 d3 d2 d1 d0: lsb common registers 00 inchsel#0 inchsel[7] inchsel[6] i nchsel[5] inchsel[4] inchsel[3] inchsel[2] inchsel[1] inchsel[0] 01 inchsel#1 inchsel[7] inchsel[6] i nchsel[5] inchsel[4] inchsel[3] inchsel[2] inchsel[1] inchsel[0] 02 inchsel#2 inchsel[7] inchsel[6] i nchsel[5] inchsel[4] inchsel[3] inchsel[2] inchsel[1] inchsel[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . 8fh inchsel#143 inchsel[7] inchsel[6] inchsel[5] inchs el[4] inchsel[3] inchsel[2] inchsel[1] inchsel[0] 100 chancfg#0 offset eql[1] eql[0] en_pe out_l evel[1] out_level[0] in_mode[1] in_mode[0] 101 chancfg#1 offset eql[1] eql[0] en_pe out_l evel[1] out_level[0] in_mode[1] in_mode[0] 102 chancfg#2 offset eql[1] eql[0] en_pe out_l evel[1] out_level[0] in_mode[1] in_mode[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . 18fh chancfg#143 offset eql[1] eql[0] en_pe out _level[1] out_level[0] in_mode[1] in_mode[0] 200 in_chan_ctrl#0 0 0 0 0 inh_en 0 los_en 0 201 in_chan_ctrl#1 0 0 0 0 inh_en 0 los_en 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 28fh in_chan_ctrl#143 0 0 0 0 inh_en 0 los_en 0 300 los_dr_sel#0 0 dr_range data_rate[5] data_rate[4] dat a_rate[3] data_rate[2] data_rate[1] data_rate[0] 301 los_dr_sel#1 0 dr_range data_rate[5] data_rate[4] dat a_rate[3] data_rate[2] data_rate[1] data_rate[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . 38fh los_dr_sel#143 0 dr_range data_rate[5] data_rate[4] d ata_rate[3] data_rate[2] data_rate[1] data_rate[0] even prbs registers a0 prbsrxctrl_even en_patrx 0 rxmux rst_rx en_rx core2rx rxcdr_pd 0 a1 prbsrxchsel_even rxchsel[7] rxchsel[6] rxchsel[5] rxch sel[4] rxchsel[3] rxchsel[2] rxchsel[1] rxchsel[0] a2 prbserror_even rxerr[7] rxerr[6] rxerr[5] rxerr[4] rxerr[3] rxerr[2] rxerr[1] rxerr[0] a3 prbsrx_dly_even 0 0 0 prbsrx_dly[4] prbsrx_dly [3] prbsrx_dly[2] prbsrx_dly[1] prbsrx_dly[0] a4 rxcdr_ctrla_even lolwinctrl[1] lolwinctrl[0] 0 0 0 1 los_en 1 a5 rxcdr_ctrlb_even softreset reserved data_rate[5] data_rate[4] data_rate[3] data_rate[2] data_rate[1] data_rate[0] a6 rxcdr_alarms_even reserved reserved reserved reserved reserved reserved los lol a7 prbstxctrl1_even 0 txmux[1] txmux[0] rst_tx en_tx tx2core pll_pd 0 a8 prbstxctrl2_even 0 0 pe_amp en_pe p e_dur sel_div2pat en_pattx pwr_trig a9 prbstxchsel_even txchsel[7] txch sel[6] txchsel[5] txchsel[4] txchsel [3] txchsel[2] txchsel[1] txchsel[0] aa pll_ctrla_ even lolwinctrl[1] lolwinctrl[0] 0 0 0 0 0 1 ab pll_ctrlb_ev en softreset reserved data_rate[5] data_rate[4] data_rate[3] data_rate[2] data_rate[1] data_rate[0] odd prbs registers ac prbsrxctrl_odd en_patrx 0 rxmux rst_rx en_rx core2rx rxcdr_pd 0 ad prbsrxchsel_odd rxchsel[7] rxchsel[6] rxchsel[5] rxchsel[4] rxchsel[3] rxchsel[2] rxchsel[1] rxchsel[0] ae prbserror_odd rxerr[7] rxerr[6] rxerr[5] rxerr[4] rxerr[3] rxerr[2] rxerr[1] rxerr[0] af prbsrx_dly_odd 0 0 0 prbsrx_dly[4] prbsrx_dly [3] prbsrx_dly[2] prbsrx_dly[1] prbsrx_dly[0] b0 rxcdr_ctrla_odd lolwinctrl[1] lolwinctrl[0] 0 0 0 1 los_en 1 b1 rxcdr_ctrlb_odd softreset reserved data_rate[5] data_rate[4] data_rate[3] data_rate[2] data_rate[1] data_rate[0] b2 rxcdr_alarms_odd reserved reserved reserved reserved reserved reserved los lol b3 prbstxctrl1_odd 0 txmux[1] txmux [0] rst_tx en_tx tx2core pll_pd 0 b4 prbstxctrl2_odd 0 0 pe_amp en_pe p e_dur sel_div2pat en_pattx pwr_trig b5 prbstxchsel_odd txchsel[7] txchsel[6 ] txchsel[5] txchsel[4] t xchsel[3] txchsel[2 ] txchsel[1] txchsel[0] b6 pll_ctrla_odd lolwinctrl[1] lolwinctrl[0] 0 0 0 0 0 1 b7 pll_ctrlb_odd softreset reserved data_rate[5] data_rate[ 4] data_rate[3] data _rate[2] data_rate[1] data_rate[0]
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 27 mindspeed proprietary and confidential local registers b8 xsetmode 0 0 0 0 0 0 xset[1] xset[0] b9 xsetcmd xsetcmd[7] xsetcmd[6] xsetcmd[5] xsetcmd [4] xsetcmd[3] xsetcmd[2 ] xsetcmd[1] xsetcmd[0] ba ioenable offset eql[1] eql[0] en_individ out_ level[1] out_level[0] in_mode[1] in_mode[0] bb corectrl 0 0 0 pe_amp pe_dur en_pe 1 en_smartpwr bf softreset srst[7] srst[6] srst[5] srst[4] srst[3] srst[2] srst[1] srst[0] c0 chiprev rev[7] rev[6] rev[5] rev[4] rev[3] rev[2] rev[1] rev[0] c1 prodcode prod[7] prod[6] prod[5] pr od[4] prod[3] prod[2] prod[1] prod[0] c3 win_inlck_lol win_inlck[7] win_inlck[6] win_inlck[5] win_i nlck[4] win_inlck[3] win_inlck[2] win_inlck[1] win_inlck[0] c4 win_outlck_lol win_outlck[7] win_outlck[6] win_outlck[5] win_o utlck[4] win_outlck[3] win_outlck[ 2] win_outlck[1] win_outlck[0] cb global_ctrl 0 0 0 0 0 1 0 clear_alarm 1a2 los_statn los_stat[7] los_stat[6] los_stat[5] los_s tat[4] los_stat[3] los_stat[ 2] los_stat[1] los_stat[0] 1a3 los_statn los_stat[7] los_stat[6] los_stat[5] los_s tat[4] los_stat[3] los_stat[ 2] los_stat[1] los_stat[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . 1b3 los_statn los_stat[7] los_stat[6] los_stat[5] los_s tat[4] los_stat[3] los_stat[ 2] los_stat[1] los_stat[0] notes: d[7]... d[0] represent the internal bus, which is ma pped to the data in both the serial and parallel mode. blank register bits are undefined for a write and read. table 3-1. control registers map (2 of 2) addr register name d7 d6 d5 d4 d3 d2 d1 d0: lsb
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 28 mindspeed proprietary and confidential 3.1 control registers descriptions table 3-2. input channel selection (inchsel: address 00h?47h/00h?8fh) (output channel = address input to route to output = data) bits type default label description 7:0 r/w 00h inchsel select input channel (data) to route to selected output (a dd ress). in#0 = 00h, in#1 = 01h, in#143 = 8fh. table 3-3. i/o input/output configuration (chancfg: address 100h?147h/100h?18fh) (selected channel + 100h is the address) bits type default label description 7 r/w 0 dc offset input dc offset 0: dc offset enable (default) 1: dc offset disable 6:5 r/w 01 eq input equalization 00: minimum eq ( 9 db) 01: small eq ( 12 db) (default) 10: medium eq ( 15 db) 11: large eq ( 18 db) 4 r/w 0 en_pe enable de-emphasis? en_individ (bah, bit 4) must be set to 1 for this bit to be functional. 0: disabled. 1: enabled. 3:2 r/w 11 out_level en_individ (bah, bit 4) must be set to 1 for these bits to be functional. 00: 500 mvp?p differential output. 01: 900 mvp?p differential output. 10: 1200 mvp?p differential output. 11: disable output. 1:0 r/w 10 in_mode en_individ (bah, bit 4) must be set to 1 for these bits to be functional. 00: reserved. 01: reserved. 10: input channel is powered down. 11: input channel is active. table 3-4. input channel control (in_chan _ctrl: address 200h?247h/200h?28fh) bits type default label description 7:4 r/w 0000 ? reserved, set to 0. 3 r/w 0 inh_en 0: inhibit disabled. 1: inhibit enabled. 2 r/w 1 ? reserved, defaults to 1 but must be set to 0. 1 r/w 1 los_en 0: los disabled. 1: los enabled (default). 0 r/w 1 ? reserved, defaults to 1 but must be set to 0.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 29 mindspeed proprietary and confidential 3.1.1 even prbs registers table 3-5. individual channel los data rate control (select channel 300h-347h/300h-38fh) bits type default label description 7 r/w 0 los_dr_sel reserved, default to 0. 6 r/w 0 dr_range 0: 2?3.2 gbps operation (default). 1: 1?1.6 gbps operation. 5:0 r/w 011010 ? select data rate. see section 4.3.9.1 . for data rate programming. 011010: 2.488 gbps (default). table 3-6. prbs rx control (even) (prbsrxctrl_even: address a0h) bits type default label description 7 r/w 0 en_patrx 0: prbsrx configured for 2 23 -1 prbs pattern. 1: prbsrx configured for simp le ?1010? or ?1100? pattern. 6 r/w reserved, must be set to 0. 5 r/w 1 rxmux select rx data input. 0: select input form cross point core. 1: select input from terminals dirxp/n. 4 r/w 1 rst_rx reset rx prbs receiver. 0: rx prbs receiver enabled. 1: rx prbs in reset. 3 r/w 0 en_rx 0: rx prbs disabled. 1: rx prbs enabled. 2 r/w 0 core2rx 0: disconnect all cro ss point outputs from prbs rx. 1: route cross point ou tputs to prbs receiver. 1 r/w 1 rxcdr_pd prbs receiver cdr control. 0: cdr is enabled. 1: cdr is disabled. 0 r/w ? ? reserved, must be set to 0. table 3-7. prbs rx channel select (even) (prbsrxchsel_even: address a1h) bits type default label description 7:0 r/w 00h rxchsel selects channel for prbs rx. table 3-8. prbs rx error count (read only) (prbserror_even: address a2h) bits type default label description 7:0 ro ? rxerr prbs rx error count register (read-only). although this is a read-only register, a write of any value must be performed to latch the latest error count. a prbs rx reset (address a0h, bit 4) will clear the pr bs rx error count register.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 30 mindspeed proprietary and confidential table 3-9. prbs rx delay select (even) (prbsrx_dly_even: address a3h) bits type default label description 7:5 r/w ? ? reserved, must be set to 0 4:0 r/w 00101 prbsrx_dly prbs rx delay select in incremen ts of 1/32 of a bit time (12.5 ps for 2.488 ghz operation). 00000: no delay. 00001: 1/32 of a bit time (12.5 ps for 2.488 ghz operation). ? 00101: 5/32 of a bit time (62.5 ps for 2.488 ghz operation) (default). ? 11111: one bit time (400 ps for 2.488 ghz operation). table 3-10. prbs rx cdr control a (even) (rxcdr_ctrla_even: address a4h) bits type default label description 7:6 r/w 00 lolwinctrl 00: lol window settings are taken from global register. 01: lol window settings are fixed to 48h (narrow) and 55h (wide). 10: lol window settings are fixed to 9 1h (narrow) and aah (wide) (recommended settings). 11: content of register rxcdr_ ctrlb is stored into a separate register, which programs the offset of the vco counter start value. 5:4 r/w ? ? reserved, must be set to 0. 3 r/w 1 ? 0: autoinhibit disabled. 1: autoinhibit enabled. 2 r/w ? ? reserved, must be set to 1. 1 r/w 1 los_en 0: los circuit disabled. 1: los enabled. 0 r/w ? ? reserved, must be set to 1. table 3-11. prbs rx cdr control b (even) (rxcdr_ctrlb_even: address a5h) bits type default label description 7 r/w 0 softreset 0: cdr is in normal mode. 1: cdr is in reset. 6 r/w 0 mspd reserved, defaults to ?0?, must be set to ?1? to use prbs rx cdr. 5:0 r/w 011010 data_rate select data rate. please refer to table 4-6 in the prbs cdr control parameters section for data rate programming. 011010: reference frequency multiplied by 128d.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 31 mindspeed proprietary and confidential table 3-12. prbs rx alarms (read only) (even) (rxcdr_alarms_even: address a6h) (cleared on write, a high alarm status gets latched into the register) bits type default label description 7:2 ro ? ? reserved. 1 ro ? los loss of signal alarm. 0 ro ? lol loss of lock alarm. table 3-13. prbs tx control 1 (eve n) (prbstxctrl1_even: address a7h) bits type default label description 7 r/w ? ? reserved, must be set to 0. 6:5 r/w 10 txmux select prbs tx clock input. 00: select clock generated by prbs tx pll. 01: select clock recovered from prbs rx cdr. 10: select clock from input pins clktxp/n. 11: none. 4 r/w 1 rst_tx 0: prbs tx pattern generator in normal operation. 1: reset prbs tx pattern generator. 3 r/w 0 en_tx 0: tx prbs disabled. 1: tx prbs enabled. 2 r/w 0 tx2core 0: disable the prbs tx from going to the inputs. 1: route prbs tx patt ern through cross point. 1 r/w 1 pll_pd prbs tx pll control. 0: tx pll enabled. 1: tx pll disabled. 0 r/w ? ? reserved, must be set to 0.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 32 mindspeed proprietary and confidential table 3-14. prbs tx control 2 (eve n) (prbstxctrl2_even: address a8h) bits type default label description 7:6 r/w ? ? reserved, must be set to 0. 5 r/w 0 pe_amp control of de-emphasis amplitude. 0: 50% de. 1: 67% de. 4 r/w 0 en_pe enable de-emphasis. 0: disable. 1: enable. 3 r/w 1 pe_dur control of de-emphasis duration. 0: approximately 1200 ps. 1: approximately 600 ps. 2 r/w 0 sel_div2_pat select tx pattern. en_pattx has to be high for this bit to be functional. 0: select 1010 pattern. 1: select 1100 pattern. 1 r/w 0 en_pattx select tx prbs or simple pattern. 0: select prbs tx pattern. 1: select simple pattern: 1010 or 1100 determined by sel_div2_pat . 0 r/w 0 pwr_trig 0: tx prbs trigger disabled. 1: tx prbs trigger enabled. table 3-15. prbs tx channel select (e ven) (prbstxchsel_even: address a9h) bits type default label description 7:0 r/w 01h txchsel select channel for prbs tx. table 3-16. prbs tx pll control a (even) (pll_ctrla_even: address aah) bits type default label description 7:6 r/w 00 lolwinctrl 00: lol window settings are taken from global register. 01: lol window settings are fixed to 48h (narrow) and 55h (wide). 10: lol window settings are fixed to 9 1h (narrow) and aah (wide) (recommended setting). 11: content of register pll_ctrlb is stored into a separate register, which programs the offset of the vco counter start value. 5:1 r/w ? ? reserved, must be set to 0. 0 r/w ? ? reserved, must be set to 1.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 33 mindspeed proprietary and confidential 3.1.2 odd prbs registers table 3-17. prbs tx pll control b (even) (pll_ctrlb_even: address abh) bits type default label description 7 r/w 0 softreset 0: pll is in normal mode. 1: pll is in reset. 6 r/w 0 mspd reserved, defaults to ?0?, must be set to ?1? to use prbs tx pll. 5:0 r/w 011010 data_rate select data rate. please refer to table 4-6 in the prbs cdr control parameters section for data rate programming. 011010: reference frequency multiplied by 128d. table 3-18. prbs rx control (odd) (prbsrxctrl_odd: address ach) bits type default label description 7 r/w 0 en_patrx 0: prbsrx configured for 2 23 -1 prbs pattern. 1: prbsrx configured for simp le ?1010? or ?1100? pattern. 6 r/w reserved, must be set to 0. 5 r/w 1 rxmux select rx data input. 0: select input from cross point core. 1: select input from terminals dirxp/n. 4 r/w 1 rst_rx reset rx prbs receiver. 0: rx prbs receiver enabled. 1: rx prbs in reset. 3 r/w 0 en_rx 0: rx prbs disabled. 1: rx prbs enabled. 2 r/w 0 core2rx 0: disconnect all cro ss point outputs from prbs rx. 1: route cross point ou tputs to prbs receiver. 1 r/w 1 rxcdr_pd prbs receiver cdr control. 0: cdr is enabled. 1: cdr is disabled. 0 r/w ? ? reserved, must be set to 0. table 3-19. prbs rx channel select (odd) (prbsrxchsel_odd: address adh) bits type default label description 7:0 r/w 01h rxchsel selects channel for prbs rx. table 3-20. prbs rx error count (read on ly) (odd) (prbserror_odd: address aeh) bits type default label description 7:0 ro ? rxerr prbs rx error count register (read-only). although this is a read-only register, a write of any value must be performed to latch the latest error count. a prbs rx reset (address a0h, bit 4) will clear the pr bs rx error count register.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 34 mindspeed proprietary and confidential table 3-21. prbs rx delay select (odd) (prbsrx_dly_odd: address afh) bits type default label description 7:5 r/w reserved, must be set to 0. 4:0 r/w 00101 prbsrx_dly prbs rx delay select in incremen ts of 1/32 of a bit time (12.5 ps for 2.488 ghz operation). 00000: no delay. 00001: 1/32 of a bit time (12.5 ps for 2.488 ghz operation). ? 00101: 5/32 of a bit time (62.5 ps for 2.488 ghz operation). ? 11111: one bit time (400 ps for 2.488 ghz operation). table 3-22. prbs rx cdr control a (odd) (rxcdr_ctrla_even: address b0h) bits type default label description 7:6 r/w 00 lolwinctrl 00: lol window settings are taken from global register. 01: lol window settings are fixed to 48h (narrow) and 55h (wide). 10: lol window settings are fixed to 9 1h (narrow) and aah (wide) (recommended setting). 11: content of register rxcdr_ ctrlb is stored into a separate register, which programs the offset of the vco counter start value. 5:4 r/w ? ? reserved, must be set to 0. 3 r/w 1 ? 0: autoinhibit disabled. 1: autoinhibit enabled. 2 r/w ? ? reserved, must be set to 1. 1 r/w 1 los_en 0: los circuit disabled. 1: los enabled. 0 r/w ? ? reserved, must be set to 1. table 3-23. prbs rx cdr control b (odd) (rxcdr_ctrlb_odd: address b1h) bits type default label description 7 r/w 0 softreset 0: cdr is in normal mode. 1: cdr is in reset. 6 r/w 0 mspd reserved, defaults to ?0?, must be set to ?1? to use prbs rx cdr. 5:0 r/w 011010 data_rate select data rate. please refer to table 4-6 in the prbs cdr control parameters section for data rate programming. 011010: reference frequency multiplied by 128d.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 35 mindspeed proprietary and confidential table 3-24. prbs rx alarms (read only) (odd) (rxcdr_alarms_odd: address b2h) bits type default label description 7:2 ro ? ? reserved. 1 ro ? los loss of signal alarm. 0 ro ? lol loss of lock alarm. table 3-25. prbs tx control 1 (odd) (prbstx_ctrl1_odd: address b3h) bits type default label description 7 r/w ? ? reserved, must be set to 0. 6:5 r/w 10 txmux select prbs tx clock input. 00: select clock generated by prbs tx pll. 01: select clock recovered from prbs rx cdr. 10: select clock from input terminals clktxp/n. 11: none. 4 r/w 1 rst_tx 0: prbs tx pattern generator in normal operation. 1: reset prbs tx pattern generator. 3 r/w 0 en_tx 0: tx prbs disabled. 1: tx prbs enabled. 2 r/w 0 tx2core 0: disable the prbs tx from going to the inputs. 1: route prbs tx patt ern through cross point. 1 r/w 1 pll_pd prbs tx pll control. 0: tx pll is enabled. 1: tx pll is disabled. 0 r/w ? ? reserved, must be set to 0.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 36 mindspeed proprietary and confidential table 3-26. prbs tx control 2 (odd) (prbstx_ctrl2_odd: address b4h) bits type default label description 7:6 r/w ? ? reserved, must be set to 0. 5 r/w 0 pe_amp control of de-emphasis amplitude. 0: 50% pe. 1: 67% pe. 4 r/w 0 en_pe enable de-emphasis. 0: disable. 1: enable. 3 r/w 1 pe_dur control of de-emphasis duration. 0: approximately 1200 ps. 1: approximately 600 ps. 2 r/w 0 sel_div2_pat select tx pattern. en_pattx has to be high for this bit to be functional. 0: select 1010 pattern. 1: select 1100 pattern. 1 r/w 0 en_pattx select tx prbs or simple pattern. 0: select prbs tx pattern. 1: select simple pattern: 1010 or 1100 determined by sel_div2_pat . 0 r/w 0 pwr_trig 0: tx prbs trigger disabled. 1: tx prbs trigger enabled. table 3-27. prbs tx channel select (odd) (prbstxchsel_odd: address b5h) bits type default label description 7:0 r/w 01h txchsel selects channel for prbs tx. table 3-28. prbs tx pll control a (odd) (pll_ctrla_odd: address b6h) bits type default label description 7:6 r/w 00 lolwinctrl 00: lol window settings are taken from global register. 01: lol window settings are fixed to 48h (narrow) and 55h (wide). 10: lol window settings are fixed to 9 1h (narrow) and aah (wide) (recommended setting). 11: content of register pll_ctr lb is stored into a separate register, which programs the offset of the vco counter start value. 5:1 r/w ? ? reserved, must be set to 0. 0 r/w ? ? reserved, must be set to 1.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 37 mindspeed proprietary and confidential 3.1.3 global registers table 3-29. prbs tx pll control b (odd) (pll_ctrlb_odd: address b7h) bits type default label description 7 r/w 0 softreset 0: cdr is in normal mode. 1: cdr is in reset. 6 r/w 0 mspd reserved, defaults to ?0?, must be set to ?1? to use prbs tx pll. 5:0 r/w 011010 data_rate select data rate. please refer to table 4-6 in the prbs cdr control parameters section for data rate programming. 011010: reference frequency multiplied by 128d. table 3-30. xset mode (xset mode: address b8h) bits type default label description 7:2 r/w ? ? reserved, must be set to 0. 1:0 r/w 00 xset selects the xset mode. 00: acl latches are transparent. any switch setting written immediat ely affects the core configuration. 01: acl latches are controlled thr ough register b9h (software xset). 10: acl latches are controlled by terminal xset (hardware control). 11: n/a. table 3-31. software xset (read back always 00h) (xset cmd: address b9h) bits type default label description 7:0 r/w ? xsetcmd register b8h (xset mode) needs to be set to 01 in order for this register to be functional. any value written to this register will update the acl with the icl.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 38 mindspeed proprietary and confidential table 3-32. i/o enable (ioenable: address bah) bits type default label description 7 r/w 0 dc offset input dc offset 0: dc offset enable (default) 1: dc offset disable 6:5 r/w 01 eq input equalization 00: minimum eq ( 9 db) 01: small eq ( 12 db) (default) 10: medium eq ( 15 db) 11: large eq ( 18 db) 4 r/w 0 en_individ this bit controls individual io control. 0: individual input/output configuration (100 to 147h/100h to 18fh) is bypassed. 1: input/outputs are individually controlled by registers 100 to 147h/100h to 18fh. 3:2 r/w 11 out_level en_individ (bah, bit 4) must be set to 0 for these bits to be functional. 00: 500 mvp?p differential on all outputs. 01: 900 mvp?p differential on all outputs. 10: 1200 mvp?p differential on all outputs. 11: disable all outputs. 1:0 r/w 10 in_mode en_individ (bah, bit 4) must be set to 0 for these bits to be functional. 00: reserved. 01: reserved. 10: all input channels are powered down. 11: all input channels are active. table 3-33. core control (corectrl: address bbh) bits type default label description 7:5 r/w ? ? reserved, must be set to 0. 4 r/w 0 pe_amp global control of de-emphasis amplitude. 0: 50% pe. 1: 67% pe. 3 r/w 1 pe_dur global control of de-emphasis duration. 0: approximately 1200 ps. 1: approximately 600 ps (default). 2 r/w 0 en_pe en_individ (bah, bit 4) must be set to 0 for this bit to be functional. 0: disable de-emphasis for all outputs. 1: enable de-emphasis for all outputs. 1 r/w ? ? reserved, must be set to 1. 0 r/w 1 en_smartpwr core smartpower ? control. 0: core fully powered. 1: core in low power mode.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 39 mindspeed proprietary and confidential table 3-34. software reset (softreset: address bfh) bits type default label description 7:0 r/w 00h srst software reset: needs tw o consecutive writes with data = aah. if second write is not a r eset, register is cleared. third write required to bring out of reset. table 3-35. chip revision (chiprev: address c0h) bits type default label description 7:0 ro ? rev chip revision number: m21131-13/m21131g-13: 05h m21131-23/m21131g-23: 05h m21151-14/m21151g-14: 05h m21151-23/m21151g-23: 05h table 3-36. product code (prodcode: address c1h) bits type default label description 7:0 ro ? prod product code number m21131 = 40h m21151 = c0h table 3-37. global lol window detector inlock value (win_inlck_lol: address c3h) bits type default label description 7:0 r/w 1eh win_inlck sets the in lock window value. table 3-38. global lol window detector outlock value (win_outlck_lol: address c4h) bits type default label description 7:0 r/w 03 win_outlck sets the out lock window value. table 3-39. global control (global_ctrl: address cbh) bits type default label description 7:3 r/w ? ? reserved, must be set to 0. 2 r/w ? ? reserved, must be set to 1. 1 r/w ? ? reserved, must be set to 0. 0 r/w 0 clear_alarms 0: all input an d prbs los alarms are active. 1: clear all prbs and input los alarms.
control registers map and descriptions 211x1-dsh-001-i mindspeed technologies ? 40 mindspeed proprietary and confidential table 3-40. los alarms register bank 1 to 18 (los_statn: 1a2?1b3h) bits type default label description 7:0 ro ? los_stat (read only, cleared by clear_alarms). 0: los alarm on cdr (n*8 +[i]) is not present. 1: los alarm on cdr ( n*8 +[i]) is present.
211x1-dsh-001-i mindspeed technologies ? 41 mindspeed proprietary and confidential 4.0 functional description 4.1 overview the m21131/m21151, designed for today?s demanding telecom and datacom applications, is a low-power cmos, high-speed 72x72/144x144 crosspoint switch with input equalization, output de-emphasis, and built-in system test features. the smartpower ? features offer dynamically scalable switch setti ngs to further reduce power consumption without affecting the operation of the remaining channels. to improve signal quality each input buffer is preceded by a programmable input equalizer (ie) and each output includes output de-emphasis (pe). the ie removes isi jitter which is usually caused by pcb skin effect losses. the ie circuit opens the input data eye in applications wher e long pcb traces and cables are used. the pe provides a boost of the high frequency content of the output signal, such that the data eye remains open after passing through a long interconnect of pcb traces and cables. there are two amplitude settings and two duration settings that can be selected on a global basis. de-emphasis can be enabled on a per-channel basis. the device supports data rates from 0 to 3.2 gbps on each channel, allowing any combination of sonet, fibre channel (1x and 2x), infiniband, gigabit ethernet and 10 gbps ethernet traffic. the switch includes a pair of on-board 2 23 -1 pseudo-random bit sequence transmitters (prbs tx) and receivers (prbs rx) for system verification purposes. three-stage switch fabrics with up to 2,880 x 2,880 ports, carrying over 10 terabits per second of traffic, can be designed using this non-blocking switch, with multi-cast and broadcast abilities. all inputs and outputs are differential pcml (positive curr ent mode logic) with supply voltages ranging from 1.2v to 2.5v. the output levels are programmable at 500 mv, 900 mv, and 1200 mv. the m21131/m21151 is available in a 1156 terminal, 35 mm, cbga (ceramic ball grid array) package. the green 72x72/144x144 crosspoint switch is the m21131g/m21151g. the green devices share the same features, specifications, and pinout as the non-green devices.
functional description 211x1-dsh-001-i mindspeed technologies ? 42 mindspeed proprietary and confidential figure 4-1. jitter removal by input equalization and output de-emphasis at 3.2 gbps tx device (no output pre-emphasis) 36" fr-4 trace and backplane connectors 3.2 gbps data eye with input eq disabled - not error free 3.2 gbps data eye with input eq enabled - error free m21131/m21151 crosspoint switch with input equalization 30" fr-4 trace and backplane connectors m21131/m21151 crosspoint switch with output pre-emphasis 3.2 gbps data eye after 30" fr4 trace with output pre- emphasis disabled - not error free 3.2 gbps data eye after 30" fr4 trace with output pre- emphasis enabled - error free
functional description 211x1-dsh-001-i mindspeed technologies ? 43 mindspeed proprietary and confidential figure 4-2. m21131/m21151 func tional block diagram pll cdr data clk prbs tx/rx even pll xenrx<0> 2 23 - 1 prbs rx xset data clk prbs tx/rx odd cdr prbs tx 2 23 - 1 prbs tx 2 23 - 1 2 23 - 1 prbs rx pcml output buffer and programmable output pre-emphasis 144x144 differential crosspoint core pcml input buffer and programmable input equalizer and los monitor active configuration latch (acl) input configuration latch (icl) parallel - serial interface and general registers switch state write bus xrst xtest xcs r/xw d[7]/do d[6]/di d[5:0] a[9:0] xds/sclk switch state read bus xrstrx<0> dirxp/n<0> outp/n<70:0>/ outp/n<142:0> clktxref<0> clktxp/n<0> trig<0> xentx<0> dotxp/n<0> perror<0> prbsrxerr<7:0> clkrxp/n<0> inp/n<0> inp/n<1> inp/n<71>/ inp/n<143> xindis outp/n<0> outp/n<1> outp/n<71>/ outp/n<143> xoutdis outp/n<71:1>/ outp/n<143:1> ser/xpar dirxp/n<1> clktxref<1> clktxp/n<1> trig<1> xentx<1> dotxp/n<1> perror<1> prbsrxerr<7:0> clkrxp/n<1> xenrx<1> xrstrx<1> 72x72/
functional description 211x1-dsh-001-i mindspeed technologies ? 44 mindspeed proprietary and confidential figure 4-3. pcml input and ou tput equivalent circuits figure 4-4. crosspoint application example inp avss avdd_io avdd_io inn avdd_io outp outn avss avdd_io pcml input pcml output 50 50 50 50 mindspeed mindspeed 72x72/ 144x144 crosspoint core o/e e/o phy/pointer processor o/e e/o pointer processor ser/des cdr optical optical driver driver ds3/e3 ds1/e1 vt/ framer/ mapper spe/ framer/ mapper line card/backplane sfp/xfp sfp/xfp optical optical dc~3.2 gbps dc~3.2 gbps video sd/hd video sd/hd
functional description 211x1-dsh-001-i mindspeed technologies ? 45 mindspeed proprietary and confidential 4.2 detailed description 4.2.1 document conventions this document uses the follo wing text styling conventions: signal names and terminal numbers are listed in all upper ca se letters denoting each functional name part, with its related signal polarity indicated by a upper case 'n' or 'p '. thus, data input signal names are indicated, for example as: 'dinp' and 'dinn' . a signal name and an associated channel number (0 through 71/0 through 143) are indicated as dinp[n] and dinn[n] where 'n' is a channel number. a register name is typed in all upper case preceded by the word register with each functional name part separated by an underscore, additionally, brackets group register bit numbers, and sub-function names are in initial caps such as for example only: 'register control_function[ 5:4] los_hyst'. in order to distinguish terminal names from internally gene rated signals, the word ?terminal? is included in reference to an input, output, or control, such as: ?the signal on terminal abc controls function x', or ?when the signal on terminal abc = h function x is enabled'. terminal function descriptions generally do not repeat the word terminal. 4.2.2 power supply configurations below is a summary of possible voltage configurations for the switch core and input/output buffers. ? 2.5v io, 1.2v core ? 1.8v io, 1.2v core ? 1.5v io, 1.2v core ? 1.2v io, 1.2v core (tied together externally) the i/o supply voltage can be chosen independently, no register bit setting is required. the a v dd _io and a v dd _core supplies are separate from the dv dd _io supply, and can be any combination of values specified in ta bl e 1 - 2 . 4.3 serial interface and switch programming the crosspoint switch uses +1.8v/+2.5v/+3.3v cmos interf ace levels to program the s witch state (ss). all input terminals have a 100 k internal pull-up, except xindis and xoutdis, which have internal 100 k pull-downs. the communication protocol may be either a serial synchronous interface or a parallel asynchronous interface using eight or ten bits. either interface can: ? program the switch state ? individually enable/disable inputs or outputs ? access control register s and auxiliary functions ? read back the current state of the switch ? control the programmable equalization this section details the operation of the i/o interface and switch programming in section 4.3.4 . the auxiliary functions and address mapping are described in the section, switch function details.
functional description 211x1-dsh-001-i mindspeed technologies ? 46 mindspeed proprietary and confidential 4.3.1 switch state register concept the various switch functions are accessed through 8-bit registers (memory), which are addressed with the 10-bit address bus. the contents of the registers are transferred via an 8-bit data bus during a read or write. the m21131/m21151 switch-state controller uses a double-b uffered register. the active configuration latch (acl) holds the actual switch setting while the input configuration latch (icl) holds either the actual switch setting or the next switch setting, depending on the mode of operation. the xsetmode register selects o ne of three modes of operation: ? default mode ?core configuration updated after every register write. with xsetmode = 00h, the first mode is enabled and is the default mode after a reset. consequently, the state of the switch changes with each write to a register determining the switch state. in the write mode, as soon as the signal on terminal xds makes a low-to-high transition, the input channel specified by data for the output selected by the 10-bit address bus passes directly through the double buffer memory (icl/acl). as soon as the desired data passes through the acl, the crosspoint core routes the selected input to the desired output to physically change the switch state. on the risi ng edge of xds, this channel is stored (latched) into both the icl and acl. ? xset mode ?core configuration updated after hardware xset command. when register xsetmode = 10 b the hardware xset mode is enabled. in this mode, the desired switch state (which may contain one or more routing changes) is written first to the icl, but the switch state does not change since the data is blocked from the acl. with either the hardware or software xset command, the contents of the icl are transferred to the acl, which physically changes the switch state in the switching core. this mode allows 1 to 144 channels to change at the same time. on the falling edge of the xset signal, the icl contents are passed to the acl an d the switch state changes. on the rising edge of the xset signal, the switch state is latched. ? xset mode ?core configur ation updated after so ftware xset command. when register xsetmode = 01b the software xset mode is selected, an d the desired switch routing is written into the appropriate registers to update the icl without affecting the acl. then, a write of any value to the xsetcmd register will update the acl with the current c ontents of the icl, and th e switch state changes. the interface is configured into the paralle l mode by forcing terminal ser/xpar low. 4.3.2 parallel i/o overview a 10-bit address bus and the register contents (read or write) are transferred via a bidirectional 8-bit data bus. the active-low data strobe (xds) latches (stores) the data into the register on the rising edge of xds. to change the switch state, the double buffer (icl/acl) is transparent (mode1) when signal xds = l in relationship to the data, consequently the switch state will change on the falling edge of signal xds. on the rising edge of xds, the switch state will be stored into the register. the active low terminal xcs gates the i/o and input control signal r/xw selects either a read or write operation. figure 4-5 illustrates the timing diagram for a parallel write operation. ta bl e 4 - 1 shows the parallel write timing specifications as defined in figure 4-5 .
functional description 211x1-dsh-001-i mindspeed technologies ? 47 mindspeed proprietary and confidential figure 4-5. parallel write timing diagram xcs r_xw xds a[9:0] d[7:0] address data write t scs_w t hcs_w t srw_w t hrw_w t sa _w t ha _w t txds_lo _w t txds_hi _w t sd t hd write access xset t sets t setw data is latched on rising edge of xds
functional description 211x1-dsh-001-i mindspeed technologies ? 48 mindspeed proprietary and confidential table 4-1. parallel i/o write timing parameter description minimum typical maximum t scs_w xcs falling edge before xds rising edge 5 ns ? ? t hcs_w xcs hold after rising edge of xds 0 ns ? ? t hrw_w r/xw hold after rising edge of xds 0 ns ? ? t srw_w r/xw setup before rising edge of xds 9 ns ? ? t txdsl_w xds low period 8 ns ? ? t txdsh_w xds high period 8 ns ? ? t sa_w address setup before rising edge of xds 6 ns ? ? t ha_w address hold after rising edge of xds 3 ns ? ? t sd_w data setup before rising edge of xds 3 ns ? ? t hd_w data hold after rising edge of xds 3 ns ? ? t setw hardware xset pulse width 20 ns ? ? t sets hardware xset setup time 3 ns ? ?
functional description 211x1-dsh-001-i mindspeed technologies ? 49 mindspeed proprietary and confidential figure 4-6 shows the timing diagram for a parallel read operation. ta bl e 4 - 2 shows the parallel read timing specifications as defined in figure 4-6 . figure 4-6. parallel read timing diagram table 4-2. parallel i/o read timing parameter description minimum typical maximum t scs_r xcs falling edge before xds falling edge 5 ns ? ? t hcs_r xcs hold after rising edge of xds 0 ns ? ? t hrw_r r/xw hold after rising edge of xds 0 ns ? ? t srw_r r/xw setup before falling edge of xds 5 ns ? ? t txdsl_r xds low period 50 ns ? ? t txdsh_r xds high period 50 ns ? ? t sa_r address setup before falling edge of xds 9 ns ? ? t ha_r address hold after rising edge of xds 2 ns ? ? t a2out address valid to data valid (on read) ? ? 24 ns t out2z xds rising edge to data high z 1 ns ? 8 ns xcs r_xw xds a[9:0] d[7:0] address data read t scs_r t hcs_r t srw _r t hrw_r t sa _r t ha_r t txds_lo _r t txds_hi _r t out2z read access t a2out
functional description 211x1-dsh-001-i mindspeed technologies ? 50 mindspeed proprietary and confidential 4.3.3 serial i/o overview the serial i/o operation is gated by chip select signal xc s (on input terminal xcs). data is shifted in on terminal sdi on the falling edge of the seri al i/o clock input (terminal sclk) , and shifted out on the serial data output (terminal sdo) on the rising edge of sclk. addressing a regist er consists of the following, as shown in figure 4-7 : a 12-bit input, consisting of the first bit (start bit, sb = 1), the second bit (operation bit: op = 1 for read, op = 0 for write), followed by the 10-bit address (most significant bit (msb) first). 4.3.3.1 timing diagram cl ock set and program modes to initiate a write sequence, as shown in figure 4-8 , terminal xcs goes low before the falling edge of sclk. on each falling edge of serial i/o clock (s clk) the 20-bit word cons isting of sb = 1, op = 0, address, and data, are latched into the input shift register. the rising edge of signal xcs must occur before the falling edge of sclk for the last bit. upon receipt of the last bit, one additional cycle of sclk is necessary before the input data transfers from the input shift register to the addressed register. if consecutive read/write cycles are being performed, it is not necessary to insert an extra clock cycle between read/write cycles, however one extra clock cycle is needed after the last data bit of the final read/write cycle to complete the operation. on a write cycle, only the first 18 bits after sb and op are used and all bits that follow are ignored. figure 4-9 illustrates the serial read mode timing diagram. to in itiate a read sequence, th e signal on terminal xcs goes low before the falling edge of sclk. on each falling edge of sclk, th e 12 bits consisting of sb = 1, op = 1, and the10-bit address are written to the serial input shift register of the m21131/m21151. on the first rising edge following the address lsb, the sb and eight bits of the data are shifted out on sdo. the first bit output on sdo for a read operation is always 0. in a read cycle, all extra clock cycles will result in invalid data. for invalid sb/op, the operation is undefined. the falling edge of xcs always resets the seri al operation for a new read/write cycle. ta bl e 4 - 3 contains the timing specifications for the serial programming interface. figure 4-7. serial word format 1 rw a[9:0] d[7:0] 19 18 17 8 7 0 start bit read/write address data lsb msb msb lsb
functional description 211x1-dsh-001-i mindspeed technologies ? 51 mindspeed proprietary and confidential figure 4-8. serial write mode figure 4-9. serial read mode 1 1 t dw tens t clk t wclk sclk sdi t cs t ch xcs t ds t dh wr a6 a7 a8 a9 a5 d7 a0 a1 d4 d5 d6 d3 d2 d1 d0 x x x x x x x x 1 1 0 x sclk xcs t rdd t rds t dw tens t ds t dh t wclk t clk t cs t ch sd o sdi rd a2 a1 a0 d6 d7 d5 d4 d3 d0 d1 d2 a6 a7 a8 a9
functional description 211x1-dsh-001-i mindspeed technologies ? 52 mindspeed proprietary and confidential 4.3.4 switch setting crosspoint functions and options are accessed through hardware terminals, or software via the serial/parallel interface. in some cases, both software and hardware can access the same function. this section describes these functions in detail and ta bl e 3 - 1 lists register functions. the setting parameters are summarized in ta b l e 3 - 1 , which contains the allowable addresses for the m21131/ m21151 crosspoint switch. the inchsel#n register controls the crosspoint connectivity. its register address, inchsel#n, is mapped to the output channel number and its associated data is the input connected to the output n. output channels 0 through 71/0 through 143 are mapped to register addresses = 00h through 37h/00h through 8fh with the output n = address. for example, if register address = 05h and data = 02h (5h = 02h), then output #5 gets input #2. any output can be routed to the internal prbs receiver input and the internal prbs transmitter output can be routed to any of the inputs. to read the current switch state (css) of the acl, the selected channel is specified by register address and the resulting data is the input channel number routed to the selected output. the next switch state (nss) in the icl, if different from the acl, cannot be read back. the default state after power on is channel 0 broadcast to all outputs (all registers cleared). 4.3.5 input/output enable and output logic swing the inputs and outputs have both a hardware global enable and a software global enable as well as individual i/o software controls. terminals xindis and xoutdis control the inputs and outp uts, and are active low (d isabled) with internal pull- downs (100 k ). when terminals xindis = l and/or xoutdis = l all inputs and/or outputs are globally disabled, respectively (default). hardware disable has priority over all software controls. if the i/os are not disabled via the hardware terminals, xindis and/or xoutdis = h, then the ioenable register selects the control status. with ioenable[4] = 0 (default), the software global enable/disable bits (ioenable[1:0] for global input) and table 4-3. serial interface timing?specified at recommended operating conditions symbol item notes minimum typical maximum units t dw data width ? 14 ? ? ns t dh data hold time ? 5 ? ? ns t ds data setup time ? 5 ? ? ns t ens enable setup time ? 5 ? ? ns t cs chip select setup time ? 2 ? t clk - 2 ns t ch chip select hold time ? 2 ? ? ns t r dd read data output delay ? 1 ? 14 ns t rds read data valid ? 9 ? ? ns t clk sclk period width ? 40 ? ? ns t wclk sclk minimum low duration ? 5 ? t clk - 5 ns t r output rise time 1 1 ? 4 ns t f output fall time 1 1 ? 4 ns notes: 1. edge rate in the high edge-rate mode.
functional description 211x1-dsh-001-i mindspeed technologies ? 53 mindspeed proprietary and confidential (ioenable[3:2] for global output) are selected. the individu al global input and output register values default to disable. with ioenable[4] = 1 , the 72/144 chancfg#n registers control the enable/disable status of each channel input and output buffer. the chancfg#n address is computed with n+100h, with the variable n mapped to both the input and output channel. consequently, chancfg#n[3:2] controls the enable/disable status of output n, and chancfg#n[1:0] controls the enable/disable status of input n. with ioenable[4] = 1, ioenable[3:2] and ioenable[1:0] have no meaning. for both inputs and outputs, a disabled state implies turning off the current sources of the i/o buffer to save power. with the built-in pull-up resistors, both ?p ? and ?n? nodes of the differential outp ut will default to th e high logic state when disabled; however, the logic levels of the ?p? and ?n? inputs to the switch core are undetermined. an additional input signal inhibit function is includ ed in the in_chan_ctrl[3] registers (200h?237h/200h?28fh) of the m21131/m21151. with in_chan_ctrl[3] = 1, the ?p? inputs to the switch core are clamped to a logic low and the ?n? inputs are clamped to a logic high. the output drive level is programmable on either a global or individual basis. with ioenable[4] = 0 (default), ioenable[3:2] = 00b selects a global default 500 mvp?p differential output level, and ioenable[3:2] = 01b selects a global default 900 mvp?p differential output level. with ioenable[3:2] = 10b a global 1200 mv differential output level is selected (1200 mv should not be used at a v dd _io = 2.5 v). with ioenable[3:2] = 11b (default) all outputs are disabled. a 500 mvp?p differential output implies a 250 mvp?p single-ended output. with ioenable[4] = 1, chancfg#n[3:2] selects the output level of each channel individually. the global enable, disable, and output swing level register s minimize the software setup overhead of the crosspoint switch after resetting; however, individual control of enab le/disable and output swing le vel is provided for maximum flexibility in some applications. 4.3.6 programmable input equalization in order to compensate for lossy external interconnects, the input buffers include a programmable equalization function. register chancfg#n[6:5] as listed in ta b l e 4 - 4 , controls channel equalization for each input independently. 4.3.7 programmable output de-emphasis similar to input equalization, each output buffer and prbs transmitter has a programmable output de-emphasis (pe) function included. when enabled, the pe will provide a high freq uency boost to the output signal, such that the data eye will be improved (more open) after a long extern al interconnect. with ioenable[4] = 0 (address bah), corectrl[2] (address bbh) globally enables/disables the pe for all outputs. corectrl[2] defaults to 0, pe off. the pe for prbs transmitters are not dependant on ioenable[4], i.e., prbstxctrl2_n[5:3] always control pe for th e prbs transmitters. with ioenable[4] = 0 and corectrl[2] = 1, pe is globally enabled and corectrl [4:3] (address bbh) globally control the pe amplitude and duration for all outputs. the default pe amplitude and duration settings are corectrl[4] = 0 and table 4-4. equalization control bits chancfg#n[6:5] description 00 minimum eq ( 9 db) 01 small eq ( 12 db) (default) 10 medium eq ( 15 db) 11 large eq ( 18 db)
functional description 211x1-dsh-001-i mindspeed technologies ? 54 mindspeed proprietary and confidential corectrl[3] = 1 which globally enable a pe of 50% for a duration of approximately 600 ps (see figure 4-10 ). for example, if the output drive level is set for 1200 mv, when there is a data transition (1-to-0 or 0-to-1) the beginning of each pulse will start at 1200 mv and decay to 600 mv in approximately 600 ps . setting corectrl[4] = 1 (prbstxctrl2_n[5] = 1) enables a higher boost of 67%. for example, if the output drive level is set for 1200 mv, the beginning of each pulse will start at 1200 mv and decay to 400 mv. corectrl[3] = 0 and prbstxctrl2_n[3] = 0 (default is 1) enable a longer decay time of approximately 1200 ps, corresponding to lower frequency boost. this is for interconnects which exhibit attenuation at lower frequencies. with ioenable[4] = 1 (address bah), pe on each output is individually enabled/disabled by chancfg#n[4]. chancfg#n[4] defaults to 0, pe off. the amplitude and duration of the pe on all of outpu ts are still controlled by corectrl[4:3]. the amplitude and duration of the pe on prbs transmitters are controlled by prbstxctrl2_n[5, 3]. table 4-5. de-emphasis control bits register bbh[4:3] description 00 50% amplitude, 1200 ps duration. 01 50% amplitude, 600 ps duration (default). 10 67% amplitude, 1200 ps duration. 11 67% amplitude, 600 ps duration. figure 4-10. definition of de-emphasis levels and duration duration b v s v pre-emphasis level = b v s v x 100
functional description 211x1-dsh-001-i mindspeed technologies ? 55 mindspeed proprietary and confidential 4.3.8 duty cycle distortion (offs et) circuit on inputs to switch each input channel has an offset circuit that can be enab led to correct for dc offset. this circuit is designed to correct duty cycle distortion (dcd) that may be present on either a single ended or differential signal at the input of the switch. it also compensates for common mode drift of the input stage over temperature and power supply variation for single ended inputs. when enabled, the offset feature removes dcd thus improving the quality of the data eye pattern. chancfg#n[7] at addresses 100h?137h/100h?18fh enables the offset function. 4.3.9 input signal activity monitor for operation at data rates of 1.0 gbps to 1.6 gbps and 2.0 gbps to 3.2 gbps, a loss of signal (los) circuit is included on each input and detects whether valid data is present. the 19.44 mhz rxrefclk clock must be provided to the m21131/m21151 and the data rate of the signal must be programmed for the los feature to function properly. los acts as an alarm and can be used to inhibit the signal into the switch core when the data to the input terminal is lost. if the input signal is clamped high or low, or if the difference between the input data rate and the programmed data ra te is greater than approximately 100 mbps, the los alarm will be activated. whenever valid data is present at the input, the los alarm is deactivated. the los circuit is disabled if register in_chan_ctrl#[1] = 0 (default 1) (addresses 200h?237h/200h?28fh). the data rate range is selected using los_dr_sel#n[6] and the data rate is programmed using los_dr_sel#n[5:0] (addresses 300h?337h/300h? 38fh). when register in_chan_ctrl#[3] = 1 (default) a los alarm issues an inhibit signal which forces the switch input to a low state. this minimizes any noise propagating to the switch in the los condition. 4.3.9.1 los data rate programming the los circuit for each input channel operates independently and employs an external 19.44 mhz clock reference, rxrefclk. the los circuit can be programmed to any rate between 2.0 ghz and 3.2 ghz or between 1.0 ghz and 1.6 ghz using register los_dr_sel#n[6:0] (300h?337h/300h?38fh). to select a desired rate, it is necessary to set los_dr_sel#n[6:0] to the value closest to the desired rate. for example if 2.64 ghz is the desired rate: los_dr_sel#n[6] = 0 and the code to be selected (los_dr_sel#n[5:0]) is 100010 (136d), which corresponds to 2.6438 ghz. the programmed frequency is exactly equal to the reference frequency multiplied by the decimal equivalent of the binary value programmed in register los_dr_sel#n[5:0] + 102d. for 1.0 gbps to 1.6 gbps operation, the dr_range bit, los_dr_sel#n[6] must be set to 1. this bit causes the multiplier set by los_dr_sel#n[5:0] to be divided by two. figure 4-11. los architecture input data reference clock (rxrefclk) data_rate los inhibit enable loss of signal detection to xpoint mux 0
functional description 211x1-dsh-001-i mindspeed technologies ? 56 mindspeed proprietary and confidential 4.3.9.2 los signal busing although each input channel has an individual los alarm, the alarms for all of the channels are wired or on chip to create the global los alarm; ther efore, an active los from one or mo re channels will generate a logic high on the global los terminal and set an alarm bit. the alarm bit can be immediately read from los_statn[7:0]. toggling register global_ctrl[0] from 0 to 1 then back to 0 will clear all alarm bits (unless a particular alarm persists, in which case this bit will remain high). 4.3.10 power-up sequen ce and device reset there are no power supplies se quence requirements for the m21131/m21151. pro per hardware reset assertion will ensure that the device will operate proper ly regardless of power supply sequence. the xrst terminal is a hardware reset to be used after power-up or as a general reset. before and during power- up, xrst must be set low. if the device is configured to use the parallel interface for programming the registers, then upon device power-up, the xrst terminal must be held low for a minimum of t reset = 10 s after all power supplies have reached the expected voltage level. once xrst is set high following t reset , the device reset is complete. any hardware reset of the device after power-up can be achieved by setting terminal xrst low for t reset > 10 s and returning it to high. table 4-6. allowed data rates with 19.44 mhz external reference rxcdr_ctrlb_n[5:0] notes bit rate in gbps multiplier 000000 1 1.983 102 000001 1 2.002 103 000010 2.022 104 ??? 011010 2.488 128 ??? 111111 1 3.208 165 note: 1. for decimal multiplier values which are not 104, 112, 120, 128, 136, 144, 152, or 160, more programming steps are required an d are outlined in the ?settings for non-standard rates? section and table 4-7 . figure 4-12. reset timing in parallel programming mode t reset >10s t reset >10s all power supplies xrst 100% 95%
functional description 211x1-dsh-001-i mindspeed technologies ? 57 mindspeed proprietary and confidential if the device is configured to use the serial interface for programming the registers (spi), then a valid spi clock (sclk) must be present at the time of reset. the xrst terminal must be held low for a minimum of t reset >= 4 sclk cycles, after a valid clock signal is a pplied. once xrst is set high following t reset , the device reset is complete. any hardware reset of the device after power up can be achieved by setting terminal xrst low for at least t reset > 4 sclk cycles and returning it to high. following reset, the device will be in the following condition: ? all registers will be set to the default values. ? a software global disables of all in put and output channels will be asserted (through th e i/o enable register). ? input channel 0 will be broadcast to all outputs (the icl and acl are cleared). ? the prbs tx and rx will be disabled. ? all error flags will be cleared if xtest = l after reset, all inputs and outputs are globally enabled and the switch is set with channel 0 broadcast to all outputs. mindspeed uses these features for inter nal die testing, but for normal operation, terminals xtest = h and xrst = h. to enable a software reset, two consecutiv e writes to the softreset register (address, bfh) value (aah) are required. if th e second write is not to the softreset regi ster, the register will be cleared and two additional consecutive writes of (aah ) will be needed to enable a software rese t. hardware reset has priority over software reset. a third write of any value is required to bring the switch out of reset. 4.3.11 product and revision codes a read to the read-only prodcode register causes a readback of the m21131/m21151 product code number. a read to the read-only chiprev register causes a readback of the version number of the chip. the contents of these registers can be used by software drivers to determine the appropriate driver routine to be used. see section 3.1.3 for details. 4.3.12 core power saving the corectrl register enables the core power-saving modes. register corectrl[1] = 0 powers down the switch core and the prbs tx/rx (default power on). figure 4-13. reset timing in serial programming mode t reset t reset sclk xrst all power supplies
functional description 211x1-dsh-001-i mindspeed technologies ? 58 mindspeed proprietary and confidential register corectrl[0] = 1 enables the smartpower ? core control (default). smartpower automatically disables portions of the core mux circuitry that are not active for certain switch configurations. this results in a sign ificant power savings compared to operations when the core mux is fully powered. the actual power saving s will vary across configurations. enabling smartpower will slightly increase the settling time of the device when a new switch core configuration is implemented, so for applications where the minimum configuration time of the switch is desired, smartpower should be disabled. most applications will us e the m21131/m211 51 with smartpower enabled. 4.3.13 prbs transmitter and receiver internally, the switch core input terminals (inp and inn) and output terminals (outp and outn) are grouped into odd and even sections, as shown in the prbs tx and rx functional block diagram, figure 4-14 . likewise, there are two prbs transmitter (tx) and receiver (rx) sections: an odd (1) section which operates with the odd numbered inputs (inp1, 3, 5, etc. and inn1, 3, 5, etc.) and outputs (outp1, 3. 5, etc. and outn1, 3, 5, etc.) an even (0) section which operates with the even numbered inputs (inp0, 2, 4, etc. and inn0, 2, 4, etc.) and outputs (outp0, 2, 4, etc. and outn0, 2, 4, etc.). as a result, there are two sets of prbs control terminals, interface terminals and control registers. see ta bl e 3 - 1 , register summary, (addresses a0 ? b7) for additional information. the references to prbs control registers in this section apply to either the odd or even prbs registers. as an example: terminal dotxp/n[1] is the prbs tx output of the odd (1) section and can only be routed to the odd numbered inputs. if an even numbered input is selected for prbstxchsel_odd[7:0], the prbs tx output will not be connected to any odd numb ered input (to connect a prbs signal to an even numbered input, the even (0) prbs tx section must be enabled and the prbstxchsel_even[7 :0] register must be properly programmed). similarly, the even (0) prbs rx section can only accept even numbered outputs (outp0, 2. 4, etc.). if an odd numbered output is selected for the even (0) prbs rx, no prbs output signal will be connected to the even (0) prbs rx block (invalid output). also, note that since the rx and tx functions are comp letely duplicated, they can be used simultaneously in parallel. for instance, prbs signals can be simultaneously routed into input 1 and input 71/input 1 and input 143. these two prbs signals can then be switched to any even and any odd outputs, respectively. the respective odd and even outputs that were selected can be connected to the prbs rx blocks. the prbs tx and rx sections operate from 1.0 gbps to 1.6 gbps and 2.0 gbps to 3.2 gbps. 4.3.13.1 prbs tx pattern generation the 2 23 -1 prbs tx (with polynomial d23+d18+1) provides a nrz prbs pattern. the prbs tx is enabled with register prbstxctrl1[3] = 1 (default 0) or with terminal xentx = l (cmos level, internal pull-up). an asynchronous reset can be performed by setting prbstxctrl1[4] = 1 and then bringing it low again. the data rate is determined by the external clock on terminal cl ktxp/n (pcml), by an external reference clock clktxref (~19.44mhz, cmos level) or by the recovered clock from the prbs rx block, which is derived from its preceding cdr). register prbstxctrl1[6:5] = 10b (default) selects the high-speed clock input, prbstxctrl1[6:5] = 00b selects the low-frequency reference clock input and prbstxctrl1[6:5] = 01b selects the recovered prbs rx clock. for the case where an external low frequency clock is provided, register prbstxctrl1[1] = 0 enables the tx pll and pll_ctrlb[6:0] sets the actual internal clock frequency into the prbs tx. for a 19.44 mhz
functional description 211x1-dsh-001-i mindspeed technologies ? 59 mindspeed proprietary and confidential reference input, the pll output frequency programming is described in ?prbs cdr control parameters? on page 59 . register pll_ctrlb[7] provides a pll software reset if required. 4.3.13.2 additional test patterns the prbs tx can also output a 0101 or a 0011 pattern. by setting register prbstxctrl2[1] = 1 (default 0) this mode is selected. if prbstxctrl2[2] = 1 then a 0011 pattern is generated otherwise a 0101 pattern is created (default). 4.3.13.3 prbs output data the output data is updated with each rising edge of clktxp. the output terminal trig (clktxp/n divided by 16) is used as a scope trigger to observe the 2 23 -1 pattern and can be disabled with register prbstxctrl2[0 = 0 (default). it is a single ended pcml output with 50 on chip source termination and 450 mvp?p single ended swing into an external 50 load. the prbs tx data can be observed at terminals dotxp and dotxn (pcml output with 50 on chip source termination and 900 mvp?p differential swing into an external 50 load) and can be routed internally to any of the inputs. when routing prbstx through the crosspoint core, dotxp/n needs to be terminated with 50 load. register prbstxctrl1[2] = 0 disables the prbs tx output to be routed to any input; with prbstxctrl1[2] = 1 (default). register prbstxchsel[7:0] se lects the input to which the prbs tx will be routed. input chan nel n is selected by setting prbstxchsel[7:0] = nh. if an invalid input is selected (n>71/143), then the prbs tx will not be routed to any input. note that the prbs tx signal will be forced into the input term inals (the on-chip prbs buffers are operating in current mode); a portion of the prbs signal will egress fr om the input terminal to wh ich the prbs transmitter is connected. the device normally connected to these termin als may need to be powered down (it is acceptable to have the 50 source termination still present) or temp orarily disconnected du ring prbs operation. 4.3.13.4 prbs rx control parameters a 2 23 -1 prbs rx takes in a nrz prbs pattern (with polynomial d23+d18+1) and checks for any bit errors. the prbs rx includes an integrated cdr which uses rxrefclk as a low-speed reference clock. the prbs rx will be enabled with regi ster prbsrxctrl[3] = 1 (default 0) or with terminal xenrx = l (cmos level, internal pull-up). when enabled, the prbs rx takes its input directly from any of the odd or even core outputs as enabled by prbsrxctrl[5] = 0, or from ex ternal inputs dirxp/n enabled by prbsrxctrl[5] = 1 (default). register prbsrxctrl[2] = 0 prevents any of the core outputs from being connected to the prbs rx. if register prbsrxctrl[2] = 1 (default), then prbsrxchsel[7:0] selects which core output channel goes to the prbs rx. in either case, the input to the prbs rx is first routed into a dedicated cdr to resample the data and to extract a clock for the prbs rx. register prbsrxctrl[1] = 0 (default 1) enables the cdr. 4.3.13.5 prbs cdr control parameters register cdr: rxcdr_ctrlb[6:0] controls the desired bit rate, and cdr: rxcdr_ct rlb[7] provides a means for a software reset. the cdr must be in lock before valid data can be passed on to the actual prbs rx circuit. register rxcdr_alarms[1:0] contain the normal cdr alarms; these bits need to be 0 for the prbs rx to produce valid error counts. for this reason the prbs rx ne eds to remain in reset while the cdr is acquiring lock. this can be done by setting register xrstrx = l (cmos level, internal pull-up) or with prbsrxctrl[4] = 1 (default 0).
functional description 211x1-dsh-001-i mindspeed technologies ? 60 mindspeed proprietary and confidential the operation of the cdr for the prbs rx section is controlled through the prbs rx cdr control a and control b registers (addresses a4h, a5h, b0h, and b1h). the cdr for the prbs rx can be reset through rxcdr_ctrlb[7]. this bit must be set to a 1 and then set back to a 0 to issue a software reset. the los circuit for the prbs rx cdr can be enabled/disabled with rxcdr_ctrla[1]. bits 5, 4, 3, 2, and 0 of this register are mindspeed reserved bits and should not be used. bits 5, 4, and 3 should be set to 0 and bits 2 and 0 should be set to 1. 4.3.14 prbs cdr data rate programming for the cdr to achieve a correct frequency acquisition, a frequency acquisition loop is present. the frequency acquisition loop employs an external clock reference, refclk. the external reference clock frequency should be 19.44 mhz 50 ppm. the cdr is able to lock the vco to any rate between 2.0 ghz and 3.2 ghz or from between 1.0 ghz and 1.6 ghz using register rxcdr_ctrlb_n[6:0] (a5h and b1h). to select a desired rate, it is necessary to set rxcdr_ctrlb_n[6:0] to the value closest to the desired rate. for example if 2.64 ghz is the desired rate: rxcdr_ctrlb_n[6] = 0 an d the code to be selected (rxcdr _ctrlb_n[5:0]) is 100010 (136d), which corresponds to 2.6438 ghz. the programmed frequency is exactly equal to the reference frequency multiplied by the decimal equivalent of the binary value programmed in register rxcdr_ctrlb_n[5:0] + 102d. for 1.0?1.6 ghz operation, the half rate bit, rxcdr_ctrlb_n[6] must be set to 1. this bit causes the multiplier set by rxcdr_ctrlb_n[5:0] to be divided by two. the frequency acquisition loop is activated if the frequency difference between vco (divided down) and the external reference clock is more than a certain value called frequency window. more precisely, if lol = h this value is called narrow frequency window (nfw) and when lol = l it is called wide frequency window (wfw) (win_inlck_lol[7:0]/win_outlck_lol[7:0]) (addresses c3h/c4h). the wfw is typically larger then nfw to provide hysteresis for the locking process. with cdrx_ctrla[3] = 1 (default) a lol alarm issues the cdr inhibit which forces the cdr output to a low-logic state. when lol = l the frequency acquisition loop is turned off to reduce jitter generation and to optimize phase lock. a frequency window detector determines whether the vco frequency is inside or outside the narrow/wide frequency window. the narrow frequency window and wide frequency window are calculated as follows: the default values for the narrow and wide window are 03h and 1eh, which corresponds to 100 ppm and 1000 ppm frequency windows. the frequency acquisition time is about 1.65 ms and is limited by the 100 ppm accuracy. 4.3.14.1 settings for non-standard rates if a data rate is selected, which does not correspond to a multiplier of 104, 112, 120, 128, 136, 144, 152, or 160, then an additional write sequence is required for proper operation: 1. the vco counter needs to have a start value different from the default value (00h). to accomplish this, the appropriate value for diff_start from ta bl e 4 - 7 should be written in to rxcdr_ctrlb_n[7:0]. 2. rxcdr_ctrla_n[7:6] should be ch anged to 11b, i.e., cfh should be written to rxcdr_ctrla_n[7:0] (initial value can be 00, 01, or 10); this latches the contents of rxcdr_ctrlb_n into a dedicated register. strt ref inlk w with f nfw refclk _ _ , 1 ) 1 ( 1 = ? ? ? ? ? ? ? ? = strt ref inlk w with f wfw refclk _ _ , 1 ) 1 ( 1 = ? ? ? ? ? ? ? ? =
functional description 211x1-dsh-001-i mindspeed technologies ? 61 mindspeed proprietary and confidential 3. rxcdr_ctrlb_n can be used as defined in the register map in ta bl e 4 - 6 . 4. rxcdr_ctrla_n[7:6] should be reset back to 00, 01, or 10. an individual channel soft reset will not clear the results of the diff_start register but this write sequence must be repeated after a hardware reset or power down. for example, for a data rate of 2.605 gbps for the even prbs receive cdr, the multiplier would be 134 and the following register commands would be required: 1. write data 5fh into register address a5h 2. write data cfh into register address a4h 3. write data 20h into register address a5h 4. write data 0fh into register address a4h the diff_start values as a function of the multiplier ratio are shown in ta bl e 4 - 7 . table 4-7. diff_start values as a function of the multiplier (1 of 3) multiplier bit rate in gbps rxcdr_ctrlb[7:0] = diff_start[7:0] 102 1.983 7fh 103 2.002 7fh 104 2.022 00h (default) 105 2.041 13h 106 2.061 27h 107 2.080 3bh 108 2.099 4eh 109 2.119 62h 110 2.138 75h 111 2.158 7fh 112 2.177 00h (default) 113 2.197 12h 114 2.216 24h 115 2.236 36h 116 2.255 49h 117 2.274 5bh 118 2.294 6dh 119 2.313 7fh 120 2.333 00h (default) 121 2.352 11h 122 2.372 22h 123 2.391 33h 124 2.411 44h 125 2.430 55h
functional description 211x1-dsh-001-i mindspeed technologies ? 62 mindspeed proprietary and confidential 126 2.449 66h 127 2.469 77h 128 2.488 00h (default) 129 2.508 10h 130 2.527 20h 131 2.547 30h 132 2.566 40h 133 2.586 4fh 134 2.605 5fh 135 2.624 6fh 136 2.644 00h (default) 137 2.663 0fh 138 2.683 1eh 139 2.702 2dh 140 2.722 3ch 141 2.741 4bh 142 2.760 5ah 143 2.780 69h 144 2.799 00h (default) 145 2.819 0eh 146 2.838 1ch 147 2.858 2ah 148 2.877 38h 149 2.897 47h 150 2.916 55h 151 2.935 36h 152 2.955 00h (default) 153 2.974 0dh 154 2.994 1bh 155 3.013 28h 156 3.033 35h 157 3.052 43h 158 3.072 50h 159 3.091 5eh 160 3.110 00h (default) 161 3.130 0ch table 4-7. diff_start values as a function of the multiplier (2 of 3) multiplier bit rate in gbps rxcdr_ctrlb[7:0] = diff_start[7:0]
functional description 211x1-dsh-001-i mindspeed technologies ? 63 mindspeed proprietary and confidential because of finite resolution in the diff_start values, the value for win_outlck_lol[7:0] should be changed to at least 0ah (default is 03h). if rates are required which correspond to a non-integer multiplier (in between 2 consecutive multipliers), the cdrs can still lock to this input, as long as the closest inte ger multiplier is selected, and the narrow and wi de frequency windows are changed to wider settings. for this purpos e, each cdr has 2 individual large frequency window settings (lolwinctrl[1:0]): rxcdr_ctrla_ n[7:6] = 01 selects 22 00/2600 ppm for the narrow and wide window of cdrx; rxcdr_ctrla_n[7:6] = 10 selects 4400/5200 ppm. rxcdr_ctrla_n[7:6] = 00 (default) selects the global frequency window settings of 100 ppm/1000 ppm (default). 4.3.14.2 prbs error detection when the prbs rx detects an error, terminal perr or will go high. the first and every additional error increments an internal 8-bi t counter (prbserror[7:0]). if the number of errors exceed s 255 (counter overflow), the counter will remain at 255 until a hardware or software reset (poweri ng down and then powering up) occurs. reading the receiver error counter register requires a write of any value to copy the current contents of the error register into the prbs error register. subsequently, a read will yield the current erro r count as of the last write. while the counter value is being r ead out, no additional errors will be counted. upon prbs reset, the prbs receiver error coun ter is cleared and perror is reset. register prbserror[7:0] will always contain the current number of error counts the value divided by the time of t he test can be used to calculate a first order estimate of the bit error rate. if there have be en more than 255 errors, the prbserro r register will always read ffh until cleared. the prbs rx can also be configured to detect all patterns that the prbs tx can generate. register prbsrxctrl[7] = 1 (default 0) selects this mode. the input data has to be a 0101 or a 0011 repeating pattern. if it does not correspond to one of them, errors will be counted. 162 3.149 19h 163 3.169 26h 164 3.188 33h 165 3.208 3fh note: if these wide window settings are not selected, a cd r with a data rate in between, for instance 2.488 gbps and 2.508 gbps, will never go out of frequency acquisition, since the frequency acquisition loop pulls the vco to either 2.488 ghz or 2.508 ghz (depending on which multiplier was chosen) and the phase loop will pull the vco to the exact data rate which is seen as an lol condition (if the data rate is more than 1000 ppm away from 2.488 gbps or 2.508 gbps). note: the perror terminal is gated with the rxcd r alarms, so that if no stable data is presented to the prbs receiver (los or lol alar m is high), this terminal will go high and will stay high until all the alarms are cleared and the prbs receiver error counter is cleared. this enables the prbs receiver to detect the all zeros case as an error condition. table 4-7. diff_start values as a function of the multiplier (3 of 3) multiplier bit rate in gbps rxcdr_ctrlb[7:0] = diff_start[7:0]
functional description 211x1-dsh-001-i mindspeed technologies ? 64 mindspeed proprietary and confidential figure 4-14. prbs tx and rx functional block diagram prbs tx (1) clk_in pll ... 50 50 ... cdr prbs rx data clk cdr prbs rx data clk prbs rx cell 0 prbs rx cell 1 (8-bit counter) (8-bit counter) ... crosspoint switch core prbs rx control register (ach) 50 ... prbs tx (0) prbs_out pll clkrxp/n[0] prbs tx cell 1 prbs tx cell 0 prbs rx channel select (even/odd) register: adh (even), a1 (odd) xrsttx<0> x xentx<0> prbs txchannel select (even/odd) register: a9h (even), b5 (odd) clktxp/n<0> clktxref<0> pll_ctrl_evenb[7:0] prbstxctrl_even1[6:5] clk_in trig<0> dotxp/n<0> prbstxctrl_even[2] clkrxp/n[1] clktxp/n<1> clktxref<1> pll_ctrlb_odd[7:0] prbstxctrl1_odd[6:5] xentx<1> prbs_out xrsttx<1> trig<1> dotxp/n<1> prbstxctrl1_odd[2] outp/n<0> outp/n<70> outp/n<71>/ outp/n<143> inp/n<0> inp/n<1> inp/n<71>/ inp/n<143> dirxp/n<0> dirxp/n<1> perror<1> perror<0> xrstrx<1> xenrx<0> xrstrx<0> xenrx<1> prbsrxctrl_odd[5] rxcdr_ctrlb_odd[7:0] rxcdr_ctrlb_even[7:0] prbsrxctrl_even[5] prbserror[7:0] prbserror[7:0]
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