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document no. doc-01626-3 www.psemi.com ?2008-2015 peregrine semiconductor corp. all rights reserved. page 1 of 16 product description peregrine?s pe97632 is a high performance fractional-n pll capable of frequency synthesis up to 3.5 ghz. the device is designed for superior phase noise performance while providing an order of magnitude reduction in current consumption, when compared with the existing commercial space plls. the pe97632 features a 10/11 dual modulus prescaler, counters, a delta sigma modulator and a phase comparator as shown in figure 1. counter values are programmable through either a serial interface or directly hard-wired. the pe97632 is optimized for commercial space applications. single event latch-up (sel) is physically impossible. fabricated in peregrine?s patented ultracmos ? technology, the pe97632 offers excellent rf performance and intrinsic radiation tolerance. product specification 3.5 ghz delta-sigma modulated fractional-n frequency synthesizer for low phase noise applications figure 1. block diagram pe97632 die features ?? 3.5 ghz operation ?? 10/11 dual modulus prescaler ?? phase detector output ?? serial or direct mode access ?? frequency selectivity: comparison frequency / 2 18 ?? low power: ?35 ma @ 3.3v ?? radiation tolerant ?? ultra-low phase noise ?? pin compatible with the pe9763 (reference application note an24 at www.psemi.com)
product specification pe97632 die page 2 of 16 ?2008-2015 peregrine semiconductor corp. all rights reserved. document no. doc-01626-3 ultracmos ? rfic solutions v dd 59 gnd 60 pd_u 61 v dd 62 v dd 63 64 65 66 gnd 67 68 21 fin 57 gnd 58 20 24 25 23 22 14 13 17 19 18 16 15 12 11 69 54 55 56 52 53 32 33 31 39 40 36 34 35 37 38 42 43 41 k 2 k 3 k 4 k 5 k 6 k 7 k 8 k 9 k 10 k 11 k 12 k 13 k 14 k 15 k 16 k 17 r 5 k 1 gnd k 0 r 4 r 0 r 2 r 3 r 1 rand_en ms2_sel v dd v dd f r a 2 direct pre_en a 3 a 1 m 6 m 8 a 0 m 7 m 5 m 4 m 0 m 2 m 3 m 1 gnd gnd pd_d v dd ld d out c ext v dd fin 10 26 27 28 29 30 v dd v dd v dd 46 44 45 47 49 48 50 v dd gnd gnd 51 n/c 70 gnd n/c n/c gnd 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 gnd gnd gnd gnd enh gnd gnd figure 2. pin configurations (top view) table 1. pin descriptions pad no. pad name valid mode type description 1 r 0 direct input r counter bit0 (lsb). 2 r 1 direct input r counter bit1. 3 r 2 direct input r counter bit2. 4 r 3 direct input r counter bit3. 5 r 4 direct input r counter bit4. 6 r 5 direct input r counter bit5 (msb). 7 k 0 direct input k counter bit0 (lsb). 8 k 1 direct input k counter bit1. 9 gnd downbond ground. 10 gnd downbond ground. 13 k 2 direct input k counter bit2. 14 k 3 direct input k counter bit3. 15 k 4 direct input k counter bit4. 11 v dd note 1 digital core v dd . 12 v dd note 1 digital core v dd . 16 k 5 direct input k counter bit5. 17 k 6 direct input k counter bit6. logo device id pad 1 indicator 1
product specification pe97632 die document no. doc-01626-3 www.psemi.com ?2008-2015 peregrine semiconductor corp. all rights reserved. page 3 of 16 18 k 7 direct input k counter bit7. 19 k 8 direct input k counter bit8. 20 k 9 direct input k counter bit9. 21 k 10 direct input k counter bit10. 22 k 11 direct input k counter bit11. 23 k 12 direct input k counter bit12. 24 k 13 direct input k counter bit13. 25 k 14 direct input k counter bit14. 26 k 15 direct input k counter bit15. 27 k 16 direct input k counter bit16. 28 k 17 direct input k counter bit17 (msb). 29 v dd note 1 digital core v dd . 30 v dd note 1 digital core v dd . 31 gnd downbond ground. 32 gnd downbond ground. 33 m 0 direct input m counter bit0 (lsb). 34 m 1 direct input m counter bit1. 35 m 2 direct input m counter bit2 36 m 3 direct input m counter bit3. 37 m 4 direct input m counter bit4. s_wr serial input serial load enable input. while s_wr is ?low?, sd ata can be serially clo cked. primary register data are transferred to the secondary register on s_wr rising edge. 38 m 5 direct input m counter bit5. sdata serial input binary serial data input. input data entered msb first. 39 m 6 direct input m counter bit6. sclk serial input serial clock input. sdata is clocked serially in to the 21-bit primary register (e_wr ?low?) or the 8-bit enhancement register (e_w r ?high?) on the rising edge of sclk. 40 m 7 direct input m counter bit7. 41 m 8 direct input m counter bit8 (msb). 42 a 0 direct input a counter bit0 (lsb). 43 a 1 direct input a counter bit1. e_wr serial input enhancement register write enable. while e_wr is ?high?, sdata can be serially clocked into the enhancement register on the rising edge of sclk. 44 a 2 direct input a counter bit2. 45 a 3 direct input a counter bit3 (msb). 46 direct both input direct mode select. ?high? enables di rect mode. ?low? enables serial mode. 47 pre_en direct input prescaler enable, active ?low?. when ?high?, f in bypasses the prescaler. 48 v dd note 1 digital core v dd . 49 gnd downbond ground. 50 gnd downbond ground. pad no. pad name valid mode type description table 1. pad descriptions (cont.)
product specification pe97632 die page 4 of 16 ?2008-2015 peregrine semiconductor corp. all rights reserved. document no. doc-01626-3 ultracmos ? rfic solutions notes: 1. all v dd pads are connected by diodes and must be supp lied with the same positive voltage level. 2. all digital input pads have 70 k ? pull-down resistors to ground. 51 nc both no connect. 52 v dd note 1 prescaler v dd . 53 f in both input prescaler input from the vco. 3.5 ghz max frequency. 54 f in both input prescaler complementary input. a bypass capacit or should be placed as close as possible to this pin and be connected in series with a 50 resistor directly to the ground plane. 55 gnd downbond ground. 56 gnd downbond ground. 57 gnd downbond ground. 58 c ext both output logical ?nand? of pd_ u and pd_ d terminated through an on chip, 2 k series resistor. con- necting c ext to an external capacitor will low pass filter the input to the inverting amplifier used for driving ld. 59 ld both output lock detect and open drain logical inversion of c ext . when the loop is in lock, ld is high im- pedance, otherwise ld is a logic low (?0?). 60 d out both output data out function, enabled in enhancement mode. 61 v dd note 1 output driver/v dd . 62 gnd downbond ground. 63 pd_d both output pd_d pulses down when f p leads f c . 64 nc both no connect. 65 pd_u both output pd_u pulses down when f c leads f p . 66 gnd downbond ground. 67 v dd note 1 output driver/v dd . 68 gnd downbond ground. 69 v dd note 1 phase detector v dd . 70 nc both no connect. 71 gnd downbond ground. 72 gnd downbond ground. 73 f r both input reference frequency input. 74 v dd note 1 reference v dd . 75 v dd note 1 digital core v dd . 76 gnd downbond ground. 77 enh both input enhancement mode. when asserted low (?0?), enh ancement register bits are functional. 78 gnd downbond ground. 79 ms2_sel both input mash 1-1 select. ?high? selects mash 1- 1 mode. ?low? selects the mash 1-1-1 mode. 80 rnd_sel both input k register lsb toggle enable. ?1? enables the toggl ing of lsb. this is equivalent to having an additional bit for the lsb of k register. the frequen cy offset as a result of enabling this bit is the phase detector comparison frequency / 2 19 . pad no. pad name valid mode type description table 1. pad descriptions (cont.)
product specification pe97632 die document no. doc-01626-3 www.psemi.com ?2008-2015 peregrine semiconductor corp. all rights reserved. page 5 of 16 table 2. absolute maximum ratings electrostatic discharge (esd) precautions when handling this ultracmos device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified in table 4 . latch-up immunity unlike conventional cmos devices, ultracmos devices are immune to latch-up. table 3. operating ratings symbol parameter/condition min max unit v dd supply voltage ?0.3 4.0 v v i voltage on any input ?0.3 v dd + 0.3 v i i dc into any input ?10 +10 ma i o dc into any output ?10 +10 ma t stg storage temperature range ?65 +150 c symbol parameter/condition min max unit v dd supply voltage 2.85 3.45 v t a operating ambient temperature range ?40 +85 c table 4. esd ratings symbol parameter/condition level unit v esd esd voltage human body model on all pins except pin 52 (note 1) 1000 v esd voltage human body model on pin 60 (notes 1 and 2) 300 v notes: 1. periodically sampled, not 100% tested. tested per mil-std-883, m3015 c2. 2. pin 60 is a test pin only. it is not used in normal operation. eldrs ultracmos devices do not include bipolar minority carrier elements and; therefore, do not exhibit en- hanced low-dose-rate sensitivity.
product specification pe97632 die page 6 of 16 ?2008-2015 peregrine semiconductor corp. all rights reserved. document no. doc-01626-3 ultracmos ? rfic solutions table 5. dc characteristics @ v dd = 3.30v, ?40 c < ta < +85 c, unless otherwise specified symbol parameter condition min typ max unit i dd prescaler enabled, v dd = 2.85?3.45v 20 35 45 ma prescaler disabled, v dd = 2.85?3.45v 8 15 23 ma all digital inputs: k[17:0], r[5:0], m[8:0], a[3:0], direct, pre_en , rand_en, m2_sel, enh (contains a 70 k ? pull-down resistor) v ih high level input voltage v dd = 2.85?3.45v 0.7 v dd v v il low level input voltage v dd = 2.85?3.45v 0.3 v dd v i ih high level input current v ih = v dd = 3.45v 100 a i il low level input current v il = 0, v dd = 3.45v ?1 a reference divider input: f r i ihr high level input current v ih = v dd = 3.45v 100 a i ilr low level input current v il = 0, v dd = 3.45v ?100 a counter and phase detector outputs: pd_ d , pd_u v old output voltage low i out = 6 ma 0.4 v v ohd output voltage high i out = ?3 ma v dd ?0.4 v digital test outputs: d out v old output voltage low i out = 200 ? a 0.4 v v ohd output voltage high i out = ?200 ? a v dd ?0.4 v lock detect outputs: (c ext , ld) v olc output voltage low, c ext i out = 0.1 ma 0.4 v v ohc output voltage high, c ext i out = ?0.1 ma v dd ?0.4 v v olld output voltage low, ld i out = 1 ma 0.4 v operational supply current
product specification pe97632 die document no. doc-01626-3 www.psemi.com ?2008-2015 peregrine semiconductor corp. all rights reserved. page 7 of 16 table 6. ac characteristics @ v dd = 3.30v, ?40 c < ta < +85 c, unless otherwise specified 5 ? notes: 1. f clk is verified during the functional pattern test. serial programmi ng sections of the functional pa ttern are clocked at 10 mhz to verify f clk specification. 2. cmos logic levels can be used to drive reference input if dc coupled. voltage input needs to be a minimum of 0.5 v pp . for optimum phase noise performance, the reference input falling edge rate should be faster than 80 mv/ns. 3. parameter is guaranteed through characterization only and is not tested. 4. parameter is verified during the element evaluation and are not tested for die sales. 5. all information in table 6 is not tested at wafer sort. symbol parameter condition min typ max unit control interface and latches (see figures 3 and 4) f clk serial data clock frequency 1 10 mhz t clkh serial clock high time 30 ns t clkl serial clock low time 30 ns t dsu sdata set-up time to sclk rising edge 10 ns t dhld sdata hold time after sclk rising edge 10 ns t pw s_wr pulse width 30 ns t cwr sclk rising edge to s_wr rising edge 30 ns t ce sclk falling edge to e_wr transition 30 ns t wrc s_wr falling edge to sclk rising edge 30 ns t ec e_wr transition to sclk rising edge 30 ns main divider (including prescaler) 4 p fin input level range external ac coupling 275 mhz freq 3200 mhz ?5 5 dbm external ac coupling 3.2 ghz < freq 3.5 ghz 3.15v vdd 3.45v 0 5 dbm main divider (prescaler bypassed) 4 f in operating frequency 50 300 mhz p f_in input level range external ac coupling ?5 5 dbm reference divider f r operating frequency 3 100 mhz p fr reference input power 2 single ended input ?2 10 dbm phase detector f c comparison frequency 3 50 mhz ssb phase noise (f in = 1.9 ghz, f r = 20 mhz, f c = 20 mhz, lbw = 50 khz, v dd = 3.3v, temp = +25 q c ) 4 ) n phase noise 100 hz offset ?89 ?83 dbc/hz ) n phase noise 1 khz offset ?96 ?91 dbc/hz ) n phase noise 10 khz offset ?101 ?96 dbc/hz ssb phase noise (f in = 1.9 ghz, f r = 20 mhz, f c = 20 mhz, lbw = 50 khz, v dd = 3.0v, temp = +25 q c ) 4 ) n phase noise 100 hz offset ?84 ?70 dbc/hz ) n phase noise 1 khz offset ?92 ?81 dbc/hz ) n phase noise 10 khz offset ?100 ?89 dbc/hz
product specification pe97632 die page 8 of 16 ?2008-2015 peregrine semiconductor corp. all rights reserved. document no. doc-01626-3 ultracmos ? rfic solutions functional description the pe97632 consists of a prescaler, counters, an 18-bit delta-sigma modulator (dsm) and a phase detector. the dual modulus prescaler divides the vco frequency by either 10/11, depending on the value of the modulus select. counters ?r? and ?m? divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. an additional counter (?a?) is used in the modulus select logic. the dsm modulates the ?a? counter outputs in order to achieve the desired fractional step. the phase-frequency detector generates up and down frequency control signals. data is written into the internal registers via the three wire serial bus. there are also various operational and test modes and a lock detect output. figure 3. functional block diagram control logic modulus select 10/11 prescaler m counter (9-bit) r counter (6-bit) phase detector r(5:0) m(8:0) a(3:0) sdata control pins f r f in 2 k ? ld c ext f in f c f p dsm + logic pd_u pd_d k(17:0)
product specification pe97632 die document no. doc-01626-3 www.psemi.com ?2008-2015 peregrine semiconductor corp. all rights reserved. page 9 of 16 main counter chain normal operating mode setting the pre_en control bit ?low? enables the 10/11 prescaler. the main counter chain then divides the rf input frequency (f in ) by an integer or fractional number derived from the values in the ?m? and ?a? counters and the dsm input word k. the accumulator size is 18 bit, so the fractional value is fixed from the ratio k/2 18 . there is an additional bit in the dsm that acts like an extra bit (19 th bit). this bit is enabled by asserting the pin rand_sel to ?high?. enabling this bit has the benefit of reducing the spurious levels. however, a small frequency offset will occur. this positive frequency offset is calculated with the following equation. f offset = [f r / (r+1)] / 2 19 (1) all of the following equations do not take into account this frequency offset. if this offset is important to a specific frequency plan, appropriate account needs to be taken. in the normal mode, the output from the main counter chain (f p ) is related to the vco frequency (f in ) by the following equation: f p = f in / [10 (m+1) + a + k/ 2 18 ] (2) where a m + 1, 1 m 511 when the loop is locked, f in is related to the reference frequency (f r ) by the following equation: f in = [10 (m+1) + a + k/ 2 18 ] [f r / (r+1)] (3) where a m + 1, 1 m 511 a consequence of the upper limit on a is that f in must be greater than or equal to 90 [f r / (r+1)] to obtain contiguous channels. the a counter can accept values as high as 15, but in typical operation it will cycle from 0 to 9 between increments in m. programming the m counter with the minimum allowed value of ?1? will result in a minimum m counter divide ratio of ?2?. prescaler bypass mode (*) setting the frequency control register bit pre_en ?high? allows f in to bypass the 10/11 prescaler. in this mode, the prescaler and a counter are powered down, and the input vco frequency is divided by the m counter directly. the following equation relates f in to the reference frequency f r : f in = (m+1) [f r / (r+1)] (4) where 1 m 511 (*) only integer mode in frequency bypass mode, neither a counter or k counter is used. therefore, only integer-n operation is possible. reference counter the reference counter chain divides the reference frequency, f r , down to the phase detector comparison frequency, f c . the output frequency of the 6-bit r counter is related to the reference frequency by the following equation: f c = f r / (r+1) (5) where 0 r 63 note that programming r with ?0? will pass the reference frequency, f r , directly to the phase detector. register programming serial interface mode while the e_wr input is ?low? and the s_wr input is ?low?, serial input data (sdata input), b 0 to b 20 , are clocked serially into the primary register on the rising edge of sclk, msb (b 0 ) first. the lsb is used as address bit. when ?0?, the contents from the primary register are transferred into the secondary register on the rising edge of either s_wr according to the timing diagrams shown in figure 4 . when ?1?, data is transferred to the auxiliary register according to the same timing diagram. the secondary register is used to program the various counters, while the auxiliary register is used to program the dsm. data are transferred to the counters as shown in table 8 .
product specification pe97632 die page 10 of 16 ?2008-2015 peregrine semiconductor corp. all rights reserved. document no. doc-01626-3 ultracmos ? rfic solutions while the e_wr input is ?high? and the s_wr in- put is ?low?, serial input data (sdata input), b 0 to b 7 , are clocked serially into the enhancement reg- ister on the rising edge of sclk, msb (b 0 ) first. the enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of e_wr ac- cording to the timing diagram shown in figure 4. after the falling edge of e_wr, the data provide control bits as shown in table 9 will have their bit functionality enabled by asserting the enh input ?low?. direct interface mode direct interface mode is selected by setting the ?direct? input ?high?. counter control bits are set directly at the pins as shown in table 7 and table 8 . table 7. secondary register programming table 8. auxiliary register programming table 9. enhancement register programming interface mode enh r 5 r 4 m 8 m 7 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 addr direct 1 r 5 r 4 m 8 m 7 pre_en m 6 m 5 m 4 m 3 m 2 m 1 m 0 r 3 r 2 r 1 r 0 a 3 a 2 a 1 a 0 x serial* 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 19 0 note: * serial data clocked serially on sclk rising edge while e_ wr ?low? and captured in secondary register on s_wr rising edg e. interface mode enh k 17 k 16 k 15 k 14 k 13 k 12 k 11 k 10 k 9 k 8 k 7 k 6 k 5 k 4 k 3 k 2 k 1 k 0 rsrv rsrv addr direct 1 k 17 k 16 k 15 k 14 k 13 k 12 k 11 k 10 k 9 k 8 k 7 k 6 k 5 k 4 k 3 k 2 k 1 k 0 x x x serial* 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 9 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 18 b 19 1 note: * serial data clocked serially on sclk rising edge while e_ wr ?low? and captured in secondary register on s_wr rising edg e. interface mode enh reserved reserved f p output power down counter load msel output f c output ld disable serial* 0 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 note: * serial data clocked serially on sclk rising edge while e_wr ?high? and captured in the double buffer on e_wr falling ed ge. msb (first in) msb (first in) (last in) lsb (last in) lsb (last in) lsb msb (first in)
product specification pe97632 die document no. doc-01626-3 www.psemi.com ?2008-2015 peregrine semiconductor corp. all rights reserved. page 11 of 16 enhancement register figure 4. serial interface mode timing diagram the functions of the enhancement register bits ar e shown below with all bits active ?high?. table 10. enhancement register bit functionality bit function description bit 0 reserve* reserved. bit 1 reserve* reserved. bit 2 f p output drives the m counter output onto the d out output. bit 3 power down power down of all functions except programming interface. bit 4 counter load immediate and cont inuous load of counter programming. bit 5 msel output drives the internal dual modul us prescaler modulus select (msel) onto the d out output. bit 6 f c output drives the reference counter output onto the d out output. bit 7 ld disable disables the ld pin for quieter operation. note: * program to 0. t dhld t dsu t clkh t clkl t cwr t pw t wrc t ec t ce e_wr sdata sclk s_wr
product specification pe97632 die page 12 of 16 ?2008-2015 peregrine semiconductor corp. all rights reserved. document no. doc-01626-3 ultracmos ? rfic solutions figure 5. typical phase noise phase detector the phase detector is triggered by rising edges from the main counter (f p ) and the reference coun- ter (f c ). it has two outputs, namely pd_ u , and pd_ d . if the divided vco leads the divided refer- ence in phase or frequency (f p leads f c ), pd_d pulses ?low?. if the divided reference leads the di- vided vco in phase or frequency (f c leads f p ), pd_ u pulses ?low?. the width of either pulse is directly proportional to phase offset between the two input signals, f p and f c . for the up and down mode, pd_ u and pd_ d drive an active loop filter which controls the vco tune voltage. the phase detector gain is equal to v dd / 2. pd_ u pulses cause an increase in vco frequency and pd_d pulses cause a decrease in vco fre- quency, for a positive kv vco. a lock detect output, ld is also provided, via the pin c ext . c ext is the logical ?nand? of pd_ u and pd_ d waveforms, which is driven through a series 2 k ? resistor. connecting c ext to an external shunt capacitor provides low pass filtering of this signal. c ext also drives the input of an internal in- verting comparator with an open drain output. thus ld is an ?and? function of pd_ u and pd_ d . a typical phase noise plot is shown below. ?trace 1? is the smoothed average and ?trace 2? is the raw data . test conditions: mash 1-1 mode, f out = 1.9204 ghz, f comparison = 20 mhz, v dd = 3.3v, temp = +25 c, loop bandwidth = 50 khz.
product specification pe97632 die document no. doc-01626-3 www.psemi.com ?2008-2015 peregrine semiconductor corp. all rights reserved. page 13 of 16 figure 6. typical spurious plot test conditions: frequency step = 400 kh z, loop bandwidth = 50 khz, f out = 1.9204 ghz, f comparison = 20 mhz, mash 1?1, v dd = 3.3v, temp = +25 c.
product specification pe97632 die page 14 of 16 ?2008-2015 peregrine semiconductor corp. all rights reserved. document no. doc-01626-3 ultracmos ? rfic solutions notes: 1. all pad locations originate from the die center and refer to the center of the pad. 2. minimum pad pitch is 150 m. pad openings are 90 m. figure 7. pad numbering 1,2 200 m v dd 59 gnd 60 pd_ u 61 v dd 62 v dd 63 64 65 66 gnd 67 68 21 f in 57 gnd 58 20 24 25 23 22 14 13 17 19 18 16 15 12 11 69 54 55 56 52 53 k 2 k 3 k 4 k 5 k 6 k 7 k 8 k 9 k 10 k 11 k 12 k 13 k 14 k 15 k 16 k 17 gnd pd_ d v dd ld d out c ext v dd f in 10 26 27 28 29 30 v dd v dd v dd 51 n/c 70 gnd n/c n/c gnd 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 table 11. mechanical specifications parameter min typ max unit test condition die size, drawn (x,y) 3306 3306 m as drawn die size, singulated (x,y)* 3522 3470 3652 3470 3622 3570 3752 3570 3722 3670 3852 3670 m including excess sapphire, max. tolerance = 100 m wafer thickness 180 200 220 m wafer size 150 mm pad 1 indicator 1 logo device id note: * there are two different singulated die sizes per reticle.
product specification pe97632 die document no. doc-01626-3 www.psemi.com ?2008-2015 peregrine semiconductor corp. all rights reserved. page 15 of 16 table 12. pin coordinates pin # pin name pin center (m) x y 1 r0 ?75.0 1578.8 2 r1 ?225.0 1578.8 3 r2 ?375.0 1578.8 4 r3 ?525.0 1578.8 5 r4 ?675.0 1578.8 6 r5 ?825.0 1578.8 7 k0 ?975.0 1578.8 8 k1 ?1125.0 1578.8 9 gnd ?1275.0 1578.8 10 gnd ?1425.0 1578.8 11 v dd ?1578.8 1425.0 12 v dd ?1578.8 1275.0 13 k2 ?1578.8 1125.0 14 k3 ?1578.8 975.0 15 k4 ?1578.8 825.0 16 k5 ?1578.8 675.0 17 k6 ?1578.8 525.0 18 k7 ?1578.8 375.0 19 k8 ?1578.8 225.0 20 k9 ?1578.8 75.0 21 k10 ?1578.8 ?75.0 22 k11 ?1578.8 ?225.0 23 k12 ?1578.8 ?375.0 24 k13 ?1578.8 ?525.0 25 k14 ?1578.8 ?675.0 26 k15 ?1578.8 ?825.0 27 k16 ?1578.8 ?975.0 28 k17 ?1578.8 ?1125.0 29 v dd ?1578.8 ?1275.0 30 v dd ?1578.8 ?1425.0 31 gnd ?1425.0 ?1578.8 32 gnd ?1275.0 ?1578.8 33 m0 ?1125.0 ?1578.8 34 m1 ?975.0 ?1578.8 35 m2 ?825.0 ?1578.8 36 m3 ?675.0 ?1578.8 37 m4 ?525.0 ?1578.8 38 m5 ?375.0 ?1578.8 39 m6 ?225.0 ?1578.8 40 m7 ?75.0 ?1578.8 pin name pin center (m) x y 41 m8 75.0 ?1578.8 42 a0 225.0 ?1578.8 43 a1 375.0 ?1578.8 44 a2 525.0 ?1578.8 45 a3 675.0 ?1578.8 46 direct 825.0 ?1578.8 47 pre_en 975.0 ?1578.8 48 v dd 1125.0 ?1578.8 49 gnd 1275.0 ?1578.8 50 gnd 1425.0 ?1578.8 51 v dd 1578.8 ?1425.0 52 v dd 1578.8 ?1275.0 53 f in 1578.8 ?1125.0 54 f in 1578.8 ?975.0 55 gnd 1578.8 ?825.0 56 gnd 1578.8 ?675.0 57 gnd 1578.8 ?525.0 58 c ext 1578.8 ?375.0 59 ld 1578.8 ?225.0 60 do 1578.8 ?75.0 61 v dd 1578.8 75.0 62 gnd 1578.8 225.0 63 pd_d 1578.8 375.0 64 nc 1578.8 525.0 65 pd_u 1578.8 675.0 66 gnd 1578.8 825.0 67 v dd 1578.8 975.0 68 gnd 1578.8 1125.0 69 v dd 1578.8 1275.0 70 v dd 1578.8 1425.0 71 gnd 1425.0 1578.8 72 gnd 1275.0 1578.8 73 f r 1125.0 1578.8 74 v dd 975.0 1578.8 75 v dd 825.0 1578.8 76 gnd 675.0 1578.8 77 enh 525.0 1578.8 78 gnd 375.0 1578.8 79 mash2sel 225.0 1578.8 80 rand_en 75.0 1578.8 pin #
product specification pe97632 die page 16 of 16 ?2008-2015 peregrine semiconductor corp. all rights reserved. document no. doc-01626-3 ultracmos ? rfic solutions advance information: the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, ultracmos and utsi are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregrine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales contact and information for sales and contact information please visit www.psemi.com . table 13. ordering information order code part marking description specification package shipping method 97632?98* fa97632 engineering die waffle pack waffle pack (5 units max) 97632?99 fa97632 flight die 81-0015 waffle pack 100 units / waffle pack 97632?00 pe97632 ek evaluation kit 1 / box note: * the 97632-98 die are es (engineering sample) units intended as initial evaluation devices for customers of the 97632-99 flight die. the 97632-98 es die provide the same electrical functionality and performance as the 97632-99 flight die, but is processed to a non-compliant flow (e.g. no qci coverage or element evaluation data). these die are obtained from non-qualified wafers so are not suitable fo r qualification, production, radiation testing or flight use.

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