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HFC0300 variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 1 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. the future of analog ic technology description HFC0300 is a variable off-time controller that uses a fixed-peak?current technique to decrease its frequency as the load lightens. as a result, it offers excellent efficiency at light-load while optimizing the efficiency under other load conditions. when the frequency decreases to threshold, the peak current decreases with the decreasing load to prevent mechanical resonance in the transformer. the controller enters burst mode when the output power falls below a given level. the HFC0300 features various protections such as thermal shutdown, v cc under-voltage lockout, overload protection, short-circuit protection, and over-voltage protection. the HFC0300 is available in soic-7 package. features ? variable off-time, current mode control ? universal main supply operation (85vac to 265vac) ? frequency foldback as load lightens ? peak-current compression to reduce transformer noise ? active-burst mode for low standby power consumption ? internal high-voltage current source ? internal 200ns leading edge blanking ? thermal shutdown (auto restart with hysteresis) ? vcc under-voltage lockout with hysteresis ? over-voltage protection on vcc pin ? timer-based overload protection ? short-circuit protection ? natural spectrum shaping for improved emi performance applications ? battery charger for portable electronics ? standby power supply ? switched-mode power supplies for mps green status, please visit mps website under quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks o f monolithic power systems, inc.
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 2 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. typical applicaion input 85vac - 265vac * * * t1 output HFC0300 1 2 3 4 5 6 8 fset hv gnd comp cs vcc drv
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 3 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. ordering information part number* package top marking free air temperature (t a ) HFC0300hs soic-7 HFC0300 -40c to +125c for tape & reel, add suffix ?z (e.g. HFC0300hs?z); for rohs compliant packaging, add suffix ?lf (e.g. HFC0300hs?lf?z) package reference absolute maxi mum ratings (1) hv breakdown voltage .............. -0.7v to +700v vcc, drv to gnd ........................ -0.3v to +30v drv to gnd ................................. -0.3v to +18v fset, comp, cs to gnd .............. -0.3v to +7v continuous power dissipation (t a = +25c) (2) soic-7??????????????....1.3w junction temperature ............................... 150c thermal shut down .................................. 150c thermal shut down hysteresis .................. 25c lead temperature .................................... 260c storage temperature .............. -60c to +150c esd capability human body model (all pins except drain) ........................................... 2.0kv esd capability machine model ................. 200v recommended operation conditions (3) maximum junction temp. (t j ) ............... +125c operating vcc range ........................ 8.2v to 20v thermal resistance (4) ja jc soic-7 .................................... 96 ...... 45 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on jesd51-7, 4-layer pcb. drv cs gnd copm hv vcc fset 1 2 3 4 8 6 5 top view soic-7
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 4 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved electrical characteristics v cc =12v, t a =25c, unless otherwise noted. parameter symbol conditions min typ max unit start-up current source (pin hv) supply current from pin hv i hv v hv =400v, vcc=6v 2 ma break-down voltage v br 700 v off-state hv leakage current i leak v hv =400v, vcc=10v 10 17 a supply voltage management (pin vcc) vcc increasing level where the current source turns off vcc off 10.7 11.7 12.7 v vcc decreasing level where the current source turns on vcc on 7.6 8.2 8.8 v vcc re-charge level where protections occurs v ccr 5.0 5.5 6.0 v vcc decreasing level where latch-off phase ends vcc latch 3.0 v internal ic consumption ,1nf load on drv pin icc fs=65khz, vcc=12v 1.3 ma internal ic consumption, latch off phase icc latch vcc=6v 500 a rising voltage threshold on vcc where controller latches off (ovp) v ovp 22.5 24 25.5 v integration time constraint on the ovp comparator t int 20 s timing capacitor(pin fset) minimum voltage on fset capacitor v fsetmin 0.82 0.88 0.94 v maximum voltage on fset capacitor v fsetmax 3.2 v source current i fset 23 28 33 a fset capacitor discharge time (active at drive turn-on) t disch 0.6 s feedback management (pin comp) over load protection set point v olp 0.80 0.85 0.90 v over load protection delay time t olp c fset =330pf 74 ms comp decreasing level where the controller enters the burst mode v burh 3.0 3.2 3.4 v comp increasing level where the controller leaves the burst mode v burl 2.9 3.1 3.3 v current sampling management (pin cs) short-circuit comparator leading-edge blanking t leb1 150 ns current-sense comparator leading-edge blanking t leb2 200 ns maximum current-sense comparator limit v limit v comp =1v 0.45 0.5 -0.55 v short-circuit protection point v scp v scp 1.0 v
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 5 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved electrical characteristics (continued) v cc =12v, t a =25c, unless otherwise noted. parameter symbol conditions min typ max unit driving signal (pin drv) sourcing resistor r h 10 ? sinking resistor r l 3 ? v drive clamp v drive vcc=18v 13.7 v pin functions soic-7 pin # name description 1 drv drive. output of the drive signal. 2 cs current sense input. 3 gnd ground. 4 comp switching frequency set. a feedback volt age of 0.85v will trigger overload protection, and a feedback voltage of 3. 1v will trigger a burst mode operation. 5 fset frequency set. maximum switching frequency set by a capacitor. 6 vcc ic supply. connected to an external bulk capacitor. if an auxiliary winding brings this pin above 24v, the controller latches off. 8 hv high-voltage source. input for t he start-up high voltage current source.
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 6 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved typical performanc e characteristics 1.5 1.7 1.9 2.1 2.3 2.5 2.7 -40 -20 0 20 40 60 80 100 120 11 11.25 11.5 11.75 12 -40 -20 0 20 40 60 80 100 120 v cch (v) v ccl (v) 7.5 7.75 8 8.25 8.5 -40 -20 0 20 40 60 80 100120 0.78 0.8 0.82 0.84 0.86 0.88 -40 -20 0 20 40 60 80 100 120 v olp (v) 68 70 72 74 76 78 -40 -20 0 20 40 60 80 100 120 t ocp (ms) 23.5 23.7 23.9 24.1 24.3 24.5 -40 -20 0 20 40 60 80 100 120 v ovp (v) 0.86 0.865 0.87 0.875 0.88 -40 -20 0 20 40 60 80 100 120 fset min (v) 26 27 28 29 30 -40 -20 0 20 40 60 80 100 120 0.48 0.485 0.49 0.495 0.5 0.505 0.51 -40 -20 0 20 40 60 80 100 120 i peak (v)
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 7 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved typical performanc e characteristics (continued) comp increasing level at which the controller enters the burst mode vs. temperature comp decreasing level at which the controller leaves the burst mode vs. temperature scp point vs. temperature 0.85 0.87 0.89 0.91 0.93 0.95 -40 -20 0 20 40 60 80 100 120 i peak (v) 3.17 3.19 3.21 3.23 3.25 -40 -20 0 20 40 60 80 100 120 v burh (v) 3.08 3.1 3.12 3.14 3.16 -40 -20 0 20 40 60 80 100 120 v burl (v)
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 8 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved block diagram c s ( 2 ) c o m p ( 4 ) v c c ( 6 ) d r v ( 1 ) h v ( 8 ) f s e t ( 5 ) power management start up unit internal power supply driving signal management fault management ovp peak current compression burst mode control frequency control olp current comparator g n d ( 3 ) otp figure 1: functional block diagram
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 9 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. operation the HFC0300 incorporates all the necessary features to build a reliable switched-mode power supply (smps). its high level of integration requires few external components. based on a fixed peak current technique, the controller decreases its frequency with the decreasing load to minimize switching loss. when the output power falls below a given level, the controller enters burst mode. it also has better emi performance because the switching frequency varies with the natural bulk ripple voltage. frequency foldback a capacitor connected to the fset pin sets the frequency at the end of charging. this capacitor charges from a constant current source and its voltage is compared with an internal threshold fixed by comp voltage (see figure 2). when this capacitor voltage reaches threshold, the capacitor discharges rapidly down to 0v, and a new period starts after a 0.6 s delay (see figure 3). s r _ q q 28a 3.3v v offset 0.88v 0.6s pulse drive fset comp vcc figure 2: voltage-controlled oscillation maximum frequency minimum frequency i fset =28a vfset controlled by the comp voltage pout decrease pout increase figure 3: comp-voltage?adjusted switching frequency start-up and under voltage lock-out initially, the internal high voltage current source drawn from the high-voltage (hv) pin powers the ic. the ic starts switching and the internal high- voltage current source turns off as soon as the voltage on vcc reaches 11.7v. then the auxiliary winding of the transformer supplies the ic before the vcc voltage falls back below 8.2v. otherwise, the switching pulse stops and the high-voltage current source turns on again. figure 4 shows the typical waveform with vcc under-voltage lockout (uvlo). v cch =11.7v v ccl =8.2v v cc internal current source driving signal on off the auxiliary winding takes over figure 4: vcc under-voltage lockout the lower threshold of vcc uvlo goes from 8.2v to 5.5v when fault conditions happen, such as over-load protection (olp), over-voltage protection (ovp), and over-temperature protection (otp). over-voltage protection by monitoring the vcc pin with a 20s time- constant filter, the HFC0300 goes into latched fault condition whenever an over-voltage condition occurs?if vcc goes above 24v, typically. the controller stays fully latched in this position until the vcc is cycled down to 3.0v, e.g. when the user unplugs the power supply from the main input and re-plugs it. over-load protection in a flyback converter, the maximum output power is limited by the maximum switching frequency and primary peak current. as the primary peak current is constant, the maximum power is limited by maximum frequency. when the switching frequency reaches the maximum,
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 10 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. the output voltage decreases if the load continues to increase. comp then drops below the over-load protection (olp) point because feedback is equivalent to an open circuit. by continuously monitoring the comp, when the comp voltage drops below 0.85v?which is considered an error?the timer starts counting. if the error flag is removed, the timer resets. if the timer reaches completion at the delay time determined by the fset capacitor (for example, 74ms at c fset =330pf) , olp takes place. this timer avoids triggering olp when the power supply is at start-up or load transition phase. therefore the power supply should start-up in less than over load protection delay time, as determined by the following equation: fset delay c t74ms 330pf ?? short circuit protection the HFC0300 shuts down when the cs voltage rises higher than 1v using short-circuit protection (scp). as soon as the fault disappears, the power supply resumes operation. during scp, the vcc uvlo lower threshold goes from 8.2v to 5.5v. thermal shutdown the HFC0300 shuts down switching when the inner temperature exceeds 150 c to prevent damaging high temperatures . as soon as the inner temperature drops below 125 c , the power supply resumes operation. during the thermal shutdown (tsd), the vcc uvlo lower threshold goes from 8.2v to 5.5v. peak current compression as the load becomes lighter, the frequency decreases and may enter the audible range. to avoid exciting mechanical resonances in the transformer and generating acoustic noise, the HFC0300 reduces the peak current as power goes down and thus reduces noise issues. figure 5 shows the curve of peak current versus comp. comp(v) peak current(v) 0.5 0.167 2.1 3.1 0.9 3.2 constant peak current peak current compression burst mode figure 5: peak current vs. comp burst operation the HFC0300 enters burst-mode operation to minimize power dissipation in no load or light load conditions. as the load decreases, the comp voltage increases; the ic stops switching when the comp voltage increases over the threshold, v bruh = 3.2v. the output voltage then drops, which causes the comp voltage to decrease further. once the comp voltage falls below the threshold v brul = 3.1v, switching resumes and the comp voltage then oscilates. the burst mode operation alternately enables and disables switching cycle of the mosfet. leading-edge blanking in order to avoid the premature termination of the switching pulse due to the parasitic capacitance, an internal leading-edge blanking (leb) unit is employed between the cs pin and the current comparator input. during the blanking time, the current comparator is disabled and can not turn off the external mosfet. figure 6 shows the leading-edge blanking. t leb =200ns v limit t figure 6: leading-edge blanking
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 11 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. start vcc>11.7v t>t olp and olp=logic high internal high voltage current source on y n soft start monitor v comp monitor vcc v comp <0.85v 0.85v3.2v switch off off time operation v comp < 3.1v n y olp=logic high y otp or scp monitor y vcc decrease to 5.5v shut down internal high voltage current source latch off the switching pulse n continuous fault monitor vcc<8.2v y n v cc >24v n y otp or scp logic high? y n uvlo, otp, scp & olp is auto restart, ovp is latch release from the latch condition, need to unplug from the main input. vcc<3v? y n shut off the switching pulse y figure 7: control flow chart
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 12 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. 11.7v 8.2v 5.5v vcc driver fault flag ovp fault occurs here driver pluses regulation occurs here high voltage current source start up normal operation normal operation normal operation olp fault occurs here on off over voltage occurs here normal operation otp fault occurs here normal operation unplug from main input normal operation normal operation olp delay figure 8: signal changes in the presence of different faults
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 13 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. application information design keys of HFC0300 current sense resistor section the peak current level is internally set to 0.5v, so the current-sense resistor sets the primary-side peak current, which determines the operation mode of the converter?such as ccm, bcm or dcm. if power supply is designed to operate at bcm at low-line input, it will operate at dcm at the high line and the same load condition. the magnetizing inductor current (reflected on the primary side) and the drain-source voltage (v ds ) of the primary mosfet is shown in figure 9. inductor current (a) v ds high line low line inductor current (a) tsecond t tsecond i primary i secondary / n 0.5v/r sense v ds i primary i secondary / n 0.5v/r sense figure 9: inductor current and voltage of primary mosfet the time duration of the secondary current can be determined by equation (1): m peak sec o li t nv ? ? ? (1) where l m is the primary magnetizing inductance, i peak is the primary peak current, and n is the turn ratio of the transformer. i peak remains the same at under different inputs and with the same output, so the time duration of secondary current is the same. the switching period can be calculated by: peak sec o ni t t 2i ? ? ? ? (2) from equation (2), the switching period remains the same at different inputs with the same output condition. since the primary-side switch on time decreases with the increasing input voltage, then the higher the input line voltage, the deeper discontinuous current mode (dcm) it will enter. usually, the parameters are designed for the minimum input condition to guarantee that the converter can deliver the required maximum output power. since n is pre-determined, if the power supply is designed to operate at boundary current mode (bcm) at the low line, the peak current can be calculated as: o peak _ bcm 2i i n(1d) ? ? ?? (3) where d is the duty ratio of the switching. then: of in o f (v v ) n d v(vv)n ?? ? ? ?? (4) if the peak current set by the current-sense resistor is larger than i peak_bcm , the power supply will enter dcm. on the other hand, if the peak current set by current sense resistor is less than i peak_bcm , the power supply will enter ccm, as shown as figure 10. here, we define k depth as the depth of ccm. valley depth peak i k i ? (5)
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 14 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. i mosfet i peak i valley figure 10: primary current at ccm so the peak current can be determined as: o peak _ ccm depth 2i i (1 d) (1 k ) n ? ? ??? ? (6) usually, bcm is preferable at power levels below 40w, and ccm is preferable at power levels higher than 40w: the higher the power delivered, the deeper the ccm adopted for higher efficiency and better thermal performance at full load. for example, for a 90w power supply, k depth should be around 0.5. the converter operation mode must be determined with each power supply specification given; i.e. determine the k depth . i peak and i valley as calculated by equations (3) through (6). select the current sense resistor using equation (7). peak sense peak v r i ? (7) where v peak is the peak voltage threshold of the current resistor; a constant 0.5v for HFC0300. chose the current resistor with the proper power rating based on the power loss given in equation (8) peak valley 22 sense peak valley sense ii 1 p[( ) (ii)]dr 212 ? ?????? (8) design of c fset and olp function the capacitor c fset sets the maximum frequency as shown in equation (9). this capacitor is charged by a constant-current source shortly after the primary side switch turns on (about 0.6s delay), and its voltage is compared with the comp voltage from feedback loop (see figure 11). when the capacitor voltage reaches threshold, the capacitor rapidly discharges down to 0v, and a new period starts. an internal delay of about 0.6s delay before c fset charges again fully discharges the voltage at the fset pin, (see figure 12). thus the switching frequency is regulated by the feedback loop like a voltage- controlled oscillation (vco). max fset 1 28ua ( 0.6us) f c 0.88v ?? ? (9) where f max is the maximum frequency set by the capacitor connected to fset pin. s r _ q q 28a 3.3v v offset 0.88v 0.6s pulse drive fset comp vcc figure 11: schematic for voltage-controlled oscillation maximum frequency minimum frequency i fset =28a vfset controlled by the comp voltage pout decrease pout increase figure 12: switching frequency as adjusted by comp voltage as described in the section above, the switching frequency reaches its maximum at low line and full load. this frequency, defined as f s (65khz in this case). set the maximum frequency (f max ) at 110% f s . the frequency increases with the increasing output power. when the frequency reaches its maximum?set by c fset ?the over- power limit drops the output voltage, saturating comp, and drops the olp threshold (0.85v). the olp uses a unique digital timer method: when comp is less than 0.85v and raises an error flag, the timer starts counting. if the error flag is removed, the timer resets. if the timer overflows after reaching 6000, olp triggers. this timer duration avoids triggering the olp when
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 15 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. the power supply is at start-up or load transition phase. therefore, set the output voltage in less than 6000 switching cycles during start-up. ramp compensation circuit if the power supply operates in ccm and the duty cycle is larger than 0.5, add a ramp compensation circuit to avoid harmonics in peak current mode control. usually, the ramp compensation rate is selected as per equation (10) o sense m vnr k l ?? ??? (10) where: ? ? ? r sense is the value of primary sense resistor for applications using the HFC0300, use the ramp compensation circuit shown in figure 13 . gnd cs drv HFC0300 1 2 3 4 5 6 8 fset hv vcc comp vcc cs 510k 33pf 1k 30k r1 r2 r3 c1 figure 13: ramp compensation circuit equation (11) estimates the compensation rate of the above circuit : drv 1 2 vr k* r ? ? (11) where v drv is the drive voltage 31 r*c ? ? select ? design summary figure 14 shows a detailed reference design of the off-time controlled flyback converter using the HFC0300. the input voltage is 90vac to 265vac and the output is 24v/1.5a. the transformer used in this design has a turn ratio of 84:14:8 (n p : n s : n aux ) with a primary inductance of 818 h. the core is ee25. figure 15, figure 16, and table 1 winding ordershow wiring schematics.
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 16 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. pgnd 4 5 3 1 pgnd pgnd agnd pgnd 6/7 9/10 agnd cn2 HFC0300 cn1 1a f1 lx1 ns np np-aux ee25 t1 comp 4 fset 5 gnd 3 vcc 6 cs 2 nc 7 drv 1 hv 8 u1 gbu406 bd1 5 rt1 2.2m r3 2.2m r5 150k r2a 150k r2b 51k r2 nc rf 10 r6 20k r7 1k r8 10k r1 1 r3c 1 r3b 1 r3a 1k r13 1 r14 11.3k r16 nc r17 20 r11a 20 r11b c1 4.7nf c2 c5 1nf c7 c8 3.3nf c9 c11 c12 c13 fr107 d2 tl431k u3 u2 pc817a ap2761i-a q1 97.6k r15 4.02k r12 2.2nf cy3 cx1 b1100 1 2 d3 3.3 r4 1 2 c3 c6 c10 l1 1 3 2 v40120c d1 figure 14: schematic of off-time flyback converter with HFC0300 sec. n 1 n 2 n 4 3 4 5 2 1 n 3 9 7 pri. 6 10 teflon tube figure 15: connection diagram
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 17 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. table 1 winding order tape(t) winding edge tape (pri.) terminal (start-end) edge tape (sec.) wire size ( ) turns ( t ) 1 n1 2mm 3->2 2mm 0.3mm*1 42 1 n2 2mm 5->4 2mm 0.2mm*1 8 3 n3 2mm 9,10->6,7 2mm 0.3mm*5 14 3 n4 2mm 2->1 2mm 0.3mm*1 42 3 experimental verification a physical prototype based on figure 13 was used to verify both the design procedure presented in this application note, and the performance. the input ranged between 90vac and 265vac, and the output was at 24v/1.5a. the converter operates in bcm at 90vac input and full load. figure 17 and figure 18 the current and drain voltage waveforms of the primary mosfet. figure 19 shows the burst mode function of the controller at light load. to minimize power dissipation at no load or light load, the HFC0300 enters burst-mode operation. as the load decreases, the comp voltage increases. the hf0300 skips switching cycles when the comp voltage increases over the threshold v burh = 3.2v. the output voltage drops, causing the comp voltage to decrease again. once the comp voltage falls below the threshold v burl = 3.1v, switching resumes. the comp voltage then rings. the burst mode operation alternately enables and disables switching cycles of the mosfet thereby reducing switching loss in the no load or light load conditions. figure 20 shows over-load protection. when comp is low, the controller stops switching after 6000 switching cycles (about 100ms for this application) figure 21 shows the measured efficiency. from the efficiency curve, the efficiency is still high at light load condition due to decreased switching frequency. also the power consumption at no load is given in table 2. in burst mode, the power loss with no load is very small, even with high line input. n1 n2 n3 n4 1t 3t 3t 2mm pri. side 2mm sec. side 1t tape: 3t figure 16: winding diagram
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 18 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. figure 17: drain current and voltage of mosfet at low-line input (90vac); ch2 - cs, ch3, v ds cs v ds v ds cs figure 18: drain current and voltage of mosfet at high-line input (230vac); cs2 - cs, ch3 - v ds
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 19 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved comp drv vout iout figure 19: burst mode; ch2 - comp, ch3 - drv figure 20: overload protection; ch1 - v out , ch2 - drv, ch4 - i out
HFC0300? variable off time controller HFC0300 rev. 1.0 www.monolithicpower.com 20 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. table 2: no-load loss at different line voltages input voltage (v ac , rms) 90 115 230 265 power loss (mw) 74.4 77.2 110.1 121.9 72.00% 74.00% 76.00% 78.00% 80.00% 82.00% 84.00% 86.00% 88.00% 90.00% 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 output current io(a) efficiency(%) vin=115vac vin=230vac figure 21: measured efficiency
HFC0300? variable off time controller notice: the information in this document is subject to change wi thout notice. users should warra nt and guarantee that third party intellectual property rights are not infringed upon w hen integrating mps products into any application. mps will not assume any legal responsibility for any said applications. HFC0300 rev. 1.0 www.monolithicpower.com 21 9/23/2011 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2011 mps. all rights reserved. package information soic-7 0.016(0.41) 0.050(1.27) 0 o -8 o detail "a" 0.010(0.25) 0.020(0.50) x 45 o see detail "a" 0.0075(0.19) 0.0098(0.25) 0.150(3.80) 0.157(4.00) pin 1 id 0.050(1.27) bsc 0.013(0.33) 0.020(0.51) seating plane 0.004(0.10) 0.010(0.25) 0.189(4.80) 0.197(5.00) 0.053(1.35) 0.069(1.75) top view front view 0.228(5.80) 0.244(6.20) side view 14 85 recommended land pattern 0.213(5.40) 0.063(1.60) 0.050(1.27) 0.024(0.61) note: 1) control dimension is in inches . dimension in bracket is in millimeters . 2) package length does not include mold flash , protrusions or gate burrs. 3) package width does not include interlead flash or protrusions. 4) lead coplanarity (bottom of leads after forming ) shall be 0.004" inches max. 5) jedec reference is ms-012. 6) drawing is not to scale . 0.010(0.25) bsc gauge plane

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