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8 bit microcontroller tlcs-870/c series TMP86P203PG
the information contained herein is subject to change without notice. 021023_d toshiba is continually working to improve the qua lity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utiliz ing toshiba products, to comply with the standards of safety in making a safe design for the entire sy stem, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most r ecent toshiba products specifications. also, please keep in mind the precauti ons and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc. 021023_a the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, of fice equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation in struments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc. unintended usage of toshiba products listed in this document shall be made at the customer's own risk. 021023_b the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohib ited under any applicable laws and regulations. 060106_q the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba for any infring ements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patents or other rights of toshiba or the third parties. 070122_c the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and reliabil ity assurance/handling precautions. 030619_s ? 2007 toshiba corporation all rights reserved
revision history date revision 2007/8/31 1 first release 2007/10/16 2 contents revised 2008/8/29 3 contents revised
caution in setting the ua rt noise rejection time when uart is used, settings of rxdnc are limited depend ing on the transfer clock specified by brg. the com- bination "o" is available but please do not select the combination "?". the transfer clock generated by timer/counter in terrupt is calculated by the following equation : transfer clock [hz] = time r/counter source clock [hz] brg setting transfer clock [hz] rxdnc setting 00 (no noise rejection) 01 (reject pulses shorter than 31/fc[s] as noise) 10 (reject pulses shorter than 63/fc[s] as noise) 11 (reject pulses shorter than 127/fc[s] as noise) 000 fc/13 o o o ? 110 (when the transfer clock gen- erated by timer/counter inter- rupt is the same as the right side column) fc/8 o ? ? ? fc/16 o o ? ? f c / 3 2ooo ? t h e s e t t i n g e x c e p t t h e a b o v eoooo

i table of contents TMP86P203PG 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin names and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. operational description 2.1 cpu core functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 memory address map ............................................................................................................................... 7 2.1.2 program memory (otp) ........................................................................................................................... 7 2.1.3 data memory (ram) ................................................................................................................................. 7 2.2 system clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.1 clock generator ........................................................................................................................................ 8 2.2.2 timing generator .................................................................................................................................... 10 2.2.2.1 configuration of timing generator 2.2.2.2 machine cycle 2.2.3 operation mode control circuit .............................................................................................................. 11 2.2.3.1 single-clock mode 2.2.3.2 stop mode 2.2.4 operating mode control ......................................................................................................................... 14 2.2.4.1 stop mode 2.2.4.2 idle1 mode 2.2.4.3 idle0 mode (idle0) 2.3 reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.1 external reset input ............................................................................................................................... 24 2.3.2 address trap reset ............................................................................................................................... ... 25 2.3.3 watchdog timer reset .............................................................................................................................. 25 2.3.4 system clock reset ............................................................................................................................... ... 25 3. interrupt control circuit 3.1 interrupt latches (il15 to il2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2 interrupt enable register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.2.1 interrupt master enable flag (imf) .......................................................................................................... 28 3.2.2 individual interrupt enable flags (ef15 to ef4) ...................................................................................... 28 note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3 interrupt sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.3.1 interrupt acceptance processing is packaged as follows. ....................................................................... 30 3.3.2 saving/restoring general-purpose registers ............................................................................................ 32 3.3.2.1 using push and pop instructions 3.3.2.2 using data transfer instructions 3.3.3 interrupt return ........................................................................................................................................ 33 3.4 software interrupt (intsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.4.1 address error detection .......................................................................................................................... 34 3.4.2 debugging .............................................................................................................................................. 34 3.5 undefined instruction interrupt (intundef) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
ii 3.6 address trap interrupt (intatrap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.7 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4. special function r egister (sfr) 4.1 sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5. i/o ports 5.1 p0 (p01 to p00) port (high current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 p1 (p12 to p10) port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.3 p2 (p20) port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.4 p3 (p37 to p30) port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6. watchdog timer (wdt) 6.1 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.2 watchdog timer control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.2.1 malfunction detection methods using the watchdog timer ................................................................... 46 6.2.2 watchdog timer enable ......................................................................................................................... 47 6.2.3 watchdog timer disable ........................................................................................................................ 48 6.2.4 watchdog timer interrupt (intwdt) ...................................................................................................... 48 6.2.5 watchdog timer reset ........................................................................................................................... 49 6.3 address trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.3.1 selection of address trap in internal ram (atas) ................................................................................ 50 6.3.2 selection of operation at address trap (atout) .................................................................................. 50 6.3.3 address trap interrupt (intatrap) ....................................................................................................... 50 6.3.4 address trap reset ............................................................................................................................... . 51 7. time base timer (tbt) 7.1 time base timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.1.1 configuration .......................................................................................................................................... 53 7.1.2 control .................................................................................................................................................... 53 7.1.3 function .................................................................................................................................................. 54 7.2 divider output (dvo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.2.1 configuration .......................................................................................................................................... 55 7.2.2 control .................................................................................................................................................... 55 8. 8-bit timercounter (tc3, tc4) 8.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.2 timercounter control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.3.1 8-bit timer mode (tc3 and 4) ................................................................................................................ 62 8.3.2 8-bit event counter mode (tc3, 4) ........................................................................................................ 63 8.3.3 8-bit programmable divider ou tput (pdo) mode (tc3, 4) ..................................................................... 63 8.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4) .................................................................. 65 8.3.5 16-bit timer mode (tc3 and 4) .............................................................................................................. 67 8.3.6 16-bit event counter mode (tc3 and 4) ................................................................................................ 68 8.3.7 16-bit pulse width modulation (pwm) output mode (tc3 and 4) .......................................................... 68
iii 8.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4) ............................................... 71 9. 8-bit ad conv erter (adc) 9.1 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 9.2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 9.3 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 9.3.1 ad converter operation ......................................................................................................................... 76 9.3.2 ad converter operation ......................................................................................................................... 76 9.3.3 stop mode during ad conversion ........................................................................................................ 77 9.3.4 analog input voltage and ad conversion result ................................................................................... 78 9.4 precautions about ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.4.1 analog input pin voltage range ............................................................................................................... 79 9.4.2 analog input shared pins ........................................................................................................................ 79 9.4.3 noise countermeasure ............................................................................................................................ 79 10. otp operation 10.1 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 10.1.1 mcu mode ............................................................................................................................................ 81 10.1.1.1 program memory 10.1.1.2 data memory 10.1.2 prom mode ......................................................................................................................................... 81 10.1.2.1 programming flowchart (high-speed program writing) 10.1.2.2 program writing using a general-purpose prom programmer 11. input/output circuitry 11.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 11.2 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 12. electrical characteristics 12.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 12.2 operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 12.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.4 ad conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 12.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.6 recommended oscillation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 12.7 dc characteristics, ac characteristics (prom mode) . . . . . . . . . . . . . . . . . . . . 94 12.7.1 read operation in prom mode ............................................................................................................ 94 12.7.2 program operation (high-speed) (topr = 25 ............................................................................. 95 12.8 handling precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 13. package dimensions this is a technical docu ment that describes the operat ing functions and electrical
iv specifications of the 8-bit microc ontroller series tlcs-870/c (lsi).
page 1 TMP86P203PG cmos 8-bit microcontroller ? the information contained herein is subject to change without notice. 021023_d ? toshiba is continually working to improve the quality and reli ability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vulnerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of sa fety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, pleas e ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling gui de for semiconductor devices,? or ?toshiba se miconductor reliability handbook? etc. 021023_a ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bod ily injury (?unintended usage?). unintended us age include atomic energy control instru ments, airplane or spaceship instruments, transporta tion instruments, traffic signal instrume nts, combustion control instruments, medi cal instru- ments, all types of safety dev ices, etc. unintended usage of toshiba products li sted in this document shall be made at the cust omer's own risk. 021023_b ? the products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any appl icable laws and regulations. 060106_q ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patents or other rights of toshiba or the third parties. 070122_c ? the products described in this document are subject to foreign exchange and foreign trade control laws. 060925_e ? for a discussion of how the reliability of microcontrollers c an be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/h andling precautions. 030619_s TMP86P203PG the TMP86P203PG is a single-chip 8-bit high-speed an d high-functionality microcomputer incorporating 2048 bytes of one-time prom. 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c series - instruction execution time : 1.60 s (at 2.5 mhz) - 132 types & 731 basic instructions 2. 11interrupt sources (external : 3 internal : 8) 3. input / output ports (14 pins) large current output: 2pins (typ. 20ma), led direct drive 4. watchdog timer 5. prescaler - time base timer - divider output function 6. 8-bit timer counter : 2 ch - timer, event counter, - programmable divider output (pdo), - pulse width modulation (pwm) output, - programmable pulse generation (ppg) modes 7. 8-bit successive approximation type ad converter (with sample hold) analog inputs: 4ch 8. low power consumption operation product no. rom (eprom) ram package emulation chip TMP86P203PG 2048 bytes 128 bytes dip20-p-300-2.54 a tmp86c908xb
page 2 1.1 features TMP86P203PG stop mode: oscillation stops. (battery/capacitor back-up.) idle0 mode: cpu stops, and only the time-based-tim er(tbt) on peripherals operate using high fre- quency clock. release by falling edge of th e source clock which is set by tbtcr. idle1 mode: cpu stops and peripherals operate us ing high frequency clock. release by interru- puts(cpu restarts). 9. rc oscillation 10. operation voltage: 4.5 v to 5.5 v at 2.5 mhz
page 3 TMP86P203PG 1.2 pin assignment figure 1-1 pin assignment vss xout test vdd p00 p01 reset ( int5 / stop ) p20 ( int0 ) p10 xin p12 ( dvo ) p31 (tc4/ pdo4/pwm4/ppg4 ) p32 p33 p35 (ain3) p36 (ain4) p37 (ain5) p30 (tc3/ pdo3/pwm3 ) p34 (ain2) p11 (int1) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10
page 4 1.3 block diagram TMP86P203PG 1.3 block diagram figure 1-2 block diagram
page 5 TMP86P203PG 1.4 pin names and functions the TMP86P203PG has mcu mode and prom mode. tabl e 1-1 shows the pin functions in mcu mode. the prom mode is explained later in a separate chapter. table 1-1 pin names and functions pin name pin number input/output functions p01 7 io port01 p00 6 io port00 p12 dvo 12 io o port12 divider output p11 int1 11 io i port11 external interrupt 1 input p10 int0 10 io i port10 external interrupt 0 input p20 stop int5 9 io i i port20 stop mode release signal input external interrupt 5 input p37 ain5 20 io i port37 ad converter analog input 5 p36 ain4 19 io i port36 ad converter analog input 4 p35 ain3 18 io i port35 ad converter analog input 3 p34 ain2 17 io i port34 ad converter analog input 2 p33 16 io port33 p32 15 io port32 p31 tc4 pdo4/pwm4/ppg4 14 io i o port31 tc4 input pdo4/pwm4/ppg4 output p30 tc3 pdo3/pwm3 13 io i o port30 tc3 input pdo3/pwm3 output xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal test 4 i test pin for out-going test. normally, be fixed to low. vdd 5 i +5v vss 1 i 0(gnd)
page 6 1.4 pin names and functions TMP86P203PG
page 7 TMP86P203PG 2. operational description 2.1 cpu core functions the cpu core consists of a cpu, a system cl ock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, and the reset circuit. 2.1.1 memory address map the TMP86P203PG memory is compos ed otp ram, and sfr(special function register). they are all mapped in 64-kbyte address space. figure 2- 1 shows the TMP86P203PG memory address map. figure 2-1 memory address map 2.1.2 program memory (otp) the TMP86P203PG has a 2048 bytes (address f800h to ffffh) of program memory (otp). 2.1.3 data memory (ram) the TMP86P203PG has 128 bytes (address 0040h to 00bfh) of internal ram. the internal ram are located in the direct area; instru ctions with shorten operations ar e available against such an area. the data memory contents become un stable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. sfr 0000 h 64 bytes sfr: ram: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers program status word random access memory includes: data memory stack 003f h ram 0040 h 128 bytes 00bf h f800 h otp program memory otp 2048 bytes ffc0 h vector table for vector call instructions (32 bytes) ffdf h ffe0 h vector table for interrupts (32 bytes) ffff h
page 8 2. operational description 2.2 system clock controller TMP86P203PG 2.2 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. figure 2-2 syst em colck control 2.2.1 clock generator the clock generator generates the basic clock which pr ovides the system clocks supplied to the cpu core and peripheral hardware. the high-frequency (fc) clock can eas ily be obtained by connecting a resonator between the xin and xout pins . clock input from an external oscillator is also possi ble. in this case, external clock is applied to xin pin with xout pin not connected. example :clears ram to ?00h?. (TMP86P203PG) ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 007fh sramclr: ld (hl), a inc hl dec bc jrs f, sramclr tbtcr syscr2 syscr1 xin xout fc 0036 h 0038 h 0039 h timing generator control register clock generator high-frequency clock oscillator timing generator system clocks clock generator control system control registers standby controller
page 9 TMP86P203PG figure 2-3 examples of resonator connection note:the function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscilla tion frequency should create the program for the adjust- ment in advance. xout xin (a) rc oscillation high-frequency clock r x c xin (open) xout xin (b) external oscillator
page 10 2. operational description 2.2 system clock controller TMP86P203PG 2.2.2 timing generator the timing generator generates the various system cloc ks supplied to the cpu core and peripheral hardware from the basic clock (fc). the timing generator provides the following functions. 1. generation of main system clock 2. generation of divider output ( dvo ) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters 6. generation of warm-up clocks for releasing stop mode 2.2.2.1 configuration of timing generator the timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. as reset and stop mode started/canceled, the prescaler and the divider are cleared to ?0?. figure 2-4 configurat ion of timing generator high-frequency clock fc divider fc/4 fc machine cycle counters 1 2 1 4 3 2 8 7 10 9 12 11 14 13 16 15 warm-up controller watchdog timer 5 6 17 18 19 20 21 timer counter, time-base-timer , divider output, etc. divider prescaler
page 11 TMP86P203PG 2.2.2.2 machine cycle instruction execution and peripheral hardware operat ion are synchronized with the main system clock. the minimum instruction execution uni t is called an ?machine cycle?. th ere are a total of 10 different types of instructions for the tlcs-870/c series: ra nging from 1-cycle instructions which require one machine cycle for execution to 10-cyc le instructions which require 10 machine cycles fo r execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 2-5 machine cycle 2.2.3 operation mode control circuit the operation mode control circuit starts and stops the oscillation circuit for the high-frequency clock. there are two operating modes: single cloc k mode and stop mode. these modes are controlled by the system con- trol registers (syscr1 and syscr2). figure 2- 6 shows the operating mode transition diagram. 2.2.3.1 single-clock mode the oscillation circuit for the high-frequency clock is used. the main-system clock is obtained from the high-frequency clock. in the single-clock mode, the machine cycle time is 4/fc [s]. (1) normal1 mode in this mode, both the cpu core and on-chip pe ripherals operate using the high-frequency clock. the TMP86P203PG is placed in this mode after reset. (2) idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2 = "1", and idle1 mode is released to normal1 mode by an interrupt request from the on-chip peri pherals or external interrupt inputs. when the imf (interrupt master enable flag) is ?1? (interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to nor mal after the interrupt service is completed. when the imf is ?0? (interrupt disable), the execution will resume with the instruction which follows the idle1 mode start instruction. (3) idle0 mode in this mode, all the circuit, except oscillator an d the timer-base-timer, stops operation. this mode is enabled by syscr2 = "1". main system clock state machine cycle s3 s2 s1 s0 s3 s2 s1 s0 1/fc [s]
page 12 2. operational description 2.2 system clock controller TMP86P203PG when idle0 mode starts, the cpu stops and the timing generator stops feeding the clock to the peripheral circuits other than tbt. then, upon de tecting the falling edge of the source clock selected with tbtcr, the timing generator starts feeding the clock to al l peripheral circuits. when returned from idle0 mode, the cpu rest arts operating, entering normal1 mode back again. idle0 mode is entered and returned regardless of how tbtcr is set. when imf = ?1?, ef6 (tbt interrupt individu al enable flag) = ?1?, and tb tcr = ?1?, interrupt pro- cessing is performed. when idle0 mode is entered while tbtcr = ?1?, the inttbt interrupt latch is set after returning to normal1 mode. 2.2.3.2 stop mode in this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. the internal status immediately prior to the halt is held with a lowest power consumption during stop mode. stop mode is started by the syst em control register 1 (syscr1), an d stop mode is released by a inputting (either level-sensitive or edge-sens itive can be programmably selected) to the stop pin. after the warm-up period is completed, the execution resumes with the instruction which follows the stop mode start instruction. note 1: the mode is released by fa lling edge of tbtcr setting. figure 2-6 operating mode transition diagram table 2-1 operating mode and conditions operating mode oscillator cpu core tbt other peripherals machine cycle time high frequency single clock reset oscillation reset reset reset 4/fc [s] normal1 operate operate operate idle1 halt idle0 halt stop stop halt ? note 1 stop pin input syscr1 = "1" syscr2 = "1" interrupt syscr2 = "1" reset release normal1 mode idle0 mode idle1 mode reset stop
page 13 TMP86P203PG note 1: when stop mode is released with reset pin input, a return is made to normal1. note 2: fc: high-frequency clock [hz], *; don?t care note 3: bits 1 and 0 in syscr1 are read as undefined data when a read instruction is executed. note 4: as the hardware becomes stop mode under outen = ?0?, input value is fixed to ?0?; therefore it may cause external interrupt request on account of falling edge. note 5: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. note 6: always set bit5 in syscr1 to "0". note 7: the warmig-up time should be set correctly for using oscillator. note 1: when syscr2 is cleard to "0", the device is reset. note 2: *: don?t care, tg: timing generator, *; don?t care note 3: bits 3, 1 and 0 in syscr2 are always read as undefined value. note 4: do not set idle and tghalt to ?1? simultaneously. note 5: because returning from idle0 to normal1 is executed by the asynchronous internal cl ock, the period of idle0 mode might be shorter than the period setting by tbtcr. note 6: when idle1 mode is released, idle is automatically cleared to ?0?. note 7: when idle0 mode is released, tghalt is automatically cleared to ?0?. note 8: always clear bit6 and 5 in syscr2 to "0". note 9: before setting tghalt to ?1?, be sure to stop peripheral s. if peripherals are not stopped, the interrupt latch of periph erals may be set after idle0 mode is released. system control register 1 syscr176543210 (0038h) stop relm 0 outen wut (initial value: 0000 00**) stop stop mode start 0: cpu core and peripherals remain active 1: cpu core and peripherals are halted (start stop mode) r/w relm release method for stop mode 0: edge-sensitive release 1: level-sensitive release r/w outen port output during stop mode 0: high impedance 1: output kept r/w wut warm-up time at releasing stop mode return to normal mode r/w 00 01 10 11 3 x 2 16 /fc 2 16 /fc 3 x 2 14 /fc 2 14 /fc system control register 2 syscr2 (0039h) 76543210 xen "0" "0" idle tghalt (initial value: 1000 *0**) xen high-frequency oscillator control 0: turn off oscillation 1: turn on oscillation r/w idle cpu and watchdog timer control (idle1 mode) 0: cpu and watchdog timer remain active 1: cpu and watchdog timer are stopped (start idle1 mode) r/w tghalt tg control (idle0 mode) 0: feeding clock to all peripherals from tg (start idle0 mode)
page 14 2. operational description 2.2 system clock controller TMP86P203PG 2.2.4 operating mode control 2.2.4.1 stop mode stop mode is controlled by the system control register 1, the stop pin input. the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting syscr1 to ?1?. during stop mode, the following status is maintained. 1. oscillations are turned off, and all internal operations are halted. 2. the data memory, registers, the program status wo rd and port output latches are all held in the status in effect before stop mode was entered. 3. the prescaler and the divider of th e timing generator are cleared to ?0?. 4. the program counter holds the address 2 ahead of th e instruction (e.g., [set (syscr1).7]) which started stop mode. stop mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the syscr1. note 1: during stop period (from start of stop mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to ?1? and interrupts may be accepted immediately after stop mode is released. before starting stop mode, therefore, disable interrupts. also, before enabling interrupts after stop mode is released, clear unnecessary interrupt latches. (1) level-sensitive release mode (relm = ?1?) in this mode, stop mode is released by setting the stop pin high. this mode is used for capacitor backup when the main power supply is cut off and long term battery backup. even if an instruction for star ting stop mode is executed while stop pin input is high, stop mode does not start but instead the warm-up sequenc e starts immediately. th us, to start stop mode in the level-sensitive release mode, it is nece ssary for the program to first confirm that the stop pin input is low. the following two methods can be used for confirmation. 1. testing a port. 2. using an external interrupt input int5 ( int5 is a falling edge-sensitive input). example 1 :starting stop mode from normal mode by testing a port p20. ld (syscr1), 01010000b ; sets up the level-sensitive release mode sstoph: test (p2prd). 0 ; wait until the stop pin input goes low level jrs f, sstoph di ; imf example 2 :starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if jrs f, sint5 port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. di ; imf
page 15 TMP86P203PG figure 2-7 level-s ensitive release mode note 1: even if the stop pin input is low after warm-up start, the stop mode is not restarted. note 2: in this case of changing to the level-s ensitive mode from the edge-s ensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. (2) edge-sensitive release mode (relm = ?0?) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in appli- cations where a relatively short pr ogram is executed repeat edly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high level. figure 2-8 edge-sensitive release mode stop mode is released by the following sequence. 1. the high-frequency clock oscillator is turned on. 2. a warm-up period is inserted to allow oscillation time to stabilize. during warm up, all internal operations remain halted. four differ ent warm-up times can be selected with the syscr1 in accordance with the resonator characteristics. 3. when the warm-up time has elapsed, normal operation resumes with the instruction follow- ing the stop mode start instruction. example :starting stop mode from normal mode di ; imf v ih normal operation warm up stop operation confirm by program that the stop pin input is low and start stop mode. always released if the stop pin input is high. stop pin xout pin stop mode is released by the hardware. normal operation normal operation normal operation v ih stop mode is released by the hardware at the rising edge of stop pin input. warm up stop mode started by the program. stop operation stop operation stop pin xout pin
page 16 2. operational description 2.2 system clock controller TMP86P203PG note 1: when the stop mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". note 2: stop mode can also be released by inputting low level on the reset pin, which immediately performs the normal reset operation. note 3: when stop mode is released with a low hold voltage, the following cautions must be observed. the power supply voltage must be at the operating voltage level before releasing stop mode. the reset pin input must also be ?h? level, rising together with the power supply voltage. in this case, if an external time const ant circuit has been connected, the reset pin input voltage will increase at a slower pace than the power supply vo ltage. at this time, there is a danger that a reset may occur if input voltage level of the reset pin drops below the non-inverting high-level input voltage (hysteresis input). note 1: the warm-up time is obtained by dividing the ba sic clock by the divider. therefore, the warm-up time may include a certain amount of error if ther e is any fluctuation of the oscillation frequency when stop mode is released. thus, the warm -up time must be considered as an approximate value. table 2-2 warm-up time example (at fc = 2.5 mhz) wut warm-up time [ms] 00 01 10 11 78.64 26.21 19.66 6.554
page 17 TMP86P203PG figure 2-9 stop mode start/release instruction address a + 4 0 instruction address a + 3 turn on turn on warm up 0 n halt set (syscr1). 7 turn off (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 instruction address a + 2 2 1 0 3 (b) stop mode release count up turn off halt oscillator circuit program counter instruction execution divider main system clock oscillator circuit stop pin input program counter instruction execution divider main system clock
page 18 2. operational description 2.2 system clock controller TMP86P203PG 2.2.4.2 idle1 mode idle1 mode is controlled by the system control register 2 (syscr2) and maskable interrupts. the fol- lowing status is maintained during this mode. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before this mode were entered. 3. the program counter holds the address 2 ahead of the instruction which starts this mode. figure 2-10 idle1 mode reset reset input ?0? ?1? (interrupt release mode) yes no no cpu and wdt are halted interrupt request imf interrupt processing normal release mode yes starting idle1 mode by instruction execution of the instruc- tion which follows the idle1 mode start instruction
page 19 TMP86P203PG ? start the idle1 mode after imf is set to "0", set the individual in terrupt enable flag (ef) which releases idle1 mode. to start idle1 mode, set syscr2 to ?1?. ? release the idle1 mode idle1 mode includes a normal release mode a nd an interrupt release mode. these modes are selected by interrupt master enable flag (imf). after releasing idle1 mode, the syscr2 is automatically cleared to ?0? and the operati on mode is returned to the mode preceding idle1 mode. idle1 mode can also be released by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. (1) normal release mode (imf = ?0?) idle1 mode is released by any interrupt source enabled by the individual interrupt enable flag (ef). after the interrupt is generated, the progra m operation is resumed from the instruction follow- ing the idle1 mode starts instruction. normally, the interrupt latches (il) of the interrupt source used for releasing must be cleared to ?0? by load instructions. (2) interrupt release mode (imf = ?1?) idle1 mode are released by any interrupt source en abled with the individual interrupt enable flag (ef) and the interrupt processing is started. afte r the interrupt is processed, the program operation is resumed from the instruction following th e instruction, which starts idle1 mode. note: when a watchdog timer interrupts is generated immediately before idle1 mode are started, the watchdog timer interrupt will be processed but idle1 mode will not be started.
page 20 2. operational description 2.2 system clock controller TMP86P203PG figure 2-11 idle 1 mode start/release halt halt halt halt operate instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 halt set (syscr2). 4 operate operate operate acceptance of interrupt ?r:wnormal release mode ?s:winterrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer (a) idle1 mode start (example: starting with the set instruction located at address a) (b) idle1 mode release
page 21 TMP86P203PG 2.2.4.3 idle0 mode (idle0) idle0 mode is controlled by the system control re gister 2 (syscr2) and the time base timer control register (tbtcr). the following status is maintained during idle0 mode. 1. timing generator stops feeding clock to peripherals except tbt. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle0 mode was entered. 3. the program counter holds the address 2 ahead of th e instruction which starts idle0 mode. note: before starting idle0 mode, be su re to stop (disable) peripherals. figure 2-12 idle0 mode yes (normal release mode) yes (interrupt release mode) no yes reset input cpu and wdt are halted reset tbt source clock falling edge tbtcr = "1" interrupt processing imf = "1" yes tbt interrupt enable no no no no stopping peripherals by instruction yes starting idle0 mode by instruction execution of the instruction which follows the idle0 mode start instruction
page 22 2. operational description 2.2 system clock controller TMP86P203PG ? start the idle0 mode stop (disable) peripherals such as a timer counter. to start idle0 mode, set syscr2 to ?1?. ? release the idle0 mode idle0 mode include a normal release mode and an interrupt release mode. this mode is selected by interrupt master flag (imf), the individual interrupt enable flag of tbt and tbtcr. after releasing idle0 mode, the syscr2 is automatically cleared to ?0? and the operation mode is returned to the mode preceding idle0 mode. before starting the idle mode, when the tbtcr is set to ?1?, inttbt interrupt latch is set to ?1?. idle0 mode can also be released by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. note: idle0 mode start/release without reference to tbtcr setting. (1) normal release mode (imf ? ? idle0 mode are released by the source clock falling edge, which is setting by the tbtcr. after the falling edge is detect ed, the program operation is resumed from the instruction following the idle0 mode start instruction. before starting the idle mode, when the tbtcr is set to ?1?, inttbt interrupt latch is set to ?1?. (2) interrupt release mode (imf ? ? idle0 mode are released by the source clock falling edge, which is setting by the tbtcr and inttbt interrupt processing is started. note 1: because returning from idle0 to normal1 is executed by the asynchronous internal clock, the period of idle0 mode might be the shorte r than the period setting by tbtcr. note 2: when a watchdog timer interrupt is generated immediately before idle0 mode is started, the watchdog timer interrupt will be processed but idle0 mode will not be started.
page 23 TMP86P203PG figure 2-13 idle0 m ode start/release halt halt operate instruction address a + 2 halt operate set (syscr2). 2 halt operate acceptance of interrupt halt ?r:wnormal release mode ?s:winterrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock tbt clock tbt clock program counter instruction execution watchdog timer main system clock program counter instruction execution watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 (a) idle0 mode start (example: starting with the set instruction located at address a (b) idle0 mode release
page 24 2. operational description 2.3 reset circuit TMP86P203PG 2.3 reset circuit the TMP86P203PG has four types of reset generation procedur es: an external reset input, an address trap reset, a watchdog timer reset and a system clock re set. of these reset, the address trap reset, the watchdog timer and the sys- tem clock reset are a malfunction reset. when the malfunction reset request is detected, reset occurs during the max- imum 24/fc[s]. the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial- ized when power is turned on. therefore, reset may occur during maximum 24/fc[s] (9.6 s at 2.5 mhz) when power is turned on. table 1-3 shows on-chip hardware initialization by reset action. 2.3.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at ?l? level for at least 3 machin e cycles (12/fc [s]) wi th the power supply volt- age within the operating voltage range and oscillation stab le, a reset is applied and the internal state is initial- ized. when the reset pin input goes high, the reset operation is rele ased and the program execution starts at the vector address stored at addresses fffeh to ffffh. figure 2-14 reset circuit table 2-3 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffeh) prescaler and divider of timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized jump status flag (jf) not initialized watchdog timer enable zero flag (zf) not initialized output latches of i/o ports refer to i/o port circuitry carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flags (ef) 0 control registers refer to each of control register interrupt latches (il) 0 ram not initialized internal reset reset vdd malfunction reset output circuit watchdog timer reset address trap reset system clock reset
page 25 TMP86P203PG 2.3.2 address trap reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (when wdtcr1 is set to ?1 ?) or the sfr area, address trap reset will be gen- erated. the reset time is maximum 24/fc[s] (9.6 s at 2.5 mhz). note:the operating mode under address tr apped is alternative of reset or interrupt. the address trap area is alter- native. note 1: address ?a? is in the sfr or on-chip ram (wdtcr1 = ?1?) space. note 2: during reset release, reset vector ?r? is read out, and an instruction at address ?r? is fetched and decoded. figure 2-15 addr ess trap reset 2.3.3 watchdog timer reset refer to 2.4 ?watchdog timer?. 2.3.4 system clock reset if the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the cpu. (the oscillation is continued without stopping.) - in case of clearing syscr2 to ? 0? . the reset time is maximum 24/fc (9.6 s at 2.5 mhz). instruction at address r 16/fc [s] maximum 24/fc [s] instruction execution internal reset jp a reset release address trap is occurred 4/fc to 12/fc [s]
page 26 2. operational description 2.3 reset circuit TMP86P203PG
page 27 TMP86P203PG 3. interrupt control circuit the TMP86P203PG has a total of 11 interrupt sources excludi ng reset. interrupts can be nested with priorities. four of the internal interrupt sources ar e non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il) , which hold interrupt requests, and independent vectors. the interrupt latch is set to ?1? by th e generation of its interrupt request wh ich requests the cpu to accept its inter- rupts. interrupts are enabled or disabled by software using the interrupt master enable fl ag (imf) and in terrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrup ts are accepted in order which is domi- nated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. note 1: to use the address trap interrupt (intatrap), clear wdtcr1 to ?0? (it is set for the ?reset request? after reset is cancelled). for details , see ?address trap?. note 2: to use the watchdog timer interrupt (intwdt), clear wdtcr1 to "0" (it is set for the "reset request" after reset is released). for details, see "watchdog timer". 3.1 interrupt latches (il15 to il2) an interrupt latch is provided for eac h interrupt source, except for a software interrupt and an executed the unde- fined instruction interrupt. when interrupt request is genera ted, the latch is set to ?1?, and the cpu is requested to accept the interrupt if its interrupt is enabled. the interrupt latch is cleared to "0" immediately after accepting inter- rupt. all interrupt latches are initialized to ?0? during reset. the interrupt latches are located on address 003ch and 003d h in sfr area. each latch can be cleared to "0" indi- vidually by instruction. however, il2 and il3 should not be cleared to "0" by software. for clearing the interrupt latch, load instruction should be used and then il2 and il3 should be set to "1". if the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if inter- rupt is requested while such instructions are executed. interrupt latches are not set to ?1? by an instruction. since interrupt latches can be read, the status fo r interrupt requests can be monitored by software. note: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf new ly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0 " automatically, clearing imf need not execute normally on interrupt factors enable condition interrupt latch vector address priority internal/external (reset) non-maskable ? fffe 1 internal intswi (software interrupt) non-maskable ? fffc 2 internal intundef (executed the undefined instruction interrupt) non-maskable ? fffc 2 internal intatrap (address trap interrupt) non-maskable il2 fffa 2 internal intwdt (watchdog timer interrupt) non-maskable il3 fff8 2 external int0 imf? ef4 = 1, int0en = 1 il4 fff6 5 external int1 imf? ef5 = 1 il5 fff4 6 internal inttbt imf? ef6 = 1 il6 fff2 7 - reserved imf? ef7 = 1 il7 fff0 8 - reserved imf? ef8 = 1 il8 ffee 9 - reserved imf? ef9 = 1 il9 ffec 10 internal inttc3 imf? ef10 = 1 il10 ffea 11 internal inttc4 imf? ef11 = 1 il11 ffe8 12 internal intadc imf? ef12 = 1 il12 ffe6 13 - reserved imf? ef13 = 1 il13 ffe4 14 - reserved imf? ef14 = 1 il14 ffe2 15 external int5 imf? ef15 = 1 il15 ffe0 16
page 28 3. interrupt control circuit 3.2 interrupt enable register (eir) TMP86P203PG interrupt service routine. however, if using multiple inte rrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". 3.2 interrupt enab le register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except fo r the non-maskable interrupts (software interrupt, undefined instruction interr upt, address trap interrupt and watchdog interrupt). non- maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt mast er enable flag (imf) and the individua l interrupt enable flags (ef). these registers are located on address 003ah and 003bh in sfr area, and they can be read and written by an instructions (including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 interrupt ma ster enable flag (imf) the interrupt enable register (imf ) enables and disables the acceptance of the whole maskable interrupt. while imf = ?0?, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to ?1?, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to ?0? after the latest status on imf is stacked. thus the maskable inter- rupts which follow are disabled. by executing return interrupt instruction [reti/retn], the stacked data, which was the status before interrup t acceptance, is loaded on imf again. the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cl eared by [ei] and [di] instruction respectively. during reset, the imf is initial- ized to ?0?. 3.2.2 individual interrupt enable flags (ef15 to ef4) each of these flags enables and disables the acceptan ce of its maskable interrupt . setting the corresponding bit of an individual interrupt enable flag to ?1? enables acceptan ce of its interrupt, and setting the bit to ?0? dis- ables acceptance. during reset, all the individual interrupt enable flags (ef15 to ef4) ar e initialized to ?0? and all maskable interrupts are not accepted until they are set to ?1?. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf become s "0" automatically, clearing imf need not execute nor- mally on interrupt service routine. however, if using mult iple interrupt on interrupt service routine, manipulat- ing ef or il should be executed before setting imf="1". example 1 :clears interrupt latches di ; imf example 2 :reads interrupt latchess ld wa, (ill) ; w example 3 :tests interrupt latches test (ill). 6 ; if il6 = 1 then jump jr f, sset
page 29 TMP86P203PG example 1 :enables interrupts individually and sets imf di ; imf example 2 :c compiler description example unsigned int _io (3ah) eirl; /* 3ah shows eirl address */ _di(); eirl = 10100000b; : _ei();
page 30 3. interrupt control circuit 3.3 interrupt sequence TMP86P203PG note 1: to clear any one of bits il6 to il4, be sure to write "1" into il2 and il3. note 2: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". note 3: do not clear il with read-modify-w rite instructions such as bit operations. note 1: *: don?t care note 2: do not set imf and the interrupt enable flag (ef15 to ef4) to ?1? at the same time. note 3: in main program, before manipulating the interrupt enable fl ag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clear ing imf need not execute normally on inter- rupt service routine. however, if using multiple interrupt on interrupt service routine, mani pulating ef or il should be exe- cuted before setting imf="1". 3.3 interrupt sequence an interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to ?0? by resetting or an instruc tion. interrupt acceptan ce sequence requires 8 machine cycles (12.8 s @2.5 mhz) after the completion of the current inst ruction. the interrupt service task term inates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [r etn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 interrupt acceptance proc essing is packaged as follows. a. the interrupt master enab le flag (imf) is cleared to ?0? in or der to disable the acceptance of any fol- lowing interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to ?0?. c. the contents of the program coun ter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the st ack in sequence of psw + imf, pch, pcl. mean- while, the stack pointer (s p) is decremented by 3. interrupt latches (initial value: 0**000** *00000**) ilh,ill (003dh, 003ch) 1514131211109876543210 il15 ?? ??? ?? ???
page 31 TMP86P203PG d. the entry address (interrupt vect or) of the corresponding interrupt service program, loaded on the vec- tor table, is transferred to the program counter. e. the instruction stored at the entry address of the inte rrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. note 1: a: return address entry address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 38/fc [s] at maximum (if the interrupt latch is set at the first machin e cycle on 10 cycle instruction) to start interrupt accept ance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return in terrupt instruction example: correspondence be tween vector table address for inttbt and the entry address of the interrupt service program figure 3-2 vector tabl e address, entry address a maskable interrupt is not accepted until the imf is set to ?1? even if th e maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to ?1? in the interrupt service program. in this case, acceptable interrupt sources are selectively en abled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to ?1?. as for non-maskable interr upt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. a b a c + 1 execute instruction sp pc execute instruction n n ? 2 n - 3 n ? 2n ? 1 n ? 1 n a + 2 a + 1 c + 2 b + 3 b + 2 b + 1 a + 1 a a ? 1 execute reti instruction interrupt acceptance execute instruction interrupt service task 1-machine cycle interrupt request interrupt latch (il) imf d2h 03h d203h d204h 06h vector table address entry address 0fh vector interrupt service program fff2h fff3h
page 32 3. interrupt control circuit 3.3 interrupt sequence TMP86P203PG 3.3.2 saving/restoring general-purpose registers during interrupt acceptance processing , the program counter (pc) and the program status word (psw, includes imf) are automati cally saved on the stack, but the accumulato r and others are not. these registers are saved by software if necessary. when multiple interrupt se rvices are nested, it is also necessary to avoid using the same data memory area for saving registers. the fo llowing methods are used to save/restore the general- purpose registers. 3.3.2.1 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested , general-purpose registers can be saved/restored using the push/pop instructions. figure 3-3 save/store register using push and pop instructions 3.3.2.2 using data transfer instructions to save only a specific register wi thout nested interrupts, data tran sfer instructions are available. example :save/store register us ing push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return example :save/store register us ing data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return pcl pch psw at acceptance of an interrupt at execution of push instruction at execution of reti instruction at execution of pop instruction b-4 b-3 b-2 b-1 b pcl pch psw pcl pch psw sp address (example) sp sp sp a w b-5
page 33 TMP86P203PG figure 3-4 saving/restoring general-purpose r egisters under interrupt processing 3.3.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. as for address trap interrupt (intatrap), it is requir ed to alter stacked data for program counter (pc) to restarting address, during interrupt service program. note:if [retn] is executed with the above data unaltered, the program returns to the address trap area and intatrap occurs again.when interrupt acceptance pr ocessing has completed, stacked data for pcl and pch are located on address (sp + 1) and (sp + 2) respectively. interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next inter- rupt can be accepted immediately after the interrupt retu rn instruction is executed. [reti]/[retn] interrupt return 1. program counter (pc) and program status word (psw, includes imf) are restored from the stack. 2. stack pointer (sp) is incremented by 3. example 1 :returning from address trap interrupt (intatrap) service program pintxx: pop wa ; recover sp by 2 ld wa, return address ; push wa ; alter stacked data (interrupt processing) retn ; return example 2 :restarting without returning interrupt (in this case, psw (includes imf) befo re interrupt acceptance is discarded.) pintxx: inc sp ; recover sp by 3 inc sp ; inc sp ; (interrupt processing) ld eirl, data ; set imf to ?1? or clear it to ?0? jp restart address ; jump into restarting address interrupt acceptance interrupt service task restoring registers saving registers interrupt return saving/restoring general-purpose registers using push/pop data transfer instruction main task
page 34 3. interrupt control circuit 3.4 software interrupt (intsw) TMP86P203PG note 1: it is recommended that stack pointer be return to rate before intatrap (increment 3 times), if return inter- rupt instruction [retn] is not utilized during inte rrupt service program under intatrap (such as example 2). note 2: when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.4 software interrupt (intsw) executing the swi instruction generates a software interr upt and immediately starts interrupt processing (intsw is highest prioritized interrupt). use the swi instruction only for detection of the address error or for debugging. 3.4.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is th e swi instruction, so a software interrupt is gener- ated and an address error is detect ed. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram or sfr areas. 3.4.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 3.5 undefined instruct ion interrupt (intundef) taking code which is not defined as authorized instru ction for instruction causes intundef. intundef is gen- erated when the cpu fetches such a co de and tries to execute it. intundef is accepted even if non-maskable inter- rupt is in process. contemporary process is broken and intundef interrupt process starts, soon after it is requested. note: the undefined instruction interrupt (intundef) forces cpu to jump into vector address, as software interrupt (swi) does. 3.6 address trap interrupt (intatrap) fetching instruction from unauthorized area for instructio ns (address trapped area) cause s reset output or address trap interrupt (intatrap). intatrap is accepted even if non-maskable interrupt is in process. contemporary pro- cess is broken and intatrap interrupt pro cess starts, soon afte r it is requested. note: the operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (wdtcr). 3.7 external interrupts the TMP86P203PG has 3 external interrupt inputs. these inputs are equipped with digital noise reject circuits (pulse inputs of less than a certa in time are elimin ated as noise). edge selection is also possible with int1. the int0 /p10 pin can be configured as ei ther an external interrupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0 / p10 pin function selection are performed by the external interrupt control register (eintcr).
page 35 TMP86P203PG note 1: in normal1 or idle1 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. note 2: when int0en = "0", il4 is not set even if a falling edge is detected on the int0 pin input. note 3: when a pin with more than one function is used as an out put and a change occurs in data or input/output status, an inter - rupt request signal is generated in a pseudo manner. in this ca se, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. source pin enable conditions release edge digital noise reject int0 int0 imf + ef4 + int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals. int1 int1 imf + ef5 = 1 falling edge or rising edge pulses of less than 15/fc or 63/fc [s] are elimi- nated as noise. pulses of 49/fc or 193/fc [s] or more are considered to be signals. int5 int5 imf + ef15 = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s ] or more are considered to be signals.
page 36 3. interrupt control circuit 3.7 external interrupts TMP86P203PG note 1: fc: high-frequency clock [hz], *: don?t care note 2: when the system clock frequency is switched between high and low or when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operat e normally. it is recommended that external interrupts are dis- abled using the interrupt enable register (eir). note 3: the maximum time from modifying int1 nc until a noise reject time is changed is 2 6 /fc. external interrupt control register eintcr76543210 (0037h) int1nc int0en - - - - int1es (initial value: 00** **0*) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise r/w int0en p10/ int0 pin configuration 0: p10 input/output port 1: int0 pin (port p10 should be set to an input mode) r/w int1 es int1 edge select 0: rising edge 1: falling edge r/w
page 37 TMP86P203PG 4. special function register (sfr) the TMP86P203PG adopts the memory mapped i/o system, an d all peripheral control and data transfers are per- formed through the special function register (sfr). the sfr is mapped on address 0000h to 003fh. this chapter shows the arrangem ent of the special function re gister (sfr) for TMP86P203PG. 4.1 sfr address read write 0000h p0dr 0001h p1dr 0002h p2dr 0003h p3dr 0004h reserved 0005h reserved 0006h reserved 0007h reserved 0008h reserved 0009h p1cr 000ah p3cr 000bh p0outcr 000ch p0prd - 000dh p2prd - 000eh adccr1 000fh adccr2 0010h reserved 0011h reserved 0012h reserved 0013h reserved 0014h reserved 0015h reserved 0016h reserved 0017h reserved 0018h reserved 0019h reserved 001ah tc3cr 001bh tc4cr 001ch ttreg3 001dh ttreg4 001eh pwreg3 001fh pwreg4 0020h adcdr1 - 0021h adcdr2 - 0022h reserved 0023h reserved 0024h reserved 0025h reserved 0026h reserved 0027h reserved
page 38 4. special function register (sfr) 4.1 sfr TMP86P203PG note 1: do not access reserved areas by the program. note 2: ?
page 39 TMP86P203PG 5. i/o ports the TMP86P203PG has 4 parallel input/output ports as follows. each output port contains a latch, which holds the output data. all input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. figure 5-1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transient input such as chattering must be processed by the pro- gram. output data changes in the s2 state of the write cycle du ring execution of the instruct ion which writes to an i/o port. note: the positions of the read and write c ycles may vary, depending on the instruction. figure 5-1 input/output timing (example) primary function secondary functions port p0 2-bit i/o port ? instruction execution cycle input strobe data input ex: ld a, (x) fetch cycle fetch cycle read cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 instruction execution cycle old new output strobe data output ex: ld (x), a fetch cycle fetch cycle write cycle s0 s1 s2 s3 s0 s1 s2 s3 s0 s1 s2 s3 (a) input timing (b) output timing
page 40 5. i/o ports TMP86P203PG 5.1 p0 (p01 to p00) port (high current) the p0 port is an 2-bit input/output port. when using th is port as an input port set the output latch to 1. when using this port as an output port, the outp ut latch data (p0dr) is output to the p0 port. when reset, the output latch (p0dr) and the push-pull co ntrol register (p0outcr) ar e initialized to 1 and 0, respectively. the p0 port allows its output circuit to be selected between n-channel open-drain i nput/output or push-pull output by the p0outcr register. when using this port as an input port, set the p0outcr register's corresponding bit to 0 after setting the p0dr to 1. the p0 port has independent data input registers. to inspect the output latch status, read the p0dr register. to inspect the pin status, r ead the p0prd register. figure 5-2 port p0 p0dr (0000h) r/w 765432 1 0 p01 p00 (initial value: **** **11) p0prd (000ch) read only 765432 1 0 p01 p00 p0outcr (000bh) r/w 765432 1 0 p0outcr1 p0outcr0 (initial value: **** **00) p0outcr controls p0 port output 0: sink open-drain input/output 1: push-pull output r/w

page 41 TMP86P203PG 5.2 p1 (p12 to p10) port the p1 port is a 3-bit input/output port that can be specified for input or output bitwise. the p1 port input/output control register (p1cr) is used to specify this port for input or output. when reset, the p1cr register is initialized to 0, with the p1 port set for input mode. the p1 port output latch is initialized to 0. the p1 port is shared with external interrupt input and divider output. when using the p1 port as function pin, set its input pins for input mode. for the output pins, first set their output latches to 1 before setting the pins for output mode. note that the p11 pin is an external interrupt input. (when used as an output port, its interrupt latch is set at the ris- ing or falling edge.) the p10 pin can be used as an input/output port or an external interrupt input by selecting its function with the external interrupt control register (int0e n). when reset, the p10 pin is chosen to be an input port. figure 5-3 port p1 p1dr (0001h) r/w 76543210 p12 dvo p11 int1 p10 int0 (initial value: **** *000) p1cr (0009h) 76543210 (initial value: **** *000) p1cr controls p1 port input/output (specified bitwise) 0: input mode 1: output mode r/w

page 42 5. i/o ports TMP86P203PG 5.3 p2 (p20) port the p2 port is a 1-bit input/output port shared with ex ternal interrupt input, and stop canceling signal input. when using this port as an input port or function pin, set the output latch to 1. the output latch is initialized to 1 when reset. we recommend using the p20 pin for exte rnal interrupt input or stop canceling signal input or as an input port. (when used as an output port, the interrupt latch is set by a falling edge.) the p2 port has independent data input registers. to inspect the output latch status, read the p2dr register. to inspect the pin status, read the p2prd register. when the p2dr or p2prd r ead instruction is executed for the p2 port, the values read from b its 7 to 1 are indeterminate. figure 5-4 port p2 note: the p20 pin is shared with the stop pin, so that when in stop mode, its output goes to a high-z state regardless of the outen status. p2dr (0002h) r/w 76543210 p20 int5 stop (initial value: **** ***1) p2prd (000dh) read only 76543210 p20

page 43 TMP86P203PG 5.4 p3 (p37 to p30) port the p3 port is an 8-bit input/output port that can be specifi ed for input or output bitwise, and is shared with analog input and 8-bit timer counter input/output. the p3 port input/output control register (p3cr) and ainds (adccr1 register bit 4) are used to specify this port for input or output. when reset, the p3cr re gister and p3dr are cleared to 0, while ainds is set to 1, so that p37 to p30 function as input port. when using the p3 port as an input port, set ainds = 1 while at the same time setting the p3cr register to 0. when using the p3 port for analog input, set ainds = 0 an d the pins selected with sa in (adccr1 register bits 3 to 0) are set for analog input no matte r what values are set in the p3dr and p3cr. when using the p3 port as an out- put port, set the p3cr to 1 and the pin associated with that bit is set for output mode, so that p3dr (output latch data) is output from that pin. when an input instruction is executed for the p3 port while using the ad converter, the pins selected for analog input read in the p3dr value into the internal circuit and th ose not selected for analog in put read in a 1 or 0 accord- ing to the logic level on each pin. even when an output instruct ion is executed, no latch data are forwarded to the pins selected for analog input. any pins of the p3 port which are not used for analog input can be used as input/output ports. during ad conver- sion, however, avoid executing output instru ctions on these ports, because this is necessary to maintain the accuracy of conversion. also, during ad conversion, take care not to enter a rapi dly changing signal to any port adjacent to analog input.
page 44 5. i/o ports TMP86P203PG figure 5-5 port p3 note 1: p30 and p31 are hysteresis inputs. note 2: input status on ports set for input mode are read in into the internal circuit. therefore, when using the ports in a mix ture of input and output modes, the contents of the output latches for the ports that are set for input mode may be rewritten by execution of bit mani pulating instructions. p3dr (0003h) r/w 76543210 p37 ain5 p36 ain4 p35 ain3 p34 ain2 p33 p32 p31 tc4 pdo4 pwm4 ppg4 p30 tc3 pdo3 pwm3 (initial value: 0000 0000) p3cr (000ah) 76543210 (initial value: 0000 0000) p3cr controls p3 port input/output (specified bitwise) 0: input mode 1: output mode r/w

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page 45 TMP86P203PG 6. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidly the cpu malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the cpu to a sy stem recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as ?reset request? or ?inter- rupt request?. upon the reset release, this signal is initialized to ?reset request?. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic inter- rupt. note: care must be taken in system des ign since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 watchdog timer configuration figure 6-1 watchdog timer configuration 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 fc/2 21 fc/2 19 fc/2 17
page 46 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86P203PG 6.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watch- dog timer is automatically enabled after the reset release. 6.2.1 malfunction detection me thods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as en dless loops or the deadlock condition s occur for some reason, the watch- dog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 is set to ?1? at this time, the reset request is generated and then internal hardware is initialized. when wdtcr1 is set to ?0?, a watchdog timer interrupt (intwdt) is generated. the watchdog timer temporarily stops counting in the stop mode including the warm-up or idle mode, and automatically restarts (continues counting) when the stop/idle mode is inactivated. note:the watchdog timer consists of an internal divider and a two-stage binary counter. when the clear code 4eh is written, only the binary counter is cleared, but not the internal divider . the minimum binary-counter overflow time, that depends on the timing at which the clear code (4eh) is written to the wdtcr2 register, may be 3/ 4 of the time set in wdtcr1. therefore, writ e the clear code using a cycle shorter than 3/4 of the time set to wdtcr1. example :setting the watchdog timer detection time to 2 21 /fc [s], and resetting the cpu malfunction detection ld (wdtcr2), 4eh : clears the binary counters. ld (wdtcr1), 00001101b : wdtt
page 47 TMP86P203PG note 1: after clearing wdtout to ?0?, the program cannot set it to ?1?. note 2: fc: high-frequency clock [hz], *: don?t care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a don?t care is read. note 4: to activate the stop mode, disable the watchdog timer or clear the counter immediately before entering the stop mode. after clearing the counter, clear the counter again immediately after the stop mode is inactivated. note 5: to clear wdten, set the register in accordance wi th the procedures shown in ?6.2.3 watchdog timer disable?. note 1: the disable code is valid only when wdtcr1 = 0. note 2: *: don?t care note 3: the binary counter of the watchdog timer must not be cleared by the interrupt task. note 4: write the clear code 4eh using a cycle shor ter than 3/4 of the time set in wdtcr1. 6.2.2 watchdog timer enable setting wdtcr1 to ?1? enables the watc hdog timer. since wdtcr1 is initialized to ?1? during reset, the watchdog timer is enabled automatically after the reset release. watchdog timer control register 1 wdtcr1 (0034h) 76543210 (atas) (atout) wdten wdtt wdtout (initial value: **11 1001) wdten watchdog timer enable/disable 0: disable (writing the disable code to wdtcr2 is required.) 1: enable write only wdtt watchdog timer detection time [s] normal1 mode write only 00 2 25 /fc 01 2 23 /fc 10 2 21 fc 11 2 19 /fc wdtout watchdog timer output select 0: interrupt request 1: reset request write only watchdog timer control register 2 wdtcr2 (0035h) 76543210 (initial value: **** ****) wdtcr2 write watchdog timer control code 4eh: clear the watchdog timer binary counter (clear code) b1h: disable the watchdog timer (disable code) d2h: enable assigning address trap area others: invalid write only
page 48 6. watchdog timer (wdt) 6.2 watchdog timer control TMP86P203PG 6.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the fo llowing procedures . setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. set the interrupt master flag (imf) to ?0?. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 to ?0?. 4. set wdtcr2 to the disable code (b1h). note:while the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. 6.2.4 watchdog time r interrupt (intwdt) when wdtcr1 is cleared to ?0?, a watchdog timer interrupt request (intwdt) is generated by the binary-counter overflow. a watchdog timer interrupt is the non-maskable interr upt which can be accepted regardless of the interrupt master flag (imf). when a watchdog timer interrupt is generated while the other interrupt including a watchdog timer interrupt is already accepted, the new watchdog timer interrupt is processed immediately and the previous interrupt is held pending. therefore, if watchdog timer interrupts are generated continuously without execution of the retn instruction, too many levels of nesting may cause a malfunction of the microcontroller. to generate a watchdog timer interrupt, set the stack pointer before setting wdtcr1. example :disabling the watchdog timer di : imf example :setting watchdog timer interrupt ld sp, 00bfh : sets the stack pointer ld (wdtcr1), 00001000b : wdtout
page 49 TMP86P203PG 6.2.5 watchdog timer reset when a binary-counter overflow occurs while wdt cr1 is set to ?1?, a watchdog timer reset request is generated. when a watchdog timer reset request is generated, the internal hardware is reset. the reset time is maximum 24/fc [s] (9.6 s @ fc = 2.5 mhz). figure 6-2 watchdog timer interrupt/reset clock binary counter overflow intwdt interrupt request (wdtcr1= "0") 2 17 /fc 2 19 /fc [s] (wdtt=11) write 4e h to wdtcr2 1 2 30 1 2 3 0 internal reset (wdtcr1= "1") a reset occurs
page 50 6. watchdog timer (wdt) 6.3 address trap TMP86P203PG 6.3 address trap the watchdog timer control register 1 and 2 share the a ddresses with the control regi sters to generate address traps. 6.3.1 selection of address tr ap in internal ram (atas) wdtcr1 specifies whether or not to generate address traps in the inte rnal ram area. to execute an instruction in the internal ram area, clear wdtcr1 to ?0?. to enable the wdtcr1 set- ting, set wdtcr1 and then write d2h to wdtcr2. executing an instruction in the sfr area generates an address trap unc onditionally regardless of the setting in wdtcr1. 6.3.2 selection of operati on at address trap (atout) when an address trap is generated, either the inte rrupt request or the reset request can be selected by wdtcr1. 6.3.3 address trap interrupt (intatrap) when a binary-counter overflow occurs during wdt cr1 set to ?0?, an address trap interrupt request (intatrap) is generated. an address trap interrupt is a non-maskable interrupt which can be accepted regardless of the interrupt mas- ter flag (imf). when an address trap interrupt is generated while th e other interrupt including a watchdog timer interrupt is already accepted, the new address trap is processed immediately and the previous interrupt is held pending. therefore, if address trap interrupts are generated continuously without execution of the retn instruction, too many levels of nesting may cause a malfunction of the microcontroller. to generate address trap interrupts, set the stack pointer beforehand. watchdog timer control register 1 wdtcr1 (0034h) 7654 3 21 0 atas atout (wdten) (wdtt) (wdtout) (initial value: **11 1001) atas select address trap generation in the internal ram area 0: generate no address trap 1: generate address traps (after setting atas to ?1?, writing the control code d2h to wdtcr2 is reguired) write only atout select opertion at address trap 0: interrupt request 1: reset request watchdog timer control register 2 wdtcr2 (0035h) 76543210 (initial value: **** ****) wdtcr2 write watchdog timer control code and address trap area control code d2h: enable address trap area selection (atrap control code) 4eh: clear the watchdog timer binary counter (wdt clear code) b1h: disable the watchdog timer (wdt disable code) others: invalid write only
page 51 TMP86P203PG 6.3.4 address trap reset while wdtcr1 is ?1?, if the cpu should start looping for some cause such as noise and attempt be made to fetch an instruction from the on-chip ram (while wdtcr1 is ?1?) or the sfr area, address trap reset will be generated. when an address tr ap reset request is generated, the internal hardware is reset. the reset time is maximum 24/fc [s] (9.6 s @ fc = 2.5 mhz).
page 52 6. watchdog timer (wdt) 6.3 address trap TMP86P203PG
page 53 TMP86P203PG 7. time base timer (tbt) the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). 7.1 time base timer 7.1.1 configuration figure 7-1 time base timer configuration 7.1.2 control time base timer is controled by time base timer control register (tbtcr). note 1: fc; high-frequency clock [hz], *; don't care note 2: the interrupt frequency (tbtck) must be selected with t he time base timer disabled (tbten="0"). (the interrupt fre- quency must not be changed with the disable from the enable state.) both frequency selection and enabling can be per- formed simultaneously. time base timer control register 7 6543210 tbtcr (0036h) (dvoen) (dvock) "0" tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal1 mode r/w 000 fc/2 23 001 fc/2 21 010 fc/2 16 011 fc/2 14 100 fc/2 13 101 fc/2 12 110 fc/2 11 111 fc/2 9 fc/2 23 fc/2 21 fc/2 16 fc/2 14 fc/2 13 fc/2 12 fc/2 11 fc/2 9 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request idle0 release request
page 54 7. time base timer (tbt) 7.1 time base timer TMP86P203PG 7.1.3 function an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider output of the timing generato which is selected by tbtck. ) after time base timer has been enabled. the divider is not cleared by the progra m; therefore, only the first interrupt may be generated ahead of the set interrupt period ( figure 7-2 ). figure 7-2 time base timer interrupt example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck
page 55 TMP86P203PG 7.2 divider output ( dvo ) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. 7.2.1 configuration figure 7-3 divider output 7.2.2 control the divider output is controlled by the time base timer control register. note: selection of divider output frequency (dvock) must be made whil e divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequen cy from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. time base timer control register 7654 321 0 tbtcr (0036h) dvoen dvock "0" (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo ) frequency selection: [hz] normal1 mode r/w 00 fc/2 13 01 fc/2 12 10 fc/2 11 11 fc/2 10 example :0.305 khz pulse output (fc = 2.5 mhz) ld (tbtcr) , 00000000b ; dvock
page 56 7. time base timer (tbt) 7.2 divider output (dvo) TMP86P203PG table 7-2 divider output freque ncy ( example : fc = 2.5 mhz ) dvock divider output frequency [hz] normal1 mode 00 0.305 k 01 0.610 k 10 1.22 k 11 2.44 k
page 57 TMP86P203PG 8. 8-bit timercounter (tc3, tc4) 8.1 configuration figure 8-1 8-bit timercouter 3, 4 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 fc/2 11 reserved reserved tc4cr tc3cr ttreg4 pwreg4 ttreg3 pwreg3 tc3 pin tc4 pin tc4s tc3s inttc3 interrupt request inttc4 interrupt request tff4 tff3 pdo 4/pwm 4/ ppg 4 pin pdo 3/pwm 3/ pin tc3ck tc4ck tc3m tc3s tff3 tc4m tc4s tff4 timer f/f4 timer f/f3
page 58 8. 8-bit timercounter (tc3, tc4) 8.1 configuration TMP86P203PG 8.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (ttreg3, pwreg3). note 1: do not change the timer register (t treg3) setting while the timer is running. note 2: do not change the timer register (pwreg3) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] note 2: do not change the tc3m, tc3ck and tff3 settings while the timer is running. note 3: to stop the timer operation (tc3s= 1
page 59 TMP86P203PG the timercounter 4 is controlled by the timercounter 4 control register (tc4cr) and two 8-bit timer registers (ttreg4 and pwreg4). note 1: do not change the timer register (t treg4) setting while the timer is running. note 2: do not change the timer register (pwreg4) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. note 1: fc: high-frequency clock [hz] note 2: do not change the tc4m, tc4ck and tff4 settings while the timer is running. note 3: to stop the timer operation (tc4s= 1
page 60 8. 8-bit timercounter (tc3, tc4) 8.1 configuration TMP86P203PG note 7: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see table 8-1. note 8: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 8- 2.
page 61 TMP86P203PG note 1: for 16-bit operations (16-bit timer/event counter, warm- up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc3ck). note 2: ?? ? ??? ????? ??? ?????? ???
page 62 8. 8-bit timercounter (tc3, tc4) 8.1 configuration TMP86P203PG 8.3 function the timercounter 3 and 4 have the 8-bit timer, 8-bit ev ent counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the time rcounter 3 and 4 (tc3, 4) are cascadable to form a 16- bit timer. the 16-bit timer has the operating modes such as the 16-bit timer, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 8.3.1 8-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cl eared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. note 2: in the timer mode, do not change the ttregj setting while the timer is running. si nce ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect immediately after the programming. therefore, if ttregi is changed while the timer is r unning, an expected operation may not be obtained. note 3: j = 3, 4 figure 8-2 8-bit timer mode timing chart (tc4) table 8-3 internal source clock for timercounter 3, 4 (internal clock) source clock resolution maximum setting time normal1, idle1 mode fc = 2.5 mhz fc = 2.5 mhz fc/2 11 [hz] 819 example :setting the timer mode with source clock fc/2 7 hz and generating an interrupt 512 s later (timercounter4, fc = 2.5 mhz) ld (ttreg4), 0ah : sets the timer register (512 1 2 3 n-1 n 0 1 n-1 n 2 0 1 2 0 n ? internal source clock counter match detect counter clear match detect counter clear tc4cr ttreg4 inttc4 interrupt request
page 63 TMP86P203PG 8.3.2 8-bit event counter mode (tc3, 4) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counti ng at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum frequenc y to be supplied is fc/2 4 hz in the normal1 or idle1 mode. note 1: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. note 2: in the event counter mode, do not change the ttre gj setting while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect immediately after the programming. therefore, if ttregi is changed whil e the timer is running, an expected operation may not be obtained. note 3: j = 3, 4 figure 8-3 8-bit event count er mode timing chart (tc4) 8.3.3 8-bit programmable divi der output (pdo) mode (tc3, 4) this mode is used to generate a pu lse with a 50% duty cycle from the pdoj pin. in the pdo mode, the up-counter counts up using the internal clock. when a match between the up-counter and the ttregj value is detected , the logic level output from the pdoj pin is switched to the opposite state and the up-counter is cleared. the inttcj interrupt request is generated at the time. the logic state opposite to the timer f/fj logic level is output from the pdoj pin. an arbitrary value can be set to the timer f/fj by tcjcr. upon reset, the timer f/fj value is initialized to 0. to use the programmable divider output, set the output latch of the i/o port to 1. note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configur ation in the programmable divider output mode, the new value programmed in ttregj is in effect immediately after programming. therefore, if ttregi is changed while the timer is running, an ex pected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr setting upon stopping of the timer. example: fixing the pdoj pin to the high level when the timercounter is stopped clr (tcjcr).3: stops the timer. clr (tcjcr).7: sets the pdoj pin to the high level. note 3: j = 3, 4 example :generating 160 hz pu lse using tc4 (fc = 2.5 mhz) setting port ld (ttreg4), 3dh : 1/160 1 0 2 n-1 n 0 1 2 0 n ? counter match detect counter clear n-1 n 2 0 1 match detect counter clear tc4cr ttreg4 inttc4 interrupt request tc4 pin input
page 64 8. 8-bit timercounter (tc3, tc4) 8.1 configuration TMP86P203PG figure 8-4 8-bit pdo mode timing chart (tc4) 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc4cr tc4cr ttreg4 timer f/f4 pdo 4 pin inttc4 interrupt request
page 65 TMP86P203PG 8.3.4 8-bit pulse wi dth modulation (pwm) output mode (tc3, 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up-counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/fj is switched to the opposite state again by the up-co unter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr, positive and negative pulses can be gen- erated. upon reset, the tim er f/fj is cleared to 0. (the logic level output from the pwmj pin is the opposite to the timer f/fj logic level.) since pwregj in the pwm mode is se rially connected to the shift regist er, the value set to pwregj can be changed while the timer is running. the value set to pwregj during a run of the timer is shifted by the inttcj interrupt request and loaded into pwregj. while the timer is stopped, the value is shifted immedi- ately after the programming of pwre gj. if executing the read instruction to pwregj during pwm output, the value in the shift register is read, but not the valu e set in pwregj. therefore, after writing to pwregj, the reading data of pwregj is previo us value until inttcj is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pw regj immediately after the inttcj interrupt request is generated (normally in the inttcj interrupt service r outine.) if the programming of pwregj and the inter- rupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next inttcj interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwmj pin holds the output status when the timer is stopped. to change the output status, program tcjcr after the timer is stopped. do not change the tcjcr upon stopping of the timer. example: fixing the pwmj pin to the high level when the timercounter is stopped clr (tcjcr).3: stops the timer. clr (tcjcr).7: sets the pwmj pin to the high level. note 3: to enter the stop mode during pwm output, stop the timer and then enter the stop mode. if the stop mode is entered without stopping the timer when fc or fc/2 is selected as the source clock, a pulse is output from the pwmj pin during the warm-up period time after exiting the stop mode. note 4: j = 3, 4 table 8-4 pwm output mode source clock resolution repeated cycle normal1, idle1 mode fc = 2.5 mhz fc = 2.5 mhz fc/2 11 [hz] 819
page 66 8. 8-bit timercounter (tc3, tc4) 8.1 configuration TMP86P203PG figure 8-5 8-bit pwm mo de timing chart (tc4) 1 0 n n+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter write to pwreg4 write to pwreg4 m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc4cr tc4cr pwreg4 timer f/f4 pwm 4 pin inttc4 interrupt request
page 67 TMP86P203PG 8.3.5 16-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. the timercounter 3 and 4 are cascad- able to form a 16-bit timer. when a match between the up-counter and the timer regi ster (ttreg3, ttreg4) valu e is detected after the timer is started by setting tc4cr to 1, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter continues counting. program the lower byte and upper byte in this order in the timer register. (programming only the uppe r or lower byte should not be attempted.) note 1: in the timer mode, fix tcjcr to 0. if not fixed, the pdoj , pwmj , and ppgj pins may output a pulse. note 2: in the timer mode, do not change the ttregj setting while the timer is running. si nce ttregj is not in the shift register configuration in the timer mode, the new value programmed in ttregj is in effect immediately after programming of ttregj. therefore, if ttreg j is changed while the time r is running, an expected operation may not be obtained. note 3: j = 3, 4 figure 8-6 16-bit timer m ode timing chart (tc3 and tc4) table 8-5 source clock for 16-bit timer mode source clock resolution maximum setting time normal1, idle1 mode fc = 2.5 mhz fc = 2.5 mhz fc/2 11 819 example :setting the timer mode with source clock fc/2 7 hz, and generating an interrupt 1.92 s later (fc = 2.5 mhz) ldw (ttreg3), 927ch : sets the timer register (1.92 s 10 2 3 mn-1 mn 0 1 mn-1 mn 2 0 1 2 0 n? m? internal source clock counter match detect counter clear match detect counter clear tc4cr ttreg3 (lower byte) inttc4 interrupt request ttreg4 (upper byte)
page 68 8. 8-bit timercounter (tc3, tc4) 8.1 configuration TMP86P203PG 8.3.6 16-bit event c ounter mode (tc3 and 4) 8.3.7 16-bit pulse width modulatio n (pwm) output mode (tc3 and 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 16 bits of resolution. the timercounter 3 and 4 are cascadable to form the 16-bit pwm signal generator. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again by the counter overflow, and the counter is cleared. the inttc4 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1 or idle1 mode. since the initial value can be set to the timer f/f4 by tc4cr, positive and negative pulses can be generated. upon reset, the timer f/f4 is cleared to 0. (the logic level output from the pwm 4 pin is the opposite to the timer f/f4 logic level.) since pwreg4 and 3 in the pwm mode are serially connected to the shift register, the values set to pwreg4 and 3 can be changed while the timer is runni ng. the values set to pwreg4 and 3 during a run of the timer are shifted by the inttcj interrupt request and loaded into pwreg4 and 3. while the timer is stopped, the values are shifted i mmediately after the programming of pwreg4 and 3. set the lower byte (pwreg3) and upper byte (pwreg3) in this order to program pwreg4 and 3. (programming only the lower or upper byte of the register should not be attempted.) if executing the read instruction to pwreg4 and 3 during pwm output, the values set in the shift register is read, but not the values set in pwreg4 and 3. therefore, after writing to the pwreg4 and 3, reading data of pwreg4 and 3 is previous value until inttc4 is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pwreg4 and 3 immediately after the inttc4 interrupt request is generated (normally in the inttc4 interrupt service routine.) if the programming of pwregj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next inttc4 interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwm 4 pin holds the output status when the timer is stopped. to change the output status, program tc4cr after the timer is stopped. do not program tc4cr upon stopping of the timer. example: fixing the pwm 4 pin to the high level when the timercounter is stopped clr (tc4cr).3: stops the timer. clr (tc4cr).7 : sets the pwm 4 pin to the high level. in the event counter mode, the up-counter counts up at the falling edge to the tc3 pin. the timercounter 3 and 4 are cascadable to fo rm a 16-bit event counter. when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected after the timer is started by setting tc4cr to 1, an inttc4 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter rest arts counting at the falling edge of the input pulse to the tc3 pin. two machine cycles are required for the low- or high-level pulse input to the tc3 pin. therefore, a maximum freque ncy to be supplied is fc/2 4 hz in the normal1 or idle1 mode. program the lower byte (ttreg3), and upper byte (ttreg4) in this order in the timer register. (programming only the upper or lower byte should not be attempted.) note 1: note 2: note 3: in the event counter mode, fix tcjcr to 0. if not fixed, the pdoj, pwmj and ppgj pins may output pulses. in the event counter mode, do not change the ttregj setti ng while the timer is running. since ttregj is not in the shift register configuration in the event counter mode, the new value programmed in ttregj is in effect imme- diately after the programming. therefore, if ttregj is changed while the timer is running, an expected operation may not be obtained. j = 3, 4
page 69 TMP86P203PG note 3: to enter the stop mode, stop the timer and then enter the stop mode. if the stop mode is entered with- out stopping of the timer when fc or fc/2 is select ed as the source clock, a pulse is output from the pwm 4 pin during the warm-up period time after exiting the stop mode. table 8-6 16-bit pwm output mode source clock resolution repeated cycle normal1, idle1 mode fc = 2.5 mhz fc = 2.5 mhz fc/2 11 819 example :generating a pulse with 6.4-ms high-lev el width and a period of 0.210 ms (fc = 2.5 mhz) setting ports ldw (pwreg3), 07d0h : sets the pulse width. ld (tc3cr), 33h : sets the operating clock to fc/2 3 , and 16-bit pwm output mode (lower byte). ld (tc4cr), 056h : sets tff4 to the initial value 0, and 16-bit pwm signal generation mode (upper byte). ld (tc4cr), 05eh : starts the timer.
page 70 8. 8-bit timercounter (tc3, tc4) 8.1 configuration TMP86P203PG figure 8-7 16-bit pwm m ode timing chart (tc3 and tc4) 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period write to pwreg3 write to pwreg4 write to pwreg4 write to pwreg3 match detect match detect an bm cp an m p tc4cr tc4cr pwreg3 (lower byte) timer f/f4 pwm 4 pin inttc4 interrupt request pwreg4 (upper byte)
page 71 TMP86P203PG 8.3.8 16-bit programmable pulse generate (ppg) ou tput mode (tc3 and 4) this mode is used to generate pulses with up to 16- bits of resolution. the timer counter 3 and 4 are cascad- able to enter the 16-bit ppg mode. the counter counts up using the inte rnal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4 ) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again when a match betw een the up-counter and th e timer register (ttreg3, ttreg4) value is detected, and the counter is cleared. the inttc4 interrupt is generated at this time. since the initial value can be set to the timer f/f4 by tc4cr, positive and negative pulses can be generated. upon reset, the timer f/f4 is cleared to 0. (the logic level output from the ppg 4 pin is the opposite to the timer f/f4.) set the lower byte and upper byte in this order to program the timer register. (ttreg3 ttreg4, pwreg3 pwreg4) (programming only the upper or lower byte should not be attempted.) for ppg output, set the output latch of the i/o port to 1. note 1: in the ppg mode, do not change the pwregi and ttregi settings while the timer is running. since pwregi and ttregi are not in the shift register c onfiguration in the ppg mode, the new values pro- grammed in pwregi and ttregi are in effect immediately after progra mming pwregi and ttregi. therefore, if pwregi and ttregi are changed whil e the timer is running, an expected operation may not be obtained. note 2: when the timer is stopped during ppg output, the ppg 4 pin holds the output status when the timer is stopped. to change the output status, program tc4cr after the timer is stopped. do not change tc4cr upon stopping of the timer. example: fixing the ppg 4 pin to the high level when the timercounter is stopped clr (tc4cr).3: stops the timer clr (tc4cr).7: sets the ppg 4 pin to the high level note 3: i = 3, 4 two machine cycles are required for the high- or low- level pulse input to the tc3 pin. therefore, a maxi- mum frequency to be supplied is fc/2 4 hz in the normal1 or idle1 mode. example :generating a pulse with 6.4-ms high-level width and a period of 104.86 ms (fc =2.5 mhz) setting ports ldw (pwreg3), 07d0h : sets the pulse width. ldw (ttreg3), 8002h : sets the cycle period. ld (tc3cr), 33h : sets the operating clock to fc/2 3 , and16-bit pwm mode (lower byte). ld (tc4cr), 057h : sets tff4 to the initial value 0, and 16-bit pwm mode (upper byte). ld (tc4cr), 05fh : starts the timer.
page 72 8. 8-bit timercounter (tc3, tc4) 8.1 configuration TMP86P203PG figure 8-8 16-bit ppg mode timing chart (tc3 and tc40) 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc4cr tc4cr pwreg3 (lower byte) timer f/f4 ppg 4 pin inttc4 interrupt request pwreg4 (upper byte) ttreg3 (lower byte) ttreg4 (upper byte)
page 73 TMP86P203PG 9. 8-bit ad converter (adc) the TMP86P203PG have a 8-bit successive approximation type ad converter. note: ad conversion characteristics are guaranteed with limited suppl y voltage range (4.5v to 5.5v). if supply voltage is less than 4. 5v then ad conversion accuracy can not be guaranteed. 9.1 configuration the circuit configuration of the 8-bit ad converter is shown in figure 9-1. it consists of control registers adccr1 and adccr2, converted value registers adcdr1 and adcdr2, a da converter, a sample-and-hold circuit, a comp arator, and a successive comparison circuit. figure 9-1 8-bit ad converter (adc) 3 4 8 8 ainds analog input multiplexer adrs r/2 r/2 r ack irefon ad conversion result register1,2 ad converter control register 1,2 adbf eocf intadc interrupt sain successive approximate circuit adccr2 adcdr1 adcdr2 adccr1 sample hold circuit y s en shift clock da converter reference voltage analog comparator control circuit vdd ain2 ain5 vss
page 74 9. 8-bit ad converter (adc) 9.1 configuration TMP86P203PG 9.2 control the ad converter consists of the following four registers: 1. ad converter control register 1 (adccr1) this register selects the analog channels in which to perform ad conversion and controls the ad con- verter as it starts operating. 2. ad converter control register 2 (adccr2) this register selects the ad conversion time and controls the connect ion of the da converter (ladder resistor network). 3. ad converted value register 1 (adcdr1) this register is used to store the digital value after being converted by the ad converter. 4. ad converted value register 2 (adcdr2) this register monitors the oper ating status of the ad converter. note 1: select analog input when ad converter stops (adcdr2 = ?0?). note 2: when the analog input is all use disabl ing, the adccr1 should be set to ?1?. note 3: during conversion, do not perform output instruction to ma intain a precision for all of the pins. and port near to analo g input, do not input intense signaling of change. note 4: the adrs is automatically cl eared to ?0? after starting conversion. note 5: do not set adccr1 newly again during ad conv ersion. before setting adccr1 newly again, check adcdr2 to see that the conversion is completed or wait until the interrupt signal (intadc) is generated (e.g., interrupt handling routine). note 6: after stop mode is started, ad converter control regi ster 1 (adccr1) is all initialized and no data can be written in th is register. therefore, to use ad converter again, set th e adccr1 newly after returning to normal1 or normal2 mode. note 7: although adccr1 is initialized to "reserved val ue" after reset, set the suitable analog input channel when using ad converter. note 8: always set bit 5 in adccr1 to ?1? and set bit 6 in adccr1 to ?0?. ad converter control register 1 adccr1 (000eh) 76543210 adrs "0" "1" ainds sain (initial value: 0001 0000) adrs ad conversion start 0: 1: ?
page 75 TMP86P203PG note 1: always set bit 0 in adccr2 to ?0? and set bit 4 in adccr2 to ?1?. note 2: when a read instruction for adccr2, bit 6 to 7 in adccr2 read in as undefined data. note 3: after stop mode is started, ad converter control regi ster 2 (adccr2) is all initialized and no data can be written in th is register. therefore, to use ad converter again, set th e adccr2 newly after returning to normal1 or normal2 mode. note 1: fc: high-frequency clock [hz] note 2: set conversion time by supply voltage(vdd) as follows. note 1: the adcdr2 is cleared to ?0? when reading the adcdr1. therefore, the ad conversion result should be read to adcdr2 more first than adcdr1. note 2: adcdr2 is set to ?1? when ad conversion starts and cleared to ?0? when the ad conversion is finished. it also is cleared upon entering stop mode. note 3: if a read instruction is executed for adcdr2, read data of bits 7, 6 and 3 to 0 are unstable. ad converter control register 2 adccr2 (000fh) 76543210 irefon ?1? ack ?0? (initial value: **0* 000*) irefon da converter (ladder resistor) connection control 0: 1: connected only during ad conversion always connected r/w ack ad conversion time select 000: 001: 010: 011: 100: 101: 110: 111: reserved reserved 78/fc 156/fc 312/fc reserved reserved reserved r/w table 9-1 ack setting and conversion time condition conversion time 2.5 mhz 2 mhz ack 000 reserved 001 reserved 010 78/fc 31.2
page 76 9. 8-bit ad converter (adc) 9.3 function TMP86P203PG 9.3 function 9.3.1 ad converter operation when adccr1 is set to "1", ad conversion of the voltage at the analog input pin specified by adccr1 is thereby started. after completion of the ad conversion, the conversion result is stored in ad converted value registers (adcdr1) and at the same time adcdr2 is set to ?1?, the ad conversion finished interrupt (intadc) is generated. adccr1 is automatically cleared after ad conversion has started. do not set adccr1 newly again (restart) during ad conversion. before setting adrs newly again, check adcdr to see that the conversion is completed or wait until the inte rrupt signal (intadc) is generated (e.g., interrupt han- dling routine). figure 9-2 ad c onverter operation 9.3.2 ad converter operation 1. set up the ad converter control register 1 (adccr1) as follows: ? choose the channel to ad convert using ad input channel select (sain). ? specify analog input enable fo r analog input control (ainds). 2. set up the ad converter control register 2 (adccr2) as follows: ? set the ad conversion time using ad conversion time (ack). for details on how to set the con- version time, refer to table 9-1. ? choose irefon for da converter control. 3. after setting up 1. and 2. above, set ad conversion start (adrs) of ad converter control register 1 (adccr1) to ?1?. 4. after an elapse of the specified ad conversion time, the ad converted value is stored in ad con- verted value register 1 (adcdr1) and the ad conv ersion finished flag (e ocf) of ad converted value register 2 (adcdr2) is set to ?1?, upon wh ich time ad conversion interrupt intadc is gener- ated. 5. eocf is cleared to ?0? by a read of the conversion result. however, if reconverted before a register read, although eocf is cl eared the previous conversi on result is retained until the next conversion is completed. a dcdr1 status eocf cleared by reading conversion result conversion result read conversion result read a dcdr2 intadc interrupt reading adcdr1 a dcdr2 a dccr1 1st conversion result 2nd conversion result indeterminate ad conversion start ad conversion start
page 77 TMP86P203PG 9.3.3 stop mode dur ing ad conversion when the stopmode is entered forcibly during ad co nversion, the ad convert operation is suspended and the ad converter is initialized (adccr1 and adccr2 are initialized to initial valu e.). also, the conversion result is indeterminate. (conversion results up to the pr evious operation are cleared, so be sure to read the con- version results before entering stopmode.) when restored from stopmode, ad conversion is not automati- cally restarted, so it is necessary to restart ad conv ersion. note that the da c onverter (ladder resistor) is automatically disconnect. example :after selecting the conversion time of 124.8 s at 2.5 mhz and the analog input channel ain3 pin, perform ad conversion once. after checking eocf, read the converted value and store the 8-bit data in address 009fh on ram. ; ain select : : : : ; before setting the ad converter register, set each port register suitably (for detail, see chapter of i/o port.) ld (adccr1), 00100011b ; select ain3 ld (adccr2), 11011000b ; select conversion time (312/fc) and operation mode : set (adccr1). 7 ; adrs = 1 (start ad conversion) sloop: test (adcdr2). 5 ; eocf = 1 ? jrs t, sloop : ld a, (adcdr1) ; read conversion result ld (9fh), a
page 78 9. 8-bit ad converter (adc) 9.3 function TMP86P203PG 9.3.4 analog input volt age and ad conversion result the analog input voltage is corresponded to the 8-bit digital value converted by the ad as shown in figure 9-3. figure 9-3 analog input voltage a nd ad conversion result (typ.) 10 01h 02h 03h fdh feh ffh 2 3 253 254 255 256 analog input voltage ad conversion result 256
page 79 TMP86P203PG 9.4 precautions about ad converter 9.4.1 analog input pin voltage range make sure the analog input pins (ain2 to ain5) are used at voltages within vss below vdd. if any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. the other analog input pins also are affected by that. 9.4.2 analog input shared pins the analog input pins (ain2 to ain5) are shared wi th input/output ports. when using any of the analog inputs to execute ad convers ion, do not execute in put/output instructions for all other ports. this is necessary to prevent the accuracy of ad conversi on from degrading. not only these analog input shared pins, some other pins may also be affected by noise arising from input/o utput to and from adjacent pins. 9.4.3 noise countermeasure the internal equivalent circuit of the analog input pins is shown in figure 9-4. the higher the output imped- ance of the analog input source, more easily they are su sceptible to noise. therefor e, make sure the output impedance of the signal source in your design is 5 k ? or less. toshiba also reco mmends attaching a capacitor external to the chip. figure 9-4 analog i nput equivalent circuit and ex ample of input pin processing da converter ain i analog comparator internal resistance a llowable signal source impedance internal capacitance 5 k ? ?
page 80 9. 8-bit ad converter (adc) 9.4 precautions about ad converter TMP86P203PG
page 81 TMP86P203PG 10. otp operation 10.1 operating mode the TMP86P203PG has mcu mode and prom mode. 10.1.1 mcu mode the mcu mode is set by fixing the test/vpp pin to the low level. (test/vpp pin cannot be used open because it has no built-in pull-down resistor). 10.1.1.1 program memory the TMP86P203PG has 2k bytes built-in one-time- prom (addresses f800 to ffffh in the mcu mode, addresses 0000 to 07ffh in the prom mode). figure 10-1 prog ram memory area note: the area that is not in use should be set data to ffh, or a general-purpose prom programmer should be set only in the program memory area to access. 10.1.1.2 data memory TMP86P203PG has a built-in 128 bytes data memory (static ram). 10.1.2 prom mode the prom mode is set by setting the reset pin, test pin and other pins as shown in table 10-1 and fig- ure 10-2. the programming and verification for the in ternal prom is acheived by using a general-purpose prom programmer with the adaptor socket. mcu mode program prom mode program 0000h 07ffh 0000h f800h ffffh don?t use ffffh (a) rom size = 2 kbytes
page 82 10. otp operation 10.1 operating mode TMP86P203PG note 1: the high-speed program mode can be used. the setti ng is different according to the type of prom pro- grammer to use, refer to each description of prom programmer. TMP86P203PG does not support the electric signatur e mode, apply the rom type of prom programmer to tc571000d/ad. always set the adapter socket switch to the "n" side when using toshiba?s adaptor socket. table 10-1 pin name in prom mode pin name (prom mode) i/o function pin name (mcu mode) a16 input program memory address input xout a15 to a8 input program memory address input p37 to p30 a7 to a0 input program memory address input p37 to p30 d7 to d0 input/output program memory data input/output p37 to p30 ce input chip enable signal input p00 oe input output enable signal input p20 pgm input program mode signal input p01 dids input prom mode control signal input p12 vpp power supply +12.75v/5v (power supply of program) test vcc power supply +6.25v/5v vdd gnd power supply 0v vss vcc input fix to "h" level in prom mode p11 reset input fix to "l" level in prom mode reset clk input input a clock from the outside xin
page 83 TMP86P203PG note 1: eprom adaptor socket (tc571000 ?
page 84 10. otp operation 10.1 operating mode TMP86P203PG 10.1.2.1 programming flowchart (high-speed program writing) figure 10-3 prog ramming flowchart the high-speed programming mode is set by applying vpp=12.75v (programming voltage) to the vpp pin when the vcc = 6.25 v. after th e address and data are fixed, the data in the address is written by applying 0.1[msec] of low level program pulse to pgm pin. then verify if the data is written. if the programmed data is incorrect, a nother 0.1[msec] pulse is applied to pgm pin. this programming procedure is repeated until correct data is r ead from the address (maximum of 25 times). subsequently, all data are programmed in all address. when all data were wr itten, verfy all address under the condition vcc=vpp=5v. v cc = 6.25 v yes no error verify n = 25? ok start v pp = 12.75 v address = start address n = 0 program 0.1 ms pulse n = n + 1 last address ? yes v cc = 5 v v pp = 5 v read all data ok address = address + 1 no pass fail error
page 85 TMP86P203PG 10.1.2.2 program writing using a general-purpose prom programmer (1) recommended otp adaptor bm11203 for TMP86P203PG (2) setting of otp adaptor set the switch (sw1) to "n" side. (3) setting of prom programmer a. set prom type to tc571000d/ad. vpp: 12.75 v (high-speed program writing mode) b. data transmission ( or copy) (note 1) the prom of TMP86P203PG is located on different address; it depends on operating mode: mcu mode and prom mode. when you write the data of rom for mask rom prod- ucts, the data shuold be transferred (or copied ) from the address for mcu mode to that for prom mode before writing operation is execute d. for the applicable program areas of mcu mode and prom mode are different, refer to TMP86P203PG" figure 10-1 program memory area ". example: in the block transfer (copy) mode, executed as below. 2kb rom capacity : 0f800~0ffffh 00000~007ffh c. setting of the program address (note 1) start address: 0000h end address: 07ffh (4) writting write and verify according to the above procedure "setting of prom programmer". (5) security bit the TMP86P203PG has a security bit in prom cell. if the security bit is programmed to 0, the content of the prom is disable to be read (ffh data) in prom mode. how to program the security bit the difference from the programmi ng procedures described in section 10.1.2.2 are follows. 1. setting otp adapter set the switch (sw1) to the "s" side. 2. setting prom programmer
page 86 10. otp operation 10.1 operating mode TMP86P203PG i )setting of programming address the security bit is in bit 0 of address 1101h. set the start address 1101h and the end address 1101h. set the data feh at the address 1101h. note 1: for the setting method, refer to each description of prom programmer. make sure to set the data of address area that is not in use to ffh. note 2: when setting mcu to the adaptor or when setting the adaptor to the prom programmer, set the first pin of the adaptor and that of prom pr ogrammer socket matched. if the first pin is con- versely set, mcu or adaptor or programmer would be damaged. note 3: the TMP86P203PG does not support the electric signature mode. if prom programmer uses the signature, t he device would be damaged because of applying voltage of 12
page 87 TMP86P203PG 11. input/output circuitry 11.1 control pins the input/output circuitries of the TMP86P203PG control pins are shown below. control pin i/o input/output circuitry remarks xin xout input output resonator connecting pins (high-frequency) r o = 0.5 k ? ? ? ?
r
page 88 11. input/output circuitry 11.2 input/output ports TMP86P203PG 11.2 input/output ports note: input staturs on pins set for input mode are read in into the internal circuit. therefore, when using the ports in a mixtu re of input and output modes, the contents of the output latches for t he ports that are set for input mode may be rewritten by exe- cution of bit manipulating instructions. port i/o input/output circuitry remarks p0 i/o sink open drain output or push-pull output hysteresis input high current output (nch) (programmable port option) r = 100 ? ? ? ? ? ?

initial "high-z" vdd r initial "high-z" disable vdd r data output pin input analog input initial "high-z" disable vdd r data output pin input initial "high-z" disable vdd r data output pin input
page 89 TMP86P203PG 12. electrical characteristics 12.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operat ion, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rati ng is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or explode resul ting in injury to the user. thus, when designing products which include this de vice, ensure that no absolute maximum rating value will ever be exceeded. (v ss = 0 v) parameter symbol pins ratings unit supply voltage v dd ? ? ? ? ? ? ? ?
page 90 12. electrical characteristics 12.1 absolute maximum ratings TMP86P203PG 12.2 operating condition the operating conditions show the conditions under which the device be used in orde r for it to operate normally while maintaining its quality. if the device is used outsid e the range of operating conditions (power supply voltage, operating temperature range, or ac/dc rated values), it may operate erratically. therefore, when designing your application equipment, always make sure its intended working conditio ns will not exceed th e range of operating conditions. note: ad conversion characteristics are guaranteed with limited supply voltage range (4.5 v to 5.5 v). if supply voltage is less than 4.5 v then ad conversion accuracy can not be guaranteed. (v ss = 0 v, topr = ?
page 91 TMP86P203PG 12.3 dc characteristics note 1: typical values show those at topr = 25 ? ? ? ?
page 92 12. electrical characteristics 12.5 ac characteristics TMP86P203PG 12.5 ac characteristics 12.6 recommended osc illation conditions figure 12-1 oscillation frequency (f c) vs rx (vdd = 5.0 v, ta = 25 ? rc oscillation xin xout r x c xin rx [k ] fc [mhz] 0 20 40 60 80 100 120 0.0 0.5 1.0 1.5 2.0 2.5 3.0 c xin = 33 pf c xin = 100 pf
page 93 TMP86P203PG figure 12-2 oscillat ion frequency (fc) vs vdd (c = 33 pf, ta = 25
page 94 12. electrical characteristics 12.6 recommended oscillation conditions TMP86P203PG 12.7 dc characteristics, ac characteristi cs (prom mode) 12.7.1 read operat ion in prom mode note: tcyc = 250 ns, f clk = 16 mhz note:dids and p37 to p30 are the signals for the TMP86P203PG. all other signals are eprom programmable. al: address input (a0 to a7) ah: address input (a8 to a15) (v ss = 0 v, topr = ?

page 95 TMP86P203PG 12.7.2 program operation (high-speed) (topr = 25
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page 96 12. electrical characteristics 12.6 recommended oscillation conditions TMP86P203PG 12.8 handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-37pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming 95 % - when using the device (oscillator) in places exposed to high electric fields such as cathode-ray tubes, we recommend electrically shielding the package in order to maintain normal operating condition.
page 97 TMP86P203PG 13. package dimensions 6.401 0.203 0.305 3.302 1.651 0.381 0.457 0.102 0.076 26.797 max 5.344max 10.922max 26.162 0.127 1.524 0.127 3.302 0.127 0.254 0.051 1.651 typ 2.54 7.62 m 0.254 0~17 11 0 20 11 0.381 min unit: mm dip20-p-300-2.54a rev 01
page 98 13. package dimensions TMP86P203PG
this is a technical document that de scribes the operating functi ons and electrical specif ications of the 8-bit microcontroller series tlcs-870/c (lsi). toshiba provides a variety of development tools a nd basic software to enable efficient software development. these development tools have specifi cations that support advances in microcomputer hardware (lsi) and can be used extensively. both the hardware and so ftware are supported continuous ly with version updates. the recent advances in cmos lsi production technology have be en phenomenal and microcomputer systems for lsi design are constant ly being improved. the products described in this document may also be revised in the future. be sure to check the latest specific ations before using. toshiba is developing highly integrated, high-perfo rmance microcomputers using advanced mos production technology and especially well proven cmos technology. we are prepared to meet the requests for custom packaging for a variet y of application areas. we are confident that our products can satisfy your application needs now and in the future.

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