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this is preliminary information on a new product foreseen to be developed. details are subject to change without notice. october 2014 docid027083 rev 1 1/37 lps22hb mems nano pressure sensor: 260-1260 hpa absolute digital output barometer datasheet - target specification features ? 260 to 1260 hpa absolute pressure range ? current consumption down to 4 a ? high overpressure capability: 20x full scale ? embedded temperature compensation ? 24-bit pressure data output ? 16-bit temperature data output ? odr from 1 hz to 75 hz ? spi and i2c interfaces ? embedded fifo ? interrupt functions: data ready, fifo flags, pressure thresholds ? supply voltage: 1.7 to 3.6 v ? high shock survivability: 22,000 g ? small and thin package ? ecopack ? lead-free compliant applications ? altimeter and barometer for portable devices ? gps applications ? weather station equipment ? sport watches description the lps22hb is an ultra-compact piezoresistive absolute pressure sensor which functions as a digital output barometer. the device comprises a sensing element and an ic interface which communicates through i 2 c or spi from the sensing element to the application. the sensing element, which detects absolute pressure, consists of a suspended membrane manufactured using a dedicated process developed by st. the lps22hb is available in a full-mold, holed lga package (hlga). it is guaranteed to operate over a temperature range extending from -40 c to +85 c. the package is holed to allow external pressure to reach the sensing element. hlga 10l 2.0 x 2.0 x 0.76 mm table 1. device summary order codes temperature range [c] package packing LPS22HBTR -40 to +85c hlga-10l tape and reel lps22hb hlga-10l tray www.st.com
contents lps22hb 2/37 docid027083 rev 1 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3.2 i 2 c - inter-ic control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0.1 bypass mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0.2 fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0.3 stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0.4 stream-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0.5 bypass-to-stream mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.0.6 bypass-to-fifo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.0.7 retrieving data from fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 i 2 c serial interface (cs = high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2.1 i 2 c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
docid027083 rev 1 3/37 lps22hb contents 37 6.3.3 spi read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.1 interrupt_cfg (0bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2 ths_p_l (0ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.3 ths_p_h (0dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.4 who_am_i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.5 ctrl_reg1 (10h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.6 ctrl_reg2 (11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.7 ctrl_reg3 (12h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.8 fifo_ctrl (14h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.9 ref_p_xl (15h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.10 ref_p_l (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.11 ref_p_h (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.12 rpds_l (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.13 rpds_h (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.14 res_conf (1ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.15 int_source (25h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.16 fifo_status (26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.17 status (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.18 press_out_xl (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.19 press_out_l (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.20 press_out_h (2ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.21 temp_out_l (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.22 temp_out_h (2ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
list of tables lps22hb 4/37 docid027083 rev 1 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. pressure and temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. i 2 c slave timing values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 8. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 9. i 2 c terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 10. sad+read/write patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 11. transfer when master is writing one byte to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12. transfer when master is writing multiple bytes to slave . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 13. transfer when master is receiving (reading) one byte of data from slave . . . . . . . . . . . . . 19 table 14. transfer when master is receiving (reading) multiple bytes of data from slave . . . . . . . . . 19 table 15. registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 16. output data rate bit configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 17. low-pass filter configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18. interrupt configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 19. fifo mode selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 20. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
docid027083 rev 1 5/37 lps22hb list of figures 37 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connections (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. spi slave timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. i 2 c slave timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 5. lps22hb electrical connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 7. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8. multiple byte spi read protocol (2-byte example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. multiple byte spi write protocol (2-byte example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. spi read protocol in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. hlga - 10l (2.0 x 2.0 x 0.76 mm typ.) outline and mechanical data . . . . . . . . . . . . . . . . . 35
block diagram and pin description lps22hb 6/37 docid027083 rev 1 1 block diagram and pin description figure 1. block diagram figure 2. pin connections (bottom view) p i 2 c spi sensing element temperature sensor sensor bias voltage and current bias clock and timing quadratic temperature compensation adc + digital filter low noise analog front end mux 32 samples fifo filter (32 samples average) dsp for temperature compensation 12 3 5 4 10 8 9 76 vdd_io scl/spc res sda/sdi/sdo sdo/sa0 vdd gnd gnd int_drdy cs
docid027083 rev 1 7/37 lps22hb block diagram and pin description 37 table 2. pin description pin number name function 1 vdd_io power supply for i/o pins 2 scl spc i 2 c serial clock (scl) spi serial port clock (spc) 3 reserved connect to gnd 4 sda sdi sdi/sdo i 2 c serial data (sda) 4-wire spi serial data input (sdi) 3-wire serial data input/output (sdi/sdo) 5 sdo sa0 4-wire spi serial data output (sdo) i 2 c less significant bit of the device address (sa0) 6cs spi enable i 2 c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) 7 int_drdy interrupt or data ready 8 gnd 0 v supply 9 gnd 0 v supply 10 vdd power supply
mechanical and electrical specifications lps22hb 8/37 docid027083 rev 1 2 mechanical and electrical specifications 2.1 mechanical characteristics vdd = 1.8 v, t = 25 c, unless otherwise noted. table 3. pressure and temperature sensor characteristics symbol parameter test condition min. typ. (1) max. unit pressure sensor characteristics pt op operating temperature range -40 +85 c pt full full accuracy temperature range 0 +65 c p op operating pressure range 260 1260 hpa p bits pressure output data 24 bits p sens pressure sensitivity 4096 lsb/ hpa p accrel relative accuracy over pressure (2) p = 800 - 1100 hpa t = 25 c 0.1 hpa p acct absolute accuracy over temperature p op t = 0 to 65 c after opc (3) 0.1 hpa p op t = 0 to 65 c no opc (3) 1 p noise rms pressure sensing noise (4) without embedded filtering 0.01 hpa rms odr pres pressure output data rate (5) 1 10 25 50 75 hz temperature sensor characteristics t op operating temperature range -40 +85 c t sens temperature sensitivity 100 lsb/c t acc temperature absolute accuracy t = 0 to 65 c 1.5 c odr t output temperature data rate (5) 1 10 25 50 75 hz 1. typical specifications are not guaranteed. 2. parameter not tested at final test 3. opc: one point calibration, see registers rpds_l/h (18h,19h). 4. pressure noise rms evaluated in a controlled environment, based on the average standard deviation of 32 measurements at highest odr. 5. output data rate is configured acting on odr[2:0] in ctrl_reg1 (10h)
docid027083 rev 1 9/37 lps22hb mechanical and electrical specifications 37 2.2 electrical characteristics vdd = 1.8 v, t = 25 c, unless otherwise noted. table 4. electrical characteristics symbol parameter test condition min. typ. (1) max. unit vdd supply voltage 1.7 3.6 v vdd_io io supply voltage 1.7 vdd+0.1 v idd supply current @ odr 1 hz lc_en bit = 0 15 a @ odr 1 hz lc_en bit = 1 4 iddpdn supply current in power-down mode 1 a 1. typical specifications are not guaranteed.
mechanical and electrical specifications lps22hb 10/37 docid027083 rev 1 2.3 communication interface characteristics 2.3.1 spi - serial peripheral interface subject to general operating conditions for vdd and t op . figure 3. spi slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. table 5. spi slave timing values symbol parameter va l u e (1) 1. values are guaranteed at 10 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production. unit min max t c(spc) spi clock cycle 100 ns f c(spc) spi clock frequency 10 mhz t su(cs) cs setup time 6 ns t h(cs) cs hold time 8 t su(si) sdi input setup time 5 t h(si) sdi input hold time 15 t v(so) sdo valid output time 50 t h(so) sdo output hold time 9 t dis(so) sdo output disable time 50
docid027083 rev 1 11/37 lps22hb mechanical and electrical specifications 37 2.3.2 i 2 c - inter-ic control interface subject to general operating conditions for vdd and t op . figure 4. i 2 c slave timing diagram note: measurement points are done at 0.2vdd_io and 0.8vdd_io, for both ports. table 6. i 2 c slave timing values symbol parameter (1) i2c standard mode (1) i2c fast mode (1) unit min max min max f (scl) scl clock frequency 0 100 0 400 khz t w(scll) scl clock low time 4.7 1.3 s t w(sclh) scl clock high time 4.0 0.6 t su(sda) sda setup time 250 100 ns t h(sda) sda data hold time 0.01 3.45 0 0.9 s t r(sda) t r(scl) sda and scl rise time 1000 20 + 0.1c b (2) 300 ns t f(sda) t f(scl) sda and scl fall time 300 20 + 0.1c b (2) 300 t h(st) start condition hold time 4 0.6 s t su(sr) repeated start condition setup time 4.7 0.6 t su(sp) stop condition setup time 4 0.6 t w(sp:sr) bus free time between stop and start condition 4.7 1.3 1. data based on standard i 2 c protocol requirement, not tested in production. 2. c b = total capacitance of one bus line, in pf. sda scl t f(sda) t su(sp) t w(scll) t su(sda) t r(sda) t su(sr) t h(st) t w(sclh) t h(sda) t r(scl) t f(scl) t w(sp:sr) start repeated start stop start
mechanical and electrical specifications lps22hb 12/37 docid027083 rev 1 2.4 absolute maximum ratings stress above those listed as ?absolute maxi mum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: supply voltage on any pin should never exceed 4.8 v. table 7. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage -0.3 to 4.8 v vdd_io i/o pins supply voltage -0.3 to 4.8 v vin input voltage on any control pin -0.3 to vdd_io +0.3 v p overpressure 2 mpa t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 2 (hbm) kv this device is sensitive to mechanical shock, improper handling can cause permanent damage to the part. this device is sensitive to electrostatic discharge (esd), improper handling can cause permanent damage to the part.
docid027083 rev 1 13/37 lps22hb functionality 37 3 functionality the lps22hb is a high reso lution, digital output pressure sensor packaged in an hlga full- mold package. the complete de vice includes a sensing element based on a piezoresistive wheatstone bridge approach, and an ic interface which communicates a digital signal from the sensing element to the application. 3.1 sensing element an st proprietary process is used to obtain a silicon membrane for mems pressure sensors. when pressure is applied, the membrane deflection induces an imbalance in the wheatstone bridge piezoresistances whose output signal is converted by the ic interface. intrinsic mechanical stoppers prevent breakage in case of excessive pressure, ensuring measurement repeatability. 3.2 i 2 c interface the complete measurement chain is composed of a low-noise amplifier which converts the resistance unbalance of the mems sensors (p ressure and temperature) into an analog voltage using an analog-to-digital converter. the pressure and temperature data may be ac cessed through an i2c/spi interface thus making the device particularly suitable fo r direct interfacing with a microcontroller. the lps22hb features a data-ready signal whic h indicates when a new set of measured pressure and temperature data are available, th us simplifying data synchronization in the digital system that uses the device. 3.3 factory calibration the ic interface is factory calibrated at three te mperatures and two pressures for sensitivity and accuracy. the trimming values are stored inside the device in a non-volatile structure. when the device is turned on, the trimming paramete rs are downloaded into the registers to be employed during normal operation which allows the device to be used without requiring any further calibration.
fifo lps22hb 14/37 docid027083 rev 1 4 fifo the lps22hb embeds 32-slot data fifo to store the pressure and temperature output values. the fifo allows consistent power saving for the system, since the host processor does not need to continuously poll data from the sensor, but it can wake up only when needed and burst the significant data out from the fifo. this buffer can work according to six different modes: bypass mode, fifo mode, stream mode, stream-to-fifo mode, bypass-to-stream mode and bypass-to-fifo mode. the fifo buffer is enabled when the fifo_en bit in ctrl_reg2 (11h) is set to ?1? and each mode is selected by the fifo_mode[2:0] bits in fifo_ctrl (14h) . fifo threshold status, fifo overrun events and the number of unread samples stored are available in the fifo_status (26h) register and can be set to generate dedicated interrupts on the int_drdy pin using the ctrl_reg3 (12h) register. 4.0.1 bypass mode in bypass mode (f_mode[2:0] in fifo_ctrl (14h) set to ?000?), the fifo is not operational and it remains empty. 4.0.2 fifo mode in fifo mode (f_mode[2:0] in fifo_ctrl (14h) set to ?001?), the data from press_out_h (2ah) , press_out_l (29h) and press_out_xl (28h) and temp_out_h (2ch) and temp_out_l (2bh) are stored in the fifo. a watermark interrupt can be enabled (s top_on_fth bi t set to ?1? in ctrl_reg2 (11h) ) in order to be raised when the fifo is filled to the level specified by the wtm[4:0] bits of fifo_ctrl (14h) . the fifo continues filling until it is full (32 slots of data for pressure and temperature output). when full, the fifo stops collecting data. 4.0.3 stream mode in stream mode (f_mode[2:0] in fifo_ctrl (14h) set to ?010?), the data from press_out_h (2ah) , press_out_l (29h) and press_out_xl (28h) and temp_out_h (2ch) and temp_out_l (2bh) are stored in the fifo. the fifo continues filling until it?s full (32 slots of data for pressure and temperature output). when full, the fifo discards the older data as the new arrive. a watermark interrupt can be enabled and set as in fifo mode. 4.0.4 stream-to-fifo mode in stream-to-fifo mode (f_mode[2:0] in fifo_ctrl (14h) set to ?011?), the data from press_out_h (2ah) , press_out_l (29h) and press_out_xl (28h) and temp_out_h (2ch) and temp_out_l (2bh) are stored in the fifo. a watermark interrupt can be enabled (s top_on_fth bi t set to ?1? in ctrl_reg2 (11h) ) in order to be raised when the fifo is filled to the level specified by the wtm[4:0] bits of fifo_ctrl (14h) .the fifo continues filling until it?s full (32 slot s of data for pressure and temperature output). when full, the fifo discards the older data as the new arrive. once a trigger event occurs, the fifo starts operating in fifo mode. a trigger event can be configured in interrupt_cfg (0bh) .
docid027083 rev 1 15/37 lps22hb fifo 37 4.0.5 bypass-to-stream mode in bypass-to-stream mode (f_mode[2:0] in fifo_ctrl (14h) set to ?100?), the fifo is in bypass mode until a trigger event occurs and the fifo starts operating in stream mode. a trigger event can be configured in interrupt_cfg (0bh) . 4.0.6 bypass-to-fifo mode in bypass-to-fifo (f_mode[2:0] in fifo_ctrl (14h) set to ?001?), the fifo is in bypass mode until a trigger event occurs and the fifo starts operating in fifo mode. a trigger event can be configured in interrupt_cfg (0bh) . 4.0.7 retrieving data from fifo when the fifo is enabled, fifo data are read from press_out_h (2ah) , press_out_l (29h) , press_out_xl (28h) , temp_out_h (2ch) and temp_out_l (2bh) registers. each time data is read from the fifo, the oldest data are placed in the press_out_h (2ah) , press_out_l (29h) , press_out_xl (28h) , temp_out_h (2ch) and temp_out_l (2bh) registers and both single-read and read-burst operations can be used. the reading address is automatically updated by the device and it rolls back to 28h when register 2ch is reached. in order to read all fifo levels in a multiple byte reading, 160 bytes (5 output registers by 32 levels) must be read.
application hints lps22hb 16/37 docid027083 rev 1 5 application hints figure 5. lps22hb electrical connections (top view) power supply decoupling capacitors c 1 ( 1 0 0 n f) and c 2 (4.7 f) should be placed as near as possible to the supply pad of the de vice (common design practice). the functionality of the device and the measured data outputs are selectable and accessible through the i2c/spi interface. when using the i 2 c, cs must be tied to vdd_io. all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 5 ). it is possible to remove vdd while maintaining vdd_io without blocking the communication bus, in this condition the measurement chain is powered off. 5.1 soldering information the hlga package is compliant with the ecopack ? standard and it is qualified for soldering heat resistance according to jedec j-std-020. 10 c2 gnd 8 9 35 4 7 6 1 2 vdd_io scl/spc sda/sdi/sdo sdo/sa0 vdd gnd int_drdy cs gnd c1 gnd
docid027083 rev 1 17/37 lps22hb digital interfaces 37 6 digital interfaces 6.1 i 2 c serial interface the registers embedded in the lps22hb may be accessed through both the i2c and spi serial interfaces. the latter may be sw config ured to operate either in 3-wire or 4-wire interface mode. the serial interfaces are mapped onto the same pads. to select/exploit the i2c interface, the cs line must be tied high (i.e. connected to vdd_io). 6.2 i 2 c serial interface (cs = high) the lps22hb i2c is a bus slave. the i2c is em ployed to write data into registers whose content can also be read back. the relevant i2c terminology is given in table 9. there are two signals associated with the i2c bus: the serial clock line (scl) and the serial data line (sda). the latter is a bi-directional line used for sending and receiving the data to/from the interface. both lines have to be connected to vdd_io through pull-up resistors. the i2c interface is compliant with fast mode (4 00 khz) i2c standards as well as with the normal mode. table 8. serial interface pin description pin name pin description cs spi enable i2c/spi mode selection (1: spi idle mode / i 2 c communication enabled; 0: spi communication mode / i 2 c disabled) scl/spc i2c serial clock (scl) spi serial port clock (spc) sda sdi sdi/sdo i2c serial data (sda) 4-wire spi serial data input (sdi) 3-wire serial data input /output (sdi/sdo) sdo sao spi serial data output (sdo) i2c less significant bit of the device address (sa0) table 9. i 2 c terminology term description transmitter the device which sends data to the bus receiver the device which receives data from the bus master the device which initiates a transfer, generates clock signals and terminates a transfer slave the device addressed by the master
digital interfaces lps22hb 18/37 docid027083 rev 1 6.2.1 i 2 c operation the transaction on the bus is started through a start (st) signal. a start condition is defined as a high-to-low transition on the data line while the scl line is held high. after this has been transmitted by the master, the bus is considered busy. the next data byte transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave. when an address is sent, each device in the system compares the first seven bits after a start condition with its address. if they match, the device considers itself addressed by the master. the slave address (sad) associated to the lps22hb is 101110xb. the sdo / sa0 pad can be used to modify the less sign ificant bit of the device addres s. if the sa0 pad is connected to voltage supply, lsb is ?1? (address 1011101b), otherwise if the sa0 pad is connected to ground, the lsb value is ?0? (address 1011100b). this solution permits to connect and address two different lps22hb devi ces to the same i2c lines. data transfer with acknowledge is mandatory. the transmitter must release the sda line during the acknowledge pulse. the receiver must then pull the data line low so that it remains stable low during the high period of the acknowledge clock pulse. a receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. the i 2 c embedded inside the asic behaves like a slave device and the following protocol must be adhered to. after the start condition (st) a slave address is sent, once a slave acknowledge has been returned (sak), an 8-bit sub-address will be transmitted (sub): the 7 lsb represent the actual register address while the msb has no meaning. the if_add_inc bit in ctrl2 register (11h) enables sub-address auto increment (if_add_inc is '1' by default), so if if_add_inc = '1' the sub (sub-address) will be automatically increased to allow multiple data read/write. the slave address is completed with a read/write bit. if the bit is ?1? (read), a repeated start (sr) condition must be issued after the two sub-address bytes; if the bit is ?0? (write) the master will transmit to the sl ave with direction unchanged. table 10 explains how the sad+read/write bit pattern is composed, listing all the possible configurations. table 10. sad+read/write patterns command sad[6:1] sad[0] = sa0 r/w sad+r/w read 101110 0 1 10111001 (b9h) write 101110 0 0 10111000 (b8h) read 101110 1 1 10111011 (bbh) w r i t e 1 0 111 0 1 0 1 0 111 0 1 0 ( b a h ) table 11. transfer when master is writing one byte to slave master st sad + w sub data sp slave sak sak sak
docid027083 rev 1 19/37 lps22hb digital interfaces 37 data are transmitted in byte fo rmat (data). each data transfer contains 8 bits. the number of bytes transferred per transfer is unlimited. da ta is transferred with the most significant bit (msb) first. if a receiver can?t receive another complete byte of data until it has performed some other functions, it can hold the clock line, scl low to force the transmitter into a wait state. data transfer only continues when the receiver is ready for another byte and releases the data line. if a slave receiver does not ack nowledge the slave address (i.e. it is not able to receive because it is performing some real-time function) the data line must be kept high by the slave. the master can then abort the transf er. a low-to-high transition on the sda line while the scl line is high is defined as a stop condition. each data transfer must be terminated by the generation of a stop (sp) condition. in order to read multiple bytes incrementing the register address, it is necessary to assert the most significant bit of the sub-address fiel d. in other words, sub(7) must be equal to 1 while sub(6-0) represents the addres s of the first register to be read. in the presented communication format mak is master acknowledge and nmak is no master acknowledge. 6.3 spi bus interface the lps22hb spi is a bus slave. the spi allows writing to and reading from the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . table 12. transfer when master is writing multiple bytes to slave master st sad + w sub data data sp slave sak sak sak sak table 13. transfer when master is receiving (reading) one byte of data from slave master st sad + w sub sr sad + r nmak sp slave sak sak sak data table 14. transfer when master is receiving (reading) multiple bytes of data from slave master st sad+w sub sr sad+r mak mak nmak sp slave sak sak sak data data data
digital interfaces lps22hb 20/37 docid027083 rev 1 figure 6. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and returns to high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in the case of multiple read/writ e bytes. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge of cs while the last bit (bit 15, bit 23,...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is writte n into the device. when 1, the data do(7:0) from the device is read. in the la tter case, the chip will drive sdo at the start of bit 8. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). in multiple read/write commands further blocks of 8 clock periods are added. when the if_add_inc bit is 0, the address used to read/write data remains the same for every block. when the if_add_inc bit is 1, the addres s used to read/write da ta is incremented at every block. the function and the behavior of sdi and sdo remain unchanged. 6.3.1 spi read figure 7. spi read protocol the spi read command is performed with 16 clock pulses. the multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 ad6 cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ad6
docid027083 rev 1 21/37 lps22hb digital interfaces 37 bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). bit 16-... : data do(...-8). further data in multiple byte reads . figure 8. multiple byte spi read protocol (2-byte example) 6.3.2 spi write figure 9. spi write protocol the spi write command is performed with 16 cl ock pulses. the multiple byte write command is performed by adding blocks of 8 clock pulses to the previous one. bit 0 : write bit. the value is 0. bit 1-7 : address ad(6:0). this is the ad dress field of the indexed register. bit 8-15 : data di(7:0) (write mode). this is the data that is written in the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writes. figure 10. multiple byte spi write protocol (2-byte example) cs spc sdi sdo cs spc sdi rw di7di6di5di4di3di2di1di0 ad5 ad4 ad3 ad2 ad1 ad0 ad6 cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ad6
digital interfaces lps22hb 22/37 docid027083 rev 1 6.3.3 spi read in 3-wire mode a 3-wire mode is entered by setting bit sim to ?1? (spi serial interface mode selection) in ctrl_reg1. figure 11. spi read protocol in 3-wire mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1-7 : address ad(6:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the data that is read from the device (msb first). a multiple read command is also available in 3-wire mode. cs spc sdi/o rw do7do6do5do4do3do2do1do0 ad5 ad4 ad3 ad2 ad1 ad0 ms ad6
docid027083 rev 1 23/37 lps22hb register mapping 37 7 register mapping table 15 provides a quick overvi ew of the 8-bit registers embedded in the device. registers marked as reserved must not be changed. writing to those registers may cause permanent damage to the device. table 15. registers address map name type register address default function and comment hex binary reserved 00 - 0a - reserved interrupt_cfg r/w 0b 00000000 ths_p_l r/w 0c 00000000 ths_p_h r/w 0d 00000000 reserved 0e - reserved who_am_i r 0f 10110001 who am i ctrl_reg1 r/w 10 00000000 ctrl_reg2 r/w 11 00010000 ctrl_reg3 r/w 12 00000000 interrupt control reserved 13 - reserved fifo_ctrl r/w 14 00000000 ref_p_xl r/w 15 00000000 ref_p_l r/w 16 00000000 ref_p_h r/w 17 00000000 rpds_l r/w 18 00000000 rpds_h r/w 19 00000000 res_conf r/w 1a 00000000 reserved 1b - 24 - reserved int_source r 25 - fifo_status r 26 - status r 27 - press_out_xl r 28 - press_out_l r29 - press_out_h r2a - temp_out_l r 2b - temp_out_h r 2c -
register mapping lps22hb 24/37 docid027083 rev 1 to guarantee the proper behavior of the device, all register addresses not listed in the above table must not be accessed and the content stored in those registers must not be changed. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up.
docid027083 rev 1 25/37 lps22hb register description 37 8 register description the device contains a set of re gisters which are used to control its behavior and to retrieve pressure and temperature data. the register address, made up of 7 bits, is used to identify them and to read/write the data through the se rial interface. 8.1 interrupt_cfg (0bh) interrupt configuration autorifp , when written to ?1?, an internal register is set with current pressure values and the bit is forced to ?0?. when the bit is enabled, the content of the internal register is subtracted from the pressure output value and result is used for the interrupt generation. the output registers ( press_out_h (2ah) , press_out_l (29h) and press_out_xl (28h) ) are updated with the actual pressure value. the reset_arp bit is used to disable the autorifp function. reset_arp is self- cleared. autozero , when set to ?1?, the actual pressure output value is copied in ref_p_h (17h) , ref_p_l (16h) and ref_p_xl (15h) . when this bit is enabled, the register content of ref_p is subtracted from the pressure output value. to disable autozero, the ref_p registers have to be cleared. 76543210 autorifp reset_arp autozero reset_az diff_en lir ple phe autorifp autorifp: autorifp enable. default value: 0. (0: normal mode; 1: autorifp enabled) reset_arp reset autorifp function. default value: 0. (0: normal mode; 1: reset autorifp function) autozero autozero enable. default value: 0. (0: normal mode; 1: autozero enabled) reset_az reset autozero function. default value: 0. (0: normal mode; 1: reset autozero function) diff_en interrupt generation enable. default value: 0 (0: interrupt generation disabled; 1: interrupt generation enabled) lir latch interrupt request to the int_so urce register. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) ple enable interrupt generation on differential pressure low event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured differential pressure value lower than preset threshold) phe enable interrupt generation on differential pressure high event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured differential pressure value higher than preset threshold)
register description lps22hb 26/37 docid027083 rev 1 the reset_az bit is used to reset the autozero function. resetting ref_p_h (17h) , ref_p_l (16h) and ref_p_xl (15h) sets the pressure reference registers rpds_h (19h) and rpds_l (18h) to the default values. reset_az is self-cleared. the diff_en bit is used to enable the computing of differential pressure output. it is recommended to enable diff_en after the configuration of ref_p_h (17h) , ref_p_l (16h) , ref_p_xl (15h) , ths_p_h (0dh) and ths_p_l (0ch) . 8.2 ths_p_l (0ch) least significant bits of the threshold value for pressure interrupt generation. the threshold value for pressure interrupt generation is a 16-bit register composed of ths_p_h (0dh) and ths_p_l (0ch) . the value is expressed as unsigned number: interrupt threshold(hpa) = (ths_p)/16. 8.3 ths_p_h (0dh) most significant bits of the threshold value for pressure interrupt generation. 8.4 who_am_i device who am i 8.5 ctrl_reg1 (10h) control register 1 76543210 ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 ths[7:0] this register contains the low part of threshold value for pressure interrupt genera- tion. 76543210 ths15 ths14 ths13 ths12 ths11 ths10 ths9 ths8 ths[15:8] this register contains the high part of threshold value for pressure interrupt genera- tion. refer to ths_p_l (0ch) . 76543210 10110001 76543210 0 (1) odr2 odr1 odr0 en_lpfp lpf_cfg bdu sim 1. this bit must be set to ?0? for proper operation of the device
docid027083 rev 1 27/37 lps22hb register description 37 when odr[2,0] are set to ?000? the device enables one-shot mode. when the one_shot bit in ctrl_reg2 (11h) is set to ?1?, a new set of data for pressure and temperature is acquired. the bdu bit is used to inhibit the update of the output registers b etween the reading of upper and lower register parts. in default mode (bdu = ?0?), the lower and upper register parts are updated continuously. when the bdu is activated (bdu = ?1?), the content of the output registers is not updated until both msb and lsb are read, avoiding the reading of values related to different samples. odr [2:0] output data rate selection. default value: 000 refer to table 16 . en_lpfp enable low-pass filter on pressure data. default value: 0 (0: low-pass filter disabled; 1: low-pass filter enabled) lpf_cfg lpf_cfg: low-pass configuration register. default value:0 refer to table 17 . bdu block data update. default value: 0 (0: continuous update; 1: output registers not updated until msb and lsb have been read) sim spi serial interface mode selection.default value: 0 (0: 4-wire interface; 1: 3-wire interface) table 16. output data rate bit configurations odr2 odr1 odr0 pressure (hz) temperature (hz) 000 one shot mode enabled 001 1 hz 1 hz 0 1 0 10 hz 10 hz 011 25 hz 25 hz 100 50 hz 50 hz 1 0 1 75 hz 75 hz table 17. low-pass filter configurations lpf_cfg filter cutoff 0 odr/9 1 odr/20
register description lps22hb 28/37 docid027083 rev 1 8.6 ctrl_reg2 (11h) control register 2 the boot bit is used to refresh the content of the internal registers stored in the flash memory block. at device power-up the content of the flash memory block is transferred to the internal registers related to the trimming functions to allow correct behavior of the device itself. if for any reason the content of the trimming registers is modified, it is sufficient to use this bit to restore the correct values. when the boot bit is set to ?1?, the content of the internal flash is copied inside the correspondin g internal registers and is used to calibrate the device. these values are factory trimmed and they are diff erent for every device. they allow correct behavior of the device and normally they should not be changed. at the end of the boot process the boot bit is set again to ?0? by hardware. the boot bit takes effect after one odr clock cycle. swreset is the software reset bit. the device is reset to the power-on configuration if the swreset bit is set to ?1? and boot is set to ?1?. the one_shot bit is used to start a new conversion when the o dr[2,0] bits in ctrl_reg1 (10h) are set to ?000?. writing a ?1? in one_shot triggers a single measurement of pressure and temperature. once the measurement is done, the one_shot bit will self-clear, the new data ar e available in the output registers, and the status_reg bits are updated. 76 5 4 3 2 1 0 boot fifo_en stop_on_fth if_add_inc i2c_dis swreset 0 (1) one_shot 1. this bit must be set to ?0? for proper operation of the device boot reboot memory content. default value: 0. (0: normal mode; 1: reboot memory content). the bit is self-cleared when the boot is completed. fifo_en fifo enable. default value: 0. (0: disable; 1: enable) stop_on_fth stop on fifo threshold. enable fifo watermark level use. default value 0 (0: disable; 1: enable) if_add_inc register address automatically incremented during a multiple byte access with a serial interface (i 2 c or spi). default value 1. (0: disable; 1 enable) i2c_dis disable i 2 c interface. default value 0. (0: i 2 c enabled;1: i 2 c disabled) swreset software reset. default value: 0. (0: normal mode; 1: software reset). the bit is self-cleared when the reset is completed. one_shot one-shot enable. default value: 0 . (0: idle mode; 1: a new dataset is acquired)
docid027083 rev 1 29/37 lps22hb register description 37 8.7 ctrl_reg3 (12h) control register 3 - int_drdy pin control register 8.8 fifo_ctrl (14h) fifo control register 76543210 int_h_l pp_od f_fss5 f_fth f_ovr drdy int_s2 int_s1 int_h_l interrupt active-high/low. default value: 0. (0: active high; 1: active low) pp_od push-pull/open drain selection on interrupt pads. default value: 0. (0: push-pull; 1: open drain) f_fss5 fifo full flag on int_drdy pin. default value: 0. (0: disable; 1: enable) f_fth fifo threshold (watermark) status on int_drdy pin. default value: 0. (0: disable; 1: enable) f_ovr fifo overrun interrupt on int_drdy pin. default value: 0. (0: disable; 1: enable) drdy data-ready signal on int_drdy pin. default value: 0. (0: disable; 1: enable) int_s[2:1] data signal on int_drdy pin control bits. default value: 00. refer to table 18 . table 18. interrupt configurations int_s2 int_s1 int_drdy pin configuration 00 data signal (in order of priority: pth_drdy or f_fth or f_ovr or f_fsss5 0 1 pressure high (p_high) 1 0 pressure low (p_low) 1 1 pressure low or high 76543210 f_mode2 f_mode1 f_mode0 wtm4 wtm3 wtm2 wtm1 wtm0 f_mode[2:0] fifo mode selection. default value: 000. refer to table 19 and section 4 for additional details. wtm[4:0] fifo watermark level selection.
register description lps22hb 30/37 docid027083 rev 1 8.9 ref_p_xl (15h) reference pressure (lsb data) the reference pressure value is a 24-bit data added to the sensor output measurement and it is composed of ref_p_h (17h) , ref_p_l (16h) and ref_p_xl (15h) . the value is expressed as 2?s complement. the reference pressure value is added to the sensor output measurement, to detect a measured pressure beyond programmed limits (refer to the ctrl_reg3 (12h) register) and for the autozero function (refer to the interrupt_cfg (0bh) register). 8.10 ref_p_l (16h) reference pressure (middle part) table 19. fifo mode selection f_mode2 f_mode1 f_mode0 fifo mode selection 00 0 bypass mode 00 1 fifo mode 0 1 0 stream mode 01 1 stream-to-fifo mode 10 0 bypass-to-stream mode 1 0 1 reserved 1 1 0 reserved 11 1 bypass-to-fifo mode 76543210 refl7 refl6 refl5 refl4 refl3 refl2 refl1 refl0 refl[7:0] this register contains the low part of the re ference pressure value. 76543210 refl15 refl14 refl13 refl12 refl11 refl10 refl9 refl8 refl[15:8] this register contains the mid part of the re ference pressure value. refer to ref_p_xl (15h) .
docid027083 rev 1 31/37 lps22hb register description 37 8.11 ref_p_h (17h) reference pressure (msb part) 8.12 rpds_l (18h) pressure offset (lsb data) the pressure offset value is a 16-bit data that can be used to implement the one-point calibration (opc) after soldering, this value is composed of rpds_h (19h) and rpds_l (18h) . the value is expressed as 2?s complement. 8.13 rpds_h (19h) pressure offset (msb data) 8.14 res_conf (1ah) low-power mode configuration 76543210 refl23 refl22 refl21 refl20 refl19 refl18 refl17 refl16 refl[23:16] this register contains the high part of the reference pressure value. refer to ref_p_xl (15h) . 76543210 rpds7 rpds6 rpds5 rpds4 rpds3 rpds2 rpds1 rpds0 rpds[7:0] this register contains the low part of the pressure offset value. 76543210 rpds15 rpds14 rpds13 rpds12 rpds11 rpds10 rpds9 rpds8 rpds[15:8] this register contains the high part of the pressure offset value. refer to rpds_l (18h) . 76 5 4 3 2 1 0 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) 0 (1) reserved (2) lc_en 1. these bits must be set to ?0? for proper operation of the device. 2. the content of this bit must not be modified for proper operation of the device lc_en low current mode enable. default 0. 0: normal mode (low-noise mode); 1: low-current mode).
register description lps22hb 32/37 docid027083 rev 1 8.15 int_source (25h) interrupt source 8.16 fifo_status (26h) fifo status 8.17 status (27h) status register 7 654321 0 boot_status 0000iapl ph boot_status if ?1? indicates that the boot (reboot) phase is running. ia interrupt active. (0: no interrupt has been generated; 1: one or more interrupt events have been generated). pl differential pressure low. (0: no interrupt has been generated; 1: low differential pressure event has occurred). ph differential pressure high. (0: no interrupt has been generated; 1: high differential pressure event has occurred). 76543210 fth_fifo ovr fss5 fss4 fss3 fss2 fss1 fss0 fth_fifo fifo threshold status. (0: fifo filling is lower than fth level, 1: fifo filling is equal or higher than fth level). ovr overrun bit status. (0: fifo not full; 1: fifo is full and at least one sample in the fifo has been overwritten). fss[5:0] fifo stored data level. (000000: fifo empty, 100000: fifo is full and has 32 unread samples). 76543210 -- -- t_or p_or -- -- t_da p_da
docid027083 rev 1 33/37 lps22hb register description 37 this register is updated every odr cycle. t_or is set to ?1? when a new temperature data is generated before the previous one has been read. p_or is set to ?1? when a new pressure data is generated before the previous one has been read. 8.18 press_out_xl (28h) pressure output value (lsb) the pressure output value is a 24-bit data that contains the measured pressure. it is composed of press_out_h (2ah) , press_out_l (29h) and press_out_xl (28h) . the value is expressed as 2?s complement. 8.19 press_out_l (29h) pressure output value (mid part) t_or temperature data overrun. (0: no overrun has occurred; 1: a new data for temperature has overwritten the previous one) p_or pressure data overrun. (0: no overrun has occurred; 1: new data for pressure has overwritten the previous one) t_da temperature data available. (0: new data for temperature is not yet available; 1: new data for temperature is available) p_da pressure data available. (0: new data for pressure is not yet available; 1: new data for pressure is available) 76543210 pout7 pout6 pout5 pout4 pout3 pout2 pout1 pout0 pout[7:0] this register contains the low part of the pressure output value. 76543210 pout15 pout14 pout13 pout12 pout11 pout10 pout9 pout8 pout[15:8] this register contains the mid part of the pressure output value. refer to press_out_xl (28h) .
register description lps22hb 34/37 docid027083 rev 1 8.20 press_out_h (2ah) pressure output value (msb) 8.21 temp_out_l (2bh) temperature output value (lsb) the temperature output value is a 16-bit data that contains the measured temperature. it is composed of temp_out_h (2ch) , and temp_out_l (2bh) . the value is expressed as 2?s complement. 8.22 temp_out_h (2ch) temperature output value (msb) the temperature output value is a 24-bit data that contains the measured temperature. it is composed of press_out_h (2ah) , and press_out_xl (28h) . the value is expressed as 2?s complement. 76543210 pout23 pout22 pout21 pout20 pout19 pout18 pout17 pout16 pout[23:16] this register contains the low part of the pressure output value. refer to press_out_xl (28h) . 76543210 tout7 tout6 tout5 tout4 tout3 tout2 tout1 tout0 tout[7:0] this register contains the low part of the temperature output value. 76543210 tout15 tout14 tout13 tout12 tout11 tout10 tout9 tout8 tout[15:8] this register contai ns the high part of the temperature output value.
docid027083 rev 1 35/37 lps22hb package mechanical data 37 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 12. hlga - 10l (2.0 x 2.0 x 0.76 mm typ.) outline and mechanical data dimensions are in millimeter unless otherwise specified outer dimensions item dimension [mm] tolerance [mm] 1 . 0 2 ] l [ h t g n e l 1 . 0 2 ] w [ h t d i w / x a m 8 . 0 ] h [ t h g i e h 5 0 . 0 5 7 2 . 0 x 5 2 . 0 e z i s d n a l 5 0 . 0 5 . 0 x h c t i p 5 0 . 0 1 y h c t i p 5 0 . 0 0 1 . 0 t e s n i d a p 8577439
revision history lps22hb 36/37 docid027083 rev 1 10 revision history table 20. document revision history date revision changes 29-oct-2014 1 initial release.
docid027083 rev 1 37/37 lps22hb 37 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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