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cy23s08 3.3 v zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-07265 rev. *o revised november 25, 2013 3.3 v zero delay buffer features zero input output propagation de lay, adjustable by capacitive load on fbk input multiple configurations (see available cy23s08 configurations on page 4) multiple low-skew outputs ? 45-ps typical output-output skew (-1) ? two banks of four outputs that can be tristated by two select inputs 10 mhz to 140 mhz operating range 65-ps typical cycle-to-cycle jitter (-1, -1h) advanced 0.65- ? m complementary metal oxide semiconductor (cmos) technology space-saving 16-pin small out line integrated circuit (soic) package 3.3-v operation spread aware functional description the cy23s08 is a 3.3-v zero delay buffer designed to distribute high-speed clocks in pc, workst ation, datacom, telecom, and other high-performance applications. the part has an on-chip pll which locks to an input clock presented on the ref pin. the pll feedback must be driven into the fbk pin, and obtained from one of the outputs. the input-to-output propagat ion delay is less than 350 ps and output-to-output skew is less than 250 ps. the cy23s08 has two banks of four outputs each, which can be controlled by the select inputs as shown in select input decoding on page 4. if all output clocks are not required, bank b can be tristated. the select in puts also enable the input clock to be directly applied to the ou tput for chip and system testing purposes. the cy23s08 pll enters a power-down state when there are no rising edges on the ref input. in this mode, all outputs are tristated and the pll is turned off, resulting in less than 50 ? a of current draw. the pll shuts down in two additional cases as shown in select input decoding on page 4. multiple cy23s08 devices acc ept the same input clock and distribute it in a system. in this case, the skew between the outputs of two devices is less than 700 ps. the cy23s08 is available in five different configurations, as shown in available cy23s08 configurations on page 4. the cy23s08-1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. the cy23s08-1h is the high-drive version of the -1, and rise and fall times on this device are much faster. the cy23s08-2 enables you to obtain 2x and 1x frequencies on each output bank. the exact configuration and output frequencies depends on which out put drives the feedback pin. the cy23s08-2h is the high drive version of the -2, and rise and fall times on this device are much faster. the cy23s08-4 enables you to obtain 2x clocks on all outputs. therefore, the part is versatile , and can be used in a variety of applications. ref clka1 clka2 clka3 clka4 fbk pll mux select input decoding s2 s1 clkb1 clkb2 clkb3 clkb4 /2 extra divider (?2, ?2h) /2 extra divider (?4) logic block diagram
cy23s08 document number: 38-07265 rev. *o page 2 of 14 contents pinouts .............................................................................. 3 pin definitions .................................................................. 3 functional overview ........................................................ 4 select input decoding ................................................. 4 available cy23s08 configurations ............................. 4 spread aware .............................................................. 4 maximum ratings ............................................................. 5 operating conditions ....................................................... 5 electrical characteristics ................................................. 5 switching characteristics ................................................ 6 switching waveforms ...................................................... 8 test circuits ...................................................................... 9 ordering information ...................................................... 10 ordering code definitions ......................................... 10 package drawings and dimensions ............................. 11 acronyms ........................................................................ 12 document conventions ................................................. 12 units of measure ....................................................... 12 document history page ................................................. 13 sales, solutions, and legal information ...................... 14 worldwide sales and design s upport ......... .............. 14 products .................................................................... 14 psoc? solutions ...................................................... 14 cypress developer community ................................. 14 technical support ................. .................................... 14
cy23s08 document number: 38-07265 rev. *o page 3 of 14 pinouts figure 1. 16-pin soic pinout (top view) 9 16 fbk clka4 clka3 v dd gnd clkb4 clkb3 s1 1 2 3 4 5 6 7 8 10 11 12 13 14 15 ref clka1 clka2 v dd gnd clkb1 clkb2 s2 pin definitions pin signal description 1 ref [1] input reference frequency, 5-v tolerant input 2 clka1 [2] clock output, bank a 3 clka2 [2] clock output, bank a 4v dd 3.3-v supply 5 gnd ground 6 clkb1 [2] clock output, bank b 7 clkb2 [2] clock output, bank b 8s2 [3] select input, bit 2 9s1 [3] select input, bit 1 10 clkb3 [2] clock output, bank b 11 clkb4 [2] clock output, bank b 12 gnd ground 13 v dd 3.3-v supply 14 clka3 [2] clock output, bank a 15 clka4 [2] clock output, bank a 16 fbk pll feedback input notes 1. weak pull-down. 2. weak pull-down on all outputs. 3. weak pull-ups on these inputs.
cy23s08 document number: 38-07265 rev. *o page 4 of 14 functional overview spread aware many systems designed now use the spread spectrum frequency ti ming generation (ssftg) technology. cypress is one of the pioneers of ssftg development, and designed this product so as not to filter off the spread spectrum feature of the reference i nput, assuming it exists. when a zero delay buffer does not pass through the ss feature, the result is a significant amount of tracki ng skew which may cause problems in systems requiring synchronization. for more details on spread spectrum timing technology, see cypress?s application note emi suppression techniques with spread spectrum frequency timing generator (ssftg) ics . select input decoding s2 s1 clock a1?a4 clock b1?b4 output source pll shutdown 0 0 tristate tristate pll y 0 1 driven tristate pll n 1 0 driven driven reference y 1 1 driven driven pll n available cy23s08 configurations device feedback from bank a frequency bank b frequency cy23s08-1 bank a or bank b reference reference cy23s08-1h bank a or bank b reference reference cy23s08-2 bank a reference reference/2 cy23s08-2h bank a reference reference/2 cy23s08-2 bank b 2 x reference reference cy23s08-2h bank b 2 x reference reference cy23s08-4 bank a or bank b 2 x reference 2 x reference note 4. output phase is indeterminant (0 or 180 from input clock). if phase integrity is required, use the cy23s08-2.
cy23s08 document number: 38-07265 rev. *o page 5 of 14 maximum ratings supply voltage to ground potential ..............?0.5 v to +7.0 v dc input voltage (except re f) ............ ?0.5 v to v dd + 0.5 v dc input voltage ref ................. .............. ........... ?0.5 to 7 v storage temperature ................................ ?65 c to +150 c max soldering temperature (10 sec.) ........................ 260 c junction temperature ................................................ 150 c static discharge voltage (per mil-std-883, method 3015) .............. ............. >2000 v operating conditions parameter [5] description min max unit v dd supply voltage 3.0 3.6 v t a ambient operating temperature, commercial 0 70 c ambient operating temperature, industrial ?40 85 c c l load capacitance, below 100 mhz ? 30 pf load capacitance, from 100 mhz to 140 mhz ? 15 pf c in input capacitance [6] ?7pf electrical characteristics for cy23s08sxc-xx commercial temperature devices parameter description test conditions min max unit v il input low voltage ? 0.8 v v ih input high voltage 2.0 ? v i il input low current v in = 0 v ? 50.0 ? a i ih input high current v in = v dd ? 100.0 ? a v ol output low voltage [7] i ol = 8 ma (-1, -2, -4) i ol = 12 ma (-1h, -2h) ?0.4v v oh output high voltage [7] i oh = ?8 ma (-1, -2, -4) i oh = ?12 ma (-1h, -2h) 2.4 ? v i dd (pd mode) power-down supply current ref = 0 mhz ? 12.0 ? a i dd supply current unloaded outputs, 100-mhz ref; select inputs at v dd or gnd ?45.0ma ? 70.0 (-1h, -2h) ma unloaded outputs, 66 mhz ref (-1, -2, -4) ? 32.0 ma unloaded outputs, 33 mhz ref (-1, -2, -4) ? 18.0 ma notes 5. multiple supplies: the voltage on any input or io pin cannot exceed the power pin during power up. power supply sequencing is not required. 6. applies to both ref clock and fbk. 7. parameter is guaranteed by design and char acterization. not 100% tested in production.
cy23s08 document number: 38-07265 rev. *o page 6 of 14 switching characteristics for cy23s08sxc-xx commercial temperature devices parameter [8] description test conditions min typ max unit t1 output frequency 30 pf load, ?1, ?1h, ?2 devices 10 ? 100 mhz t1 output frequency 30 pf load, ?4 devices 15 ? 100 mhz t1 output frequency 20 pf load, ?1h device 10 ? 133.3 mhz t1 output frequency 15 pf load, ?1, ?2 devices 10 ? 140.0 mhz t1 output frequency 15 pf load, ?4 devices 15 ? 140.0 mhz duty cycle [9] = t 2 ?? t 1 (-1, -2, -4, -1h, -2h) measured at v dd /2, f out = 66.66 mhz, 30-pf load 40.0 50.0 60.0 % duty cycle [9] = t 2 ?? t 1 (-1, -2, -4, -1h, -2h) measured at v dd /2, f out < 66.66 mhz, 15 pf load 45.0 50.0 55.0 % t3 rise time [9] (-1, -2, -4) measured between 0.8 v and 2.0 v, 30 pf load ? ? 2.20 ns t3 rise time [9] (-1, -2, -4) measured between 0.8 v and 2.0 v, 15 pf load ? ? 1.50 ns t3 rise time [9] (-1h, -2h) measured between 0.8 v and 2.0 v, 30 pf load ? ? 1.50 ns t 4 fall time [9] (-1, -2, -4) measured between 0.8 v and 2.0 v, 30 pf load ? ? 2.20 ns t 4 fall time [9] (-1, -2, -4) measured between 0.8 v and 2.0 v, 15 pf load ? ? 1.50 ns t 4 fall time [9] (-1h, 2h) measured between 0.8 v and 2.0 v, 30 pf load ? ? 1.25 ns t 5 output-to-output skew on same bank (-1) [9] all outputs equally loaded ? 45 200 ps output-to-output skew on same bank (-1h, -2, -2h) [9] all outputs equally loaded ? 105 150 ps output-to-output skew on same bank (-4) [9] all outputs equally loaded ? 70 100 ps output-to-output skew (-1h, -2h) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (-1, -2) all outputs equally loaded ? ? 300 ps output bank a to output bank b skew (-4) all outputs equally loaded ? ? 215 ps output bank a to output bank b skew (-1h) all outputs equally loaded ? ? 250 ps notes 8. all parameters are specified with loaded outputs. 9. parameter is guaranteed by design and char acterization. not 100% tested in production.
cy23s08 document number: 38-07265 rev. *o page 7 of 14 t 6 delay, ref rising edge to fbk rising edge [10] measured at v dd /2 ?250 ? ? 275 ps t 7 device-to-device skew [10] measured at v dd /2 on the fbk pins of devices ??700ps t 8 output slew rate [10] measured between 0.8 v and 2.0 v on -1h, -2h device using test circuit #2 1??v/ns t j cycle-to-cycle jitter [10] (-1, -1h) measured at 66.67 mhz, loaded outputs, 15, 30 pf loads; 133 mhz, 15 pf load ?65125ps cycle-to-cycle jitter [10] (-2) measured at 66.67 mhz, loaded outputs, 15 pf load ?85300ps cycle-to-cycle jitter [10] (-2) measured at 66.67 mhz, loaded outputs, 30 pf load ??400ps t j cycle-to-cycle jitter [10] (-4) measured at 66.67 mhz, loaded outputs, 15, 30 pf loads ??200ps t lock pll lock time [10] stable power supply, valid clocks presented on ref and fbk pins ??1.0ms switching characteristics (continued) for cy23s08sxc-xx commercial temperature devices parameter [8] description test conditions min typ max unit note 10. parameter is guaranteed by design and char acterization. not 100% tested in production.
cy23s08 document number: 38-07265 rev. *o page 8 of 14 switching waveforms figure 2. duty cycle timing figure 3. all outputs rise and fall time figure 4. ou tput-output skew figure 5. input-output propagation delay figure 6. device-device skew t 1 t 2 1.4 v 1.4 v 1.4 v output t 3 3.3 v 0 v 0.8 v 2.0 v 2.0 v 0.8 v t 4 1.4 v t 5 output output 1.4 v v dd /2 t 6 input fbk v dd /2 v dd /2 v dd /2 t 7 fbk, device 1 fbk, device 2
cy23s08 document number: 38-07265 rev. *o page 9 of 14 test circuits figure 7. test circuit 1 figure 8. test circuit 2 0.1 ? f v dd 0.1 ? f v dd clk out c load outputs gnd gnd test circuit for all parameters except t 8 v dd 0.1 ? f v dd clk out 10 pf outputs gnd gnd 1 k ? 1 k ? 0.1 ? f test circuit for t 8 , output slew rate on ?1h device test circuit # 2
cy23s08 document number: 38-07265 rev. *o page 10 of 14 ordering information ordering code definitions ordering code package type operating range pb-free CY23S08SXI-1H 16-pin soic (150 mils) industrial (?40 c to 85 c) CY23S08SXI-1Ht 16-pin soic (150 mils) ? tape and reel industrial (?40 c to 85 c) x = blank or t blank = tube; t = tape and reel high output drive strength configuration type temperature grade: i = industrial pb-free package type: s = 16-pin soic number of outputs base part number for spread aware zero delay buffers company id: cy = cypress cy i- 23s 08 h x x s 1
cy23s08 document number: 38-07265 rev. *o page 11 of 14 package drawings and dimensions figure 9. 16-pin soic (150 mils) s16.15/sz16.15 package outline, 51-85068 51-85068 *e
cy23s08 document number: 38-07265 rev. *o page 12 of 14 acronyms document conventions units of measure acronym description cmos complementary metal oxide semiconductor oe output enable pll phase-locked loop rms root mean square soic small outline integrated circuit ssftg spread spectrum frequency timing generation tssop thin shrunk small outline package symbol unit of measure c degree celsius k ? kilohm mhz megahertz a microampere f microfarad s microsecond ma milliampere ms millisecond mv millivolt ns nanosecond ? ohm pf picofarad ps picosecond vvolt wwatt
cy23s08 document number: 38-07265 rev. *o page 13 of 14 document history page document title: cy23s08, 3.3 v zero delay buffer document number: 38-07265 revision ecn orig. of change submission date description of change ** 110530 szv 12/02/01 change from spec number: 38-01107 to 38-07265 *a 122863 rbi 12/20/02 added power up requirements to operating conditions information. *b 130951 rgl 11/26/03 corrected the s witching characteristics parameters to reflect the w152 device and new characterization. *c 204201 rgl see ecn corrected the block diagram *d 231100 rgl see ecn fixed typo in table 2. *e 378878 rgl see ecn removed ?preliminary? added industrial temp and pb free devices added typical char data *f 391564 rgl see ecn changed output-to-output skew typical value from 90ps to 45ps added cycle-to-cycle jitter (-2) typical value of 85ps *g 1442823 wwz / aesa see ecn updated ordering info with status update. added new pb-free part numbers. *h 2600345 wwz / pyrs 11/03/08 updated max frequency number from 133 mhz to 140 mhz on page 1 and page 4 load capacitance description *i 2658081 kvm / pyrs 02/16/09 removed references to soic in the pinout drawing and pin description table on page 2. corrected tssop package size (fro m 150 mil to 4.4 mm) in ordering information table. added cy23s08zxc-1ht to the ordering information table. updated ordering information table to remove obsolete devices. removed status column. *j 2761988 kvm 09/10/09 added industrial temperat ure range to operating conditions table. added numerical values to operating range column of ordering information table. removed references to ?3 device. *k 2904767 cxq 04/05/10 removed the following parts from ordering information: cy23s08sxc-2, cy23s08sxc-2t, cy23s08sxi-4, cy23s08sxi-4t. updated package diagrams. *l 3011498 cxq 08/19/2010 sunset review; no technical updates. updated package spec 51-85091. added ordering code definition, added acronyms and units of measure. *m 3056348 cxq 10/12/2010 removed pruned parts from ordering information . removed 16-pin tsso p package diagram. *n 3211161 cxq 03/30/2011 removed following pruned parts form ordering information table. cy23s08sxc-1 cy23s08sxc-1t *o 4201668 cinm 11/25/2013 updated package drawings and dimensions : spec 51-85068 ? changed revision from *c to *e. updated in new template.
document number: 38-07265 rev. *o revised november 25, 2013 page 14 of 14 all products and company names mentioned in this document may be the trademarks of their respective holders. cy23s08 ? cypress semiconductor corporation, 2001-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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