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radar receive path afe: 4 - channel lna and pga data sh eet ada8282 rev. 0 document feedback information furnishe d by ana log dev ices is be lieved to be accurate a nd re liable. howeve r, no respons ibility is as sumed b y ana lo g device s f or its use , n o r f or any in fringemen ts of pa ten ts or o the r righ ts of th ird pa rt ies t hat may resu lt f rom its use. s pec if icat io ns s ubje ct to cha nge w ith ou t n ot ice . n o license is granted by im plica tion or otherw ise under any patent or pa tent r ig ht s of ana lo g dev ices . trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www.analog.com features 4 channels of low noise amplifiers (lna s ) followed by programmable gain amplifiers (pga s ) minimum ? 3 db ba ndwidth of 5 mhz typical C3 db bandwidth of 42.3 mhz typical slew rate of 28 v/ s differential input and output gain of 18 db to 36 db in 6 db steps selectabl e low noise and low power modes input referred noise o f 4.5 nv/hz at 18 .3 mw per channel input referred noise of 3.8 nv/hz at 26.5 mw per channel input referred noise of 3.6 nv/hz at 34.8 mw per channel input referred noi se of 3.4 nv /hz at 54.8 mw per channel channel to c hannel gain matching of 0.25 db absolute g ain error of 0. 5 db spi p rogrammable power - down mode (spi selectable) 3.1 v p - p differential output swing when using a 3.3 v supply 32- lead, 5 mm 5 mm lfcsp package specified from ?40c to +125c qualified for automotive applications applications automotive radar adaptive cruise control collision avoidance blind spot detection self parking elec tronic bumper s functional block dia gram +outa ?outa +ina ?ina lna pga 3nvhz +24db ?6db to +12db +outb ?outb +inb ?inb lna pga 3nvhz +24db ?6db to +12db +outc ?outc +inc ?inc lna pga 3nvhz +24db ?6db to +12db +outd ?outd +ind ?ind lna pga 3nvhz +24db ?6db to +12db ada8282 power mode spi gain select vio avdd reset sclk sdi sdo cs 13132-001 figure 1 . general description the ada8282 is designed for applications that require low cost, low power, compact size, and flexibility. the ada8282 has four parallel channels, each including a n lna and a pga. the lna and pga combine to form a signal chain that features a gain range of 18 db to 36 db in 6 db increments with a guaranteed minimum bandwidth of 5 mhz. using the highest power settings, the combined input referred voltage noise of the combined lna and pga channel is 3.4 nv/ hz at maximum gain. the ada8282 can be configured in four power modes that trade off po wer a nd noise performance to optimize the overall performance acco rding to the end application. fabricated in an advanced complementary metal - oxide semiconductor (cmos) process, the ada8282 is available in a 5 mm 5 mm, rohs - compliant, 32 - lead lfcsp. it is specified over the automotive temperature range of ?40c to +125c.
ada8282 data sheet rev. 0 | page 2 of 21 table of contents features ........................................................................................... 1 applications ................................................................................... 1 functional block diagram ............................................................ 1 general description ...................................................................... 1 revision h isto ry ............................................................................ 2 specifications ................................................................................. 3 digital specifications ................................................................. 4 absolute maximum ratings ......................................................... 5 thermal resistance ................................................................... 5 es d ca u t io n ............................................................................... 5 pin configuration and function descriptions ............................ 6 typical performance characteristics ............................................ 7 theory of operation .................................................................... 11 radar re ceive path afe .......................................................... 11 default spi settings ................................................................. 11 input impedance ...................................................................... 11 power modes ............................................................................ 11 programmable gai n range ..................................................... 12 output swing variation with gain ......................................... 12 offse t vo ltage adjustm ents .................................................... 12 single - ended or differential input ......................................... 12 short - circuit currents ............................................................ 12 spi interface ............................................................................. 12 channel to channel phase matching ..................................... 13 applications ................................................................................. 14 increased gain u sing two ada8282 devices in series ....... 14 multiplexing inputs using multiple ada8282 devices ....... 15 basic connections for a typical application ......................... 16 register map ................................................................................ 17 register summary ................................................................... 17 register details ........................................................................ 17 outline dimensions .................................................................... 21 ordering guide ............................................................................ 21 automotive pro ducts ............................................................... 21 revision history 7 /15 revision 0 : initial version
data sheet ada8282 rev. 0 | page 3 of 21 specifications avdd = 3.3 v, lna + pga gain = 36 db (lna gain = 24 db, pga gain = 12 db), t a = ?40c to +125c, pga_bias_sel = b10, lna_bias_sel= b10, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit analog channel characteristics gain 18/24/30/36 db gain range 18 db gain error 0.5 db ?3 db bandwidth v out = 100 mv p-p, gain = 36 db pga_bias_sel = b00, lna_bias_sel = b00 5 20.5 mhz pga_bias_sel = b01, lna_bias_sel = b01 5 34.2 mhz pga_bias_sel = b01, lna_bias_sel = b10 5 42.3 mhz pga_bias_sel = b11, lna_bias_sel = b11 5 52.3 mhz channel to channel gain matching frequencies up to 5 mhz 0.1 0.25 db channel to channel phase matching 1 frequencies up to 5 mhz 0.1 1 degrees slew rate 28 v/s input referred noise gain = 36 db at 2 mhz pga_bias_sel = b00, lna_bias_sel = b00 4.5 nv/hz pga_bias_sel = b01, lna_bias_sel = b01 3.8 nv/hz pga_bias_sel = b01, lna_bias_sel = b10 3.6 nv/hz pga_bias_sel = b11, lna_bias_sel = b11 3.4 nv/hz 50 impedance used for voltage to power conversion ?156 dbm/hz output referred noise gain = 18 db 36 nv/hz gain = 24 db 61 nv/hz gain = 30 db 115 nv/hz gain = 36 db 218 nv/hz offset voltage referred to input gain = 36 db 0.8 3 mv referred to output gain = 36 db 50 200 mv spi offset adjustment resolution (relative to input) lna_bias_sel = b00 113 v lna_bias_sel = b01 186 v lna_bias_sel = b10 250 v lna_bias_sel = b11 440 v spi offset adjustment range (relative to input) lna_bias_sel = b00 4 mv lna_bias_sel = b01 6 mv lna_bias_sel = b10 8 mv lna_bias_sel = b11 14 mv harmonic distortion second harmonic (hd2) v out = 2 v p-p, f in = 100 khz ?70 dbc v out = 100 mv p-p, f in = 2 mhz ?85 dbc third harmonic (hd3) v out = 2 v p-p, f in = 100 khz ?85 dbc v out = 100 mv p-p, f in = 2 mhz ?95 dbc intermodulation distortion v out = 2 v p-p, f in1 = 100 khz, f in2 = 150 khz ?72 dbc v out = 100 mv p-p, f in1 = 2 mhz, f in2 = 2.1 mhz ?83 dbc common-mode rejection ratio (cmrr) ?80 db crosstalk ?105 dbc
ada8282 data sheet rev. 0 | page 4 of 21 parameter test conditions/comments min typ max unit power supply total power dissipation pga_bias_sel = b00, lna_bias_sel = b00 73 mw pga_bias_sel = b01, lna_bias_sel = b01 106 mw pga_bias_sel = b01, lna_bias_sel = b10 139 mw pga_bias_sel = b11, lna_bias_sel = b11 219 mw power dissipation per channel 31 mw avdd 3.0 3.6 v vio 1.8 3.6 v i avdd four channels active pga_bias_sel = b00, lna_bias_sel = b00 19.6 22 ma pga_bias_sel = b01, lna_bias_sel = b01 29 32 ma pga_bias_sel = b01, lna_bias_sel = b10 37.7 42 ma pga_bias_sel = b11, lna_bias_sel = b11 60 66.3 ma one channel active 9.8 11 ma i vio 10 12 a power-down current i avdd and i vio 20 100 a power-down dissipation 0.07 0.33 mw power-up time time to operational after chip is enabled 5 s power supply rejection ratio (psrr) at dc ?80 db at 1 mhz ?80 db input input resistance differential input resistance 1.45 1.57 1.7 k common-mode input resistance 0.37 0.39 0.42 k differential input capacitance 10.8 12 13.2 pf output output voltage swing +outx (?outx), gain = 18 db 3.1 v p-p +outx (?outx), gain = 24 db, 30 db, or 36 db 6.3 v p-p output balance f in = 100 khz ?70 db short-circuit current per output at 25c 205 ma capacitive load 20% overshoot 30 pf 1 normalized to 0 phase matching at 25c; se e the theory of operation section for details. digital specifications avdd = 3.3 v, t a = ?40c to +125c, unless otherwise noted. table 2. parameter temperature min typ max unit logic input (cs ) logic 1 voltage full 1.2 vio + 0.3 v logic 0 voltage full 0.3 v input resistance 25c 15 k input capacitance 25c 0.5 pf logic inputs (sdi, sclk, reset) logic 1 voltage full 1.2 vio + 0.3 v logic 0 voltage full 0 0.3 v input resistance 25c 2.5 k input capacitance 25c 2 pf maximum sclk frequency 10 mhz logic output (sdo) logic 1 voltage (i oh = 800 a) full vio ? 0.3 v logic 0 voltage (i ol = 50 a) full 0.3 v
data sheet ada8282 rev. 0 | page 5 of 21 absolute maximum ratings table 3. parameter rating electrical avdd to epad ?0.3 v to +3.9 v +inx, ?inx, sclk, sdi, sdo, cs , vio, reset, ?outx, +outx to epad ?0.3v to avdd + 0.3 v esd ratings human body model (hbm) 4000 v charged device model (cdm) 2000 v environmental operating temperature range (ambient) ?40c to +125c storage temperature range (ambient) ?65c to +150c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance ja is specified for the worst case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 4. thermal resistance package type ja jc unit 32-lead, 5 mm 5 mm lfcsp 33.51 4.1 c/w esd caution
ada8282 data sheet rev. 0 | page 6 of 21 pin configuration and fu nction descriptions 24 +outa 23 ?outa 22 +outb 21 ?outb 20 +outc 19 ?outc 18 +outd 17 ?outd 1 2 3 4 5 6 7 8 +ina ?ina +inb ?inb +inc ?inc +ind ?ind 9 10 11 12 13 14 15 16 avdd nic nic nic nic nic nic avdd 32 31 30 29 28 27 26 25 avdd sdo sdi cs sclk reset vio avdd ada8282 top view (not to scale) notes 1. nic = no internal connection. 2. tie the exposed pad on the bottom side of the package to the analog/digital ground plane. 13132-002 figure 2. pin configuration table 5. pin function descriptions pin no. mnemonic description 0 epad exposed pad. tie the exposed pad on the bottom side of the package to the analog/digital ground plane. 1 +ina positive lna analog input for channel a. 2 ?ina negative lna analog input for channel a. 3 +inb positive lna analog input for channel b. 4 ?inb negative lna analog input for channel b. 5 +inc positive lna analog input for channel c. 6 ?inc negative lna analog input for channel c. 7 +ind positive lna analog input for channel d. 8 ?ind negative lna analog input for channel d. 9 avdd 3.3 v analog supply. 10 nic no internal connection. leave this pin floating. 11 nic no internal connection. leave this pin floating. 12 nic no internal connection. leave this pin floating. 13 nic no internal connection. leave this pin floating. 14 nic no internal connection. leave this pin floating. 15 nic no internal connection. leave this pin floating. 16 avdd 3.3 v analog supply. 17 ?outd negative analog output for channel d. 18 +outd positive analog output for channel d. 19 ?outc negative analog output for channel c. 20 +outc positive analog output for channel c. 21 ?outb negative analog output for channel b. 22 +outb positive analog output for channel b. 23 ?outa negative analog output for channel a. 24 +outa positive analog output for channel a. 25 avdd 3.3 v analog supply. 26 vio digital level select for spi and reset. this pin can accept 1.8 v to 3.3 v. 27 reset reset input. reset overrides the spi and powers down the device and returns al l settings back to default. reset is pulled to ground by default. a logic high triggers the reset. 28 sclk serial clock. 29 cs chip select bar. 30 sdi serial data input. 31 sdo serial data output. 32 avdd 3.3 v analog supply.
data sheet ada8282 rev. 0 | page 7 of 21 typical performance characteristics avdd = 3.3 v, lna + pga gain = 36 db (lna gain = 24 db, pga gain = 12 db) , t a = 25 c, pga_bias_sel = b10, lna_bias_sel= b10 , unless otherwise noted. 25000 0 5000 10000 15000 20000 number of hits gain error (db) t a = ?40c t a = +25c t a = +125c 13132-103 ?0.20 ?0.19 ?0.18 ?0.17 ?0.16 ?0.15 ?0.14 ?0.13 ?0.12 ?0.11 ?0.10 ?0.09 ?0.08 ?0.07 ?0.06 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 figure 3 . gain accuracy distribution 3000 2500 2000 1500 1000 0 500 ?150 ?100 ?50 0 50 100 150 number of hits v os (mv) t a = ?40c t a = +25c t a = +125c n: 12199 m: ?13.1269 sd: 19.535 n: 12353 m: ?7.49789 sd: 20.0841 n: 11292 m: 0.0246995 sd: 21.4755 13132- 1 10 figure 4 . output offset voltage distribution 3000 2500 2000 1500 1000 0 500 0.050 0.045 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0 number of hits dc gain mismatch (db) t a = ?40c t a = +25c t a = +125c 13132-106 figure 5 . distribution of channel to channel gain matching 350 300 250 200 150 100 50 0 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 number of hits phase mismatch (degrees) t a = ?40c t a = +125c 13132-107 figure 6 . distribution of channel to channel phase matching 0 ?20 ?40 ?60 ?80 ?120 ?100 0 5 4 3 2 1 thd (db) frequency (mhz) 24db 30db 36db 18db 13132-108 figure 7 . total harm onic distortion (thd) vs. frequency for various gains , v out = 10 dbm 1800 1600 1400 1200 1000 800 600 400 200 0 1k 1g 10m 100m 1m 100k 10k input impedance () frequency (hz) 13132-109 fig ure 8 . input impedance vs. freque ncy
ada8282 data sheet rev. 0 | page 8 of 21 time (80ns/div) analog output (1v/div) 2v 250mv analog output sdi b'00 b'11 13132-105 figure 9 . gain step transient response 30 25 20 15 10 5 0 1k 10k 100k 1m 10m 100m noise (nv/hz) frequency (hz) gain = 18db gain = 24db gain = 30db gain = 36db 13132- 11 1 fig ure 10 . input referred noi se vs. frequency 40 35 30 25 20 15 10 5 0 1k 10k 100k 1m 10m 100m noise figure (db) frequency (hz) unterminated 50 13132- 1 12 figure 11 . noise figure vs. frequency 42 ?24 ?18 ?12 ?6 0 6 12 18 24 30 36 100k 1m 10m 100m gain (db) frequency (hz) gain = 36db gain = 30db gain = 24db gain = 18db 13132- 1 13 figure 12 . frequency response at a ll g ains (bias mode 0) 42 ?24 ?18 ?12 ?6 0 6 12 18 24 30 36 100k 1m 10m 100m gain (db) frequency (hz) gain = 36db gain = 30db gain = 24db gain = 18db 13132- 1 14 figure 13 . frequency response at a ll g ains (bias mode 2) 4 ?4 ?3 ?2 ?1 0 1 2 3 0 800 700 600 500 400 300 200 100 amplitude (v) time (ns) v in gain v out 13132- 1 15 figure 14 . overdrive recovery
data sheet ada8282 rev. 0 | page 9 of 21 200 ?50 0 50 100 150 0 1000 800 600 400 200 v out (mv) time (ns) no load 5pf 33pf 66pf 100pf 13132- 1 16 figure 15 . pulse response at v arious output capacitive load s 0 100 200 300 400 500 600 700 800 900 1000 v out (v) time (ns) ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 mode 0 mode 1 mode 2 mode 3 13132-121 figure 16 . large signal pulse response for various lna and pga bias modes 500 300 320 340 360 380 400 420 440 460 480 ?40 ?25 10 5 20 35 50 65 80 95 110 125 short-circuit current (ma) temperature (c) 13132- 1 18 figure 17 . short - circuit current vs . temperature per channel 30 20 21 22 23 24 25 26 27 28 29 ?40 ?25 10 5 20 35 50 65 80 95 110 125 slew rate (v/s) temperature (c) gain = 18db gain = 24db gain = 30db gain = 36db 13132- 1 19 figure 18 . output slew rate vs. temperature 18 24 30 36 v out (v) gain (db) ?3.4 ?3.0 ?2.6 ?2.2 ?1.8 ?1.4 ?1.0 ?0.6 ?0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 13132-125 figure 19 . maximum and minimum differential v out vs. gain 4 ?4 ?3 ?2 ?1 0 1 2 3 10 100 1k 10k 100k output voltage swing (v) output load resistance () t a = ?40c t a = +25c t a = +85c 13132- 1 17 figure 20 . differential output voltage swing vs. output load resistance
ada8282 data sheet rev. 0 | page 10 of 21 120 0 20 40 60 80 100 10k 100k 1m 10m 100m psrr (db) frequency (hz) gain = 18db gain = 24db gain = 30db gain = 36db 13132-122 figure 21 . psrr vs. frequency at v arious g ains 100 0 20 40 60 80 10 30 50 70 90 100k 1m 10m 100m cmrr (db) frequency (hz) gain = 18db gain = 24db gain = 30db gain = 36db 13132-123 figure 22 . cmrr vs. frequency at v arious g ains 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 10k 100k 1m 10m 100m crosstalk (db) frequency (hz) 13132-124 figure 23 . cross talk vs. frequency ?40 ?25 10 5 20 35 50 65 80 95 110 125 supply current (ma) temperature (c) 37.55 37.60 37.65 37.70 37.75 37.80 37.85 13132-120 figure 24 . quiescent supply current vs. temperature
data sheet ada8282 rev. 0 | page 11 of 21 theory of operation radar receive path afe the primary application for the ada8282 is a high speed ramp, frequency modulated, continuous wave radar (hsr-fmcw radar). figure 25 shows a simplified block diagram of an hsr-fmcw radar system. the signal chain requires multiple channels, each including an lna and a pga. the ada8282 provides these key components in a single 5 mm 5 mm lfcsp. the performance of each component is designed to meet the demands of an hsr-fmcw radar system. some examples of these performance metrics are the lna noise, pga gain range, and signal chain bandwidth and power. the ada8282 also has adjustable power modes to adjust the power and performance level to accommodate a wide variety of applications. the ada8282 is programmable via the spi. channel gain, power mode, and offset voltage can be adjusted using the spi port. default spi settings when initially powered, the ada8282 defaults to a setting of 0x00 in register 0x17, which disables all channels. the device is enabled by writing 0x0f to register 0x17. input impedance the input impedance to the ada8282 is set by an internal 785 resistance at each input, biased to midsupply by an internal voltage buffer. both the positive and negative inputs are biased with the same network, creating a differential input impedance of 1.57 k. the input to the ada8282 is typically ac-coupled. the ac coupling capacitors operate with the input impedance of the ada8282 to create a high-pass filter with a pole at 1/(22rc), where r = 785 with a typical tolerance of 15%. power modes the ada8282 has four power modes that can be controlled through register 0x14 (bias_sel). the power modes allow a user to adjust the power and performance tradeoffs to suit the end application. use the low power mode when power savings are in demand, and use the high power mode in applications that require increased bandwidth and low noise. table 6 shows the power performance trade-offs of the various spi settings. table 6. power mode trade-offs mode setting power per channel (mw) input referred noise at 2 mhz (nv/hz) typical bandwidth (mhz), gain = 36 db b00 18.3 4.5 20.5 b01 26.5 3.8 34.2 b10 34.8 3.6 42.3 b11 54.8 3.4 52.3 pa dsp antenna vco 12-bit adc 12-bit adc 12-bit adc pga lna pga lna pga lna ada8282 ref. oscillator chirp ramp generator transmit signal generation 13132-021 figure 25. typical signal chain overview
ada8282 data sheet rev. 0 | page 12 of 21 programmable gain range the ada8282 has a programmable gain to allow adjusting of the output amplitudes of signals to accommodate a variety of applications. the gain of the ada8282 is programmable in 6 db increments from 18 db to 36 db. the gain is controlled using register 0x15. the same register controls all four channels, but each channel can be independently controlled by utilizing the appropriate bits in the register. channel a is controlled with the two lsbs of register 0x15 (bits[1:0]), channel b uses bits[3:2], channel c uses bits[5:4], and channel d uses the two msbs, bits[7:6]. the gain setting and gains are listed in table 7. table 7. gain settings register 0x15 setting gain (db) gain (v/v) b00 18 7.9 b01 24 15.9 b10 30 31.6 b11 36 63.1 output swing variation with gain the ada8282 gain is implemented using two internal gain stages. the first stage is an lna with a gain of 24 db, and the second stage is a pga with a gain that varies from ?6 db to +12 db. the output of the lna has a fixed output swing range, and is the limiting factor when the channel gain is 18 db. because of the limitations of the lna swing range, the ada8282 has an output swing that is dependent on gain, as shown in table 8. table 8. output swing at various gains gain (db) output swing (v p-p) 18 3.1 24 6.3 30 6.3 36 6.3 offset voltage adjustments register 0x10 through register 0x13 adjust the dc offset voltage of each channel. the default value of 0x20 is intended to be the setting for the offset closest to 0 v, but adjustments can be made as required by the application. the default setting (0x20) applies a zero offset, 0x00 applies the maximum negative offset, and 0x3f applies the maximum positive offset. the range and resolution of the lna_offsetx adjustments are dependent on the lna bias mode as described in table 9. table 9. offset voltage adjustments lna_bias_sel setting referred to input (rti) offset resolution (v) rti offset range (mv) b00 113 4 b01 186 6 b10 250 8 b11 440 14 vio pin the vio pin sets the voltage levels used by the spi interface. if the vio pin is tied to the 3.3 v supply, the spi port functions on 3.3 v logic. single-ended or differential input the ada8282 operates with either a differential or single-ended signal source. the maximum input voltage swing is the same in either configuration. when using a single-ended signal source, connect the unused input to ground with a capacitor. matching the ac coupling capacitor to the ac grounding capacitor optimizes cmrr performance. short-circuit currents the ada8282 typically has a 205 ma short-circuit current per output pin. the thermal implications of this current during unintended shorting of these outputs must be taken into account when designing boards with this device. spi interface the ada8282 spi interface uses a 4-wire interface to deliver a 16-bit instruction header, followed by 8 bits of data. the first bit is a read/write bit. w1 and w0 determine how many bytes are transferred, and must both be zeros for the ada8282 to write to a single register. then, a 13-bit address and an 8-bit data byte follow. the spi port operates at sclk frequencies of up to 10 mhz. for additional spi timing information, see the an-877 application note . a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 a12 w0 w1 r/w cs sclk sdi don?t care don?t care don?t care don?t care 16-bit instruction header msb-first 16-bit instruction register (n) data 13132-022 figure 26. serial instruction details
data sheet ada8282 rev. 0 | page 13 of 21 channel to channel phase matching in a multichannel radar application, matching the ac performance between channels improves the distance and angle resolution of a detected object, particularly the phase matching in the band of interest for the application. the ada8282 layout and design are optimized to increase phase matching. the ada8282 also has sufficient bandwidth to minimize any channel to channel phase variation for up to 5 mhz input signals. the phase mismatch between channels can be calibrated at a single temperature. however, any variation in phase matching over temperature can still degrade system performance. the ada8282 is characterized to capture the maximum channel to channel phase mismatch as the temperature varies from a calibration temperature of 25c. figure 27 shows a distribution of channel to channel phase mismatch for signal frequencies up to 5 mhz. when the initial phase mismatch between channels is normalized to 0 at +25c, the 6 mismatch is 0.43 at ?40c and 0.6 at +125c. 350 300 250 200 150 100 50 0 ?0.30 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 number of hits phase mismatch (degrees) t a = ?40c t a = +125c 13132-126 figure 27. channel to channel phase mismatch, normalized to 0 at 25c, lna_bias_sel = pga_bias_sel = b00, pga_gain = b11 the amount of channel to channel phase mismatch varies with the power mode. table 10 shows the 6 phase mismatch up to 5 mhz over the full temperature range for all gain settings in different power modes, when normalized to 0 at 25c in each power mode. table 10. maximum channel to channel phase mism atch over temperature after 25c calibration pga_bias_sel lna_bias_sel 6 channel to channel phase mismatch over temperature (degrees) maximum channel to channel phase mismatch (degrees) b00 b00 0.60 1 b01 b01 0.41 1 b10 b10 0.33 1 b11 b11 0.60 1
ada8282 data sheet rev. 0 | page 14 of 21 applications information increased gain using two ada8282 devices in series for applications that require gains greater than 36 db, two ada8282 devices can be used in series with each other. to optimize the signal swing for the path, increment the gains according to table 11. table 11. gain settings for two devices in series total gain (db) a1 (input side ada8282 ) gain (db) a2 (output side ada8282 ) gain (db) 36 18 18 42 18 24 48 24 24 54 30 24 60 30 30 66 36 30 72 36 36 24 +outa 23 ?outa 22 +outb 21 ?outb 20 +outc 19 ?outc 18 +outd 17 ?outd 1 2 3 4 5 6 7 8 +ina ?ina +inb ?inb +inc ?inc +ind ?ind 9 10 11 12 13 14 15 16 avdd nic nic nic nic nic nic avdd 32 31 30 29 28 27 26 25 ada8282 epad tied to ground avdd sdo sdi cs sclk reset vio avdd 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f +3.3v +3.3v +3.3v gpio: +3.3v/0v +3.3v 10k? spi bus 24 +outa 23 ?outa 22 +outb 21 ?outb 20 +outc 19 ?outc 18 +outd 17 ?outd 1 2 3 4 5 6 7 8 +ina ?ina +inb ?inb +inc ?inc +ind ?ind 9 10 11 12 13 14 15 16 avdd nic nic nic nic nic nic avdd 32 31 30 29 28 27 26 25 ada8282 epad tied to ground avdd sdo sdi cs sclk reset vio avdd 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f input a source input b source input c source input d source 0.1f 0.1f 0.1f 0.1f +3.3v +3.3v +3.3v gpio: +3.3v/0v +3.3v 10k? spi bus to adc to adc to adc to adc 13132-023 figure 28. using two ada8282 devices in series to increase gain
data sheet ada8282 rev. 0 | page 15 of 21 multiplexing inputs using multiple ada8282 devices it is possible to multiplex eight differential inputs down to four differential outputs by using two ada8282 devices. the devices can be connected such that the outputs are connected (see figure 29) as long as only one device is enabled at a time. when an ada8282 is disabled, the outputs present a 6 k load on the output bus. 24 +outa 23 ?outa 22 +outb 21 ?outb 20 +outc 19 ?outc 18 +outd 17 ?outd 1 2 3 4 5 6 7 8 +ina ?ina +inb ?inb +inc ?inc +ind ?ind 9 10 11 12 13 14 15 16 avdd nic nic nic nic nic nic avdd 32 31 30 29 28 27 26 25 ada8282 epad tied to ground avdd sdo sdi cs sclk reset vio avdd 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f input a source input b source input c source input d source 0.1f 0.1f 0.1f 0.1f +3.3v +3.3v +3.3v gpio: +3.3v/0v +3.3v 10k? spi bus 24 +outa 23 ?outa 22 +outb 21 ?outb 20 +outc 19 ?outc 18 +outd 17 ?outd 1 2 3 4 5 6 7 8 +ina ?ina +inb ?inb +inc ?inc +ind ?ind 9 10 11 12 13 14 15 16 avdd nic nic nic nic nic nic avdd 32 31 30 29 28 27 26 25 ada8282 epad tied to ground avdd sdo sdi cs sclk reset vio avdd 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f input e source input f source input g source input h source 0.1f 0.1f 0.1f 0.1f +3.3v +3.3v +3.3v gpio: +3.3v/0v +3.3v 10k? spi bus to adc to adc to adc to adc 13132-024 figure 29. multiplexing by connecting two ada8282 outputs to one output bus
ada8282 data sheet rev. 0 | page 16 of 21 basic connections for a typical application the ada8282 is typically configured to operate with a nominal 3.3 v power supply, using the epad as the analog ground connection. place the bypass capacitors as close as possible to the power supply pins to minimize the length of metal traces in series with the bypassing paths. ac couple the inputs and outputs for each channel as shown in figure 30. pull the reset pin low with a 10 k resistor and drive it with 3.3 v gpio logic. the spi pins can be directly connected to the spi bus. 24 +outa 23 ?outa 22 +outb 21 ?outb 20 +outc 19 ?outc 18 +outd 17 ?outd 1 2 3 4 5 6 7 8 +ina ?ina +inb ?inb +inc ?inc +ind ?ind 9 10 11 12 13 14 15 16 avdd nic nic nic nic nic nic avdd 32 31 30 29 28 27 26 25 ada8282 epad tied to ground avdd sdo sdi cs sclk reset vio avdd 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f input a source input b source input c source input d source 0.1f 0.1f 0.1f 0.1f +3.3v +3.3v +3.3v gpio: +3.3v/0v +3.3v 10k ? spi bus to adc to adc to adc to adc 13132-025 figure 30. typical component connections
data sheet ada8282 rev. 0 | page 17 of 21 register map register summary table 12. register summary reg. name bits bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset rw 0x00 intf_confa [7:0] intf_confa2 lsbfirst1 intf_confa1 lsbfirst0 intf_confa0 0x00 rw 0x01 soft_reset [7:0] unused soft_reset 0x00 r 0x04 chip_id1 [7:0] chip_idlow 0x82 r 0x05 chip_id2 [7:0] chip_idhi 0x82 r 0x06 revision [7:0] revision 0x00 r 0x10 lna_offset0 [7:0] unused lna_offset0 0x20 rw 0x11 lna_offset1 [7:0] unused lna_offset1 0x20 rw 0x12 lna_offset2 [7:0] unused lna_offset2 0x20 rw 0x13 lna_offset3 [7:0] unused lna_offset3 0x20 rw 0x14 bias_sel [7:0] unused pga_bias_sel lna_bias_sel 0x0a rw 0x15 pga_gain [7:0] pga_gain3 pga_gain2 pga_gain1 pga_gain0 0x00 rw 0x17 en_chan [7:0] unused en_ channel3 en_ channel2 en_ channel1 en_ channel0 0x00 rw 0x18 en_bias_gen [7:0] unused en_bias_gen 0x00 rw 0x1d sparewr0 [7:0] unused gpio_write gpio_wr_ mode 0x00 rw 0x1e sparerd0 [7:0] unused gpio_read 0x00 r register details register 0x00: interface configuration register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intf_confa2 lsbfirst1 intf_confa1 lsbfirst0 intf_confa0 the intf_confa configuration register is symmetric, as it is th e first register written and sets the data direction (lsb first or msb first). table 13. intf_confa configurat ion register bit descriptions bits bit name description reset access [7:0] intf_confa2 intf_confa2 must remain b00. 0x00 rw 5 lsbfirst1 lsbfirst1 must be set to b1 for lsb first operation and to b0 for msb first operation. 0x00 rw [4:3] intf_confa1 intf_confa1 must remain b00. 0x00 rw 2 lsbfirst0 lsbfirst0 must be set to b1 for lsb first operation and to b0 for msb first operation. 0x00 rw [1:0] intf_confa0 intf_confa0 must remain b00. 0x00 rw register 0x01: soft reset register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused soft_reset table 14. soft_reset configuratio n register bit descriptions bits bit name description reset access 0 soft_reset the soft_reset bit resets all registers to thei r default values when soft_res et is set to b1. 0x00 rw register 0x04: chip id low register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chip_idlow table 15. chip_idlow configuration register bit descriptions bits bit name description reset access [7:0] chip_idlow the chip_id1 and chip_id2 registers identify the ada8282 . 0x82 r
ada8282 data sheet rev. 0 | page 18 of 21 register 0x05: chip id high register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 chip_idhi table 16. chip_idhi configuration register bit descriptions bits bit name description reset access [7:0] chip_idhi the chip_id1 and chip_id2 registers identify the ada8282 . 0x82 r register 0x06: revision register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 revision table 17. revision configuration register bit descriptions bits bit name description reset access [7:0] revision the revision register identifies the silicon revision of the current die. 0x00 r register 0x10: lna offset 0 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused lna_offset0 table 18. lna_offset0 configuration register bit descriptions bits bit name description reset access [5:0] lna_offset0 lna_offset0 controls the offset of channel a. the default setting (0x20) applies the minimum offset, 0x00 applies the maximum negative offset, and 0x3f applies the maximum positive offset. 0x20 rw the resolution of the offset varies wi th the lna bias mode as follows: lna bias mode 0: 113 v rti offset resolution, 4 mv range. lna bias mode 1: 186 v rti offset resolution, 6 mv range. lna bias mode 2: 250 v rti offset resolution, 8 mv range. lna bias mode 3: 440 v rti offset resolution, 14 mv range. register 0x11: lna offset 1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused lna_offset1 table 19. lna_offset1 configuration register bit descriptions bits bit name description reset access [5:0] lna_offset1 lna_offset0 controls the offset of channel b. the default setting (0x20) applies the minimum offset, 0x00 applies the maximum negative offset, and 0x3f applies the maximum positive offset. 0x20 rw the resolution of the offset varies wi th the lna bias mode as follows: lna bias mode 0: 113 v rti offset resolution, 4 mv range. lna bias mode 1: 186 v rti offset resolution, 6 mv range. lna bias mode 2: 250 v rti offset resolution, 8 mv range. lna bias mode 3: 440 v rti offset resolution, 14 mv range. register 0x12: lna offset 2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused lna_offset2
data sheet ada8282 rev. 0 | page 19 of 21 table 20. lna_offset2 configuration register bit descriptions bits bit name description reset access [5:0] lna_offset2 lna_offset0 controls the offset of channel c. the default setting (0x20) applies the minimum offset, 0x00 applies the maximum negative offset, and 0x3f applies the maximum positive offset. 0x20 rw the resolution of the offset varies wi th the lna bias mode as follows: lna bias mode 0: 113 v rti offset resolution, 4 mv range. lna bias mode 1: 186 v rti offset resolution, 6 mv range. lna bias mode 2: 250 v rti offset resolution, 8 mv range. lna bias mode 3: 440 v rti offset resolution, 14 mv range. register 0x13: lna offset 3 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused lna_offset3 table 21. lna_offset3 configuration register bit descriptions bits bit name description reset access [5:0] lna_offset3 lna_offset0 controls the offset of channel d. the default setting (0x20) applies the minimum offset, 0x00 applies the maximum negative offset, and 0x3f applies the maximum positive offset. 0x20 rw the resolution of the offset varies wi th the lna bias mode as follows: lna bias mode 0: 113 v rti offset resolution, 4 mv range. lna bias mode 1: 186 v rti offset resolution, 6 mv range. lna bias mode 2: 250 v rti offset resolution, 8 mv range. lna bias mode 3: 440 v rti offset resolution, 14 mv range. register 0x14: pga bias register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused pga_bias_sel lna_bias_sel the pga bias select register allows the user to trade off power and performance (for example, bandwidth and noise). table 22. bias_sel configuration register bit descriptions bits bit name description reset access [3:2] pga_bias_sel set pga_bias_sel to b00 for the minimum pga bias and to b11 for the maximum pga bias. 0x00 rw [1:0] lna_bias_sel set lna_bias_sel to b00 for the minimum lna bias and to b11 for the maximum lna bias. 0x00 rw register 0x15: pga gain register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pga_gain3 pga_gain2 pga_gain1 pga_gain0 the pga gain register allows independent gain settings for each channel. table 23. pga_gain configuration register bit descriptions bits bit name description reset access [7:6] pga_gain3 set pga_gain3 to b00 for 18 db gain, to b01 fo r 24 db gain, to b10 for 30 db gain, and to b11 for 36 db gain for channel d 0x00 rw [5:4] pga_gain2 set pga_gain2 to b00 for 18 db gain, to b01 fo r 24 db gain, to b10 for 30 db gain, and to b11 for 36 db gain for channel c 0x00 rw [3:2] pga_gain1 set pga_gain1 to b00 for 18 db gain, to b01 fo r 24 db gain, to b10 for 30 db gain, and to b11 for 36 db gain for channel b 0x00 rw [1:0] pga_gain0 set pga_gain0 to b00 for 18 db gain, to b01 fo r 24 db gain, to b10 for 30 db gain, and to b11 for 36 db gain for channel a 0x00 rw
ada8282 data sheet rev. 0 | page 20 of 21 register 0x17: enable channel register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused en_channel3 en_channel2 en_channel1 en_channel0 the enable channel register allows individual channels to be en abled or disabled. the default mode for the channel is disabled. write 0x0f to the en_chan register to enable all channels. when a channel is disabled but the bias generator is still enabled, the channels current consumption is <100 a. when a channel is disabled, its output pins are high-z. the enable channel register resets at avdd power-on to 0x00 to avoid inrush current for f ast supply ramps. table 24. en_chan register bit descriptions bits bit name description reset access 3 en_channel3 set to b1 to enable channel d, and set to b0 to disable channel d 0x00 rw 2 en_channel2 set to b1 to enable channel c, and set to b0 to disable channel c 0x00 rw 1 en_channel1 set to b1 to enable channel b, and set to b0 to disable channel b 0x00 rw 0 en_channel0 set to b1 to enable channel a, and set to b0 to disable channel a 0x00 rw register 0x18: enable bias generator register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused en_bias_gen when any channel is enabled, the bias generator is automatically enabled. the en_bias_gen register controls whether the bias generator stays active, even when all channels are disabled. leaving the bias generator active decreases the enable time of the device. table 25. en_bias_gen register bit descriptions bits bit name description reset access 0 en_bias_gen setting en_bias_gen to 1 keeps the bias generato r active, providing a faster enable time (~2 s). 0x00 rw register 0x1d: gpio write register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused gpio_write gpio_wr_mode the gpio_wr_mode bit reconfigures the sdo pin to a general-purpose input/output (gpio) port that can be written by the gpio_write register or read by the gpio_read register. table 26. sparewr0 configuration register bit descriptions bits bit name description reset access 1 gpio_write data bit is put onto the sdo pi n when gpio write mode is active. 0x00 rw 0 gpio_wr_mode write b1 to this register to activate gpio write mode. 0x00 rw register 0x1e: gpio read register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused gpio_read table 27. sparerd0 configuration register bit descriptions bits bit name description reset access 0 gpio_read this register reflects the logic level placed on sdo when a b0 is written to gpio_wr_mode. 0x00 r
data sheet ada8282 rev. 0 | page 21 of 21 outline dimensions compliant to jedec standards mo-220-whhd. 1 0.50 bsc 3.50 ref bottom view top view pin 1 indicator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.65 3.50 sq 3.45 s eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min 04-02-2012-a figure 31. 32-lead lead frame chip scale package [lfcsp_wq] 5 mm 5 mm body, very very thin quad (cp-32-11) dimensions shown in millimeters ordering guide model 1, 2 temperature range package description package option ADA8282WBCPZ-R7 ?40c to +125c 32-lead lfcsp_wq, 7 tape and reel cp-32-11 ada8282wbcpz ?40c to +125c 32-lead lfcsp_wq cp-32-11 ada8282cp-ebz evaluation board 1 z = rohs compliant part. 2 w = qualified for auto motive applications. automotive products the ada8282w models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. note that these automotive models may have specifications that differ from the commercial models; therefore, desi gners should review the specifications section of this data sheet carefully. only the automotive grade products shown are available f or use in automotive applications. contact your local analog devices account representative for specific product ordering information and to obtain the specific automotive reliability reports for these models. ?2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d13132-0-7/15(0)

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