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head amplifier for digital ccd cameras description the CXA1690Q is a bipolar ic developed as a head amplifier for digital ccd cameras. the CXA1690Q provides the following functions: correlated double sampling, agc for ccd signals, gca for chroma signals, gca for line signals, sample and hold for a/d converters, blanking, and reference voltage output/output driver for a/d converters. features permits higher sensitivity with a high-gain agc amplifier blanking function for the purpose of calibrating the deviation in black levels of the ccd output signals permits output offset adjustment provides a regulator output pin for the reference voltage for a/d converters built-in gca that amplifies video signals (chroma and line signals) from an external source built-in sample-and-hold circuits (for both camera signals and video signals) required by external a/d converters absolute maximum ratings supply voltage v cc 14 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 460 mw operating conditions supply voltage v cc1 , 2 , 3 4.5 to 5 v ?1 e93x02b27-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA1690Q 32 pin qfp (plastic) structure bipolar silicon monolithic ic applications digital ccd cameras
?2 CXA1690Q block diagram and pin configuration clpsw rfdc loutclp camclp drv c/v sw vish visw lin amp linclp rfgca ref bottom ref top agcclp lpf camsh blk agc cdsclp2 cdsclp1 sh3 sh2 sh1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 agcclp clpob x rs pblk offset v rt v rb v cc3 pin din v cc2 nc line gnd2 rfcont pbrfc clpdm gnd1 shd shp v cc1 ccdlevel agccont agcmax cam/video pb/rec vshi cshi vshp gnd3 drvout clpdrv
3 CXA1690Q pin description (vcc = 4.5v) 1k 46a 127 30k 1k 1k 127 50k 7k 3k 2.4k v rt 100 100 127 2ma typ. 14ma typ. pin no. symbol pin voltage equivalent circuit description 1 cam video h: vcc l: gnd 18 v th = 50 vcc switches between cam mode for the camera signal system and pb and lin modes for the video signal system. 2 pb rec h: vcc l: gnd 18 v th = 50 vcc 3 vshi 1.4v this pin adjusts the slew rate when the video sample-and-hold circuit (vish) built into the cxa1690 is sampling. normally used open. r = 1k: approx. +6db; r = 5k: approx. 6db 4 cshi 1.4v this pin adjusts the slew rate when the camera sample-and- hold circuit (camsh) built into the cxa1690 is sampling. normally used open. r = 1k: approx. +6db; r = 5k: approx. 6db 5 vshp sampling 18 v th = 50 vcc pulse input for vish. 6 23 30 gnd3 gnd1 gnd2 gnd driver gnd. camera signal gnd. video signal gnd. 7 drvout camera system cam mode black level: 1.3v video system lin mode black level: 1.4v video system rf mode dc level: 2.2v driver output. standard d range. camera system signal: 870mvp-p video system pb rfc signal: 500mvp-p video system lin signal: 1.4vp-p pb rec cam video high low video system pb mode video system pb mode camera system cam mode video system lin mode high low
4 CXA1690Q 127 50 400 157 78 86 lin mode switch pb mode switch 1k cam mode switch 127 pin no. symbol pin voltage equivalent circuit description 8 clpdrv camera system cam mode black level: 2v video system lin mode clamp level: 2v video system pb mode dc level: 3v clamps and outputs the drvout (pin 7) output signal. the switch for each mode is closed and the clamp potentials applied to this pin by selecting camvideo (pin 1) or pbrfc (pin 2). 9 20 27 vcc3 vcc1 vcc2 vcc driver v cc . camera signal v cc . video signal v cc . 11 v rt 3.88v 4v regulator output. be sure to decouple this pin near the ic pins to prevent the oscillation and external noise when this pin is not used. (recommended capacitor value: 4.7f) 10 v rb 2.02v 2v regulator output v rb v rt load: 160 ? or greater. be sure to decouple this pin near the ic pins to prevent the oscillation and external noise when this pin is not used. (recommended capacitor value: 4.7f) 91a 16k 13k 6k 91a 4k 25k 1.9k 1k 91a 91a
5 CXA1690Q 39a 127 47k 125k 1k 54k 39a 12 offset 20 vcc to 50 vcc this pin offset adjusts the clpdrv black level when the cxa1690 satisfies the operating conditions for the camera signal system (when camvi is high and pbrec is low). vcc: approx. 500mv 20/50 vcc: approx. 50mv preset: approx. 70mv 70 50 v cc 500 offset voltage (v) clpdrv offset voltage (mv) v cc 20 50 0 pin no. symbol pin voltage equivalent circuit description 14 xrs 22 v th = 50 vcc 21 shp 25 v th = 50 vcc 22 shd high-speed s/h pulse input for camsh (active: low). high-speed s/h pulse input for sh1 (active: low). high-speed s/h pulse input for sh2 and sh3 (active: low). 13 pblk 18 v th = 50 vcc pulse input for blk (active: low). this pin functions only when camvi is high and pbrec is low, and calibrates the black level of the agc output waveform. when the pulse is low, the drvout potential is forced to 2v. 46a 62k 34k 1k 127 24k 200 127 200 15 clpob 18 v th = 50 vcc clamp pulse input for agcclp (active: low). 1k 127 100 sampling
6 CXA1690Q 1k 41a 127 2k 2k pin no. symbol pin voltage equivalent circuit description 16 agcclp approx. 2.8v capacitor connection for agcclp clamping. 0.1 to 1f 17 agcmax 20 vcc to 50 vcc agc amplifier max gain adjustment. 18 agccont 20 vcc to 50 vcc agc amplifier gain adjustment. min gain for v cc , max gain for v cc for both agcmax and agccont. 19 ccd level din input ccd signal black level: approx. 2.6v ccd level detector 20.5 127 4k 300 41 20.5 41 20.5 20k 20.5 38.4k 62 127 34.5k 15k 1k 15.5k 62 2k 260 200 20 50
7 CXA1690Q 127 86 86 1k 39 34k 63k 1k 1k 63k 34k 78 pin no. symbol pin voltage equivalent circuit description 24 clpdm 18 v th = 50 vcc clamp pulse input (active: low). 25 pin din black level: approx. 2.6v ccd signal input. 29 line clamp potential: approx. 2.5v lin signal input. 127 0.9 86 14k 36k 2k 2k 100 127 1k 10k 200 3
8 CXA1690Q 100 127 52k 42k 1k 35k 50 4k pin no. symbol pin voltage equivalent circuit description 31 rfcont 20 vcc to 50 vcc rfgca gain control. 32 pbrfc approx. 2.8v pbrfc signal input. 100 127 7.3k 18k 100 10k 41k 46k 10k
9 CXA1690Q electrical characteristics (ta = 25 c, v cc1 , 2 , 3 = 4.5v) max. typ. min. symbol item conditions unit cam/video = 4.5v, pb/rfc = 0v cam/video = 0v, pb/rfc = 4.5v cam/video = 4.5v, pb/rfc = 4.5v agcmax = 4.5v, agccont = 4.5v agcmax = 4.5v, agccont = 1.8v agcmax = 1.8v, agccont = 4.5v a conmax. a conmin. agcmax = 4.5v, agccont = 4.5v level at which the clpout output signal is saturated agcmax = 4.5v, agccont = 1.8v level at which the clpout output signal is saturated offset = 4.5v offset = 1.8v offset = 0v with 200 ? load with 200 ? load with 200 ? load blkof (blk = 4.5v) blkof (blk = 0v) adjust the dc level so that lin input = 15khz, 500mvp-p sine wave linclp. rfcont = 4.5v, 15khz, 80mvp-p sine wave rfcont = 1.8v, 15khz, 400mvp-p sine wave i dc i dl i dr a conmax. a conmin. a maxmin. agc g agcmax. d agcmin. d caof high caof low caof pre vrto vrbo ? vr blkof lin g rf conmax. rf conmin. ma db v v mv mv db 49 33 33 43 7.8 19 35 2.05 2.05 490 65 43 3.86 2.03 1.83 7 9.5 17 0.5 62 42 42 10 21 30 73 4.06 2.18 1.93 15 10.5 2 40 32 1.9 1.9 440 13 3.66 1.88 1.73 5 8.5 14 current consump- tion agc camclp ref blk lingca rfgca camera mode line mode rf mode agccont max. agccont min. agcmax min. amount of variation in gain dynamic range max. dynamic range min. offset high offset low offset preset vrt dc level vrb dc level vrt vrb offset gain rf cont max. rf cont min.
10 CXA1690Q clpsw rfdc loutclp camclp drv c/v sw vish visw lin amp linclp rfgca ref bottom ref top agcclp lpf camsh blk agc cdsclp2 cdsclp1 sh3 sh2 sh1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 31 32 1 agcclp clpob x rs pblk offset v rt v rb v cc3 pin din v cc2 nc line gnd2 rfcont pbrfc clpdm gnd1 shd shp v cc1 ccdlevel agccont agcmax cam/video pb/rec vshi cshi vshp gnd3 drvout clpdrv v cc v cc 0.1f 1f v cc v cc 1f 1f v cc 29 30 0.047f 200 4.7 4.7 22 20k 3v 10p measurement timing chart din lin pbrfc clpob clpdm pblk v cc gnd v cc gnd v cc gnd 1h 2s equivalent to the black differs for each test differs for each test 2s electrical characteristics measurement circuit
11 CXA1690Q application circuit agc ref top camclp loutclp rfdc c/v sw visw vish ref bottom 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 agcclp 0.1f clpob x rs pblk x rs offset v rt v rb v cc 3 v cc 50k clpdrv 1f drvout gnd3 vshp vshp cshi vshi 10k pb/ rec crm/ video 1k 0.047f pbrfc rfcont 50k gnd2 line 0.1f lin pbrfc nc v cc 2 din 1f pin ccd clpdm gnd1 shd shp v cc 1 ccdlevel agccont 50k agcmax pblk v cc clpdm v cc v cc v cc 50k v cc v cc 1f v cc v cc 10k 1k linclp lin amp sh2 cdsclp2 cdsclp1 agcclp lpf camsh rfgca drv blk sh1 sh3 clpsw shd shp v rt v rb a/d in a/d 4.7f 4.7f application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
12 CXA1690Q description of operation 1. camera signal processing system process the video signal processing pins as follows only in camera mode. <5> vshp ... connect to gnd. <29> line ... connect to gnd via the capacitor (approx. 0.01f). <31> rfcont ... connect to gnd. <32> pbrfc ... connect to gnd via the capacitor (approx. 0.01f). operating conditions the camera signal processing system operates when cam/video is high, and pb/rec is low. camera signal processing system timing chart 2s 2s basic black level 2.05v black level 2.05v 10s 2s approx. 2.5v for v cc approx. 2.1v when offset is 0v 20 50 50 50 approx. 2.0v for v cc 2.05v vf 1.25v signal level signal interval precharge level opb interval dummy pixel interval signal interval ccd output shp shd sh1 output clpdm (dummy bit section 2 for the dummy pixel interval) sh2 output sh3 output agc output n times ( ) sh3 output sh2 output x rs clpob (2 for the opb interval) camsh output pblk (10 for the dummy pixel interval) blk output camvisw output drvout output clpdm clpout output 2.6v 2.6v [ ? 1] [ ? 2] [ ? 3] [ ? 4] [ ? 5]
13 CXA1690Q cds: the ccd signal from the ccd image sensor enters pin and din where it is correlated double sampled (cds: correlated double sampling) by sh1, sh2 and sh3. the precharge level of the ccd output signal is sampled-and-held and output by the sh2 output, and the signal level is sampled-and-held and output by the sh3 output. cdsclp: the cdsclp stabilizes the dc level of the input signal, clamps (clpdm) the input signal during the dummy pixel interval for the purpose of eliminating the agc input offset, and combines the dc level ([ ? 1], [ ? 2]) of sh2 and sh3. agc: the gain can be varied with the agcmax and agccont voltage control (20/50) v cc to v cc . the maximum gain can be varied from 19 to 43db for agcmax, and from 7.9 to 43db for agccont. lpf: a primary low-pass filter has been installed for the purpose of eliminating unused bands and white noise and improving s/n. camsh: the camsh is used for camera system signal processing. it is a sample-and-hold circuit which synchronizes the data read-in timing for the external a/d. the slew rate of the input signal for the sample-and-hold circuit can be controlled by adjusting the input current to the cshi pin. agcclp: the basic black level is set ([ ? 3]) by clamping it with the clpob clock during the opb interval of the agc output waveform. the capacitance for agcclp is connected to the agcclp pin. blk: the black level is calibrated by blanking the black level signal of the agc output waveform so that it does not fall below the basic black level and replacing the dc potential. ([ ? 4]) the signal is blanked when pblk is low. c/vsw: when the cam/video and pb/rec pin voltages are set so that the camera signal processing system operates, c/vsw leads the blk output (camera signal) into the drv. in addition, when these voltages are set so that the video signal processing system operates, c/vsw leads the vish output (video signal) into the drv. clpsw: by selecting the cam/video and pb/rec pin voltages, either [camclp] is connected and lead into the clpdrv pin as the clamp for the output signal of the camera signal processing system, or [loutclp] as the clamp for the lin mode output signal or [rfdc] as the dc shift for the pbrec mode output signal of the video signal processing system. drv: drv drives the external a/d. rf mode or lin mode signals for either the camera or video signals are input to the drv and output from drvout by switching c/vsw. camclp: the signal black level interval is clamped by the clpdm clock to bring camera system signals within the allowable input voltage range for the external a/d, and the signals are output to clpout. ([ ? 5]) in addition, the camclp contains an offset control pin which adjusts the clp potential for the purpose of compensating the clamp level difference generated by the drv. refbottom, reftop: refbottom and reftop are reference voltage source for the external a/d. they are connected to vrb and vrt, and supply 2v and 4v to the a/d.
14 CXA1690Q 2. video signal processing system operating conditions the video signal processing system has two modes: lin signal mode and pbrec signal mode. the video signal processing system operates in lin signal mode when cam/video is low, and pb/rec is high. the video signal processing system operates in pbrec signal mode when pb/rec is high. video signal processing system timing chart lin mode lin input lingca output 9.5db visp drvout output (clpdrv output) 2.5v 2.1v 1.4v (2v) lin signal mode linclp: the video signal enters the lin pin. linclp sync tip clamps the input signal to allow full input. the input signal level and frequency are respectively 500mvp-p (typ.) and dc up to approx. 7mhz. linamp: this is a 9.5db gain amplifier. visw: visw switches between the lin signal and pbrfc signal for the video signal processing system. the signals are switched according to the input conditions of the cam/video and pb/rec pins. vish: the vish is used for video signal processing system. it is a sample-and-hold circuit which synchronizes the data read-in timing for the external a/d. the slew rate of the input signal for the sample-and-hold circuit can be controlled by adjusting the input current to vshi. loutclp: loutclp is a clamp circuit which operates when the lin signal is output by the drv. the clamp potential is 2v.
15 CXA1690Q pbrec signal mode rfgca: this is an amplifier which controls the gain of the video chroma rf signal input to pbrfc. the rfcont voltage can be varied from (20/50) v cc to v cc , enabling the gain to be varied from 0.5 to 17db. the input signal level and frequency are respectively 200mvp-p (typ.) and dc up to approx. 1.5mhz. rfdc: rfdc is a dc bias circuit which operates when the pbrec signal is output by the drv. the dc bias potential is 3v. pbrec mode regcaout output 0.5 to 17db drvout output (clpdrv output) 2.8v 2.9v 2.2v (3v) vish pbrec input
16 CXA1690Q example of representative characteristics agcmax control temperature characteristics gain [db] v agcmax [v] v agcmax -gain 45 40 30 20 10 0 1.5 2 3 4 4.5 v cc = 4.5v v agccont = 4.5v agccont control temperature characteristics gain [db] v agccont [v] v agcmax -gain 45 40 30 20 10 0 1.5 2 3 4 4.5 v cc = 4.5v v agccont = 4.5v agc dynamic range temperature characteristics d-range-agc dynamic range [mv] ta temperature [ c] drange-t 2200 2100 2000 10 0 20 60 40 80 10db dynamic range 40db dynamic range rfgca gain control temperature characteristics gain [db] v rfcont [v] v rfcont -gain 20 10 0 1.5 2 3 44.5 v cc = 4.500v ta = 75 c 35 c 20 c ta = 75 c 35 c 20 c ta = 75 c 35 c 20 c v agcmax = 4.5v v agccont = 1.8v v agcmax = 4.5v v agccont = 4.5v
17 CXA1690Q lingca gain control gain [db] v lincont [v] v lincont -gain 30 20 10 0 1.6 2.0 3.0 4.0 4.5 v cc = 4.5v, ta = 25 c 100 20406075 ta temperature [ c] 500.0 502.0 504.0 voff-camclp offset potential [v] 10 0 20 40 60 75 ta temperature [ c] 53.0 55.0 10 0 20 40 60 75 ta temperature [ c] 56.0 54.0 52.0 54.0 fig.5 fig.6 fig.7 when offset = 4.5v when offset = 0v when offset = 1.8v camclp offset temperature characteristics t-voff v cc = 4.5v
18 CXA1690Q package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 ?0.1 1.5 ?0.15 (8.0) 0.1 ?0.1 + 0.2 + 0.35 + 0.3 0.50 0? to 10? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 ?0.10 ( 0.30) (0.127) + 0.15 detail a : solder a 0.127 ?0.05 + 0.10 package structure sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 0.1 1.5 0.15 (8.0) 0.1 0.1 + 0.2 + 0.35 + 0.3 0.50 0 ? to 10 ? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 0.10 ( 0.30) (0.127) + 0.15 detail a : solder a 0.127 0.05 + 0.10 package structure lead plating specifications item lead material 42 alloy solder composition sn-bi bi:1-4wt% plating thickness 5-18 m spec. sony corporation

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