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___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 1 configurable four output, low jitter crystal- less? clock generator dsc 400 general description the dsc400 is a four output crystal- less? clock generator. it utilize s micrels proven puresilicon ? mems technology to provide excellent jitter and stability while incorporating additional device functionality. the frequencies of the outputs can be identical or independently derived from common plls. each output may be configured independently to support a single ended lvcmos interface or a differential interface. differential options include lvpecl, lvds, or hcsl. the dsc400 provides two independent select line s for choosing between two sets of pre- configured frequencies per bank. it also has tw o oe pins to allow for enabling and disabling outputs. the dsc400 is packaged in a 20 -pin qfn (5 mm x 3.2 mm ) and is available in e xt ended commercial and industrial te mperature grades. block diagram features ? low rms phase jitter: <1 ps (typ) ? high stability: 25 ppm , 50ppm ? wide temperature range o ext. commercial: - 20 c to 70c o industrial: - 40 c to 85c ? high supply noise rejection: -50 dbc ? four format configurable outputs: o lvpecl, lvds, hcsl, lvcmos ? available pin-selectable frequency table o 1 pin per bank for 2 frequency sets ? wide freq. range: o 2.3 mhz C 460 mhz ? 20 qfn footprint (5mm x 3.2 mm ) ? excellent shock & vibration immunity o qualified to mil-std-883 ? high reliability o 20x better mtf than quartz based devices ? wide supply range of 2.25 to 3.6 v ? lead free & rohs compliant ? aec-q100 automotive qualified applications ? communications and networks ? ethernet o 1g, 10gbase-t/kr/lr/sr, and fcoe ? storage area networks o sata, sas, fibre channel ? passive optical networks o epon, 10g-epon, gpon, 10g- pon ? hd/sd/sdi video & surveillance ? automotive ? media and video ? embedded and industrial ? downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 2 dsc400 configurable four output, low jitter crystal- less? clock generator pin description pin no. pin name pin type description 1 oe1 i output enable for bank1 (clk0 and clk3); active high C see table 1 2 nc na leave unconnected or connect to ground 3 vss power ground 4 vss power ground 5 clk0- o complement output of differential pair 0 (off when in lvcmos format) 6 clk0+ o t rue output of differential pair 0 or lvcmos output 0 7 clk1- o complement output of differential pair 1 (off when in lvcmos format) 8 clk1+ o t rue output of differential pair 1 or lvcmos output 1 9 vdd 2 power power supply for bank2 (clk1 and clk 2) 10 fsb2 i input for selecting pre-configured frequencies on bank2 ( clk 1 and clk2) 11 oe2 i output enable for bank2 (clk1 and clk2); active high C see table 1 12 nc na leave unconnected or connect to ground 13 vss power ground 14 vss power ground 15 clk2- o complement output of differential pair 2 (off when in lvcmos format) clk2+ o t rue output of differential pair 2 or lvcmos output 2 17 clk3- o complement output of differential pair 3 (off when in lvcmos format) 18 clk3+ o t rue output of differential pair 3 or lvcmos output 3 19 vdd 1 power power supply for bank1 ( clk 0 and clk 3) 20 fsb1 i input for selecting pre-configured frequencies on bank1 ( clk 0 and clk 3) pin diagram 20 qfn 5.0 3.2mm downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 3 dsc400 configurable four output, low jitter crystal- less? clock generator operational description the dsc400 is a crystal- less? clock generator. unlike older clock g enerators in the industry, it does not require an external crystal to operate; it relies on the integrated mems resonator that interfaces with internal plls. this technology enhances performance and reliability by allowing tighter frequency stability over a far wider temperature range. in addition, the high er resistance to shock and vibration decreases the aging rate to allow for much improved product life in th e system. inputs there are 4 input signals in the device. each has an internal ( 40k ) pull up to default the selection to a high (1). inputs can be controlled through hardware strapping method with a resi stor to ground to assert the input low (0). inputs may also be controlled by other component s gpios in case more than one frequency set is desired, fsb1 and fsb2 are used for independently selecting one of two sets per bank. fsb1 selects the pre -configured set on bank1 (clk0 and clk3 ) and fsb2 selects the pre-configured set on bank2 (clk1 and clk2), as shown in table 2. if there is a requirement to disable outputs, the inputs oe1 and oe2 are used in conjunction to disable the banks of outputs. outputs are disabled in tristate (hi- z) mode, see table 1 below. table 1: output enable (oe) selection table oe1 oe2 bank1 (c lk 0 & c lk 3) bank2 (c lk 1 & c lk 2) 0 0 hi -z hi -z 0 1 hi -z running 1 0 running hi -z 1 1 running running outputs the four outputs are grouped into two banks. each bank is supplied by an independent vdd to allow for optimized noise isolation between the two banks. each bank provides two synch ronous outputs generated by a common pll: ? bank1 is composed of outputs clk 0 and clk 3 ? bank2 is composed of outputs clk 1 and clk2 each output maybe pre-configured independently to be one of the following formats: lvcmos, lvds, lvpecl or hcsl. in case the output is configured to be the single ended lvcmos, the frequency is generated on the true output (c lk x + ) and the complement output (c lk x - ) is shut off in a low state. frequencies can be chosen from 2.3mhz to 460mhz for differential outputs and from 2. 3mhz to 170mhz on lvcmos outputs. power vdd1 and vdd2 supply the power to banks 1 and 2 respectively. each vdd may have diff erent supply voltage from the other as long as it is within the 2.25v to 3.6v r ange. each vdd pin should have a 0.1f capacitor to filter high frequency noise. vss is common to the entire device. downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 4 dsc400 configurable four output, low jitter crystal- less? clock generator ordering information (example shown in red font) factory configuration code assignment of qxxxx the dsc400 is meant for customers to define their own frequency requirements at the four available outputs. the qxxxx number identifies these specific customer requirements and is assigned by the factory. table 2: example of how fsb1 and fsb2 are applied and the qxxxx code ass ignment bank1 outputs fsb1 qxxxx number 1 (default) 0 q0001 c lk 0 125 mhz 150 mhz c lk 3 50 mhz 25 mhz bank2 outputs fsb2 1 (default) 0 c lk 1 156.25 mhz 100 mhz c lk 2 156.25 mhz 100 mhz dsc400- 2 1 clk2 output format 1: lvcmos 2: lvpecl 3: lvds 4: hcsl 44 3 clk3 output form at 0: off 1: lvcmos 2: lvpecl 3: lvds 4: hcsl clk1 output format 0: off 1: lvcmos 2: lvpecl 3: lvds 4: hcsl clk0 output format 1: lvcmos 2: lvpecl 3: lvds 4: hcsl packing t: tape & reel q package k : 20 qfn temp range e: - 20 o c to 70 o c i: - 40 o c to 85 o stability 1 : 50 ppm 2: 25 ppm x t x x k 1 t e t x frequency code qxxxx is assigned by factory; see table2 downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 5 dsc400 configurable four output, low jitter crystal- less? clock generator absolute maximum ratings item min max unit condition supply voltage -0.3 +4.0 v input voltage -0.3 v dd +0.3 v junction temp - +150 c storage temp - 55 +150 c soldering temp - +260 c 40 sec max. esd hbm mm cdm - 4000 400 1500 v note: 1000+ years of data retention on internal memory specifications (unless specified otherwise: t a =25 c, vdd = 3.3v) notes: 1. v dd pins should be filtered with a 0.1 f capacitor connected between v dd and v ss . 2. the addition of idd core and idd io provides total current consumption of the device 3. t su is time to 100 ppm stable output frequency after v dd is applied and outputs are enabled. 4. output waveform figures below the parameters. see output wa veform section parameter symbol condition min. typ. max. unit supply voltage 1 v dd 2.25 3.6 v supply current C core 2 i dd core oe(1:2) = 0 all outputs are disabled 40 44 ma frequency stability f all temp and vdd ranges 25 50 ppm aging C first year f y1 1 year @ 25c 5 ppm aging C after first year f y2 + year 2 and beyond @ 25c <1 /yr ppm startup time 3 t su t= 25c 5 ms input logic levels input logic high input logic low v ih v il 0.75xv dd - - 0.25xv dd v output disable time 4 t da oe(1:2) transition from 1 to 0 5 ns output enable time 4 t en oe(1:2) transition from 0 to 1 20 ns pull-up resistor r pu all input pins have an internal pull- up 40 k downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 6 dsc400 configurable four output, low jitter crystal- less? clock generator notes: 5. period jitter includes crosstalk from adjacent output 6. lvpecl applicable to ext. commercial temperature only lvpecl: typical termination scheme lvpecl outputs 6 output logic levels output logic high output logic low v oh v ol r l =50 v dd -1.08 - - v dd -1.55 v pk to pk output swing single-ended 800 mv output transition time 4 rise time fall time t r t f 20% to 80% r l =50 250 ps frequency f 0 single frequency 2.3 460 mhz output duty cycle sym differential 48 52 % supply current C io 2 i dd io per output at 125mhz 35 38 ma period jitter 5 j per clk(0:3) = 156.25 mhz 2.5 ps rms integrated phase noise j ph 200khz to 20mhz @156.25mhz 100khz to 20mhz @156.25mhz 12khz to 20mhz @156.25mhz 0.25 0.38 1.7 2 ps rms downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 7 dsc400 configurable four output, low jitter crystal- less? clock generator lvds: typical termination scheme if the 100 clamping resistor does not exist inside the receiving device, it sho uld be added externally on the pcb and placed as close as possible to the receiver. lv ds outputs output offset voltage v os r=100 differential 1.125 1.4 v delta offset voltage ?v os 50 mv pk to pk output swing v pp single-ended 350 mv output transition time 3 rise time fall time t r t f 20% to 80% r l = 50 , c l = 2pf 200 ps frequency f 0 single frequency 2.3 4 60 mhz output duty cycle sym differential 48 52 % supply current C io 2 i dd io per output at 125mhz 9 12 ma period jitter j per 2.5 ps rms integrated phase noise j ph 200khz to 20mhz @156.25mhz 100khz to 20mhz @156.25mhz 12khz to 20mhz @156.25mhz 0.28 0.4 1.7 2 ps rms downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 8 dsc400 configurable four output, low jitter crystal- less? clock generator hcsl: typical termination scheme r s is a series resistor implemented to match the trace impedance. depending on the board layout, the value may range from 0 to 30 hcsl outputs output logic levels output logic high output logic low v oh v ol r l =50 0.725 - - 0.1 v pk to pk output swing single-ended 750 mv output transition time 3 rise time fall time t r t f 20% to 80% r l =50 , c l = 2pf 200 400 ps frequency f 0 single frequency 2.3 460 mhz output duty cycle sym differential 48 52 % supply current C io 2 i dd io per output at 125mhz 20 22 ma period jitter j per 2.5 ps rms integrated phase noise j ph 200khz to 20mhz @156.25mhz 100khz to 20mhz @156.25mhz 12khz to 20mhz @156.25mhz 0.25 0.37 1.7 2 ps rms downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 9 dsc400 configurable four output, low jitter crystal- less? clock generator lvcmos: typical termination scheme r s is a series resistor implemented to match the trace impedance to that of the clock output. depending on the board layout, the value may range from 0 to 27 lvcmos outputs output logic levels output logic high output logic low v oh v ol i= 6ma 0.9xv dd - - 0.1xv dd v output transition time 3 rise time fall time t r t f 20% to 80% c l =15pf 1.1 1.3 2 2 ns frequency f 0 all temp range except auto auto temp range 2.3 170 100 mhz output duty cycle sym 45 55 % supply current C io 2 i dd io per output at 125mhz, c l =15pf 11 14 ma period jitter j per clk(0:3) =125mhz 3 ps rms integrated phase noise j ph 200khz to 20mhz @ 125mhz 100khz to 20mhz @ 125mhz 12khz to 20mhz @ 125mhz 0.3 0.38 1.7 2 ps rms downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 10 dsc400 configurable four output, low jitter crystal- less? clock generator connection diagram: the connection diagram below includes recommended capacitors to be placed on each vdd for noise filtering. downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 11 dsc400 configurable four output, low jitter crystal- less? clock generator output waveform ? differential output (lvds, lvpecl, hcsl) ? lvcmos output downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 12 dsc400 configurable four output, low jitter crystal- less? clock generator solder reflow profile msl 1 @ 260c refer to jstd- 020c ramp-u p rate (200c to peak temp) 3 c/ sec m ax . preheat time 150 c to 200c 60 -180 s ec time maintained above 217c 60 -150 s ec peak temperature 255 -260c time within 5c of actual peak 20 - 40 s ec ramp-down rate 6 c/ sec m ax . time 25c to peak temperature 8 min m ax . downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 13 dsc400 configurable four output, low jitter crystal- less? clock generator package dimensions 20 qfn, 5.0 mm x 3.2 mm downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 14 dsc400 configurable four output, low jitter crystal- less? clock generator recommended solder pad layout units: mm[inches] connect the center pad to ground plane for best thermal performance downloaded from: http:///
___________________________________________________ ___________________________________________________ _______________________ _________________ dsc400 page 15 dsc400 configurable four output, low jitter crystal- less? clock generator disclaimer: micrel makes no representations or warranties with respect to the accurac y or completeness of the information furnished in this data sheet. this info rmation is not intended as a warranty and micrel does not assume responsibility for its use. micrel re serves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectu al property rights is granted by this document. except as provided in micrels terms and conditions of sale for such products, micrel assumes no liability whatsoever, and micrel d isclaims any express or implied warranty relating to the sale and/or use of micrel products including liability or warranties relating to fitness for a particular purpose, mer chantability, or infringement of any patent, copyright or other intelle ctual property right. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems t hat (a) are intended for surgical implant into the body or (b) suppor t or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchasers use or sale of mic rel products for use in life support appliances, devices or systems is a purchasers own risk and purchaser agrees to fully indemn ify micrel for any damages resulting from such use or s ale. micrel, inc. 2180 fortune drive, san jose, california 95 131 usa phone: +1 (408) 944-0800 fax: +1 (408) 474 -1000 email: hbwhelp@micrel.com www.micrel.com downloaded from: http:///

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