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| APU3073 200815061-1/17 data and specifications subject to change without notice. description the APU3073 controller ic is designed to provide a low cost synchronous buck regulator for on-board dc to dc converter for multiple output applications. the outputs can be programmed as low as 0.8v for low voltage applications. selectable over-current protection is provided by using external mosfet's on-resistance for optimum cost and performance. this device features a programmable frequency set from 200khz to 400khz, under-voltage lockout for all input supplies, an external programmable soft-start function as well as output under-voltage detection that latches off the device when an output short is detected. synchronous controller plus one ldo controller current limit using mosfet sensing single 5v/12v supply operation programmable switching frequency up to 400khz soft-start function fixed frequency voltage mode precision reference voltage available uncommitted error amplifier available for ddr voltage tracking application package order information features synchronous pwm controller with over-current protection / ldo controller applications ddr memory source sink v tt application low cost on-board dc to dc such as 12v/5v to output voltages as low as 0.8v graphic card hard disk drive multi-output applications rohs compliant ta (c) device package 0 to 70 APU3073o 16-pin tssop technology licensed from international rectifier figure 1 - typical application of APU3073. typical application APU3073 u1 vcc vcl hdrv ldrv fb1 gnd comp ss/sd v out1 rt +5v ocset pgnd drv2 fb2 3.3v v out2 q1 c2 c11 c9 c1 c6 c7 c10 l2 l1 q4 q5 r1 r2 r8 r9 r7 r10 r11 vch v p1 v ref 12v c3 0.1uf c4 d1
2/17 APU3073 absolute maximum ratings vcc supply voltage ................................................... -0.5 - 25v vcl, vch supply voltage .......................................... -0.5 - 25v storage temperature range ...................................... -65c to 150c operating junction temperature range ..................... 0c to 125c caution: stresses above those listed in "absolute maximum ratings" may cause permanent damage to the device. parameter sym test condition min typ max units feedback voltage fb voltage fb voltage line regulation reference voltage ref voltage initial accuracy drive current uvlo uvlo threshold - vcc uvlo hysteresis - vcc uvlo threshold - vch uvlo hysteresis - vch uvlo threshold - fb1 uvlo hysteresis - fb1 supply current vcc dynamic supply current vc dynamic supply current vcc static supply current vc static supply current soft-start section charge current 5 4/17 APU3073 figure 2 - simplified block diagram of the APU3073. this pin serves as the separate ground for mosfet's driver and should be connected to system's ground plane. this pin serves as analog ground for internal reference and control circuitry. a high fre- quency capacitor must be connected from vcc pin to this pin for noise free operation. output driver for the high side power mosfet. this pin should not go negative (below ground), this may cause problem for the gate drive circuit. it can happen when the inductor current goes negative (source/sink), soft-start at no load and for the fast load transient from full load to no load. to prevent negative voltage at gate drive, a low forward voltage drop diode might be connected between this pin and ground. this pin is connected to a voltage that must be at least 4v higher than the bus voltage of the switcher (assuming 5v threshold mosfet) and powers the high side output driver. a minimum of 1 m f, high frequency capacitor must be connected from this pin to ground to provide peak drive current capability. this pin is connected to the drain of the lower mosfet via an external resister and it provides the positive sensing for the internal current sensing circuitry. the external resis- tor programs the current limit threshold depending on the r ds(on) of the power mosfet. an external capacitor can be placed in parallel with the programming resistor to provide high frequency noise filtering. pin# pin symbol pin description 12 13 14 15 16 pgnd gnd hdrv vch ocset block diagram 13 gnd 20ua 64ua max por oscillator error amp ct error comp reset dom por 0.4v fblo comp vch hdrv vcl ldrv pgnd ss/sd fb1 comp 25k 25k r s q rt rt cs comp ocset 3v 20ua v ref drv2 0.8v fb2 bias generator 1.25v 3v por vch uvlo 3.5v / 3.3v vcc 4.2v / 4.0v v p1 3v 0.8v 8 4 5 7 6 16 1 3 15 14 10 11 12 2 9 vcc en vcc 1.25v tsd APU3073 5/17 theory of operation introduction the APU3073 is designed for a two output application and it includes one synchronous buck controller and a linear regulator controller. the pwm section is a fixed frequency, voltage mode and consists of a precision ref- erence voltage, an uncommitted error amplifier, an inter- nal oscillator, a pwm comparator, an internal regulator, a comparator for current limit, gate drivers, soft-start and shutdown circuits (see block diagram). the output voltage of the synchronous converter is set and controlled by the output of the error amplifier; this is the amplified error signal from the sensed output voltage and the voltage on non-inverting input of error amplifier(v p ). this voltage is compared to a fixed frequency linear sawtooth ramp and generates fixed frequency pulses of variable duty-cycle, which drives the two n-channel ex- ternal mosfets. the timing of the ic is provided through an internal oscil- lator circuit which uses on-chip capacitor. the oscilla- tion frequency is programmable between 200khz to 400khz by using an external resistor. figure 14 shows switching frequency vs. external resistor (rt). soft-start the APU3073 has a programmable soft-start to control the output voltage rise and limit the current surge at the start-up. to ensure correct start-up, the soft-start se- quence initiates when the input supplies rise above their threshold and generates the power on reset (por) sig- nal. soft-start function operates by sourcing an internal current to charge an external capacitor to about 3v. ini- tially, the soft-start function clamps the e/a?s output of the pwm converter and disables the short circuit pro- tection. during the power up of the buck converter, the output starts at zero and voltage at fb1 is below 0.4v. the feedback uvlo is disabled during this time by in- jecting a current (64 m a) into the fb1. this generates a voltage about 1.6v (64 m a 3 25k) across the negative input of e/a and positive input of the feedback uvlo comparator (see fig3). figure 3 - APU3073 soft-start diagram. the magnitude of this current is inversely proportional to the voltage at soft-start pin. the 20 m a current source starts to charge up the exter- nal capacitor. in the mean time, the soft-start voltage ramps up, the current flowing into fb1 pin starts to de- crease linearly and so does the voltage at the positive pin of feedback uvlo comparator and the voltage nega- tive input of e/a. when the soft-start capacitor is around 1v, the current flowing into the fb1 pin is approximately 32 m a. the volt- age at the positive input of the e/a is approximately: the e/a will start to operate and the output voltage starts to increase. as the soft-start capacitor voltage contin- ues to go up, the current flowing into the fb1 pin will keep decreasing. because the voltage at pin of e/a is regulated to reference voltage 0.8v, the voltage at the fb1 is: 32 m a 3 25k = 0.8v v fb1 = 0.8-25k 3 (injected current) 20ua 64ua max por error amp 64ua 3 25k=1.6v when ss=0 por 0.4v feeback uvlo comp ss/sd fb1 comp 25k 0.8v 25k hdrv ldrv 3v 6/17 APU3073 ldo controller the ldo section is powered directly from vcc. the out- put of ldo can be set as low as 0.8v and can be pro- grammed to higher voltages by using two external resis- tors. supply voltage under-voltage lockout the under-voltage lockout circuit assures that the mosfet driver outputs, remain in the off state when- ever the supply voltage drops below set parameters. lock- out occurs if vcc or vch fall below 4.0v and 3.3v re- spectively. normal operation resumes once these volt- ages rise above the set values. shutdown the pwm section can be shutdown by pulling the soft- start pin below 0.4v. the control mosfet turns off and the synchronous mosfet turns on during shutdown. over-current protection over-current protection is achieved with a cycle by cycle scheme and it is performed by sensing current through the r ds(on) of low side mosfet. as shown in figure 5, an external resistor (r set ) is connected between ocset pin and the drain of low side mosfet (q2) and sets the current limit set point. the internal current source devel- ops a voltage across r set . when the low side switch is turned on, the inductor current flows through the q2 and results a voltage which is given by: figure 5 - diagram of the over current sensing. when voltage v ocset is below zero, the current sensing comparator flips and disables the oscillator. the high side mosfet is turned off and the low side mosfet is turned on until the inductor current reduces to below current set value. the critical inductor current can be calculated by setting: c ss = 20 m a 3 t start /1v 20 m a 3 t start /c ss = 2v-1v soft-start voltage voltage at negative input of error amp and feedback uvlo comparator voltage at fb1 pin current flowing into fb1 pin 64ua 0ua 0v 0.8v @ 1.6v 0.8v 0v 3v @ 2v @ 1v output of uvlo por the feedback voltage increases linearly as the injecting current goes down. the injecting current drops to zero when soft-start voltage is around 2v and the output volt- age goes into steady state. as shown in figure 4, the positive pin of feedback uvlo comparator is always higher than 0.4v, therefore, feed- back uvlo is not functional during soft-start. figure 4 - theoretical operation waveforms during soft-start. from this analysis, the output start-up time is defined as when soft-start capacitor voltage increases from 1v to 2v. the start-up time will be dependent on the size of the external soft-start capacitor and can be estimated by: for a given start up time, the soft-start capacitor can be calculated as: mosfet drivers the driver capabilities of both high and low side drivers are optimized to maintain fast switching transitions. they are sized to drive a mosfet that can deliver up to 20a output current. the low side mosfet diver is supplied directly by v cc while the high side driver is supplied by v c . an internal dead time control is implemented to prevent cross-conduction and allows the use of several kinds of mosfets. v ocset = i ocset 3 r set -r ds(on) 3 i l ---(1) l1 r set APU3073 ocset i ocset v out osc q1 q2 i set = i l(critical) = ---(2) r set 3 i ocset r ds(on) v ocset = i ocset 3 r set - r ds(on) 3 i l = 0 APU3073 7/17 if the over-current condition is temporary and goes away quickly, the APU3073 will resume its normal operation. if output is shorted or over-current condition persists, the output voltage will keep going down until it is below 0.4v. then the output under-voltage lock out comparator goes high and turns off both mosfets. the operation waveforms are shown in figure 6. figure 6 - diagram of over-current operation. feedback voltage switching frequency high side mosfet turn on time (t on ) average inductor current i out i out i out i out d max /f s(nom) f s(nom) 0.4v v ref =i out normal operation over current limit mode shutdown by uvlo i o(lim) i o(max) v out f s(nom) 3 v in operation in current limit is shown in figure 7, the high side mosfet is turned off and inductor current starts to decrease. because the output inductor current is higher than the current limit setpoint (i set ), the over-current com- parator keeps high until the inductor current decreases to be below i set . then another cycle starts. during over-current mode, the valley inductor current is: the peak inductor current is given as: to avoid undesirable trigger of over-current protection, this relationship must be satisfied: i l(valley) = i set i l(peak) = i set +(v in -v out ) 3 t on /l ---(3) i set =i l(valley) i l(peak) t on t off i l(avg) current limit comparator output inductor current hdrv i set / i o(nom) - d i pk-pk(nom) 2 i set = i o(lim) - ---(5) (v in -v out ) 3 v out 2 3 f s 3 l 3 v in ( ) (v in - v out ) 3 v out v in 3 l 3 f s d i pk-pk(lim) = i o(lim) = i set + ---(4) d i pk-pk(lim) 2 r set = 3 i o(lim) - ---(6) r ds(on) i ocset [ ( )] (v in -v out ) 3 v out 2 3 f s 3 l 3 v in figure 7 - operation waveforms during current limit. from figure 7, the average inductor current during the current limit mode is: the inductor's ripple current can be expressed as: combination of above equation and (4) results in: combination of equations (5) and (2) results in the rela- tionship between r set and output current limit: from the above analysis, the current limit is not only dependent on the current setting resistor r set and r ds(on) of low side mosfet but it is also dependent on the input voltage, output voltage, inductance and switching frequency as well. the cycle-by-cycle over-current limit will hold for a cer- tain amount of time, until the output voltage drops below 0.4v, the under-voltage lock out activates and latches off the output driver. the operation waveform is shown in figure 4. normal operation will resume after APU3073 is powered up again. where: i o(lim) = the output current limit -typical is 50% higher than nominal output current. v in = maximum input voltage v out = output voltage f s = switching frequency l = output inductor r ds(on) = r ds(on) of low side mosfet i ocset = oc threshold set current 8/17 APU3073 v in - v out = l 3 ; d t = d 3 ; d = 1 f s v out v in d i d t l = (v in - v out ) 3 ---(11) v out v in 3d i 3 f s where: v in = maximum input voltage v out = output voltage d i = inductor ripple current f s = switching frequency d t = turn on time d = duty cycle application information design example: the following example is a typical application for APU3073, the schematic is figure 17 on page 16. output voltage programming output voltage is programmed by reference voltage and external voltage divider. the fb pin is the inverting input of the error amplifier, which is referenced to the voltage on non-inverting pin of error amplifier. for this applica- tion, this pin (v p ) is connected to reference voltage (v ref ). the output voltage is defined by using the following equa- tion: when an external resistor divider is connected to the output as shown in figure 8. figure 8 - typical application of the apu3039 for programming the output voltage. equation (7) can be rewritten as: if the high value feedback resistors are used, the input bias current of the fb pin could cause a slight increase in output voltage. the output voltage set point can be more accurate by using precision resistor. soft-start programming the soft-start timing can be programmed by selecting the soft-start capacitance value. the start-up time of the converter can be calculated by using: for a start-up time of 5ms, the soft-start capacitor will be 0.1 m f. choose a ceramic capacitor at 0.1 m f. supply vcl and vch to drive the high side switch, it is necessary to supply a gate voltage at least 4v greater than the bus voltage. for this application, vcl and vch are biased with a sepa- rate 12v supply. input capacitor selection the input filter capacitor should be based on how much ripple the supply can tolerate on the dc input line. the ripple current generated during the on time of upper mosfet should be provided by input capacitor. the rms value of this ripple is expressed by: for higher efficiency, a low esr capacitor is recom- mended. choose two poscap from sanyo 6tpb47m (16v, 47 m f) with a max allowable ripple current of 5.2a. inductor selection the inductor is selected based on operating frequency, transient performance and allowable output voltage ripple. low inductor value results to faster response to step load (high di/dt) and smaller size but will cause larger output ripple due to increase of inductor ripple current. as a rule of thumb, select an inductor that produces a ripple current of 10-40% of full load dc. for the buck converter, the inductor value for desired operating ripple current can be determined using the fol- lowing relation: v out = v p 3 1 + ---(7) r 6 r 5 v p = v ref = 0.8v ( ) fb APU3073 v out r 5 r 6 v ref v p css @ 20 3 t start ( m f) ---(8) where t start is the desirable start-up time (s) for v in =5v, i out =8a and d=0.5, the i rms =4a i rms = i out d 3 (1-d) ---(9) where: d is the duty cycle, d=v out /v in. i rms is the rms value of the input capacitor current. i out is the output current for each channel. r 6 = r 5 3 - 1 v out v p ( ) choose r 5 = 1k. this will result to r 6 = 2.15k switcher v in = 5v v out = 2.5v i out = 8a d v out = 50mv f s = 200khz linear regulator v in = 2.5v v out = 1.6v i out = 2a supply voltage v cc =v c l=v c h=12v APU3073 9/17 if d i = 25%(i o ), then the output inductor will be: the coilcraft do5022hc series provides a range of in- ductors in different values, low profile suitable for large currents. 3.3 m h is a good choice for this application. this will result to a ripple approximately 23% of output current. output capacitor selection the criteria to select the output capacitor is normally based on the value of the effective series resistance (esr). in general, the output capacitor must have low enough esr to meet output ripple and load transient requirements, yet have high enough esr to satisfy sta- bility requirements. the esr of the output capacitor is calculated by the following relationship: the sanyo tpc series, poscap capacitor is a good choice. the 6tpc330m, 330 m f, 6.3v has an esr 40m v . se- lecting two of these capacitors in parallel, results to an esr of @ 20m v which achieves our low esr goal. the capacitor value must be high enough to absorb the inductor's ripple current. the larger the value of capaci- tor, the lower will be the output ripple voltage. power mosfet selection the APU3073 uses two n-channel mosfets. the se- lections criteria to meet power transfer requirements is based on maximum drain-source voltage (v dss ), gate- source drive voltage (v gs ), maximum output current, on- resistance r ds(on) and thermal management. the mosfet must have a maximum operating voltage (v dss ) exceeding the maximum input voltage (v in ). the gate drive requirement is almost the same for both mosfets. logic-level transistor can be used and cau- tion should be taken with devices at very low v gs to pre- vent undesired turn-on of the complementary mosfet, which results a shoot-through current. the total power dissipation for mosfets includes con- duction and switching losses. for the buck converter, the average inductor current is equal to the dc load cur- rent. the conduction loss is defined as: the r ds(on) temperature dependency should be consid- ered for the worst case operation. this is typically given in the mosfet data sheet. ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. choose irf7832 for both control mosfet and synchro- nous mosfet. this device provides low on-resistance in a compact soic 8-pin package. the mosfets have the following data: the total conduction losses will be: the switching loss is more difficult to calculate, even though the switching transition is well understood. the reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turnoff delays and rise and fall times. the control mosfet contributes to the majority of the switch- ing losses in synchronous buck converter. the synchro- nous mosfet turns on under zero voltage conditions, therefore, the turn on losses for synchronous mosfet can be neglected. with a linear approximation, the total switching loss can be expressed as: the switching time waveform is shown in figure 9. 2 2 p cond (upper switch) = i load 3 r ds(on) 3 d 3q p cond (lower switch) = i load 3 r ds(on) 3 (1 - d) 3q q = r ds(on) temperature dependency l = 3.125 m h where: d v o = output voltage ripple d i = inductor ripple current d v o = 50mv and d i @ 23% of 8a = 1.89a this results to: esr=26.5m v esr [ ---(10) d v o d i o p con(total) = p con(upper) + p con(lower) p con(total) = 0.38w where: v ds(off) = drain to source voltage at off time t r = rise time t f = fall time t = switching period i load = load current p sw = i load ---(12) 3 v ds(off) 2 t r + t f t 3 irf7832 v dss = 30v i d = 16a @ 70 8 c r ds(on) = 4m v 10/17 APU3073 f esr = ---(14) 1 2 p3 esr 3 co p sw(total) = 133mw f lc = ---(13) 1 2 p3 l o 3 c o r ds(on) = 4m v3 1.5 = 6m v i set @ i o(lim) = 8a 3 1.5 = 12a (50% over nominal output current) this results to: r set @ 4.8k v select: r set = 5k v v ds v gs 10% 90% t d (on) t d (off) t r t f figure 9 - switching time waveforms. from irf7832 data sheet we obtain: these values are taken under a certain condition test. for more details please refer to the irf7832 datasheet. by using equation (12), we can calculate the total switch- ing losses. programming the over-current limit the over-current threshold can be set by connecting a resistor (r set ) from drain of low side mosfet to the ocset pin. the resistor can be calculated by using equa- tion (2). the r ds(on) has a positive temperature coefficient and it should be considered for the worse case operation. feedback compensation the APU3073 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. to achieve fast transient response and accurate output regulation, a compensa- tion circuit is necessary. the goal of the compensation network is to provide a closed loop transfer function with the highest 0db crossing frequency and adequate phase margin (greater than 45 8 ). gain f lc 0db phase 0 8 f lc -180 8 frequency frequency -40db/decade the output lc filter introduces a double pole, ?40db/ decade gain slope above its corner resonant frequency, and a total phase lag of 180 8 (see figure 10). the reso- nant frequency of the lc filter is expressed as follows: figure 10 shows gain and phase of the lc filter. since we already have 180 8 phase shift just from the output filter, the system risks being unstable. figure 10 - gain and phase of lc filter. the APU3073?s error amplifier is a differential-input transconductance amplifier. the output is available for dc gain control or ac phase compensation. the e/a can be compensated with or without the use of local feedback. when operated without local feedback, the transconductance properties of the e/a become evi- dent and can be used to cancel one of the output filter poles. this will be accomplished with a series rc circuit from comp pin to ground as shown in figure 11. note that this method requires that the output capacitor should have enough esr to satisfy stability requirements. in general, the output capacitor?s esr generates a zero typically at 5khz to 50khz which is essential for an acceptable phase margin. the esr zero of the output capacitor expressed as fol- lows: irf7832 t r = 12.3ns t f = 21ns APU3073 11/17 first select the desired zero-crossover frequency (fo): use the following equation to calculate r 4 : where: v in = maximum input voltage v osc = oscillator ramp voltage fo = crossover frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter r 5 and r 6 = resistor dividers for output voltage programming g m = error amplifier transconductance h(s) = g m 3 3 ---(15) ( ) r 5 r 6 + r 5 1 + sr 4 c 9 sc 9 f lc = 3.41khz r 5 = 1k r 6 = 2.15k g m = 700 m mho for: v in = 5v v osc = 1.25v fo = 20khz f esr = 12khz r 4 = 3 3 3 ---(18) fo 3 f esr f lc 2 v osc v in r 5 + r 6 r 5 1 g m fo > f esr and f o [ (1/5 ~ 1/10) 3 f s for: lo = 3.3 m h co = 660 m f f z @ 75%f lc f z @ 0.75 3 1 2 p l o 3 c o ---(19) f z = 2.5khz r 4 = 24k f z = ---(17) 1 2 p3 r 4 3 c 9 |h(s=j 3 2 p3 f o )| = g m 3 3 r 4 ---(16) r 5 r 6 3 r 5 v out vp=v ref r 5 r 6 r 4 c 9 ve e/a f z h(s) db frequency gain(db) fb comp c pole figure 11 - compensation network without local feedback and its asymptotic gain plot. the transfer function (ve / v out ) is given by: the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: |h(s)| is the gain at zero cross frequency. c 9 @ 2590pf; choose c 9 =2200pf f p = 2 p3 r 4 3 1 c 9 3 c pole c 9 + c pole c pole = @ for f p << f s 2 1 p3 r 4 3 f s p3 r 4 3 f s - 1 1 c 9 this results to r 4 =23.14k choose r 4 =24k to cancel one of the lc filter poles, place the zero be- fore the lc filter resonant frequency pole: using equations (17) and (19) to calculate c 9 , we get: one more capacitor is sometimes added in parallel with c 9 and r 4 . this introduces one more pole which is mainly used to suppress the switching noise. the additional pole is given by: the pole sets to one half of switching frequency which results in the capacitor c pole: for a general solution for unconditionally stability for ceramic capacitor with very low esr and any type of output capacitors, in a wide range of esr values we should implement local feedback with a compensation network. the typically used compensation network for voltage-mode controller is shown in figure 12. 12/17 APU3073 cross over frequency: the stability requirement will be satisfied by placing the poles and zeros of the compensation network according to following design rules. the consideration has been taken to satisfy condition (20) regarding transconduc- tance error amplifier. these design rules will give a crossover frequency ap- proximately one-tenth of the switching frequency. the higher the band width, the potentially faster the load tran- sient speed. the gain margin will be large enough to provide high dc-regulation accuracy (typically -5db to - 12db). the phase margin should be greater than 45 8 for overall stability. based on the frequency of the zero generated by esr versus crossover frequency, the compensation type can be different. the table below shows the compensation type and location of crossover frequency. table - the compensation type and location of zero crossover frequency. detail information is dicussed in application note an- 1043 which can be downloaded from the ir web-site. where: v in = maximum input voltage v osc = oscillator ramp voltage lo = output inductor co = total output capacitors f o = r 7 3 c 10 3 3 v in v osc 1 2 p3 lo 3 co ---(21) figure 12 - compensation network with local feedback and its asymptotic gain plot. in such configuration, the transfer function is given by: the error amplifier gain is independent of the transcon- ductance under the following condition: by replacing z in and z f according to figure 7, the trans- former function can be expressed as: as known, transconductance amplifier has high imped- ance (current source) output, therefore, consider should be taken when loading the e/a output. it may exceed its source/sink output current capability, so that the ampli- fier will not be able to swing its output voltage over the necessary range. the compensation network has three poles and two ze- ros and they are expressed as follows: v out vp=v ref r 5 r 6 r 8 c 10 c 12 c 11 r 7 ve f z 1 f z 2 f p 2 f p 3 e/a z f z in frequency gain(db) h(s) db fb comp h(s) = 1+sr 7 3 (1+sr 8 c 10 ) (1+sr 7 c 11 ) 3 [1+sc 10 (r 6 +r 8 )] 3 [ ( )] 1 sr 6 (c 12 +c 11 ) c 12 c 11 c 12 +c 11 g m z f >> 1 and g m z in >>1 ---(20) 1 - g m z f 1 + g m z in v e v out = 1 2 p3 c 10 3 (r 6 + r 8 ) f z2 = @ 1 2 p3 c 10 3 r 6 f z1 = 1 2 p3 r 7 3 c 11 f p1 = 0 f p3 = @ 1 2 p3 r 7 3 1 2 p3 r 7 3 c 12 f p2 = 1 2 p3 r 8 3 c 10 ( ) c 12 3 c 11 c 12 +c 11 compensator type type ii (pi) type iii (pid) method a type iii (pid) method b location of zero crossover frequency (f o ) f po < f zo < f o < f s /2 f po < f o < f zo < f s /2 f po < f o < f s /2 < f zo typical output capacitor electrolytic, tantalum tantalum, ceramic ceramic APU3073 13/17 ldo section output voltage programming output voltage for ldo is programmed by reference volt- age and external voltage divider. the fb2 pin is the in- verting input of the error amplifier, which is internally ref- erenced to 0.8v. the divider is ratioed to provide 0.8v at the fb2 pin when the output is at its desired value. the output voltage is defined by using the following equation results to r 7 =1k v figure 13 - programming the output voltage for ldo. ldo power mosfet selection the first step in selecting the power mosfet for the linear regulator is to select the maximum r ds(on) based on the input to the dropout voltage and the maximum load current. results to: r ds(on)(max) = 0.45 v note that since the mosfet r ds(on) increases with tem- perature, this number must be divided by ~1.5 in order to find the r ds(on)(max) at room temperature. the irlr2703 has a maximum of 0.065 v r ds(on) at room temperature, which meets our requirements. r 7 r 10 v out2 = v ref 3 1+ ( ) for: v out2 = 1.6v v ref = 0.8v r 10 = 1k v layout consideration the layout is very important when designing high fre- quency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. start to place the power components. make all the con- nections in the top layer with wide, copper filled areas. the inductor, output capacitor and the mosfet should be close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place input capacitor directly to the drain of the high-side mosfet. to reduce the esr, replace the single input capacitor with two par- allel units. the feedback part of the system should be kept away from the inductor and other noise sources and be placed close to the ic. in multilayer pcb, use one layer as power ground plane and have a separate control circuit ground (analog ground), to which all sig- nals are referenced. the goal is to localize the high cur- rent path to a separate loop that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. figure 14 - switching frequency vs. rt. 0 50 100 150 200 250 300 350 400 450 500 0 50 100 150 200 250 300 350 400 450 500 550 rt (k v ) frequency (khz) fb2 APU3073 v out2 r 10 r 7 r ds(on) = v in(ldo) - v out2 i out2 for: v in(ldo) = 2.5v v out2 = 1.6v i out2 = 2a 14/17 APU3073 figure 15 - typical application of APU3073 for single 5v. typical application APU3073 u1 vcc vcl hdrv ldrv fb1 gnd comp ss/sd 2.5v @ 8a rt +5v ocset pgnd drv2 fb2 2.5v 1.6v @ 2a q3 irlr2703 c14 150uf c6 0.1uf c7 c11 1uf c1 47uf l2 l1 q1 irf7832 r2 r14 1k r7 r4 r9 r10 1k vch v p1 v ref c10 0.1uf c2 d2 bat54 c16 1uf c19 1uf c9b 330uf c9c 330uf c12 1uf 1k 33pf 24k 2200pf 5.1k q2 irf7832 3.3uh 2.15k 1uh c2a,b,c=47uf d3 bat54 c3 0.1uf c13 150uf APU3073 15/17 figure 16 - typical application of APU3073. typical application APU3073 u1 vch vcl hdrv ldrv fb1 gnd comp ss/sd 2.5v @ 8a rt +5v ocset pgnd drv2 fb2 3.3v 1.6v @ 1a q3 irlr2703 c14 150uf c6 0.1uf c7 c11 1uf c1 47uf l2 l1 q1 irf7832 r2 r14 1k r7 r4 r9 r10 1k vcc v p1 v ref 12v c10 0.1uf c2 d2 bat54 c16 1uf c19 1uf c9b 330uf c9c 330uf c12 1uf 1k 33pf 24k 2200pf 5.1k q2 irf7832 3.3uh 2.15k 1uh c2a,b,c=47uf c13 150uf 16/17 APU3073 figure 18 - normal condition at no load. ch1: hdrv ch2: ldrv ch4: inductor current figure 19 - gate signals when ss pin pulls low. ch1: hdrv ch2: ldrv figure 20 - soft-start. ch1: v in (5v) ch2: bias voltage (12v) ch3: v out1 (pwm) ch4: v out2 (ldo) application experimental waveforms APU3073 17/17 figure 22 - load transient response (pwm section). ch1: v out1 ch4: i out1 (0-8a) figure 21 - output shorted at start-up. ch1: v out ch4: i out application experimental waveforms figure 23 - load transient response (ldo section). ch2: v out2 ch4: i out2 (0-2a) |
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