unisonic technologies co., ltd VGA7S019 preliminary tvs www.unisonic.com.tw 1 of 7 copyright ? 2014 unisonic technologies co., ltd qw-r223-024.b 7-channel integrated esd solution for vga port with integrated level shifter and matching impedance ? description the utc VGA7S019 is an esd solution for the vga or dvi-i port connector. this device int egrates esd protection for all signals, level shifting for the ddc signals and buffering for the sync signals. esd protection for the video, ddc and sync lines is implemented with low-capacitance current steering diodes. separate positive supply rails are prov ided for the video, ddc and sync channels to facilitate interfacing with low voltage video controller ics to provide design flexibility in multi-supply-voltage environments. two non-inverting drivers provide buffering for t he hsync and vsync signals from the video controller ic (sync1, sync2). these buffers accept ttl input levels and convert them to cmos output levels that swing between ground and vcc_sync, which is typically 5v. additi onally, each driver has a series termination resistor (rt) connected to the sync_out pin, eliminating the ex ternal termination resistors typically required for the hsync and vsync lines of the video cable. at the sy nc output the utc VGA7S019 offers 65- ? , 55- ? , or 15- ? series termination resistor option to match different transmission line impedances. two n-channel mosfets provide the level shifting func tion required when the ddc controller is operated at a lower supply voltage than the monito r. the gate terminals for the mosfet s (vcc_ddc) should be connected to the supply rail (typically 3.3v) that supplies powe r to the transceivers of the ddc controller. the utc VGA7S019 confirms the iec61000-4-2 (level 4) syst em level esd protection and 15kv hbm esd protection. this device is offered in space-saving ssop-16 packages. ? features * 7 channels of esd protection for all vga port connector pins meeting iec-61000-4-2 level 4 esd requirements (8kv contact discharge) * integrated impedance matching resistors on sync lines: C VGA7S019-15: 15 ? termination C VGA7S019-55: 55 ? termination C VGA7S019-65: 65 ? termination * includes esd protection, level-shifting, buffering and sync impedance matching * 5v drivers for hsync and vsync lines * very low loading capacitance from esd protection diodes on video lines (2.5pf) * bi-directional level shifting n-channel fets provided for ddc_clk and ddc_data channels * flow-through single-in-line pin mapping ensures no additional board layout burden while placing the esd protection chip near the connector
VGA7S019 preliminary tvs unisonic technologies co., ltd 2 of 7 www.unisonic.com.tw qw-r223-024.b ? ordering information ordering number package packing VGA7S019g-xx-r16-t ssop-16 tube VGA7S019g-xx-r16-r ssop-16 tape reel note: xx: output voltage, refer to marki ng information. ? marking
VGA7S019 preliminary tvs unisonic technologies co., ltd 3 of 7 www.unisonic.com.tw qw-r223-024.b ? pin configuration ? pin description pin no. pin name description 1 vcc_sync isolated supply input for the sync_1 and sync _2 level shifters and their associated esd protection circuits 2 vcc_video supply pin specifically for the vide o_1, video_2 and video_3 esd protection circuits 3 video1 high-speed esd clamp input 4 video2 5 video3 6 gnd ground 7 vcc_ddc isolated supply input for the d dc_1 and ddc_2 level-shifting n-fet gates 8 byp bypass pin. using a 0.2f bypass capacito r will increase the esd robustness of the system. 9 ddc_out1 ddc signal output. connects to the video connector side of one of the sync lines. 10 ddc_in1 ddc signal input. connects to the vga cont roller side of one of the sync lines. 11 ddc_in2 12 ddc_out2 ddc signal output. connects to the video connector side of one of the sync lines. 13 sync_in1 sync signal buffer input. connects to t he vga controller side of one of the sync lines. 14 sync_out1 sync signal buffer output. connects to the video connector side of one of the sync lines 15 sync_in2 sync signal buffer input. connects to t he vga controller side of one of the sync lines. 16 sync_out2 sync signal buffer output. connects to the video connector side of one of the sync lines
VGA7S019 preliminary tvs unisonic technologies co., ltd 4 of 7 www.unisonic.com.tw qw-r223-024.b ? block diagram video1 video2 video3 v cc_video gnd v cc_ddc byp v sync ddc_in1 ddc_out1 sync_in1 sync_out1 sync_in2 r t r t sync_out2 ddc_out2 ddc_in2
VGA7S019 preliminary tvs unisonic technologies co., ltd 5 of 7 www.unisonic.com.tw qw-r223-024.b ? absolute maximum rating over operating free-air temperatur e range (unless otherwise noted) parameter symbol ratings unit supply voltage v cc_video , v cc _ ddc , v cc _ sync -0.5~6.0 v io voltage videox pins v io ( video ) -0.5~v cc _ video v input voltage sync pins v i ( sync ) -0.5~v cc _ sync v input voltage ddc_inx pins v i ( ddc ) -0.5~6.0 v output voltage ddc_inx pins v o ( ddc ) -0.5~6.0 v iec 61000-4-2 contact discharge video, ddc_out, sync_out pins 8 kv hbm esd video, ddc_out, sync_out pins 15 kv vcc, ddc_in, sync_in, byp pins 2 kv storage temperature t stg -55~125 c note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? recommended operating conditions over operating free-air temperat ure range (unless otherwise noted) parameter symbol min typ max unit supply voltage v cc_video , v cc_ddc , v cc _ sync 0 5.5 v io voltage videox pins v io ( video ) 0 v cc _ video v input voltage sync pins v i ( sync ) 0 v cc _ sync v input voltage ddc_inx pins v i ( ddc ) 0 5.5 v output voltage ddc_inx pins v o ( ddc ) 0 5.5 v operating temperature t a -40 85 c
VGA7S019 preliminary tvs unisonic technologies co., ltd 6 of 7 www.unisonic.com.tw qw-r223-024.b ? electrical characteristics over operating free-air temperat ure range (unless otherwise noted) parameter symbol test conditions min typ max unit v cc_video supply current i cc_video v cc_video =5v, video inputs at v cc_video or gnd 1 10 a v cc _ ddc supply current i cc _ ddc v cc _ ddc =5v 1 10 a v cc_sync supply current i cc_sync v cc_sync =5v, sync inputs at gnd or v cc_sync , sync outputs unloaded 1 50 a sync inputs at 3v; sync outputs unloaded 2.0 ma video input/output pins i io _ video v io _ video =3v 0.01 1.0 a ddc pin power down leakage current i off v cc_ddc 0.4v, v ddc_out =5v 0.01 1.0 a diode forward voltage for lower clamp of video, ddc, sync output pins v d i d =8ma, lower clamp diode -0.6 -0.8 -0.95 v dynamic resistance (video pins) r dyn_video i=1a 1.0 ? high-level sync logic input voltage v ih v cc_sync =5v 2.0 v low-level sync logic input voltage v il v cc_sync =5v 0.6 v high-level sync logic output voltage v oh i oh =0ma, v cc_sync =5v 4.85 v high-level sync logic output voltage VGA7S019-15 v oh-15 i oh =24ma, v cc_sync =5v 2 v low-level sync logic output voltage v ol i oh =0ma, v cc_sync =5v 0.15 v low-level sync logic output voltage VGA7S019-15 v ol-15 i oh =24ma, v cc_sync =5v 0.8 v sync driver output resistance VGA7S019-15 r t v cc_sync =5v, sync inputs at gnd or 3v 15 ? VGA7S019-55 55 ? VGA7S019-65 65 ? io capacitance of video pins c io_video v io =2.5v 2.5 4 pf sync driver l =>h propagation delay t plh c l =50pf; v cc =5v, input t r and t f 5ns 12 ns sync driver h =>l propagation delay t phl c l =50pf; v cc =5v, input t r and t f 5ns 12 ns sync driver output rise & fall times t r , t f c l =50pf; v cc =5v, input t r and t f 5ns 4 ns video esd diode break-down voltage v br i io =1ma 9 v
VGA7S019 preliminary tvs unisonic technologies co., ltd 7 of 7 www.unisonic.com.tw qw-r223-024.b ? typical application circuit r t vga controller 0.22f 0.1f 3.3v 5v 0.1f 5v 5v 5v r p r p byp v cc_ddc v cc_vdeo v cc_sync video1 video2 video3 sync_in2 sync_in1 ddc_in2 ddc_in1 sync_out2 sync_out1 ddc_out2 ddc_out1 utc VGA7S019 0.1f red green blue hsync vsync ddc_clk ddc_dat vga connector r p : pullup resistor for the ddc data and clock lines. typically system designer selects 47k ? pullup values r t : line termination resistor for the rgb lines. rt is se lected to match the transmission line. for a single-ended transmission line, rt can be anywhere from 50 ? to 75 ? depending on board trace impedance. some systems may require additional filters at the sync and rgb lines. the utc VGA7S019 should be placed as close to the vga port as possible. the esd protection channels video1, video2, video3 ar e identical circuits, they can be used interchangeably between the r, g, b signals. utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
|
