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high-power led driver with integr ated pwm dimming mosfet driver gen e ral description SM8205 fea t ures wide inp u t op erati ng v o lta ge ra nge from 8 v to 48 v inte rnal 2% refe renc e vo ltag e inte grate d pwm di mmi ng n-ch anne l mo sfet driv er dimmi ng ra tio: 1 000 :1 100 khz to 1 m hz pro g ramm able hig h -freq uenc y op erati o n program mab l e s l op e co mpen sat i on inp u t un der-vo l tag e pro t ect i on led sh ort-circ uit p r otec tion (scp) led ope n-vo ltag e prot ecti on (o vp) ju ncti on o v er-te m pera t ure s hutd o wn pro t ecti on dr i v ers leds in boost, buck-boost, sepic topology cycl e-by-c yc le c u rrent l i mi t soft start provi d ing sop-16 package sin g le -s tring led lcd back lig htin g high power l e d d r ive r s dc/dc boo s t / bu ck-boo s t converter auto moti ve or ind u stri al appl ic ations typical applicat ion cir cuit www.s amh op.c o m.tw 1 re v. 2. 0 @ 20 11/1 0 the sm82 05 is a curren t m ode co ntrol wide -inpu t vo ltage (8v to 4 8 v) led driv er ic spe c ifi c al ly d e si gned to power o ne or mu lti-s t ring s o f hi gh power l e ds . the 10v ga te driv er all o w the us e of s t and ard lev e l mo sfet . the l o w v o lt age 5 . 0v v cc is use d to po we r t he in terna l log i c a nd al so a c ts a s a re ferenc e vo ltag e to s e t the cu rre n t leve l. an e x te rn al resi sto r se ts the ad jus t able switc h in g f r e que ncy o f th e sm 820 5. the switc h ing frequ enc y c an b e be tween 100khz and 1mhz to opt imiz e effi cie n cy , perform anc e or exte rnal c o mpo nen t siz e . this co ntroll er us es a p eak -curren t co ntrol sc heme (wi t h p r ogram mabl e s l op e c o mpe n sa tion ), an d i n cl udes an in ternal tra n sc ond ucta nce a m pli f ier to co ntrol the out put cu rrent in c l os ed lo op, e nabl ing h i gh o u tpu t cu rre n t acc u rac y . pro g ram m abl e mosfet curre nt limi t ena ble s c u rrent limi t ing duri ng i nput und er-vol tage and out put ov erloa d co ndit i ons . an inte rnal 8 v 48 v l i ne ar regu lato r powers the ic, elim ina t ion the nee d for a se parate po wer sup p ly for th e ic. th e sm8 205 prov ides a ttl c o mp atib le pwm di mmi ng in put th at ca n ac cep t an ext e rnal co ntrol sig nal with a d u ty ratio of 0 100 % and fre que ncy o f u p to a few k ilo hertz . th e sm 820 5 also prov ide s a fault ou tput whic h can b e u s ed to dis c on nec t th e l e ds in c a se of a faul t c ondi tion , u s ing an ext e rnal dis c o nnec t n-cha nne l mo sfet. the sm82 05 als o o ffer th e fo llo wi ng protec tio n fu ncti ons : led o pen pro t ect i on (ovp), led s hort-c i rcu i t protec tion (scp), jun c tio n ove r -te m pe rature sh utdo wn an d inpu t und er vo ltag e lo cko ut (uvlo ) . l1 d1 q1 vin 8v to 48v c in vcc ss rt clim pw md com p ir e f gnd fdbk ovp sc fault cs gate vdd vi n 5 6 7 8 9 10 11 13 12 14 15 16 c dd r slope rcs q2 rs c r l1 cout rsn r co mp c comp r t r l2 r r1 r r2 r ovp1 r ovp2 1 2 3 4 c cc
SM8205 pin assignments 1 2 3 4 5 6 10 7 8 9 11 12 13 14 15 16 vcc ss rt clim pwmd co mp iref gn d fdbk ovp sc fault cs gate vdd vin or de ri ng in fo rm a t ion pin description s sop-16 (top view) de scription pin no. na me 5v lo w-dro pout vol t age regu lato r. bypa ss t o gnd with a t lea s t a 4.7 u f lo w-esr cera mic cap a ci tor. it p r ovi des 2% a ccu rate re ference volt a ge to external iref and cl im te r m ina l use for sett ing con t rol lo op re feren c e. 1 vc c 2 ss soft-sta r t tim e prog rammi ng p i n. con nec t ca pac itor fro m ss pi n to g n d t o prog ram c onv erter soft - s tart ti me. 3 rt co nnec t a re sis t or from rt to g n d to progra m the switc h in g freq uenc y. this pin prov ides a p r ogram mabl e in put curren t lim it fo r the c onv erter. th e c u rrent l i mi t can be set by u s in g a re sis t or di vid e r from the vcc pin , so ft-sta r t can als o be prov ide d us ing this pin . 4 clim 5 pwmd pwm dim m in g inp u t. hig h le vel is norma l op eratio n, whe n is pul led to g n d or l e ft o pen, switc h ing of th e sm82 05 i s d i sa bled . 6 co mp erro r-a m pl ifier o u tpu t. conn ect an rc network from co mp to g n d f o r sta b le ope ra tion . 7 iref the v o lta ge a t thi s pi n s e ts t he o u tpu t curre nt le vel . the curren t refere nce can be set u s in g a resis t or d i vi der from vcc pi n. 8 gn d g r ound return for all circuit. 9 fdbk led curren t se nse inp u t. conn ect a se nse resi sto r from l e d s t rings to g n d t o regu late led outp u t c u rrent. 10 ovp ov er-vol tage prote c tio n se nse inp u t. wh en th is p i n v o lt age exc eeds 1.2 v , the gate ou tput of th e sm820 5 is turne d of f and faul t goe s lo w. the i c wil l turn on a gain un til i nput power i s rec ycl ed. 11 sc slope co mpen sati on f o r cu rre n t s ens e. a res i sto r betwee n sc and gnd wi ll p r ogram the slo pe com pens ati on. 12 fault extern al d i mmi ng m o sfet ga te dri v er. th is p i n i s p u lle d to grou nd whe n the r e is an o u tpu t sh ort circ uit o r outp u t o v er v o lta ge fa ult c ond itio ns, and then dis c on nec t the loa d from vol t age so urce. 13 cs cu rre n t s ens e po siti ve i npu t. conn ecte d to exte rnal curren t sen s e re sis t or whic h i n turn is con nec ted t o the sou r ce o f the ext e rnal power n-mo sfet as wel l as an exte rnal s l op e com pens ati on res i s t or. 14 gate out put g a te d r ive r pin to dri v e a n ex terna l n-cha nne l po wer m o sfet. 15 vd d this pin is a regu late d 10 v sup p ly for two g a te d r ive r (g ate an d faul t), it m u st b e by pas se d wi th a low-esr c e rami c c apac ito r at le ast 1.0u f to g n d. vin 16 power sup p ly inp u t p i n. vo ltag e in put ra nge from 8 v to 46 v, pla c e a by pas s ca pac itor 1 u f 10u f to gro und as c l os e to the dev ice as p o ss ibl e in the circ uit b oard layo ut. par t number ma rk i n g sm 8205 sl xx xxx x sm 820 5sl tube 50 2 www.s amh op.c o m.tw re v. 2. 0 @ 20 11/1 0 note : the let t e r ?s? i s mark ed f o r sop p a ckage, and lett e r ? l ? i s m a r k ed f o r lead fre e par t s .
SM8205 abso lute maximum ratings par a meter ra t i ng all o t her p i ns to g n d vi n to gnd v v dd to gnd v v cc to gnd v units 50 11 5.5 gate , fault to gnd 11 v 5.5 v j unc tion temp eratu r e 15 0 j unc tion to amb i en t therm a l im ped anc e ( ja ) 10 2 / w o pera t ing jun c ti on te mpera t ure ran g e -40 + 125 sto r age tempe r ature ra nge -65 + 150 l ead temp erature (solde ring, 10s ec) 26 0 s t res s es be yo nd tho s e li s t ed un de r ? a b s o l u t e ma ximu m ra ting s may ca us e pe r m an en t da mag e t o t h e de vi ce . th es e a r e str e ss rat i ngs only , and f u n c t i onal ope r a tion of t h e device at these or any other conditi ons beyond those i ndicates in the ope r a t i on al sec t ions of the specifi c ati o n s is not i m plied. e x posu r e to m a ximum r a t i ng con d it ions for extende d peri o d s may af fec t devi c e rel i abi li t y . recomm ended oper ating conditions par a meter min units i nput volta g e 8 v symbol vin max 48 o pera t ing frequ enc y f osc 100 10 00 khz o pera t ing ambi ent te mpe r a t ure t a -20 85 elec trical ch arac terist ic s paramet e r symbol min typ ma x units condi t i ons the typ i ca lly test ing v a lu es are at v in = 12v, t a =25 , unles s o t herwis e no ted. in p u t v in inp u t dc sup p ly vol t age range 9 48 - v inpu t to v in pi n vo l t ag e i q qu ies c en t cu rr e n t - 1.9 2.2 ma p w m d =0 , no sw it c h in g i n t e r n al regulator v dd inte rnall y reg u la ted v o lta ge f o r ga te d r i v er 8 10 11 v 12v v in 48 v v in -1 8v v in 11v uvlo v dd u nde r-v o lta ge l o ck out thres hol d 6.8 7.4 v uvlo v dd u nde r-v o lta ge l o ck out hys t eres is 50 0 mv refe re nce v cc v cc pi n vo l t ag e 5.0 0 4.90 5.1 0 v v cc p i n c onn ecte d a 10uf ca pac itor t o gnd, i cc =0, pwmd =0 v cc(line ) lin e reg u lat i on of th e v cc volt age 0 - - - - - 20 mv v in =8 48v, pwm d =0 v cc(lo ad) loa d reg u la tion of th e v cc vol t age 0 - 15 mv i cc =0 3ma, pwmd =0 3 www.s amh op.c o m.tw rev . 2. 0 @ 20 11/1 0 v dd rising - v dd fa lli ng
elec trical ch arac terist ic s the typ i ca lly test ing v a lu es are at v in = 12v, t a =25 , unles s o t herwis e no ted. SM8205 symbol paramet e r min typ ma x units condi t i ons pwm d i mming v pw md (l o ) 0.8 - v - v pw md (h i ) pwm in put l o w vol t age pwm in put hig h vo ltag e 2.0 v - - r pw m d pwm pi n pu ll-do wn resi stan ce 90 10 0 13 0 k ? o ver volta g e protection v ovp ov er-vo l tage thres hol d 1.15 1.2 0 1.2 5 v ovp rising o sci llator fosc swi t ch ing f r e que ncy r t =91 0 k ? r t =30 0 k ? khz khz 10 0 30 0 11 0 90 33 0 27 0 d ma x max i mu m du ty c ycl e 92 % - - error a m plifier gb ga in b and wid t h p r o duc t 2.5 mh z - - 75p f cap a ci tanc e a t co mp p i n a v op en l oop gai n 73 - - db ou tput open ( n o t e1) v o ou tput vol t age range v cc =5 .0v 0.3 4.9 5 - g m trans con duc tanc e 63 0 - - v ua/ v gate drive r i g - sourc e i g - sink ga te short-ci rcui t curre nt ga te s i nk ing curren t 60 31 0 ma ma - - - - v ga t e =0 v, v dd = 10v v ga t e =1 0v, v dd =10v t g - rise t g - fa l l ga te dri v er o u tpu t rise time ga te dri v er o u tpu t fal l tim e 35 ns 50 - - 20 35 ns c l =100 0pf, v dd =1 0v c l =100 0pf, v dd =1 0v i f - s o urce faul t pi n sh ort-circ uit curren t 45 ma - - - - ma 60 i f - si n k faul t si nki ng c u rrent v fa ul t =0v, v dd =1 0v v fa ul t =10 v , v dd = 10v t f - ri s e t f - fa ll faul t driv er ou tput rise time faul t driv er ou tput fall time c l =100 0pf, v dd =1 0v c l =100 0pf, v dd =1 0v 16 5 ns ns 14 5 slope com p ensat i on v s c (p ea k) sc pin peak vo ltag e 1.5 v r t =91 0 k ? , r sl op e =30 k ? - - - - - - i slo p e current s ourc e ou t of sc pi n 0 10 0 - ua g sl o p e internal current mirror ratio 1.8 2 2.2 r cs =1k ? , r sl ope = 30k ? output shor t-circuit t of f(s.c) propa gati on ti me fo r sho r t-circ uit d e tec t ion ns 20 0 - - i re f =400 mv, f db k =0 -1 v, faul t goe s fro m hi gh to low g ire f ampl ifie r gain at iref pi n i re f =400 mv 2 2.1 1.7 - - ( c ontinued) current sense t pd propa gati on d e lay tim e 15 0 - - ns o vp= 0- 2v s t ep t bl ank lea din g ed ge b l an king 10 0 ns - - t delay delay to o u tpu t of pwm com parat or 15 0 ns - - co mp =c lim = v cc , vc s=0-600mv step ther m al protection t sd t hys therm a l s hutd o wn tem pera t ure therm a l s hutd o wn hy ste r e s is 14 0 40 - - - - not e1: guara n teed by des ign 4 www.s amh op.c o m.tw rev . 2. 0 @ 20 11/1 0
SM8205 5 www.samho p .com.tw re v. 2. 0 @ 20 11/1 0 tes t co ndi tion s v in =12v, c vcc = 10uf, c vdd =1 . 0 uf , r t =91 0 k, t a =25 , un les s ot herwise not ed. typica l operation ch ara cterist i c pwm d = 0v
SM8205 www.samho p .com.tw re v. 2. 0 @ 20 11/1 0 6 10% t o 9 0 % 9 0 % to 10 % f pw m =1khz typic a l opera t ion c hara cteristic tes t co ndi tion s v in =12v, c vcc = 10uf, c vdd =1 . 0 uf , r t =91 0 k, t a =25 , un les s ot herwise not ed.
SM8205 b l oc k di agr a m 2 di s 10 0k 1. 2 v dis po r q q r s os c dis 1 : 2 ra m p 10 0ns bla n k i ng r s q 10 v ld o 5v ld o uvl o po r 6. 5v /7v vdd gate fault ovp gn d pw m d co mp iref fdbk rt sc cs clim vc c vin e.a pwm c o mpa r at or cu r r e n t- limit c o mpar ato r to in tern al circ u i t 7 www.s amh op.c o m.tw rev . 2. 0 @ 20 11/1 0 / 7 ss dis 10u a
SM8205 basic ope r ation o vervie w the sm820 5 is a curren t -mode , hi gh-bri ghtn e ss led driv er de sig ned to con t rol a s i ngl e-stri ng l e d curren t regu lato r with t w o e x te r n al n-cha nne l mosfets. it int egrate s all t he bu ildi ng bl ock s nec ess a ry to i m pl emen t a fi xed - freque ncy , pe ak-c urrent-m ode con t rol with prog ra mma ble s l ope comp ens atio n to co ntrol th e duty cy cle of t he pwm con t roll er. the sm82 05 allo ws imp l em enta t ion of di fferen t c onv erter topo log i es s u ch as sepic, bo ost, buck -b o o st , buck regul ator. b a sic ope ratin g dis c us sio n that fo llows it will b e hel pful to re fer to th e bl ock di agram of th e ic. in norma l o perati on wi th th e pwmd p i n low le vel , the gate a nd fault p i ns are d r iven to g n d, the co mp pin i s hig h impe dan ce to sto r e the prev iou s switc h ing sta t e o n th e e x tern al c o mp ens atio n c apa cito r, and the fdbk pin bi as curren t is red u ce d t o le aka ge lev e ls . when t he pwm pin t r a n si tion s hig h lev e l, th e gate pin trans itio n hi gh aft e r a sh ort-del ay. at th e sa me tim e , the int e rnal os ci llat o r g ene ra tes a pu lse to s e t the sr l a tch , turni ng on th e exte rnal po we r mo sfet s w itch (g ate goe s hig h ), a vo ltag e i npu t p r o porti ona l t o th e switch cu rre n t, s ens ed by an exte rnal curre nt s ens e res i s t or co nnec ted from cs an d g n d. this v o lta ge is add ed to a sta b ili zin g s l op e co mpe n sa tion ramp and the resu ltin g is fed i n to the pos itiv e termi nal of th e pwm com parat or. the cu rre n t in the ext e rnal in duc tor i n cre a se s s t ea dily duri ng th e time the s w i t ch is on . when this non -i nve r sion inp u t v o lta ge exc eed s i n ve rs ion in put vol t age of the error amp lifi e r e.a, the sr latc h i s res e t and the ex terna l power swi t ch i s tu r n ed o ff. during the swi t ch off ph ase , t h e i n du c t or c u r r en t de c r e a s e s. at th e co m p l e t i o n of eac h os cil l ato r cyc le, i n tern al si gna ls s u ch as s l ope co mpen sati on retu rn to t heir sta r ting po int an d a new cycle beg ins wi th th e se t pul se from th e oscil l ato r . minimum input voltage at vin pin the sm8 205 con t ain s two int e rnal h i gh -volt age s t artup regu lato r t hat al lows th e vin pin to be c onn ecte d dire ctly to line v o lta ge as hig h a s 4 6 v. th e 5 v lo w dropo ut l i ne ar regu lato r v cc , is u s ed to power in terna l pwm con t roll er, co ntrol l ogi c, erro r a m pl ifie r a nd a s th e refe re nce for the led outp u t cu rrent as well a s to s e t s w i t ch c u rrent l i mi t. in a ppli c ati on, c onn ect a by pas s ca pac itor fro m thi s pin to g n d, the re com m en ded c apa cita nce range is fro m 4.7 u f to 10uf. anoth e r 10 v ldo reg u la tor v dd , i s f o r ex ternal po we r mosfets driv er, o n th e c ondi tion tha t v in 12v, th e regu lato r g enera t es a 1 0 v sup p ly . if 7v v in 1 1 v, t he v dd is eq ual to v in m i nu s d r op vo ltage ac ro ss by pas s switc h . w h en the v o lta ge on the vdd pin reac hes t he risi ng thre sho l d of 7v, the g a te d r ive r is ena ble d . the g a te d r i v er will rem a in e nab les u n til v dd fal l s be low 6.5 v . co nnec t a by pas s ca pac itor fro m this pin to gnd, the reco mme nded ca pac itan ce rang e is from 1.0u f to 10 uf. gate drive r voltage (v dd ) the sm820 5's 10 v ldo reg u lato r p o wers up the switch ing mosfet d r i v er. us e at l eas t a 1 u f low-esr ceram i c c apac itor from v dd to gnd fo r b e st perform anc e. care ful cho i ce of a l o wer q g fet wi ll all o w high er switc h ing freque ncy , lea d ing to sma lle r magn etic s. the vdd pin h a s it o w n u nde rvol tage dis able (uvlo ) s e t to 6.5v (typ ica l val ue) to prote c t the exte rnal mosfet f r o m e xce ssi ve power d i ss ipa t ion cau s ed by n o t b e ing ful l y e nha nced . control and ref e rence v o l t age (v cc ) the sm8 205 h a s a 2 % ac curat e , 5v refe re nce , v cc . it provi des po we r to mos t o f th e i n terna l c i rcu i t b l oc ks exc ept for the g a te driv ers. it als o can b e use d as the re feren c e for the l e d ou tput c u rrent as wel l as to s e t the switch cu rre n t l i mit throu gh a resi sto r div i der. co nne ct a at le ast 4.7u f cera mic cap a ci tor from v cc to gnd. oscill ator and swi t ching frequency (r t ) the in terna l osc ill ator of t he sm82 05 i s prog ramma ble from 10 0khz to 1 m hz us ing a sin g le re sis t or at r t , d o not l eave this pin ope n. use th e fol l owing formu l a to cal c ula t e th e r t value (1% resistors) : f osc (khz ) * 11 * 10 -9 1 r t f osc (k hz ) r t (k ? ) tab l e 1 . op erati ng freq uen cy se lec t ion 10 0 20 0 30 0 10 00 60 0 50 0 91 0 45 5 30 3 91 15 2 18 2 no te: hig her f r e que ncy op erati on yiel ds sma lle r com pone nt si ze b u t in crea ses switch ing los s es and gate drivi ng c u rrent, a nd m a y n o t al low suf f ici entl y hi gh or l o w duty cy cl e o perati on. lower frequ enc y o perat ion giv e s bette r pe rforma nce an d effic i en cy bu t h a s la rger exte rnal com pone nt s i ze . soft -start (s s) the so ft-sta r t f eatu r e allo ws the led out put c u rrent to gradu ally reac h th e led cu rre n t?s rate , the r e b y re duc ing start-u p stres s e s an d inp u t su rge c u rrent. at p o wer up, after th e v cc an d in put un der-vo l tag e lo cko ut thre sho l ds are s a tis f ie d, a n in terna l 1 0ua c u rrent so urce cha r ges an exte rnal capa cit o r co nnec ted to th e ss pin . the cap a cit o r v o lta ge wi ll ramp up sl owly and will li mit the co mp pi n vo ltag e an d th e switc h c u rrent. 8 www.s amh op.c o m.tw rev. 2.0 @ 2 011 /10
SM8205 over-voltage protection ( o vp) ov er v o lta ge prote c tio n i s ach i ev ed by con nec ting the out put v o lta ge to the o vp pin throug h a re sis t or di vid e r. the vo ltag e at the o vp p i n is c ons tantl y com pared to the i n tern al 1. 2v. when the ou tput vol t age a t led load termi nal is e xce ede d 1 . 2v, the ic i s t u rned of f, imm edi atel y, at the s a me ti me the g a te a nd fault pin s goes l o w. power on aga in to resu me this s i tua t ion . the outp u t v o lt age can be se t by s e lec t ing the v a lue s o f r1 and r2 (see figu re 1) a cco rding to th e fol l owing equ atio n: r1 r2 v out ovp sm8 205 r2 r1+r2 1.2 ? v out = fi gure 1. o v er-v olta ge p r o t ec tion resis t or c onn ecti on 1. 2v pwm dimming (pwmd) pwm dim m ing can b e ac hiev ed b y driv ing t he pwmd p i n wi t h a ttl c o m p at i b le s o ur ce . th e pwm s i gn a l i s co nnec ted in ternal ly to the thre e d i ffe re nt node ? the trans con duc tanc e a m pl ifie r, the faul t ou tput, and the g a te ou t p ut . when the pwmd sig nal is hi gh, th e gate an d fault pin s are e nabl ed, a nd the outp u t of the ea a m pli f ier is co nnec ted to t he ex terna l com pens ati on net wo rk . thus , the int e rnal amp lifi e r c ontrol s th e l e d c u rren t. whe n the pwmd s i gna l goes l o w, t he outp u t of the ea ampl ifie r is dis c on nec ted fro m the co mpe n sa tion n e twork. so, the int egrati ng ca pac itor ma inta ins th e vol t age acros s it. the gate i s d i sa bled , the co nve r ter st ops switc h ing an d the faul t pin g oes low, turn ing o ff the dis c onn ect switch . by turni ng off th e dis c on nec t switch a c tio n , the o u tpu t ca paci t or is pre v ent ed fro m be ing dis c ha rged, and thus the pwm dim m ing resp ons e of the b oos t co nve r ter imp r ovs drama t ic ally . when the v o lta ge at pwmd is greate r than 2 . 0v, the pwm di mmin g m o sfet turn s o n an d when the vo ltage on pwmd is bel ow 0.8v, t he pwm d i mmi ng mo sfet turns off. led cur r ent refer e nce (iref) the l e d c u rren t is p r opo tion al to the v o lt age at iref. appl yin g an ex terna l dc vo ltag e a t iref or usi ng a pot enti onme t er from iref to gnd allo w a nalo g dim m ing of th e led c u rrent. g a te driver (ga t e) ex terna l m o sfets are d r i v en by the sm82 05's inte rnal low im ped anc e ga te drive r . the s e drive r are bia s ed from the v dd a nd h a ve a sou r c e cu rre n t of 1 50ma a nd a s i nk curren t o f 30 0ma, to switc h a gro und -re f erenc ed n- cha nnel mo sfet in h i gh -p ower ap pli c ati ons . the ave r a ge c u rrent dema nde d from the s upp ly to drive the exte rnal mo sfet dep ends o n th e to tal gate c harge (qg ) and th e o pera t ing freq uen cy of th e con v erte r, f sw . use the fol l owin g equ atio n to ca lcul ate th e driv er sup p ly current i gate re qui red fo r the s w itch ing mosfet: dimming mo sfet driver (fau lt) i gate = qg x f sw the sm 8205 req u ires an ex ternal n-cha nnel mo sfet for pwm d i mmi ng. conn ect th e gate o f t he mo sfet to the outp u t of the dim m ing d r i v er, faul t, f o r no rmal opera t ion . the d i mm ing drive r is c apa ble of s ourci ng o r sin k ing up to 50 ma of curren t. led current-sense input (fdbk) the c u rren t thro ugh the led stri ng is set via the va lue cho s en f o r the c u rrent sens e res i sto r , rsn. thi s va lue can be c a lc ula t ed u s in g eq uati on o f bel ow: v ire f r sn i le d = fdbk r sn fault SM8205 i le d c ou t fig u re 2 . led forward curren t contro ls pat h an othe r im porta nt param eter to be aware of in the bo ost con t rolle r d e si gn, is th e rippl e curren t. the amo unt of ri ppl e c u rrent throu gh t he led strin g i s e qual to the outp u t ripp le v o lta ge d i vi ded by l e d ac resi stan ce (r le d is pro v ide d by t he led manu fac t urer) plu s the c u rrent sen s e and r on o f th e m o sfet resis t or. the am ount of allo wa ble ri ppl e cu rre n t th rough the led string is depe nde nt up on th e ap pli c ati on a nd d e si gn?s dis c ret i on. the e quat ion is s hown a s be low: v out(ripp l e ) r le d + r on + r sn i le d = 9 www.s amh op.c o m.tw rev. 2.0 @ 2 011 /10
SM8205 slope com p ensation ( s c) the sm82 05 us es an in ternal ram p vol t age ge nera t or (typ ical ly a t 1.5v pe ak ) f o r slo pe co mpe n sa tion , by an ex ternal res i s t or c onn ects sc p i n to gnd to ge nerat e a resp ecti ve ram p curren t sou r c e for sl ope c o mp ens ation us e. in a fi xed ope rating freq uenc y, slop e c o mp ens ation is nec ess a ry, partic ularl y , the o pera t ing duty cy cle grea ter than 0.5. c hoo sin g a sl ope c o mp ens atio n which is one-h a lf o f the down s l op e of t he in duc tor c u rrent to ens ure t he s t abi lity ope ratio n . 1 : 2 ramp sc cs 1. 5v/t r sl ope figu re 3. the fu ncti ona l bloc k o f the ra mp curren t slop e com pen sati on ca n be p r o g ram m ed b y two resi stors rslope a nd rsc. ass u mi ng a down slo pe o f ds (a/ua) for t he ind u cto r cu rrent, the slope co mpen sati on re sis t ors can be c o mp uted as: 10 ? r sc ds ? 10 ? ts ? r cs 6 r sl ope = a typica l value for r sc is 62 0 . current sense (cs) 100ns bl anki n g the curre nt s ens e i nput of the sm82 05 b u il t-in a 1 00ns (typ ical , se e fig u re 3 . ) bla n ki ng ti me t o prev ent spu r ious turn o ff due to the i n iti a l c u rrent s p ik e when th e ex terna l power mo sfet tu rns on . sm 820 5 inc l ude s two hig h - sp eed c o mp arator ? one i s us ed du ring n o rma l ope ratio n , na mel y is pwm c o mpa r ator, a noth e r on e is us ed to limi t th e max i mum in put cu rre n t durin g inpu t und er-vol tage or ov erloa d c ondi tion s, whic h n a mel y is cu rre n t-lim it c o mpa r ator. the sm820 5 in tegra t es an i n tern al re sis t or di vid e r net work , whi c h step s down the vol t age at the com p pin by a fac t or of 7 (see ic? s bl ock dia g ram). th is s t eps down v o lta ge is fed to one o f the pwm c o mpa r ator as the cu rre n t re feren c e. the refere nce to the oth e r co mpara t ors (cu r re nt-lim it co mpara t or), wh ich a c ts to lim it th e ma ximu m in ductor current, is g i ve n externa lly. it i s rec o mm ende d th at th e s ens e res i sto r rcs be ch osen s o as to prov ide ab out 250 mv c u rrent s ense sig nal . current limit (clim) the sm 820 5 fe atures a cu rre n t l i mit prote c ti on f eatu r e to preve n t a n y curren t runa wa y c ond itio ns. cu rre n t l i mit has to be s e t b y a resis t or d i vi der fro m the v cc (5 v ) re feren c e av ail able o n the ic. assu ming a m a xi mum opera t ing indu cto r c u rrent i pk (inc lud i ng t he rip p le curren t ), the vol t age at th e clim pin can set as: v clim 1.2 ? i pk ? r cs + 5 ? r sc ( ) r sl ope ? d ma x no te that th is eq uati on as su mes a c u rrent l i mit a t 1 20% of the ma xim u m in put c u rrent. als o , if v clim i s gre a t er than 450m v, the s a tu ra tion of th e int e rnal e.a ampl ifie r wil l d e termi ne the l i mi t on the inp u t c u rrent ra ther than the cl im p i n. in s u ch a cas e , the sen s e re sis t or r cs sho u ld be red u ce d til l v clim re duc es b e lo w 4 50m v. inter n al transconductance er ror amplifier the sm 820 5 h a s a buil t -in trans con duc tanc e ampl ifie r use d to am pli f y the error sig nal insi de th e fee dba ck l oop. the am pli f ied curren t -sen se s i gn al is con nec ted t o the nega tiv e inp u t of th e g m a m pl ifie r with the c u rrent re feren c e c onn ecte d to iref. the o u tpu t of th e op -amp is con t rolle d b y the inp u t a t pwmd. wh en the si gnal at pwm d is h i gh, th e outp u t of the op -a mp co nne cts to co mp; wh en the si gna l a t pwmd is low, the ou tput of the o p -am p di sco nne cts from co mp to kee p th e ch arge on the com pens atio n ca pac itor. whe n the v o lta ge at pwm d goe s h i gh , th e v o lta ge on the co mpe n sa tion cap a cit o r fo rc es the co nve r ter i n to a s t ead y s t ate . com p is con nec ted to the ne gativ e inp u t o f th e pwm com parato r with cmo s inp u t throu gh a bu ffer, forward diod e an d 7:1 resi sto r d i vi der, whi c h d r aw a sm all curren t from th e c o mp ens atio n c apa cito r at comp and thus prev ent dis c h a rge of th e c o mp ens atio n c apa cito r wh en th e pwmd inp u t i s lo w. fault protection the sm8 205 i n cl udes a ou tput o v er-vo l tag e and led sho r t - c i rcu i t p r otec tion s. bo th p r otec tion fea t ures are latc hed , wh ich me ans that the power to the ic mus t be r e cycled to rese t t he ic. the ic a l so b u il t-in a fault pin wh ich g oes l o w d u rin g any f ault c ond itio ns. at st art-up, a mono sho t circ uit (trig ger by po r th e circ uit), res e t an inte rn al sr f ilp-fl op whi c h cau s es faul t to g o h i gh, and rem a in s hig h du ri ng no rmal o perat ion. th is a l so allo ws th e g a te dri v e to func tion n o rmal ly. this p i n can be us ed to driv e an ex terna l switch q 2 (see t y pi cal appl ica t ion o n pag e 1 ) , whi c h will d i sc onne ct the l oad durin g a fau l t co ndit i on. th is di sc onne ct swit ch is very impo rtant in a boo st co nve r t e r, as tu rn ing o ff the switch ing msofet (q 1) du ring an o u tpu t sh ort-ci rc uit con d itio n will not rem o ve the fa ult (q 1 is not i n the path of th e fau l t c u rrent), the disc onn ect switc h will hel p to dis c onn ect the sho r t ed l oad from th e in put. 10 www.s amh op.c o m.tw rev. 2.0 @ 2 011 /10
SM8205 led short - circuit protection the l e d s hort-ci rcui t con d iti on is ind i ca ted by faul t. at start-up , a mono sho t c i rcu i t (trigg ered by th e por circuit), rese t an in terna l sr fl ip-flo p, whi c h cau s es faul t to go high , an d re main s h i gh duri ng n o rma l ope ratio n . thi s als o al lows th e g a te d r i v er to func tion norm a lly . th e stea dy sta t e curren t i s re flec ted in the refere nce v o lta ge c onne cte d to the t r a n sc ond uct ance amp lifi e r. th e ins t anta neo us out put cu rre n t is se nsed from fdbk te rmina l o f the op-a m p. th e s hort-c i rcui t thres hol d c u rrent is in ternal ly set to 200 % of the st eady sta t e c u rrent. du ring sho r t-circ uit c ond itio n, whe n the cu rre n t ex ce eds the i n tern all y se t thre sho l d, t he sr fli p - flo p is s e t an d faul t g oes low. mea n whil e, the g a te driv er o f the power mo sfet is i nhi bite d, provi d in g a lat c hin g p r o t ec tion . the con v erte r ca n be rese t by cy cli ng th e in put v o lt age for op eratin g ag ain . current sense filter cs r cs ga t e sm82 05 d1 c in paras i tic ci rc uit cap a ci tanc e, i ndu ctan ce a nd gate driv er cu rre n t c r eate a sp ike in the c u rrent sen s e vo ltag e a t the poi nt where q1 turns on. in ord e r to p r e v en t thi s s p ike from te rmina l the o n -tim e prema t urel y, ev ery c i rcui t sh ould ha ve a low-pas s f ilte r tha t c onsi s ts of r f a nd c f , sh own in fig u re 4 . the tim e c ons tant of th is filte r sh ould be lon g enou gh to redu ce the para s iti c spi k e wi thou t sig n ifi c an tly affec t ing the s hap e of th e ac tual curren t se nse vol t age . the reco mme nde d ran ge fo r r f is bet wee n 10 ? and 500 ? , an d c f is b e tween 100 pf and 2.2 n f. fi gure 4. add i ng a lo w-p a ss filt er to p r eve n t p r e m atu r e trig gerin g r f c f q1 vi n thermal shutdown intern al t herma l sh utd o wn ci rcui try is pro v id ed t o pro t ect the sm820 5 i n t he eve n t t hat the max i mu m j unc tion temp erature i s exc eed ed. when a c ti vate d, typ i cal l y at 140 , the cont ro lle r is force d to dis abl e th e ou tput gate an d fault d r i v ers in low-sta t e. afte r the temp erature is re duc ed (t ypi c al hys t eres is is 2 5 ) the gate driv er wi ll b e re-en abl ed. 11 www.s amh op.c o m.tw rev. 2.0 @ 2 011 /10
SM8205 application circuit 1 ? for a boost dc to dc converter vi n r cs q1 r sl ope r sc c dd ov p v out fdb k sc fa ul t cs ga te vd d v in r t vc c ss rt cl im pwm d com p ir ef gn d d1 l1 r fd1 r fd2 r p1 r p2 c o c in c cc r 1 r 2 r 3 r 4 r com p c co mp 16 15 14 12 13 9 10 11 1 2 3 4 5 6 7 8 sm820 5 a ppli cation circuit 2 ? for a speic led d r iver vi n r cs q1 r sl o p e r sc c dd ov p v out fd bk sc fa u l t cs ga te vd d v in r t vc c ss rt cl im pwm d co mp ire f gn d d1 l1 r p1 r p2 c o c in c cc r 1 r 2 r 3 r 4 r co mp c com p 16 15 14 12 13 9 10 11 1 2 3 4 5 6 7 8 sm82 05 l2 c1 r sn 12 www. s am hop. com .tw rev. 2.0 @ 2 011 /10
pack age d i m e nsions SM8205 16 pin sop SM8205 13 www.s amh op.c o m.tw rev. 2.0 @ 2 011 /10 16 9 1 8 e x y c1 c2 d b e a a1 c l h recommended land pattern dim inches millim e ters mi n ma x mi n ma x a a1 b c d e e h l x y c1 c2 0 . 053 2 0 . 068 8 1.35 1.75 0 . 004 0 0 . 009 6 0.10 0.25 0.01 3 0.02 0 0.33 0.51 0 . 007 5 0 . 009 6 0.19 0.25 0 . 385 9 0 . 393 7 9.80 10 . 0 0 0 . 149 7 0 . 157 4 3.80 4.00 0 . 228 4 0 . 244 0 5.80 6.20 0.05 0 bsc. 1.27 bsc. 0.01 6 0 0.05 0 8 0.40 0 1.27 8 0 . 023 6 0.60 0 . 059 0 1.50 0 . 212 5 5.4 0 . 049 9 1.27

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