? semiconductor components industries, llc, 2015 may, 2015 ? rev. 3 1 publication order number: nvmfd5483nl/d nvmfd5483nl power mosfet 60 v, 36 m , 24 a, dual n?channel features ? small footprint (5x6 mm) for compact designs ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? 175 c operating temperature ? nvmfd5483nlwf ? wettable flank option for enhanced optical inspection ? aec?q101 qualified and ppap capable ? this is a pb?free device maximum ratings (t j = 25 c unless otherwise noted) parameter symbol value unit drain?to?source v oltage v dss 60 v gate?to?source v oltage v gs 20 v continuous drain current r jc (notes 1, 2, 4) steady state t c = 25 c i d 24 a t c = 100 c 17 power dissipation r jc (notes 1, 2) t c = 25 c p d 44.1 w t c = 100 c 22.1 continuous drain current r ja (notes 1, 3 & 4) steady state t a = 25 c i d 6.4 a t a = 100 c 4.5 power dissipation r ja (notes 1 & 3) t a = 25 c p d 3.1 w t a = 100 c 1.5 pulsed drain current t a = 25 c, t p = 10 s i dm 153 a operating junction and storage temperature t j , t stg ?55 to 175 c source current (body diode) i s 39 a single pulse drain?to?source avalanche energy (t j = 25 c, v gs = 10 v, i l(pk) = 28 a, l = 0.1 mh) e as 39 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. thermal resistance maximum ratings (note 1) parameter symbol value unit junction?to?case ? steady state (note 2) r jc 3.4 c/w junction?to?ambient ? steady state (note 3) r ja 49 1. the entire application environment impacts the thermal resistance values shown, they are not constants and are only valid for the particular conditions noted. 2. surface?mounted to an ideal (infinite) heat sink. 3. surface?mounted on fr4 board using a 650 mm 2 , 2 oz. cu pad. 4. maximum current for pulses as long as 1 second are higher but are dependent on pulse duration and duty cycle. ordering information www. onsemi.com device package shipping ? v (br)dss r ds(on) max i d max 60 v 36 m @ 10 v 24 a ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. dfn8 5x6 (so8fl) case 506bt marking diagram 45 m @ 4.5 v nvmfd5483nlt1g dfn8 (pb?free) 1500/ tape & ree l xxxxxx = 5483nl xxxxxx = (nvmfd5483nl) or xxxxxx = 5483lw xxxxxx = (nvmfd5483nlwf) a = assembly location y = year w = work week zz = lot traceability d1 d1 d2 d2 s1 g1 s2 g2 dual n?channel d1 s1 g1 xxxxxx aywzz 1 d2 d1 d2 s2 g2 d2 d1 NVMFD5483NLWFT1G dfn8 (pb?free) 1500/ tape & ree l nvmfd5483nlwft3g dfn8 (pb?free) 5000/ tape & ree l nvmfd5483nlt3g dfn8 (pb?free) 5000/ tape & ree l
nvmfd5483nl www. onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain?to?source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 60 v drain?to?source breakdown voltage temperature coefficient v (br)dss /t j reference to 25 c i d = 250 a 63 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 60 v t j = 25 c 1.0 a t j = 125 c 10 gate?to?source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 5) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.5 2.5 v gate threshold voltage temperature coefficient v gs(th) /t j reference to 25 c i d = 250 a ?5.2 mv/ c drain?to?source on resistance r ds(on) v gs = 10 v, i d = 15 a 29 36 m v gs = 4.5 v, i d = 15 a 36 45 charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 25 v 668 pf output capacitance c oss 152 reverse transfer capacitance c rss 67 total gate charge q g(tot) v gs = 10 v, v ds = 48 v, i d = 10 a 23.4 nc threshold gate charge q g(th) 0.65 gate?to?source charge q gs 2.14 gate?to?drain charge q gd 9.16 total gate charge q g(tot) v gs = 4.5 v, v ds = 48 v, i d = 10 a 13.2 nc switching characteristics (note 6) turn?on delay time t d(on) v gs = 4.5 v, v ds = 48 v, i d = 5.0 a, r g = 2.5 6.8 ns rise time t r 10.3 turn?off delay time t d(off) 37.5 fall time t f 23.5 drain?source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 10 a t j = 25 c 0.87 1.2 v t j = 125 c 0.82 reverse recovery time t rr v gs = 0 v, d is /d t = 100 a/ s, i s = 10 a 30 ns charge time t a 23.3 discharge time t b 6.7 reverse recovery charge q rr 35 nc 5. pulse test: pulse width = 300 s, duty cycle 2%. 6. switching characteristics are independent of operating junction temperatures.
nvmfd5483nl www. onsemi.com 3 typical characteristics figure 1. on?region characteristics figure 2. transfer characteristics v ds , drain?to?source voltage (v) v gs , gate?t o?source voltage (v) 5 4 3 2 1 0 0 5 10 15 20 25 30 5.0 4.0 3.0 2.0 1.0 0 5 10 15 20 30 figure 3. on?resistance vs. v gs figure 4. on?resistance vs. drain current and gate voltage v gs , gate?t o?source voltage (v) i d , drain current (a) 10 9 8 7 6 5 2 0.02 0.03 0.06 0.08 18 14 10 630 2 0.02 0.03 0.06 figure 5. on?resistance variation with temperature figure 6. drain?to?source leakage current vs. voltage t j , junction temperature ( c) v ds , drain?to?source voltage (v) 125 100 75 50 25 0 ?25 ?50 0 0.4 0.8 1.0 1.2 1.6 1.8 2.4 55 50 40 30 25 20 10 5 1.0e?12 i d , drain current (a) i d , drain current (a) r ds(on) , drain?to?source resistance (m ) r ds(on) , drain?to?source resistance (normalized) i dss , leakage (a) v gs = 10 to 4.5 v 4.1 v 3.9 v 3.7 v 3.5 v 3.3 v 3.1 v 2.9 v 2.7 v v ds = 5 v t j = 125 c t j = ?55 c t j = 25 c 0.04 0.05 0.07 i d = 10 a t j = 25 c 26 22 0.01 0.04 0.05 t j = 25 c v gs = 4.5 v v gs = 10 v 1.4 i d = 10 a v gs = 15 v t j = 125 c t j = 150 c t j = 25 c 15 35 45 60 1.0e?11 1.0e?10 1.0e?09 1.0e?08 1.0e?07 1.0e?06 1.0e?05 1.0e?04 r ds(on) , drain?to?source resistance (m ) 25 4 3 175 2.0 2.2 10 9 8 7 6 4.5 3.5 2.5 1.5 0.6 0.2 150
nvmfd5483nl www. onsemi.com 4 typical characteristics figure 7. capacitance variation figure 8. gate?to?source and drain?to?source voltage vs. total charge v ds , drain?to?source voltage (v) q g , total gate charge (nc) 50 40 30 20 60 10 0 0 100 200 300 400 500 1000 12 10 8 6 4 2 0 0 4 10 12 figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current r g , gate resistance ( ) v sd , source?to?drain voltage (v) 100 10 1 1 10 100 1000 0.8 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 3 4 5 7 9 10 figure 11. maximum rated forward biased safe operating area v ds , drain?to?source voltage (v) 100 10 1 0.1 0.01 0.1 1 10 1000 c, capacitance (pf) v gs , gate?t o?source voltage (v) t, time (ns) i s , source current (a) i d , drain current (a) t j = 25 c v gs = 0 v c iss c oss c rss 2 6 8 t j = 25 c v dd = 48 v i d = 10 a qt q gs v dd = 48 v v gs = 4.5 v i d = 5 a t r t f t d(off) t d(on) 0.7 0.9 2 6 8 t j = 25 c v gs = 0 v t c = 25 c v gs = 10 v single pulse r ds(on) limit thermal limit package limit 10 s 10 ms dc 600 700 24 18 16 14 q gd 100 800 900 20 22 100 s 1 ms
nvmfd5483nl www. onsemi.com 5 typical characteristics figure 12. thermal response pulse time (sec) 0.01 0.001 10 0.0001 0.1 0.00001 1 0.000001 0.001 0.1 1 10 100 r(t) ( c/w) 100 1000 50% duty cycle single pulse 20% 10% 5% 2% 1% 0.01
nvmfd5483nl www. onsemi.com 6 package dimensions dfn8 5x6, 1.27p dual flag (so8fl?dual) case 506bt issue e *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.27 0.75 1.40 3.70 4.56 8x pitch 6.59 4.84 1.00 dimension: millimeters 2.30 4x 0.70 5.55 4x 0.56 2x 2.08 2x m 3.25 h ??? 3.50 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. 4. profile tolerance applies to the exposed pad as well as the terminals. 5. dimensions d1 and e1 do not include mold flash, protrusions, or gate burrs. 6. seating plane is defined by the terminals. a1 is defined as the distance from the seating plane to the lowest point on the package body. 7. a visual indicator for pin 1 must be located in this area . 1234 5 6 top view side view bottom view d1 e1 h d e b a 0.20 c 0.20 c 2x 2x dim min millimeters a 0.90 a1 ??? b 0.33 c 0.20 d 5.15 bsc d1 4.70 d2 3.90 e 6.15 bsc e1 5.70 e2 3.90 e 1.27 bsc g 0.45 k 0.51 l 0.48 a 0.10 c 0.10 c 14 8 e 8x d2 b1 e2 b a 0.10 b c 0.05 c l detail a a1 c 4x 5 max ??? ??? 0.42 ??? 4.90 4.10 5.90 4.15 0.55 ??? 0.61 m n 1.80 2.00 7 8 n pin one identifier note 7 note 4 c seating plane detail a note 6 4x k note 3 d3 1.50 1.70 b1 0.33 0.42 4x d3 g 4x detail b detail b alternate construction k1 0.56 ??? k1 3.75 12 max 1.10 0.05 0.51 0.33 5.10 4.30 6.10 4.40 0.65 ??? 0.71 2.20 1.90 0.51 ??? on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 nvmfd5483nl/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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