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n2812hkim 201111213-s00001 no.a1872-1/26 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 ver.1.04 lc87f7dj2c overview the lc87f7dj2c is an 8-bit microcomputer that, centered around a cpu running at a minimum bus cycle time of 50ns, integrates on a single chip a number of hard ware features such as 19 2k-byte flash rom (onboard programmable), 8k-byte ram, an on-chip debugger, a lcd controller/driver, sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit pwms), four 8-bit timers with a prescaler, a 16-bit timer with a prescaler (may be di vided into 8-bit timers), a base timer serving as a time-of-day clock, a day and time coun ter, a synchronous sio inte rface (with automatic block transmission/reception capabilities), an asynchronous/synchronous sio interface, two uart ports (f ull duplex), an 12-bit 15-channel ad converter, two 12-bit pwm channels, a high-speed clock counter, a system clock frequency divider, a small signal detector, two re mote control receive functions, and a 31 -source 10-vector interrupt feature. features ? flash rom ? capable of on-board-programming with wide range, 3.0 to 3.6v, of voltage source. ? block-erasable in 2-byte units ? 196608 8 bits ? ram ? 8192 9 bits ? minimum bus cycle time ? 50.0ns (20mhz) v dd =2.7 to 3.6v note: the bus cycle time here refers to the rom read speed. ordering number : ENA1872A ordering number : ENA1872A cmos ic from 192k byte, ram 8k byte on-chip 8-bit 1-chip microcontroller * this product is licensed from silicon storage technology, inc. (usa).
lc87f7dj2c no.a1872-2/26 ? minimum instruction cycle time (tcyc) ? 150ns (20mhz) v dd =2.7 to 3.6v ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1 bit units 29 (p0n, p1n, p70 to p73, p8n, xt2) ? normal withstand voltage input port 1 (xt1) ? lcd ports segment output 54 (s00 to s53) common output 4 (com0 to com3) bias terminals for lcd driver 3 (v1 to v3) other functions input/output ports 54 (p3n, pan, pbn, pcn, pdn, pen, pfn,) input ports 7 (pln) ? dedicated oscillator ports 2 (cf1, cf2) ? reset pin 1 ( res ) ? power pins 6 (v ss 1 to v ss 3, v dd 1 to v dd 3) ? lcd controller 1) seven display modes are available (static, 1/2, 1/3, 1/4 duty 1/2, 1/3 bias) 2) segment output and common output can be switched to general-purpose input/output ports ? small signal detection (mic signals etc) 1) counts pulses with the level which is greater than a preset value 2) 2-bit counter ? timers ? timer 0: 16-bit timer/counter with two capture registers. mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-b it capture registers) + 8-bit counter (with two 8-bit capture registers) mode 2: 16-bit timer with an 8-bit programmabl e prescaler (with two 16-bit capture registers) mode 3: 16-bit counter (with two 16-bit capture registers) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-bit prescaler (with t oggle outputs) + 8-bit timer/counter with an 8- bit prescaler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 8: 16-bit timer mode 0: 8-bit timer with an 8-bit prescaler 2 channels mode 1: 16-bit timer with an 8-bit prescaler ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes ? day and time counter 1) using with a base timer, it can be used as 65000 day + minute + second counter.
lc87f7dj2c no.a1872-3/26 ? high-speed clock counter 1) can count clocks with a maximum clock rate of 20mhz (at a main clock of 10mhz). 2) can generate output real-time. ? sio ? sio0: 8-bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tcyc) 3) automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) ? sio1: 8-bit asynchronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8-data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8-data bits, stop detect) ? uart1 ? full duplex ? 7/8/9 bit data bits selectable ? 1 stop bit (2-bit in continuous data transmission) ? built-in baudrate generator ? uart2 ? full duplex ? 7/8/9 bit data bits selectable ? 1 stop bit (2-bit in continuous data transmission) ? built-in baudrate generator ? ad converter: 12 bits 15 channels ? pwm: multi frequency 12-bit pwm 2 channels ? remote control receiver circuit1 1) noise rejection function (units of noise rejection filter: about 120 s, when selecting a 32.768khz crystal oscillator as a clock.) 2) supporting reception form ats with a guide- pulse of half-clock/clock/none. 3) determines a end of reception by detecting a no-signal periods (no carrier). (supports same reception format with a different bit length.) 4) x?tal hold mode release function ? remote control receiver circuit2 1) noise rejection function (units of noise rejection filter: about 120 s, when selecting a 32.768khz crystal oscillator as a clock.) 2) supporting reception form ats with a guide- pulse of half-clock/clock/none. 3) determines a end of reception by detecting a no-signal periods (no carrier). (supports same reception format with a different bit length.) 4) x?tal hold mode release function ? watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable ? clock output function 1) able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock. 2) able to output oscillation clock of sub clock.
lc87f7dj2c no.a1872-4/26 ? interrupts ? 31 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than th e current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 /remote control receiver1 4 0001bh h or l int3/base timer/int5/remote control receiver2 5 00023h h or l t0h/int6 6 0002bh h or l t1l/t1h/int7 7 00033h h or l sio0/uart1 receive/uart2 receive/t8l/t8h 8 0003bh h or l sio1/uart1 transmit/uart2 transmit 9 00043h h or l adc/mic/t6/t7/pwm4/pwm5 10 0004bh h or l port 0/t4/t5 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? iflg (list of interrupt source flag function) 1) shows a list of interrupt source flags that cau sed a branching to a particular vector address (shown in the diagram above). ? subroutine stack levels: 4096 levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? rc oscillation circuit (internal): for system clock ? cf oscillation circuit: for system clock, with internal rf and external rd ? crystal oscillation circuit: for low-speed system clock, with internal rf and external rd ? frequency variable rc oscillation circuit (internal): for system clock 1) adjustable in 4% (typ.) step from a selected center frequency. 2) measures the frequency of the source oscillation cloc k using the input signal from xt1 as the reference. ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz). ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. (some parts of the serial transfer function stops operation.) 1) oscillation is not halted automatically. 2) canceled by a system reset or occurrence of an interrupt continued on next page.
lc87f7dj2c no.a1872-5/26 continued from preceding page. ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc, x?tal, and frequency variable rc oscillators automatically stop operation. 2) there are three ways of resetting the hold mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, int2 , int4, and int5 pins to the specified level (3) having an interrupt source established at port 0 ? x'tal hold mode: suspends instruction execution and the opera tion of the peripheral circu its except the base timer and the remote control receiver circuit. 1) the cf, rc, and frequency variable rc oscillators automatically stop operation. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are five ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) setting at least one of the int0, int1, int2 , int4, and int5 pins to the specified level (3) having an interrupt source established at port 0 (4) having an interrupt source established in the base timer circuit (5) having an interrupt source establishe d in the remote control receiver circuit ? on-chip debugger ? supports software debugging with the ic mounted on the target board. ? package form ? qip100e(14 20): lead-free type/halogen-free type ? tqfp100(14 14): lead-free type/halogen-free type (under development) ? development tools ? on-chip debugger: tcb87 typeb +lc87f7dj2c or tcb87 typec(3lines cable)+lc87f7dj2c ? flash rom programming boards package programming boards qip100e(14 20) w87fq100 tqfp100(14 14) w87fsq100 ? flash rom programmer maker model supported version device flash support group, inc. (fsg) single af9708 af9709/af9709b/af9709c (including product of ando electric co., ltd) (note 2) lc87f7dj2c gang af9723/af9723b(main body) (including product of ando electric co., ltd) (note 2) lc87f7dj2c af9833(unit) (including product of ando electric co., ltd) (note 2) flash support group, inc. (fsg) + our company (note 1) onboard single/gang af9101/af9103(main body) (fsg) (note 2) lc87f7dj2c sib87(interface driver) (our company model) our company single/gang skk/skk type b (sanyo fws) application version after 1.05 chip data version after 2.23 lc87f7dj2c onboard single/gang skk-dbg type b (sanyo fws) note 1: with the fsg onboard programmer (af9101/af9103) and the serial interface driver provided by our company, pc-less standalone onboard programming is possible note 2: depending on programming cond itions, it is necessary to use a dedicat ed programming device and a program. please contact our company or fsg if you have any questions or difficulties regarding this matter.
lc87f7dj2c no.a1872-6/26 package dimensions unit : mm (typ) 3151a package dimensions unit : mm (typ) 3274 [under development] sanyo : qip100e(14x20) 20.0 23.2 14.0 17.2 0.15 0.8 (2.7) 3.0max 0.1 0.3 0.65 (0.58) 130 80 51 31 50 100 81 sanyo : tqfp100(14x14) 100 125 26 50 51 75 76 14.0 (1.0) (1.0) 0.1 0.125 16.0 0.2 0.5 1.2max 0.5 14.0 16.0
lc87f7dj2c no.a1872-7/26 pin assignments qip100e(14 20) ?lead-free type/halogen-free type? s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 s15/pb7 s14/pb6 s13/pb5 s12/pb4 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1/pa1 p06/t6o p07/t7o p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/micin p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/nkin p73/int3/t0in/rmin s0/pa0 v3/pl6/an14/dbgp2 s47/pf7/int7 s46/pf6/int6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 v ss 2 v dd 2 s23/pc7 s22/pc6 s21/pc5 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 v2/pl5/an13/dbgp1 v1/pl4/an12/dbgp0 com0/pl0 com1/pl1 com2/pl2 com3/pl3 p30/int4/t1in/int6/t0lcp1/pwm4/s48 p31/int4/t1in/pwm5/s49 v ss 3 v dd 3 p32/int4/t1in/utx1/s50 p33/int4/t1in/urx1/s51 p34/int5/t1in/int7/t0hcp1/utx2/s52 p35/int5/t1in/urx2/s53 p00/dgbp0 p01/dgbp1 p02/dgbp2 p03/int6 p04/int7 p05/cko lc87f7dj2c top view
lc87f7dj2c no.a1872-8/26 tqfp100(14 14) ?lead-free type/halogen-fr ee type? (under development) p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml p17/t1pwmh/buz res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/micin p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/nkin s47/pf7 v3/pl6/an14/dbgp2 v2/pl5/an13/dbgp1 v1/pl4/an12/dbgp0 com0/pl0 com1/pl1 com2/pl2 com3/pl3 p30/int4/t1in/int6/t0lcp1/pwm4/s48 p31/int4/t1in/pwm5/s49 v ss 3 v dd 3 p32/int4/t1in/utx1/s50 p33/int4/t1in/urx1/s51 p34/int5/t1in/int7/t0hcp1/s52 p35/int5/t1in/s52 p00/dgbp0 p01/dgbp1 p02/t8lo/dgbp2 p03/t8ho p04 p05/cko p06/t6o p07/t7o p10/so0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 s19/pc3 s18/pc2 s17/pc1 s16/pc0 s15/pb7 s14/pb6 s13/pb5 s12/pb4 s11/pb3 s10/pb2 s9/pb1 s8/pb0 s7/pa7 s6/pa6 s5/pa5 s4/pa4 s3/pa3 s2/pa2 s1/pa1 s0/pa0 p73/int3/t0in/rmin s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 v ss 2 v dd 2 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 lc87f7dj2c top view 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
lc87f7dj2c no.a1872-9/26 system block diagram interrupt control standby control ir pla flash rom clock generator cf rc x?tal pc bus interface port 0 port 1 sio0 sio1 timer 0 (high speed clock counter) timer 1 base timer lcd controller int0 to 7 noise rejection filter port 3 port 7 port 8 adc small signal detector acc b register c register psw rar ram stack pointer watchdog timer alu timer 6 timer 7 timer 4 timer 5 vmrc uart1 on-chip debugger pwm4/5 timer 8 remote control receiver circuit 1 day and time counter remote control receiver circuit 2 uart2
lc87f7dj2c no.a1872-10/26 pin description pin name i/o description option v ss 1 v ss 2 v ss 3 - - power supply pin no v dd 1 v dd 2 v dd 3 - + power supply pin no port 0 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? input for hold release ? input for port 0 interrupt ? shared pins p03: int6 input p04: int7 input p05: clock output (system clock/can selected from sub clock) p06: timer 6 toggle output p07: timer 7 toggle output on chip debugger pins: dbgp0 to dbgp2(p00 to p02) yes p00 to p07 port 1 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: timer 1pwml output p17: timer 1pwmh output/beeper output yes p10 to p17 port 3 i/o ? 6-bit i/o port ? segment output for lcd ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p30 to p33: int4 input/hold release input/ti mer 1 event input/timer 0l capture input/ timer 0h capture input p34 to p35: int5 input/hold release input/ti mer 1 event input/timer 0l capture input/ timer 0h capture input p30: pwm4 output/int6 input/timer 0l capture 1 input p31: pwm5 output p32: uart1 transmit p33: uart1 receive p34: uart2 transmit/int7 inpu t/timer 0h capture 1 input p35: uart2 receive interrupt acknowledge type yes p30 to p35 rising falling rising & falling h level l level int4 int5 int6 int7 enable enable enable enable enable enable enable enable enable enable enable enable disable disable disable disable disable disable disable disable continued on next page.
lc87f7dj2c no.a1872-11/26 continued from preceding page. pin name i/o description option port 7 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? shared pins p70: int0 input/hold release input/timer 0l capture input/watchdog timer output p71: int1 input/hold release input/timer 0h capture input p72: int2 input/hold release input/timer 0 event input/timer 0l capture input/ high speed clock counter input p73: int3 input (with noise filter)/time r 0 event input/timer 0h capture input/ remote control receiver input ad converter input ports: an8 (p70), an9 (p71) interrupt acknowledge type no p70 to p73 rising falling rising & falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable port 8 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? shared pins ad converter input ports: an0 to an7 small signal detector input port: micin (p87) no p80 to p87 s0/pa0 to s7/pa7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pa) no s8/pb0 to s15/pb7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pb) no s16/pc0 to s23/pc7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pc) no s24/pd0 to s31/pd7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pd) no s32/pe0 to s39/pe7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pe) no s40/pf0 to s47/pf7 i/o ? segment output for lcd ? can be used as general-purpose i/o port (pf) pf6: int6 input pf7: int7 input no com0/pl0 to com3/pl3 i/o ? common output for lcd ? can be used as general-purpose input port (pl) no v1/pl4 to v3/pl6 i/o ? lcd output bias power supply ? can be used as general-purpose input port (pl) ? shared pins ad converter input ports: an12 (v1) to an14 (v3) on-chip debugger pins: dbgp0 (v1) to dbgp2 (v3) no res input reset pin no xt1 input ? 32.768khz crystal oscillator input pin ? shared pins general-purpose input port ad converter input port: an10 must be connected to v dd 1 if not to be used. no xt2 i/o ? 32.768khz crystal oscillator output pin ? shared pins general-purpose i/o port ad converter input port: an11 must be set for oscillation and kept open if not to be used. no cf1 input ceramic resonator input pin no cf2 output ceramic resonator output pin no
lc87f7dj2c no.a1872-12/26 port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p00 to p07 each bit 1 cmos programmable 2 nch-open drain programmable p10 to p17 each bit 1 cmos programmable 2 nch-open drain programmable p30 to p35 each bit 1 cmos programmable 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable p80 to p87 - no nch-open drain no s0/pa0 to s47/pf7 - no cmos programmable com0/pl0 to com3/pl3 - no input only no v1/pl4 to v3/pl6 - no input only no xt1 - no input only no xt2 - no output for 32.768khz crystal oscillator (nch-open drain when in general-purpose output mode) no user option list option name option type mask version *1 flash version option selected in units of specified item port output form p00 to p07 ? ? each bit cmos nch-open drain p10 to p17 ? ? each bit cmos nch-open drain p30 to p35 ? ? each bit cmos nch-open drain program start address - *2 ? - 00000h 1ff00h * 1: mask option selection - no change possible after the mask is completed. * 2: program start address of the mask version is 00000h. *1 connect the ic as shown below to minimize the noise input to the v dd 1 pin. be sure to electrically short the v ss 1, v ss 2, and v ss 3 pins. *2 the internal memory is sustained by v dd 1. if none of v dd 2 and v dd 3 are backed up, the high level output at the ports are unstable in the hold backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. make sure that the port outputs are held at the low level in the hold backup mode. power supply lsi v dd 1 for backup *2 v dd 2 v dd 3 v ss 3 v ss 2 v ss 1
lc87f7dj2c no.a1872-13/26 absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +4.6 v supply voltage for lcd vlcd v1/pl4, v2/pl5, v3/pl6 v dd 1=v dd 2=v dd 3 -0.3 v dd input voltage v i (1) port l xt1, cf1, res -0.3 v dd +0.3 v i (2) v dd 2, v dd 3 v ss v dd +0.1 input/output voltage v io (1) ports 0, 1, 3, 7, 8 ports a, b, c ports d, e, f, xt2 -0.3 v dd +0.3 high level output current peak output current ioph(1) ports 0, 1, 32 to 35 ? cmos output selected ? current at each pin -10 ma ioph(2) ports 30, 31 ? cmos output selected ? current at each pin -20 ioph(3) ports 71 to 73 current at each pin -5 ioph(4) ports a, b, c ports d, e, f current at each pin -5 mean output current (note 1-1) iomh(1) ports 0, 1, 32 to 35 ? cmos output selected ? current at each pin -7.5 iomh(2) ports 30, 31 ? cmos output selected ? current at each pin -15 iomh(3) ports 71 to 73 current at each pin -3 iomh(4) ports a, b, c ports d, e, f current at each pin -3 total output current ioah(1) ports 0, 1, 32 to 35 total of all pins -25 ioah(2) ports 30, 31 total of all pins -25 ioah(3) ports 0, 1, 3 total of all pins -45 ioah(4) ports 71 to 73 total of all pins -5 ioah(5) ports a, b, c total of all pins -25 ioah(6) ports d, e, f total of all pins -25 ioah(7) ports a, b, c ports d, e, f total of all pins -45 low level output current peak output current iopl(1) ports 0, 1, 32 to 35 current at each pin 20 iopl(2) ports 30, 31 current at each pin 30 iopl(3) ports 7, 8, xt2 current at each pin 10 iopl(4) ports a, b, c ports d, e, f current at each pin 10 mean output current (note 1-1) ioml(1) ports 0, 1, 32 to 35 current at each pin 15 ioml(2) ports 30, 31 current at each pin 20 ioml(3) ports 7, 8, xt2 current at each pin 7.5 ioml(4) ports a, b, c ports d, e, f current at each pin 7.5 total output current ioal(1) ports 0, 1, 32 to 35 total of all pins 45 ioal(2) ports 30, 31 total of all pins 45 ioal(3) ports 0, 1, 3 total of all pins 80 ioal(4) ports 7, 8, xt2 total of all pins 20 ioal(5) ports a, b, c total of all pins 45 ioal(6) ports d, e, f total of all pins 45 ioal(7) ports a, b, c ports d, e, f total of all pins 80 maximum power dissipation pd max qip100e(14 20) ta=-40 to +85 c mw tqfp100(14 14) ta=-40 to +85 c note 1-1: the mean output current is a mean value measured over 100ms. continued on next page.
lc87f7dj2c no.a1872-14/26 continued from preceding page. parameter symbol pin/remarks conditions specification v dd [v] min typ max unit operating ambient temperature topr -40 +85 c storage ambient temperature tstg -55 +125 allowable operating range at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit operating supply voltage (note 2-1) v dd (1) v dd 1=v dd 2=v dd 3 0.150 s tcyc 200 s 2.7 3.6 v memory sustaining supply voltage vhd v dd 1 ram and register contents sustained in hold mode. 2.0 3.6 high level input voltage v ih (1) ports 0, 3, 8 ports a, b, c, d, e, f port l output disabled 2.7 to 3.6 0.3v dd +0.7 v dd v ih (2) port 1 ports 71 to 73 p70 port input/ interrupt side ? output disabled ? when int1vtsl=0 (p71 only) 2.7 to 3.6 0.3v dd +0.7 v dd v ih (3) p71 interrupt side ? output disabled ? when int1vtsl=1 2.7 to 3.6 0.85v dd v dd v ih (4) p87 small signal input side output disabled 2.7 to 3.6 0.75v dd v dd v ih (5) p70 watchdog timer side output disabled 2.7 to 3.6 0.9v dd v dd v ih (6) xt1,xt2,cf1, res 2.7 to 3.6 0.75v dd v dd low level input voltage v il (1) ports 0, 3, 8 ports a, b, c, d, e, f port l output disabled 2.7 to 3.6 v ss 0.2v dd v il (2) port 1 ports 71 to 73 p70 port input/ interrupt side ? output disabled ? when int1vtsl=0 (p71 only) 2.7 to 3.6 v ss 0.2v dd v il (3) p71 interrupt side ? output disabled ? when int1vtsl=1 2.7 to 3.6 v ss 0.45v dd v il (4) p87 small signal input side output disabled 2.7 to 3.6 v ss 0.25v dd v il (5) p70 watchdog timer side output disabled 2.7 to 3.6 v ss 0.8v dd -1.0 v il (6) xt1,xt2,cf1, res 2.7 to 3.6 v ss 0.25v dd instruction cycle time (note 2-2) tcyc 2.7 to 3.6 0.150 200 s external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division ratio=1/1 ? external system clock duty=505% 2.7 to 3.6 0.1 20 mhz ? cf2 pin open ? system clock frequency division ratio=1/2 2.7 to 3.6 0.2 40 note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. continued on next page. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lc87f7dj2c no.a1872-15/26 continued from preceding page. parameter symbol pin/remarks conditions specification v dd [v] min typ max unit oscillation frequency range (note 2-3) fmcf(1) cf1, cf2 ? 20mhz ceramic oscillation ? see fig. 1. 2.7 to 3.6 20 mhz fmrc internal rc oscillation 2.7 to 3.6 0.3 1.0 2.0 fmvmrc(1) ? frequency variable rc source oscillation ? when vmraj2 to 0=4, vmfaj2 to 0=0, vmsl4m=0 2.7 to 3.6 10 fmvmrc(2) ? frequency variable rc source oscillation ? when vmraj2 to 0=4, vmfaj2 to 0=0, vmsl4m=1 2.7 to 3.6 4 fsx?tal xt1, xt2 ? 32.768khz crystal oscillation ? see fig. 2. 2.7 to 3.6 32.768 khz frequency variable rc oscillation usable range opvmrc(1) when vmsl4m=0 2.7 to 3.6 8 10 12 mhz opvmrc(2) when vmsl4m=1 2.7 to 3.6 3.5 4 4.5 frequency variable rc oscillation adjustment range vmadj(1) each step of vmrajn (wide range) 2.7 to 3.6 8 24 64 % vmadj(2) each step of vmfajn (small range) 2.7 to 3.6 1 4 8 note 2-3: see tables 1 and 2 for the oscillation constants. electrical characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high level input current i ih (1) ports 0, 1, 3, 7, 8 ports a, b, c ports d, e, f port l ? output disabled ? pull-up resistor off ? v in =v dd (including output tr's off leakage current) 2.7 to 3.6 1 a i ih (2) res v in =v dd 2.7 to 3.6 1 i ih (3) xt1, xt2 ? for input port specification ? v in =v dd 2.7 to 3.6 1 i ih (4) cf1 v in =v dd 2.7 to 3.6 15 i ih (5) p87 small signal input side v in =vbis+0.5v (vbis: bias voltage) 2.7 to 3.6 1.5 5.5 10 low level input current i il (1) ports 0, 1, 3, 7, 8 ports a, b, c ports d, e, f port l ? output disabled ? pull-up resistor off ? v in =v ss (including output tr's off leakage current) 2.7 to 3.6 -1 i il (2) res v in =v ss 2.7 to 3.6 -1 i il (3) xt1, xt2 ? for input port specification ? v in =v ss 2.7 to 3.6 -1 i il (4) cf1 v in =v ss 2.7 to 3.6 -15 i il (5) p87 small signal input side v in =vbis-0.5v (vbis : bias voltage) 2.7 to 3.6 -10 -5.5 -1.5 continued on next page.
lc87f7dj2c no.a1872-16/26 continued from preceding page. parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high level output voltage v oh (1) ports 0, 1, 32 to 35 i oh =-0.4ma 2.7 to 3.6 v dd -0.4 v v oh (2) ports 30, 31 i oh =-1.6ma 2.7 to 3.6 v dd -0.4 v oh (3) ports 71 to 73 i oh =-0.4ma 2.7 to 3.6 v dd -0.4 v oh (4) ports a, b, c ports d, e, f i oh =-0.4ma 2.7 to 3.6 v dd -0.4 low level output voltage v ol (1) ports 0, 1, 32 to 35 ports 30,31 (pwm function output mode) i ol =1.6ma 2.7 to 3.6 0.4 v ol (2) ports 30, 31 (port function output mode) i ol =5ma 2.7 to 3.6 0.4 v ol (3) ports 7, 8 xt2 i ol =1.6ma 2.7 to 3.6 0.4 v ol (4) ports a, b, c ports d, e, f i ol =1.6ma 2.7 to 3.6 0.4 lcd output voltage regulation vodls s0 to s53 ? i o =0ma ? vlcd, 2/3vlcd,1/3vlcd level output ? see fig. 8. 2.7 to 3.6 0 0.2 vodlc com0 to com3 ? i o =0ma ? vlcd, 2/3vlcd,1/2vlcd, 1/3vlcd level output ? see fig. 8. 2.7 to 3.6 0 0.2 lcd bias resistor rlcd(1) resistance per one bias resister see fig. 8. 2.7 to 3.6 60 k rlcd(2) resistance per one bias resister 1/2 mode see fig. 8. 2.7 to 3.6 30 resistance of pull-up mos tr. rpu(1) ports 0, 1, 3, 7 ports a, b, c ports d, e, f v oh =0.9v dd 2.7 to 3.6 18 50 150 hysterisis voltage vhys(1) ports 1, 7 res 2.7 to 3.6 0.1v dd v vhys(2) p87 small signal input side 2.7 to 3.6 0.1v dd pin capacitance cp all pins ? for pins other than that under test: v in =v ss ? f=1mhz ? ta=25 c 2.7 to 3.6 10 pf input sensitivity vsen p87 small signal input side 2.7 to 3.6 0.12v dd vp-p
lc87f7dj2c no.a1872-17/26 serial i/o characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) at v dd =2.7v to 3.6v, 0.190 s tcyc 200 s parameter symbol pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(1) sck0(p12) see fig. 6. 2.7 to 3.6 2 tcyc low level pulse width tsckl(1) 1 high level pulse width tsckh(1) 1 tsckha(1) ? continuous data transmission/reception mode ? see fig. 6. ? (note 4-1-2) 4 output clock frequency tsck(2) sck0(p12) ? cmos output selected ? see fig. 6. 2.7 to 3.6 4/3 low level pulse width tsckl(2) 1/2 tsck high level pulse width tsckh(2) 1/2 tsckha(2) ? continuous data transmission/reception mode ? cmos output selected ? see fig. 6. tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tcyc serial input data setup time tsdi(1) sb0(p11), si0(p11) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.7 to 3.6 0.03 s data hold time thdi(1) 0.03 serial output input clock output delay time tdd0(1) so0(p10), sb0(p11) ? continuous data transmission/reception mode ? (note 4-1-3) 2.7 to 3.6 (1/3)tcyc +0.05 tdd0(2) ? synchronous 8-bit mode ? (note 4-1-3) 1tcyc +0.05 output clock tdd0(3) (note 4-1-3) (1/3)tcyc +0.05 note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
lc87f7dj2c no.a1872-18/26 2. sio1 serial i/o characteristics (note 4-2-1) parameter symbol pin/remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(3) sck1(p15) see fig. 6. 2.7 to 3.6 2 tcyc low level pulse width tsckl(3) 1 high level pulse width tsckh(3) 1 output clock frequency tsck(4) sck1(p15) ? cmos output selected ? see fig. 6. 2.7 to 3.6 2 low level pulse width tsckl(4) 1/2 tsck high level pulse width tsckh(4) 1/2 serial input data setup time tsdi(2) sb1(p14), si1(p14) ? must be specified with respect to rising edge of sioclk. ? see fig. 6. 2.7 to 3.6 0.03 s data hold time thdi(2) 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk. ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.7 to 3.6 (1/3)tcyc +0.05 note 4-2-1: these specifications are theoretical values. add margin depending on its use. pulse input conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high/low level pulse width tpih(1) tpil(1) int0(p70), int1(p71), int2(p72), int4(p30 to p33), int5(p34 to p35), int6(p30), int7(p34) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.7 to 3.6 1 tcyc tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 3.6 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 3.6 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.7 to 3.6 256 tpih(5) tpil(5) micin(p87) condition that signal is accepted to small signal detection counter. 2.7 to 3.6 1 tpih(6) tpil(6) rmin(p73) condition that si gnal is accepted to remote control receiver circuit. 2.7 to 3.6 4 rmck (note5-1) tpil(7) res resetting is enabled. 2.7 to 3.6 200 s note 5-1: rmck is an unit for the base clock (40tcyc/ 50tcyc/sub-clock) of remote control receiver circuit.
lc87f7dj2c no.a1872-19/26 ad converter characteristics at v ss 1 = v ss 2 = v ss 3 =0v <12bits ad converter mode at ta =-30 to +70 c> parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p80) to an7(p87), an8(p70), an9(p71), an10(xt1), an11(xt2) 2.7 to 3.6 12 bit absolute accuracy et (note 6-1) 2.7 to 3.6 16 lsb conversion time tcad ? see conversion time calculation formulas. (note 6-2) 2.9 to 3.6 32 115 s 2.7 to 3.6 45 115 analog input voltage range vain 2.7 to 3.6 v ss v dd v analog port input current iainh vain=v dd 2.7 to 3.6 1 a iainl vain=v ss 2.7 to 3.6 -1 <8bits ad converter mode at ta =-30 to +70 c> parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p80) to an7(p87), an8(p70), an9(p71), an10(xt1), an11(xt2) 2.7 to 3.6 8 bit absolute accuracy et (note 6-1) 2.7 to 3.6 1.5 lsb conversion time tcad ? see conversion time calculation formulas. (note 6-2) 2.7 to 3.6 20.00 90 s 2.7 to 3.6 34.27 90 analog input voltage range vain 2.7 to 3.6 v ss v dd v analog port input current iainh vain=v dd 2.7 to 3.6 1 a iainl vain=v ss 2.7 to 3.6 -1 12bits ad converter mode: tcad(conversion time)=((52/(division ratio)) + 2) (1/3) tcyc 8bits ad converter mode: tcad(conversion time)=((32/(division ratio)) + 2) (1/3) tcyc external oscillation fmcf [mhz] operating supply voltage range v dd [v] system division ratio (sysdiv) cycle time tcyc [ns] ad division ratio (addiv) ad conversion time (tcad) [ s] 12bit ad 8bit ad 20 2.9 to 3.6 1/1 150 1/16 41.70 25.70 15 2.7 to 3.6 1/1 200 1/16 55.6 34.27 note 6-1: the quantization error (1/2lsb ) must be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 6-2: the conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. the conversion time is 2 times the normal-time conversion time when: ? the first ad conversion is performed in the 12-bit ad conversion mode after a system reset. ? the first ad conversion is performed after the ad conversion mode is switched from 8-bit to 12-bit conversion mode.
lc87f7dj2c no.a1872-20/26 consumption current characteristics at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit normal mode consumption current (note 7-1) iddop(1) v dd 1 =v dd 2 =v dd 3 ? fmcf=15mhz ceramic oscillation mode ? fmx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 6.1 15.6 ma iddop(2) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz crys tal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 0.4 1.7 iddop(3) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz crys tal oscillation mode ? internal rc oscillation stopped. ? system clock set to 10mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 2.7 to 3.6 4.3 12.0 iddop(4) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz crys tal oscillation mode ? internal rc oscillation stopped. ? system clock set to 4mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 2.7 to 3.6 2.1 6.6 iddop(5) ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz crys tal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 19.3 73 a note 7-1: the consumption current value includes none of the currents that flow into the output tr and internal pull-up resistors. continued on next page.
lc87f7dj2c no.a1872-21/26 continued from preceding page. parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit halt mode consumption current (note 7-1) iddhalt(1) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fmx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 2.7 6.8 ma iddhalt(2) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz crys tal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 0.2 0.75 iddhalt(3) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz crys tal oscillation mode ? internal rc oscillation stopped. ? system clock set to 10mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 2.7 to 3.6 1.6 4.6 iddhalt(4) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz crys tal oscillation mode ? internal rc oscillation stopped. ? system clock set to 4mhz with frequency variable rc oscillation ? 1/1 frequency division ratio 2.7 to 3.6 0.7 1.75 iddhalt(5) ? halt mode ? fmcf=0hz (oscillation stopped) ? fmx?tal=32.768khz crys tal oscillation mode ? system clock set to 32.768khz side ? internal rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 12.4 54.9 a hold mode consumption current iddhold(1) v dd 1 ? hold mode ? cf1=v dd or open (external clock mode) 2.7 to 3.6 0.06 18.4 timer hold mode consumption current iddhold(2) v dd 1 ? timer hold mode ? cf1=v dd or open (external clock mode) ? fmx?tal=32.768khz crystal oscillation mode 2.7 to 3.6 10.14 34.4 note 7-1: the consumption current value includes none of the currents that flow into the output tr and internal pull-up resistors.
lc87f7dj2c no.a1872-22/26 f-rom write characteristics at ta = +10c to +55c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/rem arks conditions specification v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? 128-byte programming ? erasing current included 3.0 to 3.6 ma programming time tfw(1) ? 128-byte programming ? erasing current included ? time for setting up 128-byte data is excluded. 3.0 to 3.6 ms uart (full duplex) operating conditions at ta = -40 to +85c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit transfer ate ubr utx(p32), urx(p33) 2.7 to 3.6 16/3 8192/3 tcyc data length: 7/8/9 bits (lsb first) stop bits: 1 bit (2-bit in continuous data transmission) parity bits: none example of 8-bit data transmission mode processing (transmit data=55h) example of 8-bit data reception m ode processing (r eceive data=55h) transmit data (lsb first) start of transmission end of transmission ubr start bit stop bit ubr receive data (lsb first) start of reception end of reception start bit stop bit
lc87f7dj2c no.a1872-23/26 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main system clock oscillation circuit that are measured using a our designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf1 [ ] rd1 [ ] typ [ms] max [ms] 20mhz murata cstce20m0v51-r0 (5) (5) open 150 2.7 to 3.6 0.05 0.15 values shown in parentheses are capacitance included in the oscillator cstls20m0x51-b0 (5) (5) open 0 2.7 to 3.6 0.05 0.15 15mhz cstce15m0v53-rc (15) (15) open 220 2.7 to 3.6 0.05 0.15 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 4). characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a our designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c3 [pf] c4 [pf] rf2 [ ] rd2 [ ] typ [s] max [s] 32.768khz epson toyocom mc-306 18 18 open 560k 2.7 to 3.6 1.4 3.0 applicable cl value= 12.5pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see figure 4). note: the components that are in volved in oscillation should be placed as close to the ic an d to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf2 c1 rd1 c2 cf rf1
lc87f7dj2c no.a1872-24/26 figure 3 ac timing measurement point reset time and oscillation stabilization time hold reset signal and oscillation stabilization time figure 4 oscillation stabilization times operating v dd lower limit power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unpredictable reset instruction execution v dd 0v internal rc oscillation cf1, cf2 xt1, xt2 state hold reset signal hold reset signal valid tmscf tmsx?tal hold halt hold reset signal absent 0.5v dd
lc87f7dj2c no.a1872-25/26 figure 5 reset circuit figure 6 serial i/o waveforms figure 7 pulse input timing signal waveform c res v dd r res res note: determine the value of c res and r res so that the reset signal is present for a period of 200 s after the supply voltage goes beyond the lower limit of the ic's operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transfer period (sio0 only) data ram transfer period (sio0 only)
lc87f7dj2c no.a1872-26/26 figure 8 lcd bias resistor ps vlcd sw: on (vlcd=v dd ) 2/3vlcd 1/2vlcd 1/3vlcd sw : on/off (programmable) v dd gnd rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d rl c d on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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