? semiconductor components industries, llc, 2015 may, 2015 ? rev. 6 1 publication order number: esd8351/d esd8351, szesd8351 esd protection diodes low capacitance esd protection diode for high speed data line the esd8351 series esd protection diodes are designed to protect high speed data lines from esd. ultra?low capacitance and low esd clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. features ? low capacitance (0.55 pf max, i/o to gnd) ? protection for the following iec standards: iec 61000?4?2 (level 4) iso 10605 ? low esd clamping voltage ? sz prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? usb 2.0 ? esata maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit operating junction temperature range t j ?55 to +125 c storage temperature range t stg ?55 to +150 c lead solder temperature ? maximum (10 seconds) t l 260 c iec 61000?4?2 contact (esd) iec 61000?4?2 air (esd) iso 10605 330 pf / 2 k contact esd esd esd 15 15 30 kv kv kv maximum peak pulse current 8/20 s @ t a = 25 c i pp 5.0 a stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. see application note and8308/d for further description of survivability specs. marking diagrams x3dfn2 case 152af pin configuration and schematic www. onsemi.com x, xx = specific device code m = date code = 1 cathode 2 anode sod?323 case 477 sod?523 case 502 sod?923 case 514ab pin 1 m 1 2 ae m 1 2 af 12 m ac m see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information l
esd8351, szesd8351 www. onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter v rwm working peak voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current v hold holding reverse voltage i hold holding reverse current r dyn dynamic resistance i pp maximum peak pulse current v c clamping voltage @ i pp v c = v hold + (i pp * r dyn ) i v v c v rwm v hold v br r dyn v c i r i t i hold ?i pp r dyn i pp v c = v hold + (i pp * r dyn ) electrical characteristics (t a = 25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm i/o pin to gnd 3.3 v breakdown voltage v br i t = 1 ma, i/o pin to gnd 5.5 7.0 7.8 v reverse leakage current i r v rwm = 3.3 v, i/o pin to gnd 500 na holding reverse voltage v hold i/o pin to gnd 1.15 v holding reverse current i hold i/o pin to gnd 20 ma clamping voltage tlp (note 2) see figures 1 through 11 v c i pp = 8 a iec 61000?4?2 level 2 equivalent ( 4 kv contact, 4 kv air) 6.5 v i pp = 16 a iec 61000?4?2 level 4 equivalent ( 8 kv contact, 15 kv air) 11.2 clamping voltage (note 3) v c i pp = 5 a t p = 8 x 20 s 8.2 v dynamic resistance r dyn pin1 to pin2 pin2 to pin1 0.62 0.59 junction capacitance c j v r = 0 v, f = 1 mhz v r = 0 v, f = 2.5 ghz 0.37 0.35 0.55 0.45 pf product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. for test procedure see figures 8 and 9 and application note and8307/d. 2. ansi/esd stm5.5.1 ? electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. 3. non?repetitive current pulse at t a = 20 c, per iec 61000?4?5 waveform.
esd8351, szesd8351 www. onsemi.com 3 figure 1. cv characteristics c (pf) v bias (v) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 capacitance (pf) frequency 0 0.1 0.2 0.3 0.4 0.5 1.0 123 567 9 db frequency (hz) ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 1e7 1e8 1e9 1e10 20 16 14 12 8 4 2 0 02 20 16 14 12 46810 tlp current (a) v c , voltage (v) 3e10 m1 m2 0.6 0.7 0.8 0.9 4810 18 6 10 18 10 8 6 4 2 0 equivalent v iec (kv) 20 16 14 12 8 4 2 0 02 20 16 14 12 46810 tlp current (a) v c , voltage (v) 18 6 10 18 10 8 6 4 2 0 equivalent v iec (kv) figure 2. clamping voltage vs peak pulse current ( t p = 8/20 s) v pk (v) i pk (a) 0 1 2 3 4 5 10 1 1.5 2 3 3.5 4 5 6 7 8 9 2.5 4.5 5.5 figure 3. rf insertion loss figure 4. capacitance over frequency figure 5. positive tlp i?v curve figure 6. negative tlp i?v curve 6
esd8351, szesd8351 www. onsemi.com 4 latch?up considerations on semiconductor?s 8000 series of esd protection devices utilize a snap?back, scr type structure. by using this technology, the potential for a latch?up condition was taken into account by performing load line analysis of common high speed serial interfaces. example load lines for latch?up free applications and applications with the potential for latch?up are shown below with a generic iv characteristic of a snapback, scr type structured device overlaid on each. in the latch?up free load line case, the iv characteristic of the snapback protection device intersects the load?line in one unique point (v op , i op ). this is the only stable operating point of the circuit and the system is therefore latch?up free. in the non?latch up free load line case, the iv characteristic of the snapback protection device intersects the load?line in two points (v opa , i opa ) and (v opb , i opb ). therefore in this case, the potential for latch?up exists if the system settles at (v opb , i opb ) after a transient. because of this, esd8351 series should not be used for hdmi applications ? esd8104 or esd8040 have been designed to be acceptable for hdmi applications without latch?up. please refer to application note and9116/d for a more in?depth explanation of latch?up considerations using esd8000 series devices. figure 7. example load lines for latch?up free applications and applications with the potential for latch?up esd8351 potential latch up: hdmi 1.4/1.3a tmds esd8351 latch up free: usb 2.0 ls/fs, usb 2.0 hs, usb 3.0 ss, displayport i i ssmax i opb i opa v v opb v opa v dd v op v dd v i i ssmax i op table 1. summary of scr requirements for latch?up free applications application vbr (min) (v) ih (min) (ma) vh (min) (v) on semiconductor esd8000 series recommended pn hdmi 1.4/1.3a tmds 3.465 54.78 1.0 esd8104, esd8040 usb 2.0 ls/fs 3.301 1.76 1.0 esd8004, esd8351 usb 2.0 hs 0.482 n/a 1.0 esd8004, esd8351 usb 3.0 ss 2.800 n/a 1.0 esd8004, esd8006, esd8351 displayport 3.600 25.00 1.0 esd8004, esd8006, esd8351
esd8351, szesd8351 www. onsemi.com 5 iec 61000?4?2 spec. level test volt- age (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000?4?2 w aveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 8. iec61000?4?2 spec figure 9. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000?4?2 waveform. since the iec61000?4?2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d.
esd8351, szesd8351 www. onsemi.com 6 transmission line pulse (tlp) measurement transmission line pulse (tlp) provides current versus voltage (i?v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 10. tlp i?v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 11 where an 8 kv iec 61000?4?2 current waveform is compared with tlp current pulses at 8 a and 16 a. a tlp i?v curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. figure 10. simplified schematic of a typical tlp system dut l s oscilloscope attenuator 10 m v c v m i m 50 coax cable 50 coax cable figure 11. comparison between 8 kv iec 61000?4?2 and 8 a and 16 a tlp waveforms ordering information device package shipping ? esd8351ht1g, SZESD8351HT1G* sod?323 (pb?free) 3000 / tape & reel esd8351xv2t1g, szesd8351xv2t1g* sod?523 (pb?free) 3000 / tape & reel esd8351p2t5g, szesd8351p2t5g* sod?923 (pb?free) 8000 / tape & reel esd8351mut5g, szesd8351mut5g* x3dfn2 (pb?free) 15000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *sz prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable.
esd8351, szesd8351 www. onsemi.com 7 package dimensions x3dfn2, 0.62x0.32, 0.355p, (0201) case 152af issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. a b e d bottom view b e 2x l2 2x top view 2x a a1 0.05 c 0.05 c c seating plane side view dim min max millimeters a 0.25 0.33 a1 ??? 0.05 b 0.22 0.28 e 0.355 bsc l2 0.17 0.23 mounting footprint* dimensions: millimeters 0.74 1 0.30 0.31 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 2 1 see application note and8398/d for more mounting details a m 0.05 b c a m 0.05 b c 2x 2x recommended pin 1 indicator (optional) d 0.58 0.66 e 0.28 0.36
esd8351, szesd8351 www. onsemi.com 8 package dimensions sod?323 case 477?02 issue h h e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters. 3. lead thickness specified per l/f drawing with solder plating. 4. dimensions a and b do not include mold flash, protrusions or gate burrs. 5. dimension l is measured from end of radius. note 3 d 1 2 b e a3 a1 a c note 5 l h e dim min nom max millimeters a 0.80 0.90 1.00 a1 0.00 0.05 0.10 a3 0.15 ref b 0.25 0.32 0.4 c 0.089 0.12 0.177 d 1.60 1.70 1.80 e 1.15 1.25 1.35 0.08 2.30 2.50 2.70 l 0.031 0.035 0.040 0.000 0.002 0.004 0.006 ref 0.010 0.012 0.016 0.003 0.005 0.007 0.062 0.066 0.070 0.045 0.049 0.053 0.003 0.090 0.098 0.105 min nom max inches 1.60 0.063 0.63 0.025 0.83 0.033 2.85 0.112 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
esd8351, szesd8351 www. onsemi.com 9 package dimensions sod?523 case 502 issue e notes: 6. dimensioning and tolerancing per asme y14.5m, 1994. 7. controlling dimension: millimeters. 8. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 9. dimensions d and e do not include mold flash, pro- trusions, or gate burrs. e d ?x? ?y? b 2x m 0.08 x y a h c dim min nom max millimeters d 1.10 1.20 1.30 e 0.70 0.80 0.90 a 0.50 0.60 0.70 b 0.25 0.30 0.35 c 0.07 0.14 0.20 l 0.30 ref h 1.50 1.60 1.70 12 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* e e recommended top view side view 2x bottom view l2 l 2x 2x 0.48 0.40 2x 1.80 dimension: millimeters package outline l2 0.15 0.20 0.25
esd8351, szesd8351 www. onsemi.com 10 package dimensions sod?923 case 514ab issue c notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish. minimum lead thickness is the minimum thickness of base material. 4. dimensions d and e do not include mold flash, pro- trusions, or gate burrs. dim min nom max millimeters a 0.34 0.37 0.40 b 0.15 0.20 0.25 c 0.07 0.12 0.17 d 0.75 0.80 0.85 e 0.55 0.60 0.65 0.95 1.00 1.05 l 0.19 ref h e 0.013 0.015 0.016 0.006 0.008 0.010 0.003 0.005 0.007 0.030 0.031 0.033 0.022 0.024 0.026 0.037 0.039 0.041 0.007 ref min nom max inches d e c a ?y? ?x? 2 1 dimensions: millimeters *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* see application note and8455/d for more mounting details 1.20 2x 0.25 2x 0.36 package outline b 2x 0.08 xy top view h e side view 2x bottom view l2 l 2x l2 0.05 0.10 0.15 0.002 0.004 0.006 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 esd8351/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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