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single/dual battery, 0. 9?3.6 v, 16?8 kb, smartclock, 12/10-bit adc mcu c8051f91x-c8051f90x rev. 1.3 11/13 copyright ? 2013 by silicon laboratories c8051f91x-c8051f90x ultra-low power - 160 a/mhz in active mode (24.5 mhz clock) - 2 s wake-up time (two-cell mode) - 10 na sleep mode with memory retention - 50 na sleep mode with brownout detector - 300 na sleep mode with lfo (?f912/02 only) - 600 na sleep mode with external crystal supply voltage 0.9 to 3.6 v - one-cell mode supports 0.9 to 1.8 v operation (?f9 11/01). ?f912 and ?f902 devices can operate from 0.9 to 3.6 v continuously - two-cell mode supports 1.8 to 3.6 v operation - built-in dc-dc converter with 1.8 to 3.3 v output for use in on e-cell mode - built-in ldo regulator allows a high analog supply voltage and low digital core voltage - 2 built-in supply monitors (brownout detectors) 12-bit or 10-bit analog to digital converter - 1 lsb inl (10-bit mode); 1.5 lsb inl (12-bit mode, ?f912/02 only) no missing codes - programmable throughput up to 300 ksps (10-bit mode) or 75 ksps (12-bit mode, ?f912/02 only) - up to 15 external inputs - on-chip voltage reference - on-chip pga allows measuring voltages up to twice the reference voltage - 16-bit auto-averaging accumulator with burst mode provides increased adc resolution - data dependent windowed interrupt generator - built-in temperature sensor two comparators - programmable hysteresis and response time - configurable as wake-up or reset source - up to 15 capacitive touch sense inputs 6-bit programmable current reference - up to 500 a. can be used as a bias or for gen erating a custom reference voltage - pwm enhanced mode on ?f912/02 devices high-speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 25 mips th roughput with 25 mhz clock - expanded interrupt handler memory - 768 bytes ram - 16 kb (?f912/1) or 8 kb (?f902/1) flash; in-system prog rammable digital peripherals - 16 port i/o; all 5 v tolerant with high sink current an d programmable drive strength - hardware smbus? (i 2 c? compatible), 2 x spi?, and uart serial ports available concurrently - four general purpose 16-bit counter/timers - programmable 16-bit counte r/timer array with six capture/compare modules and watchdog timer clock sources - internal oscillators: 24.5 mhz, 2% accuracy supp orts uart operation; 20 mhz low power oscil lator requires very little bias current - external oscillator: crystal, rc, c, or cmos clock - smartclock oscillator: 32 khz crystal or internal lo w frequency oscillator (?f912/02) or self-oscillate mode - can switch between clock s ources on-the-fly; useful in implementing various power saving modes on-chip debug - on-chip debug circuitry fac ilitates full-speed, non- intrusive in-system debug (no emulator required) - provides 4 breakpoints, single stepping - inspect/modify memory and registers - complete development kit packages - 24-pin qfn (4x4 mm) - 24-pin qsop (easy to hand-solder) - tested die available temperature range: ?40 to +85 c analog peripherals 12/10-bit 75/300 ksps adc 16/8 kb isp flash 768 b sram por debug circuitry flexible interrupts 8051 cpu (25 mips) temp sensor digital i/o 24.5 mhz precision internal oscillator high-speed controller core a m u x crossbar voltage comparators + ? wdt uart smbus pca timer 0 timer 1 timer 2 timer 3 port 0 2 x spi iref port 1 port 2 + ? vreg 20 mhz low power internal oscillator vref crc hardware smartclock external oscillator
c8051f91x-c8051f90x 2 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 3 table of contents 1. system overview............ ............................................................................. ........... 20 1.1. cip-51? microcontroller core.. ............................................................. ........... 23 1.1.1. fully 8051 compatible...... ............................................................. ........... 23 1.1.2. improved throughput ............ ........................................................ ........... 23 1.1.3. additional features .......... ............................................................. ........... 23 1.2. port input/output....... ............................................................................. ........... 24 1.3. serial ports ............ ................................................................................ ........... 25 1.4. programmable counter array ... ............................................................. ........... 25 1.5. sar adc with 16-bit auto-averaging accumulator and autonomous low power burst mode26 1.6. programmable current reference (iref0) ..... .............. ............... ........... ......... 27 1.7. comparators .......................................................................................... ........... 27 2. ordering information...... ............................................................................. ........... 30 3. pinout and package definitions..... ............... ............................................. ........... 31 4. electrical characteristics.......... .................................................................. ........... 42 4.1. absolute maximum specificati ons ...................... ................................. ............. 42 4.2. electrical characterist ics.................. ........................................................ ......... 43 5. sar adc with 16-bit auto-averaging accumulator and autonomous low power burst mode68 5.1. output code formatting ......... ............................................................... ........... 69 5.2. modes of operation ............. .................................................................. ........... 70 5.2.1. starting a conversion....... ............................................................. ........... 70 5.2.2. tracking modes................ ............................................................. ........... 71 5.2.3. burst mode ........... ......................................................................... ........... 72 5.2.4. settling time r equirements ................ .......................................... ........... 74 5.2.5. gain setting........ ........................................................................... ........... 75 5.3. 8-bit mode.......... .................................................................................. ............. 75 5.4. 12-bit mode (c8051f912/02 only) . ................. .............. ............... ........... ......... 75 5.5. low power mode (c8051f912/902 only) .............................................. ........... 75 5.6. programmable window detector ........................................................... ........... 83 5.6.1. window detector in sing le-ended mode .......... ............................ ........... 85 5.6.2. adc0 specifications......... ............................................................. ........... 85 5.7. adc0 analog multiplexer........ ............................................................... ........... 86 5.8. temperature sensor ............ .................................................................. ........... 88 5.8.1. calibration .......... ........................................................................... ........... 89 5.9. voltage and ground reference options............... ................................. ........... 91 5.10.external voltage references.... ............................................................. ........... 92 5.11.internal voltage references ..... ............................................................. ........... 92 5.12.analog ground referenc e................................................................... ............. 92 5.13.temperature sensor enable .... ............................................................. ........... 92 5.14.voltage reference electrical specifications .. .......................................... ......... 93 6. programmable current reference (iref0) ....... .......................................... ......... 94 6.1. pwm enhanced mode .............. ............................................................. ........... 94
c8051f91x-c8051f90x 4 rev. 1.3 6.2. iref0 specifications............ .................................................................. ........... 95 7. comparators ................ ................................................................................ ........... 96 7.1. comparator inputs .... ............................................................................. ........... 96 7.2. comparator outputs ............ .................................................................. ........... 97 7.3. comparator response time................. ................................................. ........... 98 7.4. comparator hysteresis ............... ........................................................... ........... 98 7.5. comparator register descripti ons...................... ................................. ............. 99 7.6. comparator0 and comparator1 analog multiple xers........................... ........... 103 8. cip-51 microcontroller .............. .................................................................. ......... 106 8.1. performance .......................................................................................... ......... 106 8.2. programming and debugging suppor t ................................................ ........... 107 8.3. instruction set ........... ............................................................................. ......... 107 8.3.1. instruction and cpu timing .. ........................................................ ......... 107 8.4. cip-51 register descriptions.... ............................................................. ......... 112 9. memory organization..... ............................................................................. ......... 115 9.1. program memory ................. .................................................................. ......... 116 9.1.1. movx instruction and program memory ... ................................. ........... 116 9.2. data memory ............ ............................................................................. ......... 116 9.2.1. internal ram ........ ......................................................................... ......... 116 9.2.2. external ram ....... ......................................................................... ......... 117 10. on-chip xram......... .................................................................................. ........... 118 10.1.accessing xram.......... ......................................................................... ......... 118 10.1.1.16-bit movx example ....... ........................................................... ......... 118 10.1.2.8-bit movx example ......... ........................................................... ......... 118 10.2.special function registers..... ............................................................... ......... 119 11. special function registers ...... .................................................................. ......... 120 11.1.sfr paging .............. ............................................................................. ......... 121 12. interrupt handler ............ ............................................................................. ......... 127 12.1.enabling interrupt sources ..... ............................................................... ......... 127 12.2.mcu interrupt source s and vectors.............. ................................................. 127 12.3.interrupt priorities ..... ............................................................................. ......... 128 12.4.interrupt latency....... ............................................................................. ......... 128 12.5.interrupt register de scriptions ............. ................................................. ......... 130 12.6.external interrupts int0 and int1 ................. ................................................. 137 13. flash memory ................. ............................................................................. ......... 139 13.1.programming the flash memory .......................................................... ......... 139 13.1.1.flash lock and key functi ons ................ .............. ............... .................. 139 13.1.2.flash erase procedure ...... ........................................................... ......... 140 13.1.3.flash write procedure ..... ............................................................. ......... 140 13.2.non-volatile data storage ... .................................................................. ......... 140 13.3.security options ....... ............................................................................. ......... 141 13.4.determining the devi ce part number at run time ..... ................................... 143 13.5.flash write and erase guidelines ............... .......................................... ......... 143 13.5.1.vdd maintenance and the vd d monitor .......... ............................ ......... 143 13.5.2.pswe maintenance ......... ............................................................. ......... 144
c8051f91x-c8051f90x rev. 1.3 5 13.5.3.system clock ....... ......................................................................... ......... 144 13.6.minimizing flash read current .. ........................................................... ......... 145 14. power management........ ............................................................................. ......... 149 14.1.normal mode ............ ............................................................................. ......... 150 14.2.idle mode............... ................................................................................ ......... 151 14.3.stop mode ......... .................................................................................. ........... 151 14.4.suspend mode ............. ......................................................................... ......... 152 14.5.sleep mode .............. ............................................................................. ......... 152 14.6.configuring wakeup sources... ............................................................. ......... 153 14.7.determining the event that caused the last wakeup... ............... .................. 154 14.8.power management spec ifications ........ ............................................... ......... 157 15. cyclic redundancy check unit ( crc0) .............. .............. ............... .................. 158 15.1.crc algorithm............ ........................................................................... ......... 158 15.2.32-bit crc algorithm.. ........................................................................... ......... 160 15.3.preparing for a crc ca lculation .......... ................................................. ......... 161 15.4.performing a crc calculation . ............................................................. ......... 161 15.5.accessing the crc0 result ..... ............................................................. ......... 161 15.6.crc0 bit reverse feat ure.............. ............................................................... 165 16. on-chip dc-dc converter (dc0) .............. ................................................. ......... 166 16.1.startup behavior....... ............................................................................. ......... 167 16.2. high power applications ......... ........................................................... ......... 168 16.3.pulse skipping mode........... .................................................................. ......... 168 16.4.enabling the dc-dc c onverter ............ ................................................. ......... 169 16.5.minimizing power supply nois e ............................................................ ......... 170 16.6.selecting the optimum switch size............. .......................................... ......... 170 16.7.dc-dc converter clocking opti ons ................ .............. ............... .................. 170 16.8.dc-dc converter behavior in sleep mode .......... ................................. ......... 171 16.9.bypass mode (c8051f912/02 only) .. .................................................. ........... 171 16.10.low power mode (c8051f912/02 only) ........... ................................. ........... 172 16.11.passive diode mode (c8051f912/02 only)........ ................................. ......... 172 16.12.dc-dc converter register descriptions ....... .............. ............... .................. 173 16.13.dc-dc converter specif ications ................. ................................................. 175 17. voltage regulator (vreg0) ...... .................................................................. ......... 176 17.1.voltage regulator elec trical specifications ............... ............................ ......... 176 18. reset sources.......... .................................................................................. ........... 177 18.1.power-on (vbat supply monitor) reset ...... ................................................. 178 18.2.power-fail (vdd/dc+ supply monitor) reset...... ................................. ......... 179 18.3.external reset .......... ............................................................................. ......... 182 18.4.missing clock detector reset ... ............... ............................................. ......... 182 18.5.comparator0 reset ............. .................................................................. ......... 182 18.6.pca watchdog timer reset ..... ............... ............................................. ......... 182 18.7.flash error reset ..... ............................................................................. ......... 183 18.8.smartclock (real time clock) reset ................ ................................. ......... 183 18.9.software reset ......... ............................................................................. ......... 183 19. clocking sources ........... ............................................................................. ......... 185
c8051f91x-c8051f90x 6 rev. 1.3 19.1.programmable precision inte rnal oscillator ....... ................................. ........... 186 19.2.low power internal oscillator. ............................................................... ......... 186 19.3.external oscillator drive circuit................ ............................................. ......... 186 19.3.1.external crystal mode...... ............................................................. ......... 186 19.3.2.external rc mode... ...................................................................... ......... 188 19.3.3.external capacitor mode.. ............................................................. ......... 189 19.3.4.external cmos clock mode ................. ................................................. 189 19.4.special function registers for select ing and configuring the system clock 190 20. smartclock (real time clock) .. ............................................................... ......... 193 20.1.smartclock interface .... ...................................................................... ......... 194 20.1.1.smartclock lock and key functions......... ................................. ......... 194 20.1.2.using rtc0adr and rtc0dat to a ccess smartclock internal registers 195 20.1.3.rtc0adr short stro be feature............. .............. ............... .................. 195 20.1.4.smartclock interface auto read feature .................. ................. ........... 195 20.1.5.rtc0adr autoincrement feature.......... .............. ............... .................. 196 20.2.smartclock clocking sources . ........................................................... ......... 199 20.2.1.using the smartclock oscillator with a crystal or external cmos clock . 199 20.2.2.using the smartclock o scillator in self-oscillate mo de............. ......... 200 20.2.3.using the low fr equency oscillator (lfo) ........... ............... .................. 200 20.2.4.programmable load capacitance.............. ................................. ........... 201 20.2.5.automatic gain control (cryst al mode only) and smartclock bias dou- bling ............ ................................................................................ ......... 202 20.2.6.missing smartclock detect or ............... .............. ............... .................. 204 20.2.7.smartclock oscillator cryst al valid detector .......... ................. ........... 204 20.3.smartclock timer and alarm function .............. ................................. ......... 204 20.3.1.setting and reading the smartclock timer value ..... ................ ......... 204 20.3.2.setting a smartclock alar m ............................... ............... .................. 205 20.3.3.software considerat ions for using the smartclock timer and alarm . 205 21. port input/output............ ............................................................................. ......... 210 21.1.port i/o modes of operation .................................................................. ......... 211 21.1.1.port pins configured for analog i/o............. ................................. ......... 211 21.1.2.port pins configured for digital i/o...... ................................................. 211 21.1.3.interfacing port i/o to 5 v and 3.3 v logic... ................................. ......... 212 21.1.4.increasing port i/ o drive strength ... ............................................. ......... 212 21.2.assigning port i/o pins to analog and digital functions.. ............ .................. 212 21.2.1.assigning port i/o pins to analog functions ...... ................................... 212 21.2.2.assigning port i/o pins to digital func tions............. ............ .................. 213 21.2.3.assigning port i/o pi ns to external digital ev ent capture functions .... 213 21.3.priority crossbar decoder ... .................................................................. ......... 214 21.4.port match ............. ................................................................................ ......... 220 21.5.special function register s for accessing and configuring port i/ o .............. 222 22. smbus ................. ......................................................................................... ......... 230 22.1.supporting documents ............. ............................................................. ......... 231
c8051f91x-c8051f90x rev. 1.3 7 22.2.smbus configuration... ............... ........................................................... ......... 231 22.3.smbus operation ....... ........................................................................... ......... 232 22.3.1.transmitter vs. receiver.. ............................................................. ......... 232 22.3.2.arbitration......... ............................................................................. ......... 233 22.3.3.clock low extension........ ............................................................. ......... 233 22.3.4.scl low timeout.... ...................................................................... ......... 233 22.3.5.scl high (smbus free) ti meout .............. ................................. ........... 233 22.4.using the smbus........ ........................................................................... ......... 234 22.4.1.smbus configuration regist er................ .............. ............... .................. 235 22.4.2.smb0cn control register . ........................................................... ......... 238 22.4.3.hardware slave address recognition ........... ............................... ......... 241 22.4.4.data register ....... ......................................................................... ......... 243 22.5.smbus transfer modes... ...................................................................... ......... 244 22.5.1.write sequence (master) ...... ........................................................ ......... 244 22.5.2.read sequence (master) ...... ........................................................ ......... 245 22.5.3.write sequence (slave) ........ ........................................................ ......... 246 22.5.4.read sequence (slave) ........ ........................................................ ......... 247 22.6.smbus status decoding ........................................................................ ......... 247 23. uart0................ ........................................................................................... ......... 252 23.1.enhanced baud rate g eneration.................. ................................................. 253 23.2.operational modes ....... ......................................................................... ......... 254 23.2.1.8-bit uart ........... ......................................................................... ......... 254 23.2.2.9-bit uart ........... ......................................................................... ......... 255 23.3.multiprocessor communications ... ........................................................ ......... 255 24. enhanced serial peripheral interface (spi0 and spi1)........ ............ .................. 260 24.1.signal descriptions....... ......................................................................... ......... 261 24.1.1.master out, slave in (mos i)...................... ................................. ........... 261 24.1.2.master in, slave out (miso)............... .......................................... ......... 261 24.1.3.serial clock (sck) ........... ............................................................. ......... 261 24.1.4.slave select (nss) .......... ............................................................. ......... 261 24.2.spi master mode oper ation ........................................................................... 262 24.3.spi slave mode operation ..... ............................................................... ......... 264 24.4.spi interrupt sources .......... .................................................................. ......... 264 24.5.serial clock phase and polari ty ............. ............................................... ......... 265 24.6.spi special function registers . ............... ............................................. ......... 267 25. timers................ ............................................................ ............... .............. ........... 27 4 25.1.timer 0 and ti mer 1 ............... ............................................................... ......... 276 25.1.1.mode 0: 13-bit counter/timer ................. .............. ............... .................. 276 25.1.2.mode 1: 16-bit counter/timer ................. .............. ............... .................. 277 25.1.3.mode 2: 8-bit counter/tim er with auto-reload.......... ................. ........... 278 25.1.4.mode 3: two 8-bit counter /timers (timer 0 only)..... ................. ........... 279 25.2.timer 2 ............. .................................................................................. ........... 284 25.2.1.16-bit timer with auto-rel oad............... ................................................. 284 25.2.2.8-bit timers with auto-rel oad............... ................................................. 285 25.2.3.comparator 0/smartclo ck capture mode ............... ................. ........... 286
c8051f91x-c8051f90x 8 rev. 1.3 25.3.timer 3 ............. .................................................................................. ........... 290 25.3.1.16-bit timer with auto-rel oad............... ................................................. 290 25.3.2.8-bit timers with auto-rel oad............... ................................................. 291 25.3.3.comparator 1/external oscillator capture mode ....... ................. ........... 292 26. programmable counter array ....... ............................................................. ......... 296 26.1.pca counter/timer ............. .................................................................. ......... 297 26.2.pca0 interrupt sources....... .................................................................. ......... 298 26.3.capture/compare modules ...... ............................................................. ......... 300 26.3.1.edge-triggered captur e mode................. .............. ............... .................. 301 26.3.2.software timer (compare) mode................. ................................. ......... 302 26.3.3.high-speed output mode ..... ........................................................ ......... 303 26.3.4.frequency output mode ....... ........................................................ ......... 304 26.3.5. 8-bit, 9-bit, 10-bi t and 11-bit pulse width modulator modes ............... 305 26.3.6. 16-bit pulse width m odulator mode........... ................................. ......... 307 26.4.watchdog timer mode .... ...................................................................... ......... 308 26.4.1.watchdog timer operation ... ........................................................ ......... 308 26.4.2.watchdog timer usage ........ ........................................................ ......... 309 26.5.register descriptions for pca0 ............................................................. ......... 310 27. c2 interface ................ .................................................................................. ......... 316 27.1.c2 interface registers......... .................................................................. ......... 316 27.2.c2 pin sharing ......... ............................................................................. ......... 319 document change list............... ...................................................................... ........ 320 contact information.......... ................................................................................ ........ 322
c8051f91x-c8051f90x rev. 1.3 9 list of figures figure 1.1. c8051f912 block diagr am ...................... ................................. ............. 21 figure 1.2. c8051f911 block diagr am ...................... ................................. ............. 21 figure 1.3. c8051f902 block diagr am ...................... ................................. ............. 22 figure 1.4. c8051f901 block diagr am ...................... ................................. ............. 22 figure 1.5. port i/o functional block diagram .... .......................................... ........... 24 figure 1.6. pca block dia gram................. .................................................. ............. 25 figure 1.7. adc0 functional bl ock diagram.............. ................................. ............. 26 figure 1.8. adc0 multiplexer bl ock diagram ............. ................................. ............. 27 figure 1.9. comparator 0 func tional block diagram ............... ............ ........... ......... 28 figure 1.10. comparator 1 func tional block diagram .. ................................ ........... 28 figure 3.1. qfn-24 pinout diagr am (top view) .......... ................................. ........... 34 figure 3.2. qsop-24 pi nout diagram f912 (top view) ....... ............... ........... ......... 35 figure 3.3. qfn-24 package mark ing diagram ........... ................................. ........... 36 figure 3.4. qsop-24 pa ckage marking diagram ... .............. ............... ........... ......... 37 figure 3.5. qfn-24 package drawin g ................ .......................................... ........... 38 figure 3.6. typical qfn-24 landi ng diagram.............. ................................. ........... 39 figure 3.7. qsop-24 pa ckage diagram ............. .......................................... ........... 40 figure 3.8. qsop-24 land ing diagram ............. .......................................... ......... 41 figure 4.1. active mode curr ent (external cmos clock) ..... ............... ........... ......... 48 figure 4.2. idle mode current (exter nal cmos clock) ......... ............... ........... ......... 49 figure 4.3. typical dc-dc converter effici ency (high current, vdd/dc+ = 2 v) ... 50 figure 4.4. typical dc-dc converter effici ency (high current, vdd/dc+ = 3 v) ... 51 figure 4.5. typical dc-dc converter effici ency (low current, vdd/dc+ = 2 v).... 52 figure 4.6. typical one-cell suspend mode current... ................................. ........... 53 figure 4.7. typical voh curves, 1.8?3.6 v ............... ................................. ............. 55 figure 4.8. typical voh curves, 0.9?1.8 v ............... ................................. ............. 56 figure 4.9. typical vol curves, 1.8?3.6 v ......... .......................................... ........... 57 figure 4.10. typical vol curves, 0.9?1.8 v .............. ................................. ............. 58 figure 5.1. adc0 functional bl ock diagram.............. ................................. ............. 68 figure 5.2. 10-bit adc tr ack and conversion example timing (bursten = 0).... 71 figure 5.3. burst mode tracking example wit h repeat count set to 4 .......... ......... 73 figure 5.4. adc0 equivalent i nput circuits ............. .............. ............... ........... ......... 74 figure 5.5. adc window co mpare example: right-justi fied single-ended data ... 85 figure 5.6. adc window co mpare example: left-justif ied single-ended data...... 85 figure 5.7. adc0 multiplexer bl ock diagram ............. ................................. ............. 86 figure 5.8. temperature sensor transfer function .............. ............... ........... ......... 88 figure 5.9. temperature sensor error with 1-point calibration (v ref = 1.68 v) ..... 89 figure 5.10. voltage re ference functional block diagram.. ........................... ......... 91 figure 7.1. comparator 0 func tional block diagram ............... ............ ........... ......... 96 figure 7.2. comparator 1 func tional block diagram ............... ............ ........... ......... 97 figure 7.3. comparator hysteres is plot ........... ............................................. ........... 98 figure 7.4. cpn multiplexer blo ck diagram................ ................................. ........... 103 figure 8.1. cip-51 block diagram.. ............................................................... ......... 106
c8051f91x-c8051f90x 10 rev. 1.3 figure 9.1. c8051f91x-c8051f90x memory map .. .............. ............... .................. 115 figure 9.2. flash program memory map............. .......................................... ......... 116 figure 13.1. flash program me mory map (16 kb and 8 kb dev ices).......... ........... 141 figure 14.1. c8051f91x-c8051f90x power distribution........... ................. ........... 150 figure 15.1. crc0 block diagram .. ............... ............................................... ......... 158 figure 15.2. bit reverse register ................................................................. ......... 165 figure 16.1. dc-dc conv erter block diagram...... ................................................. 166 figure 16.2. dc-dc conv erter configuration options ........ ................................... 169 figure 18.1. reset sources......... .................................................................. ......... 177 figure 18.2. power-fail reset timing diagram ........... ................................. ......... 178 figure 18.3. power-fail reset timing diagram ........... ................................. ......... 179 figure 19.1. clocking sources bl ock diagram ............. ................................. ......... 185 figure 19.2. 25 mhz external cr ystal example.......... ................................. ........... 187 figure 20.1. smartclock block di agram............. ................................................. 193 figure 20.2. interpreting oscillation robustness (duty cycle) test results.......... 202 figure 21.1. port i/o functional block diagram ................ ............................ ......... 210 figure 21.2. port i/o cell block diagram ............ .......................................... ......... 211 figure 21.3. crossbar priority decoder with no pins skipped ................. .............. 215 figure 21.4. crossbar priority decoder with crystal pins sk ipped ............. ........... 216 figure 22.1. smbus block diagram .. ............... ............................................. ......... 230 figure 22.2. typical smbus configuration .......... .......................................... ......... 231 figure 22.3. smbus transaction .... ............................................................... ......... 232 figure 22.4. typical smbus scl generation......................................................... 235 figure 22.5. typical master wr ite sequence ............... ................................. ......... 244 figure 22.6. typical ma ster read sequence ........ ................................................. 245 figure 22.7. typical sl ave write sequence ... ............................................... ......... 246 figure 22.8. typical slave read sequence ................. ................................. ......... 247 figure 23.1. uart0 block diagram ............. ................................................. ......... 252 figure 23.2. uart0 baud rate logi c ........................................................... ......... 253 figure 23.3. uart interconnect di agram ............. ................................................. 254 figure 23.4. 8-bit uart timing diagram...................................................... ......... 254 figure 23.5. 9-bit uart timing diagram...................................................... ......... 255 figure 23.6. uart multi-proc essor mode interconne ct diagram .......... ................ 256 figure 24.1. spi block di agram .............. ............................................................... 260 figure 24.2. multiple-master mode connection diagram .............................. ......... 263 figure 24.3. 3-wire single master and 3-wire single slave mode connection diagram 263 figure 24.4. 4-wire single master mode and 4-wire slave mode connection diagram 263 figure 24.5. master mode data/ clock timing .............. ................................. ......... 265 figure 24.6. slave mode data/clock timing (ckpha = 0) ... ............... .................. 266 figure 24.7. slave mode da ta/clock timing (ckpha = 1) ... ............... .................. 266 figure 24.8. spi master timing (ckpha = 0)..... .......................................... ......... 271 figure 24.9. spi master timing (ckpha = 1)..... .......................................... ......... 271 figure 24.10. spi slave timing (c kpha = 0).............. ................................. ......... 272
c8051f91x-c8051f90x rev. 1.3 11 figure 24.11. spi slave timing (c kpha = 1).............. ................................. ......... 272 figure 25.1. t0 mode 0 bl ock diagram............... .......................................... ......... 277 figure 25.2. t0 mode 2 bl ock diagram............... .......................................... ......... 278 figure 25.3. t0 mode 3 bl ock diagram............... .......................................... ......... 279 figure 25.4. timer 2 16-bit mode block diagram ........ ................................. ......... 284 figure 25.5. timer 2 8-bit mode block diagram ................... ............... .................. 285 figure 25.6. timer 2 capture mode block diagram .............. ............... .................. 286 figure 25.7. timer 3 16-bit mode block diagram ........ ................................. ......... 290 figure 25.8. timer 3 8-bit mode block diagram ................... ............... .................. 291 figure 25.9. timer 3 capture mode block diagram .............. ............... .................. 292 figure 26.1. pca block diagram.... ............................................................... ......... 296 figure 26.2. pca counter/timer block diagram.......... ................................. ......... 298 figure 26.3. pca interrupt blo ck diagram ................. ................................. ........... 299 figure 26.4. pca capture mode dia gram............. ................................................. 301 figure 26.5. pca software time r mode diagram ........ ................................. ......... 302 figure 26.6. pca high-speed out put mode diagram....... ............................ ......... 303 figure 26.7. pca frequen cy output mode ........... ................................................. 304 figure 26.8. pca 8-bit pwm mode diagram ................................................ ......... 305 figure 26.9. pca 9, 10 and 11-bi t pwm mode diagram .. ............................ ......... 306 figure 26.10. pca 16-bit pwm mode ........................................................... ......... 307 figure 26.11. pca module 5 with watchdog ti mer enabled ..... ................. ........... 308 figure 27.1. typical c2 pin shar ing............. ................................................. ......... 319
c8051f91x-c8051f90x 12 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 12 list of tables table 2.1. product selecti on guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 3.1. pin definitions for the c8051f91x-c8051f90x . . . . . . . . . . . . . . . . . . . 31 table 3.2. qfn-24 package di mensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 3.3. pcb land pattern ......... ............................................................... ........... 39 table 3.4. qsop-24 package dimens ions ................. ................................. ........... 40 table 3.5. pcb land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 4.1. absolute maximum rati ngs ................... .............. ............... ........... ......... 42 table 4.2. global electrical char acteristics ............ .............. ............... ........... ......... 43 table 4.3. port i/ o dc electrical char acteristics ......... ................................. ........... 54 table 4.4. reset electric al characteristics ...... ............................................. ........... 59 table 4.5. power managem ent electrical specifications .... ............................ ......... 60 table 4.6. flash electrical char acteristics ...... ............................................. ........... 60 table 4.7. internal precision o scillator electrical characteri stics ........... ................ 60 table 4.8. internal low-power oscillator electrical characteri stics ........... ............. 60 table 4.9. smartclock characterist ics ............. .......................................... ........... 61 table 4.10. adc0 electric al characteristics ....... .......................................... ........... 61 table 4.11. temperature sensor electrical char acteristics ............. .............. ......... 62 table 4.12. voltage reference elec trical characteristics ....... ............ ........... ......... 63 table 4.13. iref0 electrical char acteristics .......... .............. ............... ........... ......... 64 table 4.14. comparator electrical characteristics .... ................................. ............. 65 table 4.15. vreg0 electric al characteristics .... .......................................... ........... 66 table 4.16. dc-dc converter ( dc0) electrical characteristi cs ................. ............. 67 table 5.1. representative conversion times and energy consumption for the sar adc with 1.65 v high-s peed vref . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 8.1. cip-51 instruct ion set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 11.1. special f unction register (sfr) memory m ap (page 0x0) . . . . . . . . 120 table 11.2. special f unction register (sfr) memory m ap (page 0xf) . . . . . . . . 121 table 11.3. special f unction registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 12.1. interrupt summar y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 table 13.1. flash security summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 14.1. power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 table 15.1. example 16-bit crc out puts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 15.2. example 32-bit crc ou tputs ............ ................................................. 161 table 16.1. ipeak inductor current limit settings . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 19.1. recommended xfcn settings for crys tal mode . . . . . . . . . . . . . . . . 187 table 19.2. recommended xfcn se ttings for rc and c modes . . . . . . . . . . . . . 188 table 20.1. smartclock internal registers ............. ................................. ........... 194 table 20.2. smartclock lo ad capacitance settings . . . . . . . . . . . . . . . . . . . . . 201 table 20.3. smartclock bias settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 table 21.1. port i/o a ssignment for analog functi ons . . . . . . . . . . . . . . . . . . . . . 212 table 21.2. port i/o assi gnment for digital functions . . . . . . . . . . . . . . . . . . . . . . 213 table 21.3. port i/o assignmen t for external digital event capture functions . . 213 table 22.1. smbus clock source sele ction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235
c8051f91x-c8051f90x 13 rev. 1.3 table 22.2. minimum sda setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . 236 table 22.3. sources for hardware changes to smb0cn . . . . . . . . . . . . . . . . . . . 240 table 22.4. hardware address recognition ex amples (ehack = 1) . . . . . . . . . . 241 table 22.5. smbus status decoding wi th hardware ack generation disabled (ehack = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 table 22.6. smbus status decoding wi th hardware ack generation enabled (ehack = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 table 23.1. timer settings for standard baud rates using the internal 24.5 mhz o scillator . . . . . . . . . . . . . . . . . . . . . . . 259 table 23.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator . . . . . . . . . . . . . . . . . . . . . 259 table 24.1. spi slave timing paramete rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 table 25.1. timer 0 running modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 table 26.1. pca timebase input opti ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 table 26.2. pca0cpm and pc a0pwm bit settings for pca capture/compare mod- ules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 table 26.3. watchdog timer timeout in tervals . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
c8051f91x-c8051f90x rev. 1.3 14 list of registers sfr definition 5.1. adc0cn : adc0 control ........... .......................................... ........... 73 sfr definition 5.2. adc0cf: adc0 configuration ........ ................................. ............. 74 sfr definition 5.3. adc0 ac: adc0 accumulator configuratio n ................. ................ 75 sfr definition 5.4. adc0pwr: adc0 burst mode power-up time ............... ............. 76 sfr definition 5.5. adc0tk: adc0 burst mode track time ....... ............ ........... ......... 77 sfr definition 5.6. adc0h: adc0 data word high byte ......... ............... ........... ......... 78 sfr definition 5.7. adc0l: adc0 data word low byte ....... ............................ ........... 78 sfr definition 5.8. adc0gth: adc0 greater-than high byte ... ............ ........... ......... 79 sfr definition 5.9. adc0gtl: adc0 greater-than low byte .... ............ ........... ......... 79 sfr definition 5.10. adc0lth: adc0 less-than high byte ...... ............ ........... ......... 80 sfr definition 5.11. adc0ltl: ad c0 less-than low byte ........ ............ ........... ......... 80 sfr definition 5.12. adc0 mx: adc0 input channel select .... ........................... ......... 83 sfr definition 5.13. toffh: temperature sensor offset high by te .............. ............. 86 sfr definition 5.14. toffl : temperature sensor offset low byte ............ ................ 86 sfr definition 5.15. ref0cn: volt age reference control .......... ............ ........... ......... 89 sfr definition 6.1. iref 0cn: current reference control .... ............................ ........... 90 sfr definition 6.2. iref0cf: cu rrent reference configuration .. ............ ........... ......... 91 sfr definition 7.1. cpt0cn: comparator 0 control ................. ............... ........... ......... 95 sfr definition 7.2. cpt0 md: comparator 0 mode selection .. ........................... ......... 96 sfr definition 7.3. cpt1cn: comparator 1 control ................. ............... ........... ......... 97 sfr definition 7.4. cpt1 md: comparator 1 mode selection .. ........................... ......... 98 sfr definition 7.5. cpt0 mx: comparator0 input channel sele ct ............... .............. 100 sfr definition 7.6. cpt1 mx: comparator1 input channel sele ct ............... .............. 101 sfr definition 8.1. dpl: data po inter low byte ......... .............. ............... .................. 108 sfr definition 8.2. dph: data pointer high byte . ............................................. ......... 108 sfr definition 8.3. sp: sta ck pointer ................. ............................................... ......... 109 sfr definition 8.4. acc: accumulator ........ ............................................................... 109 sfr definition 8.5. b: b r egister ............... ........................................................ ......... 109 sfr definition 8.6. psw: program status word ..... .......................................... ......... 110 sfr definition 10.1. emi0 cn: external memory interface co ntrol .............. .............. 115 sfr definition 11.1. sfr page: sfr page ............. .......................................... ......... 118 sfr definition 12.1. ie: in terrupt enable .............. ............................................. ......... 127 sfr definition 12.2. ip: inte rrupt priority ............ ............................................... ......... 128 sfr definition 12.3. eie1 : extended interrupt enable 1 ......... ................................... 129 sfr definition 12.4. eip1 : extended interrupt priority 1 ....... ............................ ......... 130 sfr definition 12.5. eie2 : extended interrupt enable 2 ......... ................................... 131 sfr definition 12.6. eip2 : extended interrupt priority 2 ....... ............................ ......... 132 sfr definition 12.7. it01cf: int0 /int1 configuration .... ................................. ......... 134 sfr definition 13.1. psctl: prog ram store r/w control ................................ ......... 142 sfr definition 13.2. flk ey: flash lock and key ..... ................................................. 143 sfr definition 13.3. flscl: flash scale ............. ............................................. ......... 144 sfr definition 13.4. flwr: flash wr ite only ............. .............. ............... .................. 144 sfr definition 14.1. pmu0cf: powe r management unit configuration 1,2 ................ 151
c8051f91x-c8051f90x 15 rev. 1.3 sfr definition 14.2. pmu0md: po wer management unit mode .... ................. ........... 152 sfr definition 14.3. pcon: powe r management control register ................ ........... 153 sfr definition 15.1. crc0cn : crc0 control ........ .......................................... ......... 158 sfr definition 15.2. crc0in: crc0 data input ............ ................................. ........... 159 sfr definition 15.3. crc0da t: crc0 data output ............. ............................ ......... 159 sfr definition 15.4. crc0auto: crc0 automatic control ........ ............ .................. 160 sfr definition 15.5. crc0cnt: crc0 automatic flash sector count .......... ........... 160 sfr definition 15.6. crc0flip: crc0 bit flip .............. ................................. ........... 161 sfr definition 16.1. dc0cn: dc-dc converter control ............. ............ .................. 169 sfr definition 16.2. dc0cf: dc- dc converter configuration .... ............ .................. 170 sfr definition 16.3. dc0md: dc-dc mode .................. ................................. ........... 171 sfr definition 17.1. reg0cn: vo ltage regulator control .......... ............ .................. 172 sfr definition 18.1. vdm0cn: v dd/dc+ supply monitor control ................. ........... 177 sfr definition 18.2. rstsrc : reset source ......... .......................................... ......... 180 sfr definition 19.1. clksel: clock select ............ .......................................... ......... 186 sfr definition 19.2. oscicn: inte rnal oscillator control ......... ............... .................. 187 sfr definition 19.3. oscicl: intern al oscillator calibration .... ............... .................. 187 sfr definition 19.4. oscx cn: external oscillator control ................. .............. ......... 188 sfr definition 20.1. rtc0key: smartclock lock and key ........ ................. ........... 193 sfr definition 20.2. rtc0adr: smartclock address .. ................................. ......... 194 sfr definition 20.3. rtc0dat: sm artclock data ........ ................................. ......... 194 internal register definition 20. 4 . rtc0cn: smartclock control ............................. 202 internal register definition 20.5. rtc0xcn: smartclock oscillator control ........... 203 internal register definition 20.6. rtc0xcf: smartclock o scillator configuration . 204 internal register definition 20.7. rtc0pin: smartclock pin configuration ............ 204 internal register definition 20.8. capturen: smartclock ti mer capture .. ........... 205 internal register definition 20.9. alar mn: smartclock alarm programmed value 205 sfr definition 21.1. xbr0: port i/o crossbar register 0 ..... ............................ ......... 213 sfr definition 21.2. xbr1: port i/o crossbar register 1 ..... ............................ ......... 214 sfr definition 21.3. xbr2: port i/o crossbar register 2 ..... ............................ ......... 215 sfr definition 21.4. p0mask: port 0 mask register ...... ................................. ........... 216 sfr definition 21.5. p0mat: port0 match register ....... ................................. ........... 216 sfr definition 21.6. p1mask: port 1 mask register ...... ................................. ........... 217 sfr definition 21.7. p1mat: port1 match register ....... ................................. ........... 217 sfr definition 21.8. p0: port0 ....... .................................................................. ........... 219 sfr definition 21.9. p0skip: port0 skip .............. ............................................. ......... 219 sfr definition 21.10. p0mdin: port 0 input mode ............ ................................. ......... 220 sfr definition 21.11. p0md out: port0 output mode ................. ............ .................. 220 sfr definition 21.12. p0drv: port0 drive strength .................... ............ .................. 221 sfr definition 21.13. p1: po rt1 ............ ............................................................. ......... 222 sfr definition 21.14. p1skip: port1 skip ............ ............................................. ......... 222 sfr definition 21.15. p1mdin: port 1 input mode ............ ................................. ......... 223 sfr definition 21.16. p1md out : port1 output mode ................. ............ .................. 223 sfr definition 21.17. p1drv: port1 drive strength .................... ............ .................. 224 sfr definition 21.18. p2: po rt2 ............ ............................................................. ......... 224
c8051f91x-c8051f90x rev. 1.3 16 sfr definition 21.19. p2md out: port2 output mode ................. ............ .................. 225 sfr definition 21.20. p2drv: port2 drive strength .................... ............ .................. 225 sfr definition 22.1. smb0cf: smbu s clock/configuration ........ ............ .................. 233 sfr definition 22.2. smb0cn: smbu s control .............. ................................. ........... 235 sfr definition 22.3. smb0 adr: smbus slave address ......... ................................... 238 sfr definition 22.4. smb0adm: smbus slave address mask .... ............ .................. 238 sfr definition 22.5. smb0dat: smbu s data ................ ................................. ........... 239 sfr definition 23.1. scon0: serial port 0 control ..... .............. ............... .................. 253 sfr definition 23.2. sbuf0: seri al (uart0) port data buffer . ............... .................. 254 sfr definition 24.1. spincf g: spi configuration .. .......................................... ......... 264 sfr definition 24.2. spincn: spi co ntrol .............. .......................................... ......... 265 sfr definition 24.3. spinckr: spi clock rate ...... .......................................... ......... 266 sfr definition 24.4. spindat: spi data ............. ............................................. ......... 266 sfr definition 25.1. ckcon: clock control ........... .......................................... ......... 271 sfr definition 25.2. tcon: timer c ontrol .............. .......................................... ......... 276 sfr definition 25.3. tmod: timer m ode ................ .......................................... ......... 277 sfr definition 25.4. tl0: timer 0 low byte ......... ............................................. ......... 278 sfr definition 25.5. tl1: timer 1 low byte ......... ............................................. ......... 278 sfr definition 25.6. th0: timer 0 high byte .............. .............. ............... .................. 279 sfr definition 25.7. th1: timer 1 high byte .............. .............. ............... .................. 279 sfr definition 25.8. tmr2cn: timer 2 control ............. ................................. ........... 283 sfr definition 25.9. tmr2rll: ti mer 2 reload register low byte ............... ........... 284 sfr definition 25.10. tmr2 rlh: timer 2 reload re gister high byte . ..................... 284 sfr definition 25.11. tmr2l: timer 2 low byte .... .......................................... ......... 285 sfr definition 25.12. tmr2h timer 2 high byte ........... ................................. ........... 285 sfr definition 25.13. tmr3 cn: timer 3 control .... .......................................... ......... 289 sfr definition 25.14. tmr3 rll: timer 3 reload re gister low byte ... ..................... 290 sfr definition 25.15. tmr3 rlh: timer 3 reload re gister high byte . ..................... 290 sfr definition 25.16. tmr3l: timer 3 low byte .... .......................................... ......... 291 sfr definition 25.17. tmr3h timer 3 high byte ........... ................................. ........... 291 sfr definition 26.1. pca0cn : pca control ........... .......................................... ......... 306 sfr definition 26.2. pca0md: pca mo de ............. .......................................... ......... 307 sfr definition 26.3. pca0pwm: pca pwm configuration ......... ............ .................. 308 sfr definition 26.4. pc a0cpmn: pca capture/compare mode ................ .............. 309 sfr definition 26.5. pca 0l: pca counter/timer low byte ................. ..................... 310 sfr definition 26.6. pca0h: pca counter/timer high byte ....... ............ .................. 310 sfr definition 26.7. pca0cpln: pca capture module low byte . ................. ........... 311 sfr definition 26.8. pca0cphn: pca capture module high byte ................ ........... 311 c2 register definition 27.1. c2ad d: c2 addr ess ....... .............. ............... .................. 312 c2 register definition 27.2. devi ceid: c2 device id .............. ............... .................. 313 c2 register definition 27.3. revi d: c2 revision id ............... ................................... 313 c2 register definition 27.4. fp ctl: c2 flash programming cont rol ............. ........... 314 c2 register definition 27.5. fp dat: c2 flash programming data ................. ........... 314 sfr definition 5.1. adc0cn: adc0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 sfr definition 5.2. adc0cf: adc0 c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
c8051f91x-c8051f90x 17 rev. 1.3 sfr definition 5.3. adc0 ac: adc0 accumulator configuration . . . . . . . . . . . . . . . . . 79 sfr definition 5.4. adc0 pwr: adc0 burst mode power-up time . . . . . . . . . . . . . . 80 sfr definition 5.5. adc0tk : adc0 burst mode track time . . . . . . . . . . . . . . . . . . . . 81 sfr definition 5.6. adc0h: adc0 data word high byte . . . . . . . . . . . . . . . . . . . . . . 82 sfr definition 5.7. adc0l: adc0 data word low byte . . . . . . . . . . . . . . . . . . . . . . . 82 sfr definition 5.8. adc0gth: a dc0 greater-than high byte . . . . . . . . . . . . . . . . . . 83 sfr definition 5.9. adc0gtl: ad c0 greater-than low byte . . . . . . . . . . . . . . . . . . 83 sfr definition 5.10. adc0lth: ad c0 less-than high byte . . . . . . . . . . . . . . . . . . . 84 sfr definition 5.11. adc0ltl: adc0 less-than low byte . . . . . . . . . . . . . . . . . . . . 84 sfr definition 5.12. adc0mx : adc0 input channel sele ct . . . . . . . . . . . . . . . . . . . . 87 sfr definition 5.13. toffh: temper ature sensor offset high byte . . . . . . . . . . . . . . 90 sfr definition 5.14. toffl : temperature sensor offset low by te . . . . . . . . . . . . . . 90 sfr definition 5.15. ref0cn : voltage reference contro l . . . . . . . . . . . . . . . . . . . . . 93 sfr definition 6.1. iref0c n: current reference control . . . . . . . . . . . . . . . . . . . . . . 94 sfr definition 6.2. iref0c f: current reference configuration . . . . . . . . . . . . . . . . . 95 sfr definition 7.1. cpt0cn: comparator 0 control . . . . . . . . . . . . . . . . . . . . . . . . . . 99 sfr definition 7.2. cpt0 md: comparator 0 mode se lection . . . . . . . . . . . . . . . . . . 100 sfr definition 7.3. cpt1cn : comparator 1 control . . . . . . . . . . . . . . . . . . . . . . . . . 101 sfr definition 7.4. cpt1 md: comparator 1 mode se lection . . . . . . . . . . . . . . . . . . 102 sfr definition 7.5. cpt0 mx: comparator0 input channel select . . . . . . . . . . . . . . . 104 sfr definition 7.6. cpt1 mx: comparator1 input channel select . . . . . . . . . . . . . . . 105 sfr definition 8.1. dpl: da ta pointer low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 sfr definition 8.2. dph: data pointer high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 sfr definition 8.3. sp: stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 sfr definition 8.4. acc: a ccumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 sfr definition 8.5. b: b regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 sfr definition 8.6. psw: pr ogram status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 sfr definition 10.1. emi0 cn: external memory interface cont rol . . . . . . . . . . . . . . 119 sfr definition 11.1. sfr page: sfr page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 sfr definition 12.1. ie: interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 sfr definition 12.2. ip: interr upt prior ity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 sfr definition 12.3. eie1: extended interrupt enable 1 . . . . . . . . . . . . . . . . . . . . . . 133 sfr definition 12.4. eip1: extended interrupt priority 1 . . . . . . . . . . . . . . . . . . . . . . 134 sfr definition 12.5. eie2: extended interrupt enable 2 . . . . . . . . . . . . . . . . . . . . . . 135 sfr definition 12.6. eip2: extended interrupt priority 2 . . . . . . . . . . . . . . . . . . . . . . 136 sfr definition 12.7. it01cf: int0 /int1 configuration . . . . . . . . . . . . . . . . . . . . . . . 138 sfr definition 13.1. psctl: program store r/w control . . . . . . . . . . . . . . . . . . . . . 146 sfr definition 13.2. flkey: flash lock and key . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 sfr definition 13.3. flscl: flash scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 sfr definition 13.4. flwr: flash write only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 sfr definition 14.1. pmu0cf: powe r management unit configuration 1,2 . . . . . . . . . . . 155 sfr definition 14.2. pmu0md: powe r management unit mode . . . . . . . . . . . . . . . . 156 sfr definition 14.3. pcon: powe r management control register . . . . . . . . . . . . . . 157 sfr definition 15.1. crc0cn: crc0 c ontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 sfr definition 15.2. crc0in: crc0 da ta input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
c8051f91x-c8051f90x rev. 1.3 18 sfr definition 15.3. crc0da t: crc0 data output . . . . . . . . . . . . . . . . . . . . . . . . . 163 sfr definition 15.4. crc0 auto: crc0 automatic control . . . . . . . . . . . . . . . . . . . 164 sfr definition 15.5. crc0cnt: crc0 automatic flash sector count . . . . . . . . . . . 164 sfr definition 15.6. crc0flip: crc0 bi t flip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 sfr definition 16.1. dc0cn: dc-dc converter control . . . . . . . . . . . . . . . . . . . . . . 173 sfr definition 16.2. dc0cf: dc- dc converter configuration . . . . . . . . . . . . . . . . . 174 sfr definition 16.3. dc0md: dc-dc mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 sfr definition 17.1. reg0cn: volt age regulator control . . . . . . . . . . . . . . . . . . . . 176 sfr definition 18.1. vdm0cn: v dd/dc+ supply monitor control . . . . . . . . . . . . . . 181 sfr definition 18.2. rstsrc: reset source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 sfr definition 19.1. clksel: clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 sfr definition 19.2. oscicn: inter nal oscillator control . . . . . . . . . . . . . . . . . . . . . 191 sfr definition 19.3. oscicl: intern al oscillator calibration . . . . . . . . . . . . . . . . . . . 191 sfr definition 19.4. oscxcn: external oscillator c ontrol . . . . . . . . . . . . . . . . . . . . 192 sfr definition 20.1. rtc0key: smartclock lock and key . . . . . . . . . . . . . . . . . . 197 sfr definition 20.2. rtc0 adr: smartclock address . . . . . . . . . . . . . . . . . . . . . . 198 sfr definition 20.3. rtc0da t: smartclock data . . . . . . . . . . . . . . . . . . . . . . . . . 198 internal register definition 20. 4. rtc0cn: smartclock control . . . . . . . . . . . . . . . 206 internal register definition 20.5. rtc0xcn: smartclock oscillator control . . . . . . 207 internal register definition 20.6. rtc0xcf: smartclock o scillator configuration . 208 internal register definition 20.7. rtc0pin: smartclock pin configuration . . . . . . 208 internal register definition 20.8. capturen: smartclock ti mer capture . . . . . . . 209 internal register definition 20.9. alar mn: smartclock alarm programmed value 209 sfr definition 21.1. xbr0: port i/o crossbar regist er 0 . . . . . . . . . . . . . . . . . . . . . 217 sfr definition 21.2. xbr1: port i/o crossbar regist er 1 . . . . . . . . . . . . . . . . . . . . . 218 sfr definition 21.3. xbr2: port i/o crossbar regist er 2 . . . . . . . . . . . . . . . . . . . . . 219 sfr definition 21.4. p0mask : port0 mask register . . . . . . . . . . . . . . . . . . . . . . . . . 220 sfr definition 21.5. p0mat: port0 ma tch register . . . . . . . . . . . . . . . . . . . . . . . . . . 220 sfr definition 21.6. p1mask : port1 mask register . . . . . . . . . . . . . . . . . . . . . . . . . 221 sfr definition 21.7. p1mat: port1 ma tch register . . . . . . . . . . . . . . . . . . . . . . . . . . 221 sfr definition 21.8. p0: port0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 sfr definition 21.9. p0ski p: port0 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 sfr definition 21.10. p0mdin : port0 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 sfr definition 21.11. p0mdout: port 0 output mode . . . . . . . . . . . . . . . . . . . . . . . . 224 sfr definition 21.12. p0drv: port0 drive strength . . . . . . . . . . . . . . . . . . . . . . . . . 225 sfr definition 21.13. p1: port1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 sfr definition 21.14. p1 skip: port1 skip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 sfr definition 21.15. p1mdin : port1 input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 sfr definition 21.16. p1mdout: port 1 output mode . . . . . . . . . . . . . . . . . . . . . . . . 227 sfr definition 21.17. p1drv: port1 drive strength . . . . . . . . . . . . . . . . . . . . . . . . . 228 sfr definition 21.18. p2: port2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 sfr definition 21.19. p2mdout: port 2 output mode . . . . . . . . . . . . . . . . . . . . . . . . 229 sfr definition 21.20. p2drv: port2 drive strength . . . . . . . . . . . . . . . . . . . . . . . . . 229 sfr definition 22.1. smb0cf: smbus clock/configuration . . . . . . . . . . . . . . . . . . . 237 sfr definition 22.2. smb0cn : smbus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239
c8051f91x-c8051f90x 19 rev. 1.3 sfr definition 22.3. smb0a dr: smbus slave address . . . . . . . . . . . . . . . . . . . . . . 242 sfr definition 22.4. smb0adm: sm bus slave address mask . . . . . . . . . . . . . . . . . 242 sfr definition 22.5. smb0dat: smbus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 sfr definition 23.1. scon0: serial port 0 control . . . . . . . . . . . . . . . . . . . . . . . . . . 257 sfr definition 23.2. sbuf0: serial (uart0) port data buffer . . . . . . . . . . . . . . . . . 258 sfr definition 24.1. spincf g: spi configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 sfr definition 24.2. spincn: spi control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 sfr definition 24.3. spinckr: spi clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 sfr definition 24.4. spindat: spi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 sfr definition 25.1. ckcon: clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 sfr definition 25.2. tcon: timer cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 sfr definition 25.3. tmod: ti mer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 sfr definition 25.4. tl0: timer 0 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 sfr definition 25.5. tl1: timer 1 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 sfr definition 25.6. th0: timer 0 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 sfr definition 25.7. th1: timer 1 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 sfr definition 25.8. tmr2cn: timer 2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 sfr definition 25.9. tmr2rll: ti mer 2 reload register low byte . . . . . . . . . . . . . 288 sfr definition 25.10. tmr2 rlh: timer 2 reload re gister high byte . . . . . . . . . . . 288 sfr definition 25.11. tmr2l: timer 2 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 sfr definition 25.12. tmr2h timer 2 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 sfr definition 25.13. tmr3cn: timer 3 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 sfr definition 25.14. tmr3 rll: timer 3 reload regi ster low byte . . . . . . . . . . . . 294 sfr definition 25.15. tmr3 rlh: timer 3 reload re gister high byte . . . . . . . . . . . 294 sfr definition 25.16. tmr3l: timer 3 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 sfr definition 25.17. tmr3h timer 3 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 sfr definition 26.1. pca0cn: pca control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310 sfr definition 26.2. pca0md: pca mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 sfr definition 26.3. pca0pwm: pc a pwm configuration . . . . . . . . . . . . . . . . . . . . 312 sfr definition 26.4. pc a0cpmn: pca capture/compare mode . . . . . . . . . . . . . . . 313 sfr definition 26.5. pca0l: pca counter/timer low byte . . . . . . . . . . . . . . . . . . . 314 sfr definition 26.6. pca0h: pca counter/timer high byte . . . . . . . . . . . . . . . . . . . 314 sfr definition 26.7. pca0cpln: pca capture module low byte . . . . . . . . . . . . . . . 315 sfr definition 26.8. pca0cphn: pca capture module high byte . . . . . . . . . . . . . . 315 c2 register definition 27.1. c2add: c2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 c2 register definition 27.2. device id: c2 device id . . . . . . . . . . . . . . . . . . . . . . . . 317 c2 register definition 27.3. revid: c2 revision id . . . . . . . . . . . . . . . . . . . . . . . . . 317 c2 register definition 27.4. fp ctl: c2 flash programming cont rol . . . . . . . . . . . . 318 c2 register definition 27.5. fp dat: c2 flash programming data . . . . . . . . . . . . . . 318
c8051f91x-c8051f90x rev. 1.3 20 1. system overview c8051f91x-c8051f90x devices are fully integrated mixed-signal system-on-a- chip mcus. highlighted features are listed below. refer to ta b l e 2.1 for specific product feature sele ction and part ordering numbers. ? single/dual battery operation with on-chip dc-dc boost converter ? high-speed pipelined 8051-compatible microcontroller core (up to 25 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? 10-bit 300 ksps or 12-bit 75 ksps single-ended adc with analog multiplexer ? 6-bit programmable current reference. re solution can be increased with pwm ? precision programmable 24.5 mhz internal oscillator with spread s pectrum technology ?16 kb or 8 kb of on-chip flash memory ? 768 bytes of on-chip ram ?smbus/i 2 c, enhanced uart, and two enhanced spi serial interfaces implemented in hardware ? four general-purpose 16-bit timers ? programmable counter/timer array (pca) with six capture/compare modules and watchdog timer func tion ? on-chip power-on reset, v dd monitor, and temperature sensor ? two on-chip voltage comparators with 15 capacitive touch sense inputs. ? 16 port i/o (5 v tolerant) with on-chip power-on reset, v dd monitor, watchdog timer, and clock oscillator, the c8051f91x- c8051f90x devices are truly stand-alone system-o n-a-chip solutions. the flash memory can be reprogrammed even in-circuit, providing non-volatile da ta storage, and also allowing field upgrades of the 8051 firmware. user software has complete control of all peripherals, and may individually shut down any or all peripherals for power savings. the on-chip silicon labs 2- wire (c2) d evelopment interface allo ws non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digita l peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions, a llowing in-system debugging without occupying package pins. each device is specified for 0.9 to 1.8 v, 0.9 to 3.6 v, or 1.8 to 3.6 v operation over the industrial tem perature range (?40 to +85 c). the port i/o and rst pins are tolerant of input signals up to 5 v. the c80 51f91x-c8051f90x devices are available in 24-p in qfn or qsop packages. both package options are lead-free and rohs compliant. see table 2.1 for ordering information. block diagrams are included in figure 1.1 through figure 1.4 .
c8051f91x-c8051f90x 21 rev. 1.3 figure 1.1. c8051f912 block diagram figure 1.2. c8051f911 block diagram port 0 drivers digital peripherals uart timers 0, 1, 2, 3 pca/ wdt smbus priority crossbar decoder p0.0/vref p0.1/agnd p0.2/xtal1/rtcout p0.3/xtal2/wakeout p0.4/tx p0.5/rx p0.6/cnvstr p0.7/iref0 crossbar control port i/o configuration cip-51 8051 controller core 16k byte isp flash program memory 256 byte sram sfr bus 512 byte xram port 1 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 port 2 drivers spi 0,1 analog peripherals comparators + - power net vdd/dc+ gnd/dc- xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset/pmu reset c2d c2ck/rst wake 12/10-bit 75/300ksps adc a m u x temp sensor external vref internal vref vdd xtal2 low power 20 mhz oscillator 6-bit iref vref gnd p1.6 iref0 cp0, cp0a p2.7/c2d + - cp1, cp1a smartclock oscillator xtal3 xtal4 dc/dc converter gnd vreg digital power analog power crc engine vbat dcen port 0 drivers digital peripherals uart timers 0, 1, 2, 3 pca/ wdt smbus priority crossbar decoder p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7/iref0 crossbar control port i/o configuration cip-51 8051 controller core 16k byte isp flash program memory 256 byte sram sfr bus 512 byte xram port 1 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 port 2 drivers spi 0,1 analog peripherals comparators + - power net vdd/dc+ gnd/dc- xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset/pmu reset c2d c2ck/rst wake 10-bit 300ksps adc a m u x temp sensor external vref internal vref vdd xtal2 low power 20 mhz oscillator 6-bit iref vref gnd p1.6 iref0 cp0, cp0a p2.7/c2d + - cp1, cp1a smartclock oscillator xtal3 xtal4 dc/dc converter gnd vreg digital power analog power crc engine vbat dcen
c8051f91x-c8051f90x rev. 1.3 22 figure 1.3. c8051f902 block diagram figure 1.4. c8051f901 block diagram port 0 drivers digital peripherals uart timers 0, 1, 2, 3 pca/ wdt smbus priority crossbar decoder p0.0/vref p0.1/agnd p0.2/xtal1/rtcout p0.3/xtal2/wakeout p0.4/tx p0.5/rx p0.6/cnvstr p0.7/iref0 crossbar control port i/o configuration cip-51 8051 controller core 8k byte isp flash program memory 256 byte sram sfr bus 512 byte xram port 1 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 port 2 drivers spi 0,1 analog peripherals comparators + - power net vdd/dc+ gnd/dc- xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset/pmu reset c2d c2ck/rst wake 12/10-bit 75/300ksps adc a m u x temp sensor external vref internal vref vdd xtal2 low power 20 mhz oscillator 6-bit iref vref gnd p1.6 iref0 cp0, cp0a p2.7/c2d + - cp1, cp1a smartclock oscillator xtal3 xtal4 dc/dc converter gnd vreg digital power analog power crc engine vbat dcen port 0 drivers digital peripherals uart timers 0, 1, 2, 3 pca/ wdt smbus priority crossbar decoder p0.0/vref p0.1/agnd p0.2/xtal1 p0.3/xtal2 p0.4/tx p0.5/rx p0.6/cnvstr p0.7/iref0 crossbar control port i/o configuration cip-51 8051 controller core 8k byte isp flash program memory 256 byte sram sfr bus 512 byte xram port 1 drivers p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 port 2 drivers spi 0,1 analog peripherals comparators + - power net vdd/dc+ gnd/dc- xtal1 sysclk system clock configuration external oscillator circuit precision 24.5 mhz oscillator debug / programming hardware power on reset/pmu reset c2d c2ck/rst wake 10-bit 300ksps adc a m u x temp sensor external vref internal vref vdd xtal2 low power 20 mhz oscillator 6-bit iref vref gnd p1.6 iref0 cp0, cp0a p2.7/c2d + - cp1, cp1a smartclock oscillator xtal3 xtal4 dc/dc converter gnd vreg digital power analog power crc engine vbat dcen
c8051f91x-c8051f90x 23 rev. 1.3 1.1. cip-51? microcontroller core 1.1.1. fully 8051 compatible the c8051f91x-c8051f90x family utilizes silicon labs' proprietary cip-51 microcontroller core. the cip- 51 is fully compatible with the mc s-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the cip-51 core offers all the peripherals included with a standard 8052. 1.1.2. improved throughput the cip-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. in a standard 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute with a maximum system clock of 12-to-24 mhz. by contrast, the cip-51 cor e executes 70% of its instructions in one or two sy stem clock cycles, with only four instructions taking more than four system clock cycles. the cip-51 has a total of 109 instructions. the table be low shows the total number of instructions that require each execution time. with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. 1.1.3. additional features the c8051f91x-c8051f90x soc family includes several key enhancements to the cip-51 core and peripherals to improve performance and ease of use in end applications. the extended interrupt handler provides multiple int errupt sources into t he cip-51 allowing numerous analog and digital peripherals to interrupt the cont roller. an interrupt driv en system requires less intervention by the mcu, giving it more effective throughput. the extra interrupt sources are very useful when building multi-task ing, real-time systems. eight reset sources are available: power-on reset circuitry (por), an on-chip v dd monitor (forces reset when power supply voltage drops below safe leve ls), a watchdog timer, a missing clock detector, smartclock oscillator fail or alarm, a voltage level det ection from comparator0, a forced software reset, an external reset pin, and an illegal flash access protection circuit. each reset source exce pt for the por, reset input pin, or flash error may be disabled by the user in software. the wdt may be permanently disabled in software after a powe r-on reset during mcu initialization. the internal oscillator factory calibra ted to 24.5 mhz and is accurate to 2% over the full temperature and supply range. the internal os cillator period can also be adjusted by user fi rmware. an ad ditional 20 mhz low power oscillator is also available which facilitat es low-power operation. an external oscillator drive circuit is included, allowing an external crystal, cerami c resonator, capacitor, rc, or cmos clock source to generate the system clock. if desired, the system cloc k source may be switched on-the-fly between both internal and external oscillator circ uits. an external oscilla tor can also be extremely useful in low power applications, allowing the mcu to run from a slow (pow er saving) source, while pe riodically switching to the fast (up to 25 mhz) internal oscillator as needed. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1
c8051f91x-c8051f90x rev. 1.3 24 1.2. port input/output digital and analog resources are available through 16 i/o pins. port pins are organized as three byte-wide ports. port pins p0.0?p1.6 can be de fined as digital or analog i/o. digital i/o pins can be assigned to one of the internal digital resources or used as general purpose i/o (gpio). analog i/o pins are used by the internal analog resources. p2.7 can be used as gpio and is shared with the c2 interface data signal (c2d). see section ?27. c2 interface? on page 316 for more details. the designer has complete control over which digital an d analog functions are as signed to individual port pins, limited only by the nu mber of physical i/o pins. this resour ce assignment flexibility is achieved through the use of a priority crossbar decoder. see section ?21.3. priority crossbar decoder? on page 214 for more information on the crossbar. all port i/os are 5 v tolerant when used as digital inputs or open-d rain outputs. for port i/os configured as push-pull outputs, current is sourced from the vdd/dc+ supply. port i/os used for analog functions can operate up to the vdd/dc+ supply voltage. see section ?21.1. port i/o modes of operation? on page 211 for more information on port i/o operating modes and th e electrical specifications chapter for detailed electrical specifications. figure 1.5. port i/o functional block diagram xbr0, xbr1, xbr2, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 port match p0mask, p0mat p1mask, p1mat uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 7 pca 4 cp0 cp1 outputs spi0 spi1 4 p1 i/o cells p1.0 p1.6 7 (port latches) p0 (p0.0-p0.7) (p1.0-p1.6) 8 7 p1 p2 i/o cell p2 (p2.7) 1 1 pnmdout, pnmdin registers p2.7 to analog peripherals (adc0, cp0, and cp1 inputs, vref, iref0, agnd) external interrupts ex0 and ex1
c8051f91x-c8051f90x 25 rev. 1.3 1.3. serial ports the c8051f91x-c8051f90x family includes an smbus/i 2 c interface, a full-duplex uart with enhanced baud rate configuration, and two en hanced spi interfaces. each of the se rial buses is fully implemented in hardware and makes extensive use of the cip-51's inte rrupts, thus requiring very little cpu intervention. 1.4. programmable counter array an on-chip programmable counter/timer array (pca) is included in addition to the four 16-bit general purpose counter/timers. the pca c onsists of a dedicated 16-bit c ounter/timer time base with six programmable capture/compare module s. the pca clock is derived from one of six sources: the system clock divided by 12, the system clock divided by 4, ti mer 0 overflows, an external clock input (eci), the system clock, or the external oscilla tor clock source divided by 8. ?f9 12 and ?f902 device s also support a smartclock divided by 8 clock source. each capture/compare module can be configured to oper ate in a va riety of modes: edge-triggered capture, software timer, high-speed output, pulse width modulator (8, 9, 10, 11, or 16-bit), or frequency output. additionally, capture/compare module 5 offers watchd og timer (wdt) capabilit ies. following a system reset, module 5 is configured and enabled in wdt mode. the pca capture/compare module i/o and external clock input may be routed to port i/o via the digital crossbar. figure 1.6. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 cex1 eci crossbar cex2 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 capture/compare module 4 capture/compare module 3 capture/compare module 5 / wdt cex4 cex5 cex3 smartclock/8* * only available on ?f912 and ?f902 devices.
c8051f91x-c8051f90x rev. 1.3 26 1.5. sar adc with 16-bit auto-averag ing accumulator and autonomous low power burst mode c8051f91x-c8051f90x devices have a 300 ksps, 10-bit or 75 ksps 12-bit successive-approximation- r egister (sar) adc with integrated track-and-hold an d programmable window detector. adc0 also has an autonomous low power burst mode which can automatically enable adc0, capture and accumulate samples, then place adc0 in a low power shutdown mode without cpu intervention. it also has a 16-bit accumulator that can automatically average the adc re sults, providing an effective 11, 12, or 13 bit adc result without any additional cpu intervention. the adc can sample the voltage at any of the gpio pi n s (with the exception of p2.7) and has an on-chip attenuator that allows it to measure voltages up to twice the voltage reference. additional adc inputs include an on-chip temperature sensor, the vdd/dc+ supply voltage, the vbat supply voltage, and the internal digital supply voltage. figure 1.7. adc0 functional block diagram adc0cf amp0gn ad0tm ad08be ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10/12-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int bursten ad0en timer 0 overflow timer 2 overflow timer 3 overflow start conversion 000 ad0busy (w) vdd adc0lth ad0wint 001 010 011 100 cnvstr input window compare logic adc0ltl adc0gth adc0gtl adc0l ain+ from amux0 burst mode logic adc0tk adc0pwr 16-bit accumulator
c8051f91x-c8051f90x 27 rev. 1.3 figure 1.8. adc0 multiplexer block diagram 1.6. programmable current reference (iref0) c8051f91x-c8051f90x devices include an on-chip prog rammable current reference (source or sink) with two output current settings: low power mode and high current mode. the maximum current output in low power mode is 63 a (1 a steps) and the maximum current ou tp ut in high current mode is 504 a (8 a step s). 1.7. comparators c8051f91x-c8051f90x devices include two on-chip programmable voltage comparators: comparator 0 (cpt0) which is shown in figure 1.9 ; comparator 1 (cpt1) which is shown in figure 1.10 . the two comparators operate identically but ma y dif fer in their ability to be used as reset or wake-up sources. see section ?18. reset sources? on page 177 and the section ?14. power management? on page 149 for details on reset sources and low power mode wake-up source s, respec tively. the comparator offers programmable response time a nd hysteresis, an analog in put multiplexer, and two outputs that are optionally available at the port pins : a synchronous ?latched? output (cp0, cp1), or an asynchronous ?raw? output (cp0a, cp1a). the asyn chronous cp0a signal is available even when the system clock is not active. this allows the comparator to operate and generate an output when the device is in some low power modes. the comparator inputs may be connected to port i/o pins or to o ther internal signals. port pins may also be used to directly sense capacitive touch switches. adc0 temp sensor amux vbat adc0mx ad0mx4 ad0mx3 ad0mx2 ad0mx1 am0mx0 ain+ p0.0 p1.6 digital supply vdd/dc+ programmable attenuator gain = 0. 5 or 1
c8051f91x-c8051f90x rev. 1.3 28 figure 1.9. comparator 0 functional block diagram figure 1.10. comparator 1 functional block diagram vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp0 + px.x cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 rising-edge cp0 falling-edge cp0 interrupt px.x px.x px.x cp0 - (asynchronous) analog input multiplexer vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp1 + px.x cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 cpt0md cp1rie cp1fie cp1md1 cp1md0 cp1 cp1a cp1 rising-edge cp1 falling-edge cp1 interrupt px.x px.x px.x cp1 - (asynchronous) analog input multiplexer
c8051f91x-c8051f90x 29 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 30 2. ordering information table 2.1. product selection guide ordering part number 1 mips (peak) flash memory (kb) ram (bytes) smartclock real time clock smbus/i 2 c uart enhanced spi timers (16-bit) programmable counter array digital port i/os 10-bit 300ksps adc programmable current reference internal voltage reference temperature sensor analog comparators lead-free (rohs compliant) c8051f9xx plus features 2 package c8051f912-d-gm 25 16 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? ? qfn-24 c8051f912-d-gu 25 16 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? ? qsop-24 c8051f912-d-gdi 25 16 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? ? tested die c8051f911-d-gm 25 16 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? qfn-24 c8051f911-d-gu 25 16 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? qsop-24 c8051f911-d-gdi 25 16 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? tested die c8051f902-d-gm 25 8 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? ? qfn-24 c8051f902-d-gu 25 8 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? ? qsop-24 c8051f902-d-gdi 25 8 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? ? tested die c8051f901-d-gm 25 8 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? qfn-24 c8051f901-d-gu 25 8 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? qsop-24 C8051F901-D-GDI 25 8 768 ? 1 1 2 4 ? 16 ? ? ? ? 2 ? tested die 1. s tarting with silicon revision c, the ordering part numbers have been updated to include the silicon revision and use this format: "c8051f912-c-gm". package marking diagrams are included as figure 3.3 and figure 3.4 to help identify the silicon revision. 2. t he 'f9xx plus features are a set of enhancements that allow greater power ef ficiency and increased functionality. they include 12-bit adc mode, pwm enhanced iref, ultr a-low power smartclock lfo, vbat input voltage from 0.9 to 3.6 v, and vbat battery low indicator. the 'f9xx pl us features are described in detail in "an431: f93x-f90x software porting guide."
c8051f91x-c8051f90x 31 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 31 3. pinout and package definitions table 3.1. pin definitions for the c8051f91x-c8051f90x name pin numbers type description ?f912-gm ?f902-gm ?f911-gm ?f901-gm ?f912-gu ?f902-gu ?f911-gu ?f901-gu vbat 5 8 p in battery supply voltage. c8051f911/01 devices: must be 0.9 to 1.8 v in single-cell battery mode and 1.8 to 3.6 v in dua l-cell battery mode. c8051f912/02 devices: must be 0.9 to 3.6 v in single-cell battery mode and 1.8 to 3.6 v in dua l-cell battery mode. v dd / dc+ 3 6 p in p out power supply voltage. must be 1.8 to 3.6 v. this supply voltage is not re quired in low power sleep mode. this voltage must always be > vbat. positive output of the dc-dc converter. in single-cell battery mode, a 1 f ceramic capacitor is required between dc+ and dc?. this pin can supply power to external devices when operating in single- cell battery mode. dc? / gnd 1 4 p in g dc-dc converter return current path . in single-cell battery mode, this pin is typically not connected to ground. in dual-cell battery mode, this pi n must be connected directly to ground. gnd 2 5 g required ground. dcen 4 7 p in g dc-dc enable pin. in single-cell battery mode, this pin must be conne cted to vbat through a 0.68 h inductor. in dual-cell battery mode, this pi n must be connected directly to ground. rst / c2ck 6 9 d i/o d i/o device reset. open-drain out put of internal por or v dd monitor. an external source can initiate a system reset by driving this pin low for at least 15 s. a 1 k to 5 k pullup to v dd is recom - mended. see section ?18. reset sources? on page 177 for a com - plete description. clock signal for the c2 debug interface. p2.7/ c2d 7 10 d i/o d i/o port 2.7. this pin can only be used as gpio. the crossbar cannot route signa ls to this pin and it cannot be configured as an analog input. see port i/o section for a complete description. bi-directional data signal for the c2 debug interface. *note: a vailable only on the c8051f912/02.
c8051f91x-c8051f90x 32 rev. 1.3 xtal3 9 12 a in smartclock oscillator crystal input. see section 20 for a complete description. xtal4 8 11 a out smartclock oscillator crystal output. see section 20 for a complete description. p0.0 v ref 24 3 d i/o or a i n a in a out port 0.0. see port i/o secti on for a complete description. external v ref input. internal v ref output. external v ref decoupling capacitors are recommended. see section ?5.9. voltage and ground reference options? on page 91 . p0.1 agnd 23 2 d i/o or a i n g port 0.1. see port i/o secti on for a complete description. optional analog ground. see section ?5.9. voltage and ground reference options? on page 91 . p0.2 xtal1 rtcout* 22 1 d i/o or a i n a in port 0.2. see port i/o secti on for a complete description. external clock input. this pin is the external oscillator return for a cryst al or resonator. see section ?19. clocking sources? on page 185 . buffered smartclock oscillator output. p0.3 xtal2 wakeout* 21 24 d i/o or a i n a out d in a in port 0.3. see section ?21. port input/output? on page 210 for a complete description. external clock output. this pin is the excitation driver for an exter - nal crystal or resonator. external clock input. this pin is the external clock input in external cmos clock m ode. external clock input. this pin is the external clock input in capaci - tor or rc oscillator configurations. see section ?19. clocking sources? on page 185 for complete details. wake-up request signal to wake up external devices (e.g. an external dc-dc converter). p0.4 tx 20 23 d i/o or a i n d out port 0.4. see section ?21. port input/output? on page 210 for a complete description. uart tx pin. see section ?21. port input/output? on page 210 . p0.5 rx 19 22 d i/o or a i n d in port 0.5. see section ?21. port input/output? on page 210 for a complete description. uart rx pin. see section ?21. port input/output? on page 210 . table 3.1. pin definitions for the c8051f91x-c8051f90x (continued) name pin numbers type description ?f912-gm ?f902-gm ?f911-gm ?f901-gm ?f912-gu ?f902-gu ?f911-gu ?f901-gu *note: available only on the c8051f912/02.
c8051f91x-c8051f90x rev. 1.3 33 p0.6 cnvstr 18 21 d i/o or a i n d in port 0.6. see section ?21. port input/output? on page 210 for a complete description. external convert start input for adc0. see section ?5.7. adc0 analog multiplexer? on page 86 for a complete description. p0.7 iref0 17 20 d i/o or a i n a out port 0.7. see section ?21. port input/output? on page 210 for a complete description. iref0 output. see iref section for complete description. p1.0 16 19 d i/o or a in port 1.0. see section ?21. port input/output? on page 210 for a complete description. may also be used as sck for spi1. p1.1 15 18 d i/o or a in port 1.1. see section ?21. port input/output? on page 210 for a complete description. may also be used as miso for spi1. p1.2 14 17 d i/o or a in port 1.2. see section ?21. port input/output? on page 210 for a complete description. may also be used as mosi for spi1. p1.3 13 16 d i/o or a in port 1.3. see section ?21. port input/output? on page 210 for a complete description. may also be used as nss for spi1. p1.4 12 15 d i/o or a in port 1.4. see section ?21. port input/output? on page 210 for a complete description. p1.5 11 14 d i/o or a in port 1.5. see section ?21. port input/output? on page 210 for a complete description. p1.6 10 13 d i/o or a in port 1.6. see section ?21. port input/output? on page 210 for a complete description. table 3.1. pin definitions for the c8051f91x-c8051f90x (continued) name pin numbers type description ?f912-gm ?f902-gm ?f911-gm ?f901-gm ?f912-gu ?f902-gu ?f911-gu ?f901-gu *note: available only on the c8051f912/02.
c8051f91x-c8051f90x 34 rev. 1.3 figure 3.1. qfn-24 pinout diagram (top view) p2.7/c2d xtal4 xtal3 p1.6 p1.5 p1.4 10 11 12 8 7 9 gnd/dc? gnd vdd/dc+ dcen vbat rst/c2ck 4 5 6 2 1 3 p0.5/rx p0.4/tx p0.3/xtal2/wakeout* p0.2/xtal1/rtcout* p0.1/agnd p0.0/vref 22 23 24 20 19 21 c8051f912/02-gm c8051f911/01-gm top view gnd (optional connection) p1.3 p1.2 p1.1 p1.0 p0.7/iref0 p0.6/cnvstr 15 14 13 17 18 16 *note: signal only available on 'f912 and 'f902 devices.
c8051f91x-c8051f90x rev. 1.3 35 figure 3.2. qsop-24 pinout diagram f912 (top view) p0.2/xtal1/rtcout* p0.3/xtal2/wakeout* p0.4/tx p0.5/rx p0.6/cnvstr p0.7/iref0 p1.0 p1.1 p1.2 p1.3 c8051f912/02 ? gu c8051f911/01 ? gu p0.1/agnd p0.0/vref gnd vdd/dc+ dcen vbat p2.7/c2d p1.4 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 xtal4 xtal3 11 12 p1.5 p1.6 14 13 gnd/dc- rst/c2ck *note: signal only available on 'f912 and 'f902 devices.
c8051f91x-c8051f90x 36 rev. 1.3 figure 3.3. qfn-24 package marking diagram first character of the trace code identifies the silicon revision
c8051f91x-c8051f90x rev. 1.3 37 figure 3.4. qsop-24 package marking diagram first character of the trace code identifies the silicon revision
c8051f91x-c8051f90x 38 rev. 1.3 figure 3.5. qfn-24 package drawing table 3.2. qfn-24 package dimensions dimension min typ max dimension min typ max a 0.70 0.75 0.80 l 0.30 0.40 0.50 a1 0.00 0.02 0.05 l1 0.00 ? 0.15 b 0.18 0.25 0.30 aaa ? ? 0.15 d 4.00 bsc bbb ? ? 0.10 d2 2.55 2.70 2.80 ddd ? ? 0.05 e 0.50 bsc eee ? ? 0.08 e 4.00 bsc z ? 0.24 ? e2 2.55 2.70 2.80 y ? 0.18 ? notes: 1. al l dimensions shown are in millimeters (mm) unless otherwise noted. 2. d imensioning and tolerancing per ansi y14.5m-1994. 3. t his drawing conforms to the jedec solid state outline mo-220, variation wggd except for custom features d2, e2, z, y, and l which are toleranced per supplier designation. 4. r ecommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
c8051f91x-c8051f90x rev. 1.3 39 figure 3.6. typical qfn-24 landing diagram table 3.3. pcb land pattern dimension min max dimension min max c1 3.90 4.00 x1 0.20 0.30 c2 3.90 4.00 x2 2.70 2.80 e 0.50 bsc y1 0.65 0.75 y2 2.70 2.80 notes: general 1. al l dimensions shown are in millim eters (mm) unless otherwise noted. 2. t his land pattern design is based on the ipc-7351 guidelines. solder mask design 1. al l metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a st ainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. t he ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. a 2 x 2 array of 1.0 x 1.0 mm square openings on 1.30 mm pitch should be used for the ce nter ground pad. card assembly 1. a no-cl ean, type-3 solder paste is recommended. 2. t he recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
c8051f91x-c8051f90x 40 rev. 1.3 figure 3.7. qsop-24 package diagram table 3.4. qsop-24 package dimensions dimension min nom max dimension min nom max a ? ? 1.75 e 0.635 bsc a1 0.10 ? 0.25 l 0.40 ? 1.27 b 0.20 ? 0.30 0 ? 8 c 0.10 ? 0.25 aaa 0.20 d 8.65 bsc bbb 0.18 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.10 notes: 1. al l dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensi oning and tolerancing per ansi y14.5m-1994. 3. thi s drawing conforms to jedec outline mo-137, variation ae. 4. recommend ed card reflow profile is per the jede c/ipc j-std-020 specification for small body components.
c8051f91x-c8051f90x rev. 1.3 41 figure 3.8. qsop-24 landing diagram table 3.5. pcb land pattern dimension min max c 5.20 5.30 e 0.635 bsc x 0.30 0.40 y 1.50 1.60 notes: general 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. t his land pattern is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-solder mask defined (nmsd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a st ainless steel, laser-cut and electro-polished stenc il with trapezoidal walls should be used to assure good solder paste release. 2. t he stencil thickne ss should be 0.125 mm (5 mils). 3. t he ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. card assembly 1. a no-cl ean, type 3 solder paste is recommended. 2. t he recommended card reflow profile is per the je dec/ipc j-std-020 specification for small body components.
c8051f91x-c8051f90x 42 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 42 4. electrical characteristics throughout the electrical characteristics chapter , ?vdd? refers to the vdd/dc+ supply voltage. blue ind icates a feature only available on ?f912 and ?f902 devices. 4.1. absolute maximum specifications table 4.1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any port i/o pin or rst with respect to gnd vdd > 2.2 v vdd < 2.2 v ?0.3 ?0.3 ? ? 5.8 vdd + 3.6 v voltage on vbat with respect to gnd one-cell mode (f912/02 one-cell mode (f911/01) two-cell mode ?0.3 ?0.3 ?0.3 ? ? ? 4.0 2.0 4.0 v voltage on vdd/dc+ with respect to gnd ?0.3 ? 4.0 v maximum total current through vbat, dcen, vdd/dc+ or gnd ?? 500ma maximum current through rst or any port pin ?? 100ma maximum total current through all port pins ?? 200ma dc-dc converter output power ? ? 110 mw note: stresses above those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functi onal operation of the devices at those or any other condit ions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
c8051f91x-c8051f90x 43 rev. 1.3 4.2. electrical characteristics table 4.2. global electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise specified. see "a n358: optimizing low po wer operatio n of the ?f9xx" for details on how to achieve the supply current specifications listed in this table. parameter conditions min typ max units battery supply voltage (vbat) one-cell mode (f912/02) one-cell mode (f911/01) two-cell mode 0.9 0.9 1.8 1.2 1.2 2.4 3.6 1.8 3.6 v supply voltage (vdd/dc+) one-cell mode two-cell mode 1.8 1.8 1.9 2.4 3.6 3.6 v minimum ram data retention voltage 1 vdd (not in sleep mode) vbat (in sleep mode) ? ? 1.4 0.3 ? 0.5 v sysclk (system clock) 2 0?25mhz t sysh (sysclk high time) 18 ? ? ns t sysl (sysclk low time) 18 ? ? ns specified operating temperature range ?40 ? +85 c notes: 1. based on device characterization data; not production tested. 2. sysclk m ust be at least 32 khz to enable debugging. 3. dig ital supply current depends upon the particular code being executed. the values in this table are obtained with the cpu executing an ?sjmp $? lo op, which is the compiled form of a while(1) loop in c. one iteration requires 3 cpu clock cycles, and the flas h memory is read on each cycle. t he supply current will vary slightly based on the physical location of the sjmp instruction and the number of flash addr ess lines that toggle as a result. in the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte flash address boundary (e.g., 0x007f to 0x0080). real-world code wi th larger loops and longer linear sequences will have few transitions across the 64-byte address boundaries. 4. includ es oscillator and regulator supply current. 5. idd ca n be estimated for frequencies < 14 mhz by simply multiplying the frequency of interest by the fre quency sensitivity number for that range, then adding an offset of 90 a. when using these numbers to estimate i dd for >14 mhz, the estimate shou ld be the current at 25 mhz minus the difference in current ind icated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 20 mhz, i dd = 4 ma ? (25 mhz ? 20 mhz) x 0.102 ma/mhz = 3.5 ma assuming the same oscil lator setting. 6. th e supply current specifications in table 4.2 are fo r two cell mode. the vbat current in one-cell mode can be estimated using the following equation: the vbat voltage is the voltage at the vbat pin, typically 0.9 to 1.8 v. the supply current (two-cell mode) is the da t a sheet specification for supply current. the supply voltage is the voltage at the vdd/dc+ p in, typically 1.8 to 3.3 v (default = 1.9 v). the dc-dc converter efficiency can be estimated using figure 4.3 ? figure 4.5 . 7. idle idd can be estimated by t aking the current at 25 mhz minus the difference in current indicated by the fre quency sensitivity number. for example: v dd = 3.0 v; f = 5 mhz, idle i dd = 2.1 ma ? (25 mhz ? 5 mhz) x 0.079 ma/mhz = 0.52 ma. 8. inte rnal lfo only available on ?f912 and ?f902 devices. 9. abil ity to disable vbat supply monitor only available on ?f912 and ?f902 devices. vbat current (one-cell mode) supply voltage supply current (two-cell mode) dc-dc converter efficiency vbat voltage ---------------------------------------------------------------------------------------------------------------------------------- - =
c8051f91x-c8051f90x rev. 1.3 44 digital supply current?cpu active (normal mode, fetching instructions from flash) i dd 3, 4, 5, 6 v dd = 1.8?3.6 v, f = 24.5 mhz (includes precision oscillator current) ?4.05.0 ma v dd = 1.8?3.6 v, f = 20 mhz (includes low power oscillator current) ?3.4? ma v dd = 1.8 v, f = 1 mhz v dd = 3.6 v, f = 1 mhz (includes external oscillator/gpio current) ? ? 265 305 ? ? a a v dd = 1.8?3.6 v, f = 32.768 khz (includes smartclock oscillator current) ?84? a i dd frequency sensitivity 3, 5, 6 v dd = 1.8?3.6 v, t = 25 c, f < 14 mhz (flash oneshot active, see section 13.6) ?191?a/mhz v dd = 1.8?3.6 v, t = 25 c, f > 14 mhz (flash oneshot bypassed, see section 13.6) ?102?a/mhz table 4.2. global electrical characteristics (continued) ?40 to +85 c, 25 mhz system clock un less otherwise specified. see "an358: op timizing low power operation of the ?f9xx" for details on how to achieve the supply current specifications listed in this table. parameter conditions min typ max units notes: 1. based on device characterization data; not production tested. 2. sysclk must be at least 32 khz to enable debugging. 3. digital supply current depends upon the particular code being executed. the values in this table are obtained with the cpu executing an ?sjmp $? lo op, which is the compiled form of a while(1) loop in c. one iteration requires 3 cpu clock cycles, and the flas h memory is read on each cycle. t he supply current will vary slightly based on the physical location of the sjmp instruction and the number of flash addr ess lines that toggle as a result. in the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte flash address boundary (e.g., 0x007f to 0x0080). real-world code wi th larger loops and longer linear sequences will have few transitions across the 64-byte address boundaries. 4. includes oscillator and regulator supply current. 5. idd can be estimated for frequencies < 14 mhz by simply multiplying the frequency of interest by the frequency sensitivity number for that range, then adding an offset of 90 a. when using these numbers to estimate i dd for >14 mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 20 mhz, i dd = 4 ma ? (25 mhz ? 20 mhz) x 0.102 ma/mhz = 3.5 ma assuming the same oscillator setting. 6. the supply current specifications in table 4.2 are fo r two cell mode. the vbat current in one-cell mode can be estimated using the following equation: the vbat voltage is the voltage at the vbat pin, typically 0.9 to 1.8 v. the supply current (two-cell mode) is the da ta sheet specification for supply current. the supply voltage is the voltage at the vdd/dc+ pin, typically 1.8 to 3.3 v (default = 1.9 v). the dc-dc converter efficiency can be estimated using figure 4.3?figure 4.5. 7. idle idd can be estimated by taking t he current at 25 mhz minus the differ ence in current indicated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 5 mhz, idle i dd = 2.1 ma ? (25 mhz ? 5 mhz) x 0.079 ma/mhz = 0.52 ma. 8. internal lfo only available on ?f912 and ?f902 devices. 9. ability to disable vbat supply monitor only available on ?f912 and ?f902 devices. vbat current (one-cell mode) supply voltage supply current (two-cell mode) dc-dc converter efficiency vbat voltage ---------------------------------------------------------------------------------------------------------------------------------- - =
c8051f91x-c8051f90x 45 rev. 1.3 digital supply current?cpu inactive (idle mo de, not fetching instructions from flash) i dd 4, 6, 7 v dd = 1.8?3.6 v, f = 24.5 mhz (includes precision oscillator current) ?2.13.0 ma v dd = 1.8?3.6 v, f = 20 mhz (includes low power oscillator current) ?1.6? ma v dd = 1.8 v, f = 1 mhz v dd = 3.6 v, f = 1 mhz (includes external oscillator/gpio current) ? ? 160 185 ? ? a a v dd = 1.8?3.6 v, f = 32.768 khz (includes smartclock oscillator current) ?82? a i dd frequency sensitivity 1,6, 7 v dd = 1.8?3.6 v, t = 25 c ? 79 ? a/mhz table 4.2. global electrical characteristics (continued) ?40 to +85 c, 25 mhz system clock un less otherwise specified. see "an358: op timizing low power operation of the ?f9xx" for details on how to achieve the supply current specifications listed in this table. parameter conditions min typ max units notes: 1. based on device characterization data; not production tested. 2. sysclk must be at least 32 khz to enable debugging. 3. digital supply current depends upon the particular code being executed. the values in this table are obtained with the cpu executing an ?sjmp $? lo op, which is the compiled form of a while(1) loop in c. one iteration requires 3 cpu clock cycles, and the flas h memory is read on each cycle. t he supply current will vary slightly based on the physical location of the sjmp instruction and the number of flash addr ess lines that toggle as a result. in the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte flash address boundary (e.g., 0x007f to 0x0080). real-world code wi th larger loops and longer linear sequences will have few transitions across the 64-byte address boundaries. 4. includes oscillator and regulator supply current. 5. idd can be estimated for frequencies < 14 mhz by simply multiplying the frequency of interest by the frequency sensitivity number for that range, then adding an offset of 90 a. when using these numbers to estimate i dd for >14 mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 20 mhz, i dd = 4 ma ? (25 mhz ? 20 mhz) x 0.102 ma/mhz = 3.5 ma assuming the same oscillator setting. 6. the supply current specifications in table 4.2 are fo r two cell mode. the vbat current in one-cell mode can be estimated using the following equation: the vbat voltage is the voltage at the vbat pin, typically 0.9 to 1.8 v. the supply current (two-cell mode) is the da ta sheet specification for supply current. the supply voltage is the voltage at the vdd/dc+ pin, typically 1.8 to 3.3 v (default = 1.9 v). the dc-dc converter efficiency can be estimated using figure 4.3?figure 4.5. 7. idle idd can be estimated by taking t he current at 25 mhz minus the differ ence in current indicated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 5 mhz, idle i dd = 2.1 ma ? (25 mhz ? 5 mhz) x 0.079 ma/mhz = 0.52 ma. 8. internal lfo only available on ?f912 and ?f902 devices. 9. ability to disable vbat supply monitor only available on ?f912 and ?f902 devices. vbat current (one-cell mode) supply voltage supply current (two-cell mode) dc-dc converter efficiency vbat voltage ---------------------------------------------------------------------------------------------------------------------------------- - =
c8051f91x-c8051f90x rev. 1.3 46 digital supply current?suspend and sleep mode digital supply current 6 (suspend mode) v dd = 1.8?3.6 v, two-cell mode ? 77 ? a digital supply current (sleep mode, smartclock run- ning, 32.768 khz crystal) 1.8 v, t = 25 c 3.0 v, t = 25 c 3.6 v, t = 25 c 1.8 v, t = 85 c 3.0 v, t = 85 c 3.6 v, t = 85 c (includes smartclock oscillator and vbat supply monitor) ? ? ? ? ? ? 0.60 0.75 0.85 1.30 1.60 1.90 ? ? ? ? ? ? a digital supply current 8 (sleep mode, smartclock run- ning, internal lfo ) 1.8 v, t = 25 c (includes smartclock oscillator and vbat supply monitor) ?0.3? a table 4.2. global electrical characteristics (continued) ?40 to +85 c, 25 mhz system clock un less otherwise specified. see "an358: op timizing low power operation of the ?f9xx" for details on how to achieve the supply current specifications listed in this table. parameter conditions min typ max units notes: 1. based on device characterization data; not production tested. 2. sysclk must be at least 32 khz to enable debugging. 3. digital supply current depends upon the particular code being executed. the values in this table are obtained with the cpu executing an ?sjmp $? lo op, which is the compiled form of a while(1) loop in c. one iteration requires 3 cpu clock cycles, and the flas h memory is read on each cycle. t he supply current will vary slightly based on the physical location of the sjmp instruction and the number of flash addr ess lines that toggle as a result. in the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte flash address boundary (e.g., 0x007f to 0x0080). real-world code wi th larger loops and longer linear sequences will have few transitions across the 64-byte address boundaries. 4. includes oscillator and regulator supply current. 5. idd can be estimated for frequencies < 14 mhz by simply multiplying the frequency of interest by the frequency sensitivity number for that range, then adding an offset of 90 a. when using these numbers to estimate i dd for >14 mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 20 mhz, i dd = 4 ma ? (25 mhz ? 20 mhz) x 0.102 ma/mhz = 3.5 ma assuming the same oscillator setting. 6. the supply current specifications in table 4.2 are fo r two cell mode. the vbat current in one-cell mode can be estimated using the following equation: the vbat voltage is the voltage at the vbat pin, typically 0.9 to 1.8 v. the supply current (two-cell mode) is the da ta sheet specification for supply current. the supply voltage is the voltage at the vdd/dc+ pin, typically 1.8 to 3.3 v (default = 1.9 v). the dc-dc converter efficiency can be estimated using figure 4.3?figure 4.5. 7. idle idd can be estimated by taking t he current at 25 mhz minus the differ ence in current indicated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 5 mhz, idle i dd = 2.1 ma ? (25 mhz ? 5 mhz) x 0.079 ma/mhz = 0.52 ma. 8. internal lfo only available on ?f912 and ?f902 devices. 9. ability to disable vbat supply monitor only available on ?f912 and ?f902 devices. vbat current (one-cell mode) supply voltage supply current (two-cell mode) dc-dc converter efficiency vbat voltage ---------------------------------------------------------------------------------------------------------------------------------- - =
c8051f91x-c8051f90x 47 rev. 1.3 digital supply current (sleep mode) 1.8 v, t = 25 c 3.0 v, t = 25 c 3.6 v, t = 25 c 1.8 v, t = 85 c 3.0 v, t = 85 c 3.6 v, t = 85 c (includes vbat supply monitor) ? ? ? ? ? ? 0.05 0.08 0.12 0.75 0.90 1.20 ? ? ? ? ? ? a digital supply current (sleep mode, vbat supply monitor disabled ) 9 1.8 v, t = 25 c ? 0.01 ? a table 4.2. global electrical characteristics (continued) ?40 to +85 c, 25 mhz system clock un less otherwise specified. see "an358: op timizing low power operation of the ?f9xx" for details on how to achieve the supply current specifications listed in this table. parameter conditions min typ max units notes: 1. based on device characterization data; not production tested. 2. sysclk must be at least 32 khz to enable debugging. 3. digital supply current depends upon the particular code being executed. the values in this table are obtained with the cpu executing an ?sjmp $? lo op, which is the compiled form of a while(1) loop in c. one iteration requires 3 cpu clock cycles, and the flas h memory is read on each cycle. t he supply current will vary slightly based on the physical location of the sjmp instruction and the number of flash addr ess lines that toggle as a result. in the worst case, current can increase by up to 30% if the sjmp loop straddles a 64-byte flash address boundary (e.g., 0x007f to 0x0080). real-world code wi th larger loops and longer linear sequences will have few transitions across the 64-byte address boundaries. 4. includes oscillator and regulator supply current. 5. idd can be estimated for frequencies < 14 mhz by simply multiplying the frequency of interest by the frequency sensitivity number for that range, then adding an offset of 90 a. when using these numbers to estimate i dd for >14 mhz, the estimate should be the current at 25 mhz minus the difference in current indicated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 20 mhz, i dd = 4 ma ? (25 mhz ? 20 mhz) x 0.102 ma/mhz = 3.5 ma assuming the same oscillator setting. 6. the supply current specifications in table 4.2 are fo r two cell mode. the vbat current in one-cell mode can be estimated using the following equation: the vbat voltage is the voltage at the vbat pin, typically 0.9 to 1.8 v. the supply current (two-cell mode) is the da ta sheet specification for supply current. the supply voltage is the voltage at the vdd/dc+ pin, typically 1.8 to 3.3 v (default = 1.9 v). the dc-dc converter efficiency can be estimated using figure 4.3?figure 4.5. 7. idle idd can be estimated by taking t he current at 25 mhz minus the differ ence in current indicated by the frequency sensitivity number. for example: v dd = 3.0 v; f = 5 mhz, idle i dd = 2.1 ma ? (25 mhz ? 5 mhz) x 0.079 ma/mhz = 0.52 ma. 8. internal lfo only available on ?f912 and ?f902 devices. 9. ability to disable vbat supply monitor only available on ?f912 and ?f902 devices. vbat current (one-cell mode) supply voltage supply current (two-cell mode) dc-dc converter efficiency vbat voltage ---------------------------------------------------------------------------------------------------------------------------------- - =
c8051f91x-c8051f90x rev. 1.3 48 figure 4.1. active mode current (external cmos clock) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 4100 4200 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 frequency (mhz) supply current (ua) f < 14 mhz oneshot enabled f > 14 mhz oneshot bypassed < 160 ua/mhz 185 ua/mhz 215 ua/mhz 300 ua/mhz 200 ua/mhz
c8051f91x-c8051f90x 49 rev. 1.3 figure 4.2. idle mode current (external cmos clock) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 4100 4200 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 frequency (mhz) supply current (ua)
c8051f91x-c8051f90x rev. 1.3 50 figure 4.3. typical dc-dc converter efficiency (high current, vdd/dc+ = 2 v) load current (ma) efficiency (%) 9%$7 9 9%$7 9 9%$7 9 9%$7 9 9%$7 9 9%$7 9 9%$7 9 6:6(/ 6:6(/ x+,qgxfwrusdfndjh(65 2kpv 9'''& 90lqlpxp3xovh:lgwk qv3xovh6nlsslqj'lvdeohg 1rwh(iilflhqf\dwkljkfxuuhqwvpd\ehlpsuryhge\fkrrvlqjdq lqgxfwruzlwkdorzhu(65
c8051f91x-c8051f90x 51 rev. 1.3 figure 4.4. typical dc-dc converter efficiency (high current, vdd/dc+ = 3 v) load current (ma) efficiency (%) 9%$7 9 9%$7 9 9%$7 9 9%$7 9 9%$7 9 9%$7 9 9%$7 9 6:6(/ 6:6(/ x+,qgxfwrusdfndjh(65 2kpv 9'''& 90lqlpxp3xovh:lgwk qv 3xovh6nlsslqj'lvdeohg 1rwh(iilflhqf\dwkljkfxuuhqwvpd\ehlpsuryhge\ fkrrvlqjdqlqgxfwruzlwkdorzhu(65
c8051f91x-c8051f90x rev. 1.3 52 figure 4.5. typical dc-dc converter efficiency (low current, vdd/dc+ = 2 v) load current (ma) efficiency (%) 9%$7 9 9%$7 9 9%$7 9 9%$7 9 9%$7 9 9%$7 9 9%$7 9 x+,qgxfwrusdfndjh(65 2kpv 6:6(/ 9'''& 90lqlpxp3xovh:lgwk qv
c8051f91x-c8051f90x 53 rev. 1.3 figure 4.6. typical one-cell suspend mode current 9%$79 9%$7&xuuhqwx$ 0lq3xovh:lgwkqv 0lq3xovh:lgwkqv 0lq3xovh:lgwkqv 0lq3xovh:lgwkqv x+,qgxfwrusdfndjh(65 2kpv 6:6(/ 9'''& 9/rdg&xuuhqw x$
c8051f91x-c8051f90x rev. 1.3 54 table 4.3. port i/o dc electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage high drive strength, pndrv.n = 1 io h = ?3 ma, port i/o push-pull ioh = ?10 a, port i/o push-pull ioh = ?10 ma, port i/o push-pull low drive strength, pndrv.n = 0 ioh = ?1 ma, port i/o push-pull ioh = ?10 a, port i/o push-pull ioh = ?3 ma, port i/o push-pull v dd ? 0.7 v dd ? 0.1 v dd ? 0.7 v dd ? 0.1 ? ? ? see chart ? ? see chart ? ? ? ? ? v output low voltage high drive strength, pndrv.n = 1 i ol = 8.5 ma i ol = 10 a i ol = 25 ma low drive strength, pndrv.n = 0 i ol = 1.4 ma i ol = 10 a i ol = 4 ma ? ? ? ? ? ? ? ? see chart ? ? see chart 0.6 0.1 ? 0.6 0.1 ? v input high voltage v dd = 2.0 to 3.6 v v dd ? 0.6 ??v v dd = 0.9 to 2.0 v 0.7 x vdd ? ? v input low voltage v dd = 2.0 to 3.6 v ? ? 0.6 v v dd = 0.9 to 2.0 v ? ? 0.3 x vdd v input leakage current weak pullup off weak pullup on, v in = 0 v, v dd = 1.8 v weak pullup on, vin = 0 v, v dd = 3.6 v ? ? ? ? 4 20 1 ? 35 a
c8051f91x-c8051f90x 55 rev. 1.3 figure 4.7. typical voh curves, 1.8?3.6 v typical voh (high drive mode) 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 0 5 10 15 20 25 30 35 40 45 50 load current (ma) voltage vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v typical voh (low drive mode) 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 3.6 0123456789101112131415 load current (ma) voltage vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v
c8051f91x-c8051f90x rev. 1.3 56 figure 4.8. typical voh curves, 0.9?1.8 v typical voh (high drive mode) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 0123456789101112 load current (ma) voltage vdd = 1.8v vdd = 1.5v vdd = 1.2v vdd = 0.9v typical voh (low drive mode) 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 0123 load current (ma) voltage vdd = 1.8v vdd = 1.5v vdd = 1.2v vdd = 0.9v
c8051f91x-c8051f90x 57 rev. 1.3 figure 4.9. typical vol curves, 1.8?3.6 v typical vol (high drive mode) 0 0.3 0.6 0.9 1.2 1.5 1.8 -80 -70 -60 -50 -40 -30 -20 -10 0 load current (ma) voltage vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v typical vol (low drive mode) 0 0.3 0.6 0.9 1.2 1.5 1.8 -10-9-8-7-6-5-4-3-2-1 0 load current (ma) voltage vdd = 3.6v vdd = 3.0v vdd = 2.4v vdd = 1.8v
c8051f91x-c8051f90x rev. 1.3 58 figure 4.10. typical vol curves, 0.9?1.8 v typical vol (high drive mode) 0 0.1 0.2 0.3 0.4 0.5 -5 -4 -3 -2 -1 0 load current (ma) voltage vdd = 1.8v vdd = 1.5v vdd = 1.2v vdd = 0.9v typical vol (low drive mode) 0 0.1 0.2 0.3 0.4 0.5 -3 -2 -1 0 load current (ma) voltage vdd = 1.8v vdd = 1.5v vdd = 1.2v vdd = 0.9v
c8051f91x-c8051f90x 59 rev. 1.3 table 4.4. reset electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units rst output low voltage i ol = 1.4 ma, ??0.6 v rst input high voltage v dd = 2.0 to 3.6 v v dd ? 0.6 ?? v v dd = 0.9 to 2.0 v 0.7 x v dd ?? v rst input low voltage v dd = 2.0 to 3.6 v ??0.6 v v dd = 0.9 to 2.0 v ?? 0.3 x v dd v rst input pullup current rst = 0.0 v, vdd = 1. 8 v rst = 0.0 v, vdd = 3. 6 v ? ? 4 20 ? 35 a vdd/dc+ monitor threshold (v rst ) early warning reset trigger ( all power modes except sleep) 1.8 1.7 1.85 1.75 1. 9 1.8 v vbat ramp time for power on one-cell mode: vbat ramp 0?0.9 v two-cell mode: vbat ramp 0?1.8 v ?? 3 ms vbat monitor threshold (v por ) initial power-on (vbat rising) early warning brownout condition (vbat falling) recovery from brownout (vbat rising) ? 0.9 0.7 ? 0.75 1.0 0.8 0.95 ? 1.1 0.9 ? v missing clock detector timeout time from last system clock rising edge to reset initiation 100 525 1000 s m inimum system clock w/ missing clock detector enabled system clock frequency which triggers a mis sing clock detector timeout ? 2 10 khz reset t ime delay delay between release of any reset sou rce and code execution at location 0x0000 ?10? s minimum rst low time to generate a system reset 15 ? ? s v dd monitor turn-on time ? 300 ? ns v dd monitor supply current ?10? a *note: blue indicates a feature only available on ?f912 and ?f902 devices.
c8051f91x-c8051f90x rev. 1.3 60 table 4.5. power management electrical specifications v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units idle mode wake-up time 2 ? 3 sysclks suspend mode wake-up time low power oscillator ? 400 ? ns precision oscillator ? 400 ? ns sleep mode wake-up time two-cell mode ? 2 ? s one-cell mode ? 10 ? s table 4.6. flash electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units flash size c8051f912/1 16384* ? ? bytes c8051f902/1 8192 ? ? bytes scr atchpad size 512 ? 512 bytes endurance 1 k 90 k ? er ase/write cycles erase cycle time 28 32 36 ms w rite cycle time 57 64 71 s *note: on 16 kb devices, 1024 bytes at addresses 0x3c00 to 0x3fff are reserved. table 4.7. internal precision oscillator electrical characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specified; us ing factory-calibrated settings. parameter conditions min typ max units oscillator frequency ?40 to +85 c, v dd = 1.8?3.6 v 24 24.5 25 mhz os cillator supply current (from v dd ) 25 c; includes bias current of 90 ?100 a ?300*? a *note: does not include clock divider or clock tree supply current. table 4.8. internal low-power oscillator electrical characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specified; us ing factory-calibrated settings. parameter conditions min typ max units oscillator frequency ?4 0 to +85 c, v dd = 1.8?3.6 v 18 20 22 mhz oscillator supply current (from v dd ) 25 c no separate bias current required. ?100*? a *note: does not include clock divider or clock tree supply current.
c8051f91x-c8051f90x 61 rev. 1.3 table 4.9. smartclock characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise specified; us ing factory-calibrated settings. parameter conditions min typ max units oscillator frequency (lfo) 13.1 16.4 19.7 khz note: blue indicates a feature only available on ?f912 and ?f902 devices. table 4.10. adc0 electrical characteristics v dd = 1.8 to 3.6v v, vref = 1.65 v (refsl[1:0] = 11), ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 12-bit mode 10-bit mode 12 10 bits integral nonlinearity 12-bit mode 2 10-bit mode ? ? 1 0.5 1.5 1 lsb differential nonlinearity (guaranteed monotonic) 12-bit mode 2 10-bit mode ? ? 0.8 0.5 1 1 lsb offset error 12-bit mode 10-bit mode ? ? <1 <1 2 2 lsb full scale error 12-bit mode 3 10-bit mode ? ? 1 1 4 2.5 lsb dynamic performance (10 khz sine-wave single-ended input, 1 db below full scale, maximum sampling rate) signal-to-noise plus distortion 4 12-bit mode 10-bit mode 62 54 65 58 ? ? db signal-to-distortion 4 12-bit mode 10-bit mode ? ? 76 73 ? ? db spurious-free dynamic range 4 12-bit mode 10-bit mode ? ? 82 75 ? ? db conversion rate sar conversion clock normal mode low power mode ? ? ? ? 8.33 4.4 mhz conversion time in sar clocks 10-bit mode 8-bit mode 13 11 ? ? ? ? clocks track/hold acquisition time initial acquisition subsequent acquisitions (dc in put, burst mode) 1.5 1.1 ? ? us throughput rate 12-bit mode 10-bit mode ? ? ? ? 75 300 ksps notes: 1. blue i ndicates a feature only available on ?f912 and ?f902 devices. 2. inl and dnl specifications for 12-bit mode do not include the first or last four adc codes. 3. t he maximum code in 12-bit mode is 0xfffc. the full scale error is referenced from the maximum code. 4. performance in 8-bit mode is similar to 10-bit mode.
c8051f91x-c8051f90x rev. 1.3 62 analog inputs adc input voltage range single ended (ain+ ? gnd) 0 ? vref v absolute pin voltage with res pect to gnd single ended 0 ? v dd v sampling capacitance (c8051f912/11/02/01) 1x gain 0.5x gain ? 28 26 ? pf input multiplexer impedance ? 5 ? k power specifications power supply current (v dd supplied to adc0) conversion mode (300 ksps) tracking mode (0 ksps) ? ? 720 680 ? ? a power supply rejection internal high speed vref external vref ? ? 67 74 ? ? db table 4.11. temperature sensor electrical characteristics v dd = 1.8 to 3.6v v, ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units linearity ? 1 ? c slope ? 3.40 ? mv/c slope error 1 ? 40 ? v/c offset temp = 25 c ? 1025 ? mv offset error 1 temp = 25 c ? 18 ? mv temperature sensor settling ti me 2 initial voltage=0 v initial voltage=3.6 v ? ? 3.0 6.5 s supply current ? 35 ? a notes: 1. re presents one standard deviation from the mean. 2. t he temperature sensor settling time, resulting from an adc mux change or enabling of the temperature sensor, varies with the voltage of the previously sample d channel and can be up to 6 s if the previously sampled channel voltage was greater than 3 v. to mini mize the temperature sensor settling time, the adc mux can be momentarily set to ground before being set to the temperature sensor output. this ensures that the temperature sensor output will settle in 3 s or less. table 4.10. adc0 electrical characteristics (continued) v dd = 1.8 to 3.6v v, vref = 1.65 v (refsl[1:0] = 11), ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units notes: 1. blue indicates a feature only available on ?f912 and ?f902 devices. 2. inl and dnl specifications for 12-bit mode do not include the first or last four adc codes. 3. the maximum code in 12-bit mode is 0xfffc. the full scale error is referenced from the maximum code. 4. performance in 8-bit mode is similar to 10-bit mode.
c8051f91x-c8051f90x 63 rev. 1.3 table 4.12. voltage reference electrical characteristics v dd = 1.8 to 3.6 v, ? 40 to +85 c unless otherwise specified. parameter conditions min typ max units internal high speed reference (refsl[1:0] = 11) output voltage ?40 to +85 c, v dd = 1.8?3.6 v 1.60 1.65 1.70 v vref turn-on time ? ? 1.5 s supply current normal power mode low power mode ? ? 260 140 ? ? a internal precision reference (refsl[1:0] = 00, refoe = 1) output voltage ?40 to +85 c, v dd = 1.8?3.6 v 1.645 1.680 1.715 v vref short-circuit current ? 10 ? ma load regulation load = 0 to 200 a to agnd ? 400 ? v/a vref turn-on time 1 4.7 f tantalum, 0.1 f ceramic byp ass, settling to 0.5 lsb ? 15 ? ms vref turn-on time 2 0.1 f ceramic bypass, settling to 0. 5 lsb ? 300 ? s vref turn-on time 3 no bypass cap, settling to 0.5 lsb ? 25 ? s supply current ? 15 ? a external reference (ref sl[1 :0] = 00, refoe = 0) input voltage range 0 ? v dd v input current sample rate = 300 ksps; vref = 3. 0 v ? 5.25 ? a note: blue indicates a feature only available on ?f912 and ?f902 devices.
c8051f91x-c8051f90x rev. 1.3 64 table 4.13. iref0 electrical characteristics v dd = 1.8 to 3.6 v, ? 40 to +85 c, unless otherwise specified. parameter conditions min typ max units static performance resolution 1 6 bits output compliance range low power mode, source high current mode, source low power mode, sink high current mode, sink 0 0 0.3 0.8 ? ? ? ? v dd ? 0.4 v dd ? 0.8 v dd v dd v integral nonlinearity ? <0.2 1.0 lsb differential nonlinearity ? <0.2 1.0 lsb offset error ? <0.1 0.5 lsb full scale error 2 low power mode, source ? ? 5 % high current mode, source ? ? 6 % low power mode, sink ? ? 8 % high current mode, sink ? ? 8 % absolute current error low power mode so urcing 20 a ? <1 3 % dynamic performance output settling time to 1/2 lsb ? 300 ? ns startup time ? 1 ? s power consumption net power supply current (v dd supplied to iref0 minus any output source current) low power mode, source iref0dat = 000001 ? 10 ? a iref0dat = 111111 ? 10 ? a high current mode, source iref0dat = 000001 ? 10 ? a iref0dat = 111111 ? 10 ? a low power mode, sink iref0dat = 000001 ? 1 ? a iref0dat = 111111 ? 11 ? a high current mode, sink iref0dat = 000001 ? 12 ? a iref0dat = 111111 ? 81 ? a notes: 1. re fer to ?pwm enhanced mode? on page 94 for information on how to improve iref0 resolution. 2. full scale is 63 a in low power mode and 504 a in high power mode.
c8051f91x-c8051f90x 65 rev. 1.3 table 4.14. comparator electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units response time: mode 0, v dd = 2.4 v, v cm * = 1.2 v cp0+ ? cp0? = 100 mv ? 130 ? ns cp0+ ? cp0? = ?100 mv ? 200 ? ns response time: mode 1, v dd = 2.4 v, v cm * = 1.2 v cp0+ ? cp0? = 100 mv ? 210 ? ns cp0+ ? cp0? = ?100 mv ? 410 ? ns response time: mode 2, v dd = 2.4 v, v cm * = 1.2 v cp0+ ? cp0? = 100 mv ? 420 ? ns cp0+ ? cp0? = ?100 mv ? 1200 ? ns response time: mode 3, v dd = 2.4 v, v cm * = 1.2 v cp0+ ? cp0? = 100 mv ? 1750 ? ns cp0+ ? cp0? = ?100 mv ? 6200 ? ns common-mode rejection ratio ? 1.5 4 mv/v inverting or non- inverting input v oltage range ?0.25 ? v dd + 0.25 v input capacitance ? 12 ? pf input bias current ? 1 ? na input offset voltage ?7 ? +7 mv power supply power supply rejection ? 0.1 ? mv/v power-up time vdd = 3.6 v ? 0.6 ? s vdd = 3.0 v ? 1.0 ? s vdd = 2.4 v ? 1.8 ? s vdd = 1.8 v ? 10 ? s supply current at dc mode 0 ? 23 ? a mode 1 ? 8.8 ? a mode 2 ? 2.6 ? a mode 3 ? 0.4 ? a *note: vcm is the common-mode voltage on cp0+ and cp0?.
c8051f91x-c8051f90x rev. 1.3 66 hysteresis mode 0 hysteresis 1 (cpnhyp/n1?0 = 00) ? 0 ? mv hysteresis 2 (cpnhyp/n1?0 = 01) ? 8.5 ? mv hysteresis 3 (cpnhyp/n1?0 = 10) ? 17 ? mv hysteresis 4 (cpnhyp/n1?0 = 11) ? 34 ? mv mode 1 hysteresis 1 (cpnhyp/n1?0 = 00) ? 0 ? mv hysteresis 2 (cpnhyp/n1?0 = 01) ? 6.5 ? mv hysteresis 3 (cpnhyp/n1?0 = 10) ? 13 ? mv hysteresis 4 (cpnhyp/n1?0 = 11) ? 26 ? mv mode 2 hysteresis 1 (cpnhyp/n1?0 = 00) ? 0 1 mv hysteresis 2 (cpnhyp/n1?0 = 01) 2 5 10 mv hysteresis 3 (cpnhyp/n1?0 = 10) 5 10 20 mv hysteresis 4 (cpnhyp/n1?0 = 11) 12 20 30 mv mode 3 hysteresis 1 (cpnhyp/n1?0 = 00) ? 0 ? mv hysteresis 2 (cpnhyp/n1?0 = 01) ? 4.5 ? mv hysteresis 3 (cpnhyp/n1?0 = 10) ? 9 ? mv hysteresis 4 (cpnhyp/n1?0 = 11) ? 17 ? mv table 4.15. vreg0 electrical characteristics v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units input voltage range 1.8 ? 3.6 v bias current normal, idle, suspend, or stop mode ? 20 ? a table 4.14. comparator electrical characteristics (continued) v dd = 1.8 to 3.6 v, ?40 to +85 c unless otherwise noted. parameter conditions min typ max units *note: vcm is the common-mode voltage on cp0+ and cp0?.
c8051f91x-c8051f90x 67 rev. 1.3 table 4.16. dc-dc converter (dc0) electrical characteristics vbat = 0.9 to 1.8 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units input voltage range c8051f912/02 c8051f911/01 0.9 0.9 ? ? 3.6 1.8 v input inductor value 500 680 900 nh input inductor current rat - ing 250 ? ? ma inductor dc resistance ? ? 0.5 input capacitor value source impedance < 2 ? ? 4.7 1.0 ? ? f output voltage range target output = 1.8 v target output = 1.9 v target output = 2.0 v target output = 2.1 v target output = 2.4 v target output = 2.7 v target output = 3.0 v target output = 3.3 v 1.73 1.83 1.93 2.03 2.30 2.60 2.90 3.18 1.80 1.90 2.00 2.10 2.40 2.70 3.00 3.30 1.87 1.97 2.07 2.17 2.50 2.80 3.10 3.42 v output load regulation target output = 2.0 v, 1 to 30 ma target output = 3.0 v, 1 to 20 ma ? ? 0.3 1 ? ? % output current (based on output power spec) target output = 1.8 v target output = 1.9 v target output = 2.0 v target output = 2.1 v target output = 2.4 v target output = 2.7 v target output = 3.0 v target output = 3.3 v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 36 34 32 30 27 24 21 19 ma output power ? ? 65 mw bias current (normal current mode) from vbat supply from vdd/dc+ supply ? ? 80 100 ? ? a bias current (low power mode) from vbat supply from vdd/dc+ supply ? ? 70 85 ? ? clocking frequency 1.6 2.4 3.2 mhz maximum dc load current dur ing startup ? ? 1 ma capacitance connected to ou tput 0.8 1.0 2.0 f
c8051f91x-c8051f90x rev. 1.3 68 5. sar adc with 16-bit auto -averaging accumulator and autonomous low power burst mode the adc0 on c8051f91x-c8051f90x devices is a 300 ksps, 10-bit or 75 ksps, 12-bit (?f912/02 only) successiv e-approximation-register (sar) adc with integrated track-and-hold and programmable window detector. adc0 also has an autonomous low powe r burst mode which can automatically enable adc0, capture and accumulate samples, then place adc0 in a low power shutdown mode without cpu intervention. it also has a 16-bit accumulator that can automatically oversample and average the adc results. see section 5.4 for more details on usi ng the adc in 12-bit mode. the adc is fully configurable under software control vi a special function registers. the adc0 operates in single-ended mode and may be configured to measure various different signals using the analog multiplexer described in section ?5.7. adc0 analog mult iplexer? on page 86 . the voltage reference for the adc is selected as described in section ?5.9. voltage and ground reference options? on page 91 . figure 5.1. adc0 functional block diagram adc0cf amp0gn ad0tm ad08be ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10/12-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int bursten ad0en timer 0 overflow timer 2 overflow timer 3 overflow start conversion 000 ad0busy (w) vdd adc0lth ad0wint 001 010 011 100 cnvstr input window compare logic adc0ltl adc0gth adc0gtl adc0l ain+ from amux0 burst mode logic adc0tk adc0pwr 16-bit accumulator
c8051f91x-c8051f90x 69 rev. 1.3 5.1. output code formatting the registers adc0h and adc0l contain the high and low bytes of the output conversion code from the adc at the completion of each conversion. data can be right-justified or left-justified, depending on the setting of the ad0sjst[2:0]. when the repeat count is set to 1, conversion codes are represented as 10- bit unsigned integers. inputs are measured from 0 to vref x 1023/1024. example c ode s are shown below for both right-justified and left-justified data. unused bits in the adc0h and adc0l registers are set to 0. when the repeat count is greater than 1, the output conversion code represents the accumulated result of the conversions performed and is updated after the last co nversion in the series is finished. sets of 4, 8, 16, 32, or 64 consecutive samples can be accumulated and represented in unsigned integer format. the repeat count can be selected using the ad0rpt bits in the adc0ac register. when a repeat count higher than 1, the adc output must be right-justified (ad0sjst = 0xx); unused bits in the adc0h and adc0l re gisters are set to 0. the example below shows the ri ght-justified result for various input voltages and repeat counts. notice that accumulating 2 n samples is equivalent to left-shifting by n bit positions when all samples returned from the adc have the same value. the ad0sjst bits can be used to format the contents of the 16-bit accumulator. the accumulated result can be shifted right by 1, 2, or 3 bit positions. base d on the principles of oversampling and averaging, the effective adc resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4. the example below shows how to increase the effective adc resolution by 1, 2, and 3 bits to obtain an effective adc resolution of 11-bit, 12-bit, or 13-bit respectively wi thout cpu intervention. input voltage right-justified adc0h:adc0l (ad0sjst = 000) lef t-justified adc0h:adc0l (ad0sjst = 100) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 input voltage repeat count = 4 repeat count = 16 repeat count = 64 v ref x 1023/1024 0x0ffc 0x3ff0 0xffc0 v ref x 512/1024 0x0800 0x2000 0x8000 v ref x 511/1024 0x07fc 0x1ff0 0x7fc0 0 0x0000 0x0000 0x0000 input voltage repeat count = 4 shift right = 1 11-bit result repeat count = 16 shift right = 2 12-bit result repeat count = 64 shift right = 3 13-bit result v ref x 1023/1024 0x07f7 0x0ffc 0x1ff8 v ref x 512/1024 0x0400 0x0800 0x1000 v ref x 511/1024 0x03fe 0x04fc 0x0ff8 0 0x0000 0x0000 0x0000
c8051f91x-c8051f90x rev. 1.3 70 5.2. modes of operation adc0 has a maximum conversion speed of 300 ksps in 10-bit mode. the adc0 conversion clock (sar clk) is a divided version of the system clock when burst mode is disa bled (bursten = 0), or a divided version of the low power o scillator when burst mode is enabl ed (bursen = 1). the clock divide value is determined by the ad0s c bits in the adc0cf register. 5.2.1. starting a conversion a conversion can be initiated in one of five ways, dep ending on the programmed states of the adc0 start of conversion mode bits (ad0cm2 ? 0) in register adc0cn. conversions may be initiated by one of the following: 1. writing a 1 to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e., timed co ntinuous conversions) 3. a timer 2 overflow 4. a timer 3 overflow 5. a rising edge on the cnvstr input signal (pin p0.6) writing a 1 to ad0busy provides software contro l of adc0 whereby conversions are performed "on- demand". during conversion, the ad0busy bit is set to logic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0bu sy triggers an interrupt (when enabl ed) and sets the adc0 interrupt flag (ad0int). when polling for adc conversion comple tions, the adc0 interrupt flag (ad0int) should be used. converted data is available in the adc0 data registers, adc0h:adc0l, wh en bit ad0int is logic 1. when t imer 2 or timer 3 overflows are used as the conversion so urce, low byte overflows are used if timer 2/3 is in 8-bit mode; high byte overflows are used if timer 2/3 is in 16-bit mode. see ?25. timers? on page 274 for timer configuration. important note about using cnvstr: th e cnvstr input pin also functions as port pin p0.6. when the cnvstr input is used as the adc0 conversion source, port pin p0.6 should be skipped by the digital crossbar. to configure the crossbar to skip p0.6, set to 1 bit 6 in register p0skip. see ?21. port input/output? on page 210 for details on port i/o configuration. important note: when operating the device in one-cell mode, there is an option available to automatically synchronize the start of conversion with the quietest portion of the dc-dc converter switching cycle. activating this option may help to reduce interference from internal or external power supply noise generated by the dc-dc converter. a sserting this bit will hold off the star t of an adc conversion initiated by any of the methods described above until the adc re ceives a synchronizing signal from the dc-dc converter. the delay in initiation of the conversion can be as much as one cycle of the dc-dc converter clock, which is 625 ns at the minimum dc-dc clock frequency of 1.6 mhz. t he synchronization feature also causes the dc-dc converter clock to be used as the adc0 conversion clock. the maximum conversion rate will be limited to approximately 170 ksps at the maximum dc-dc converter clock rate of 3.2 mhz. in this mo de, the adc0 sar conversion clock divider must be set to 1 by setting ad0sc[4:0] = 00000b in sfr register adc0cf. to provide additional flexibility in minimizing noise, th e adc0 conversion clock provided by the dc-dc converter can be inverted by setting th e ad0ckinv bit in the dc0cf register. for additional information on the synchronization feature, see the description of the sync bit in ?sfr definition 16.1. dc0cn: dc-dc converter co ntrol? on page 173 and the description of the ad0ckinv bit in ?sfr definition 16.2. dc0cf: dc-dc converter conf igu ration? on page 174 . this bit must be set to 0 in two-cell mode for the adc to operate.
c8051f91x-c8051f90x 71 rev. 1.3 5.2.2. tracking modes each adc0 conversion must be preceded by a minimum tracking time in order for the converted result to be accurate. the minimum tracking time is given in table 4.10 . the ad0tm bit in register adc0cn controls the adc0 track-and-hold mode. in its defaul t state when burst mode is disabled, the adc0 input is continuously tracked, except when a conversion is in progress. when the ad0tm bit is logic 1, adc0 op erates in low-power track-and-hold mode. in this mode, each conversion is preceded by a tracking period of 3 sar clocks (after the start-of-conversion signa l). when the cnvstr signal is used to initiate conversions in low-power tracking mode, adc0 tra cks only when cnvstr is low; conversion begins on the rising edge of cnvstr (see figure 5.2 ). tracking can also be disabled (shutdown) when the device is in low power standby or sleep modes. low-power track- an d-hold mode is also useful when amux settings are frequently changed, due to the settli ng time requirements described in section ?5.2.4. settling time requirements? on page 74 . figure 5.2. 10-bit adc track and conversion example timing (bursten = 0) write '1' to ad0busy, timer 0, timer 2, timer 1, timer 3 overflow (ad0cm[2:0]=000, 001,010 011, 101) ad0tm=1 track convert low power mode ad0tm=0 track or convert convert track low power or convert sar clocks sar clocks b. adc0 timing for internal trigger source 123456789 cnvstr (ad0cm[2:0]=100) ad0tm=1 a. adc0 timing for external trigger source sar clocks track or convert convert track ad0tm=0 track convert low power mode low power or convert 10 11 12 13 14 123456789 10 11 12 13 14 123456789 10 11 12 13 14 15 16 17
c8051f91x-c8051f90x rev. 1.3 72 5.2.3. burst mode burst mode is a power saving feature that allows adc0 to remain in a low power state between conversions. when burst mode is enabled, adc0 wakes from a low power state, accumulates 1, 4, 8, 16, 32, or 64 using an internal burst mode clock (approximately 20 mhz), then re-enters a low power state. since the burst mode clock is independent of the sys tem clock, adc0 can perfo rm multiple conversions then enter a low power state within a single system cl ock cycle, even if the system clock is slow (e.g. 32.768 khz), or suspended. burst mode is enabled by setting bursten to logic 1. when in burst mode, ad0en controls the adc0 id le power state (i.e. the state adc0 enters when not tracking or performing conversions). if ad0en is set to logic 0, adc0 is powered down after each burst. if ad0en is set to logic 1, adc0 remain s e nabled after each burst. on each convert start signal, adc0 is awak ened from its idle power state. if adc0 is powered down, it will automatically power up and wait th e programmable po wer-up time controlled by the ad0pwr bits. otherwise, adc0 will start tracking and converting immediately. figure 5.3 shows an example of burst mode operation with a slow system clock and a repeat count of 4. when burst mode is enabled, a single conv ert start will initiate a numb er of conversions e qual to th e repeat count. when burst mode is disabled, a convert start is required to initiate each conversion. in both modes, the adc0 end of conversion interrupt flag (ad0int) will be set after ?repea t count? conversions have been accumulated. similarl y, the window comparator will not compare the result to the greater-than and less-than registers until ?repeat count? conversions have been accumulated. in burst mode, tracking is determ ine d by the settings in ad0pwr and ad0tk. the default settings for these registers will work in most applications without modification; howeve r, settling time requirements may need adjustment in some applications. refer to section ?5.2.4. settling time requirements? on page 74 for more details. notes: ? setting ad0tm to 1 will insert an additional 3 sar clocks of tracking before each co nversion, regard - less of the settings of ad0pwr and ad0tk. ? when using burst mode, care must be taken to issue a con vert start signal no faster than once every four sysclk periods. this includes external convert start signals. ? a rising edge of external start-of-conversion (c n vstr) will cause only one adc conversion in burst mode, regardless of the value of the repeat count field. the end-of-conversio n interrupt will occur after the number of conversions spec ified in repeat count have comple ted. in other words, if repeat count is set to 4, four pulses on cnvstr will cause an adc end-of-conversion interrupt. re fer to the bottom portion of figure 5.3, ?burst mode tracking example wi th rep eat count set to 4,? on page 73 for an example. ? to start multiple conversions in burst mode with one external start-of-conversion signal, the external int errupts (/int0 or /int1) or port match can be used to trigger an is r that writes to ad0busy. exter - nal interrupts are configurable to be active low or ac tive high, edge or level sensitive, but is only avail - able on a limited number of pins. port match is only le vel sensitive, but is available on more port pins than the external interrupts. refer to section ?12.6. external interrupts int0 and int1? on page 137 for details on external interrupts and section ?21.4. port match? on page 220 for details on port match.
c8051f91x-c8051f90x 73 rev. 1.3 figure 5.3. burst mode tracking example with repeat count set to 4 track.. system clock convert start (ad0busy or timer overflow) post-tracking ad0tm = 01 ad0en = 0 powered down powered down t c power-up and idle t c t c t c power-up and idle t c.. dual-tracking ad0tm = 11 ad0en = 0 powered down powered down t c power-up and track t c t c t c power-up and track t c.. ad0pwr post-tracking ad0tm = 01 ad0en = 1 idle idle t c t c t c t c t c.. dual-tracking ad0tm = 11 ad0en = 1 track track t c t c t c t c t c.. t c t c t c t c t = tracking c = converting convert start (cnvstr) post-tracking ad0tm = 01 ad0en = 0 powered down powered down t c power-up and idle power-up and idle t c.. dual-tracking ad0tm = 11 ad0en = 0 powered down powered down t c power-up and track power-up and track t c.. ad0pwr post-tracking ad0tm = 01 ad0en = 1 idle idle t c dual-tracking ad0tm = 11 ad0en = 1 track track t c t c t c t = tracking c = converting idle..
c8051f91x-c8051f90x rev. 1.3 74 5.2.4. settling time requirements a minimum amount of tracking time is required before each conversion can be performed, to allow the sampling capacitor voltage to settle. this tracking time is determined by the amux0 resistance, the adc0 sampling capacitance, any external source resistance, and the accuracy required for the conversion. note that in low-power tracking mode, three sar clocks ar e used for tracking at the start of every conversion. for many applications, t hese three sar clocks will meet the minimum tracking time requirements, and higher values for the ex ternal source impedance will increase the required tracking time. figure 5.4 shows the equivalent adc0 input circuit. the re quired adc0 settling time for a given settling accuracy (sa) may be approximated by equation 5.1 . when measuring the temperature sensor output or v dd with respect to gnd, r total reduces to r mux . see ta b l e 4.10 for adc0 minimum settling time requirements as well as the mux impedance and sampling capacitor values. equation 5.1. adc0 settling time requirements where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the r equired settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the ad c resolution in bits (10). figure 5.4. adc0 equivalent input circuits t 2 n sa ------ - ?? ?? r total c sample r mux c sample rc input = r mux * c sample mux select p0.x note: the value of csample depends on the pga gain. see table 4.10 for details.
c8051f91x-c8051f90x 75 rev. 1.3 5.2.5. gain setting the adc has gain settings of 1x and 0.5x. in 1x mo de, the full scale reading of the adc is determined directly by v ref . in 0.5x mode, the full-scale reading of the adc occurs when the input voltage is v ref x 2. th e 0.5x gain setting can be useful to obtain a higher input voltage range when using a small v ref voltage, or to measure input voltages that are between v ref and v dd . gain settings for the adc are controlled by the amp0gn bit in register adc0cf. 5.3. 8-bit mode setting the adc08be bit in register adc0cf to 1 will put the adc in 8- bit mode. in 8-bit mode, only the 8 msbs of data are converted, allowing the conversi on to b e completed in two fewer sar clock cycles than a 10-bit conversion. this can result in an overall lower power consumption since the system can spend more time in a low power mode. the two lsbs of a conversion are always 00 in this mode, and the adc0l register will always read back 0x00. 5.4. 12-bit mode (c8051f912/02 only) c8051f912/02 devices have an enhanced sar converter that provides 12-bit re solution while retaining the 10- and 8-bit operating modes of the other de vices in the family. when configured for 12-bit conversions, the adc performs four 10-bit conversions using four different reference voltages and combines the results into a single 12-bit value. unlike simple averaging techniques, this method provides true 12-bit resolution of ac or dc input signals without depending on noise to provide dithering. the converter also employs a hardware dynamic element matching algorithm that reconfigures the largest elements of the internal dac for each of the four 10 -bit conversions to cancel the any matching errors, enabling the converter to achieve 12-bit linearity pe rformance to go along with its 12-bit resolution. for best performance, the low power os cillator should be selected as the system clock source while taking 12-bit adc measurements. the 12-bit mode is enabled by setting the ad012be bit ( adc0ac.7) to logic 1 and configuring burst mode for four conversions as described in section 5.2.3 . the conversion can be initiated using any of the methods described in section 5.2.1 , and the 12-bit result will appear in the adc0h and adc0l registers. since the 12-bit result is formed from a combination of four 10-bit results, the maximum output value is 4 x (1023) = 4092, rather than the max value of (2^12 ? 1) = 4 095 that is produced by a traditional 12-bit converter. to further increase resolution, the burst mode repeat value may be configured to any multiple of four conversions. for example, if a repeat value of 16 is selected, the adc0 output will be a 14-bit number (sum of four 12-bit numbers) with 13 effective bits of resolution. 5.5. low power mode (c8051f912/902 only) the c8051f912/02 sar converter provides a low power mode that allows a significant reduction in operating current when operating at low sar clock fre quencies. low power mode is enabled by setting the ad0lpm bit (adc0pwr.7) to 1. in general, low po wer mode is recommended when operating with sar conversion clock frequency at 4 mhz or less. see t he electrical characteristics chapter for details on power consumption and the maximum clock frequencies allowed in each mode. setting the low power mode bit reduces the bias currents in both the sar converter and in the high-speed voltage reference.
c8051f91x-c8051f90x rev. 1.3 76 table 5.1. representative conversion times and energy consumption for the sar adc with 1.65 v high-speed vref normal power mode low power mode 8 bit 10 bit 12 bit 8 bit 10 bit 12 bit highest nominal sar clock frequency 8.17 mhz (24.5 / 3) 8.17 mhz (24.5 / 3) 6.67 mhz (20.0 / 3) 4.08 mhz (24.5 / 6) 4.08 mhz (24.5 / 6) 4.00 mhz (20.0 / 5) total number of conversion clocks required 11 13 52 (13*4) 11 13 52 (13*4) total tracking time (min) 1.5 us 1.5 us 4.8 us (1.5+3*1.1) 1 .5 us 1.5 us 4.8 us (1.5+3*1.1) total time for one conversion 2.85 us 3.09 us 12.6 us 4.19 us 4.68 us 17.8 us adc throughput 351 ksps 323 ksps 79 ksps 238 ksps 214 ksps 56 ksps energy per conversion 8.2 nj 8.9 nj 36.5 nj 6.5 nj 7.3 nj 27.7 nj note: this table assumes that the 24.5 mhz precision oscilla tor is used for 8- and 10-bit modes, and the 20 mhz low power oscillator is used for 12-bit mode. the values in the table assume that the oscillators run at their nominal frequencies. the maximum sar clock values given in table 4.10 allow for maximum oscillation frequencies of 25.0 mhz and 22 mhz for the precision and low-power oscillators, respectively, when using the given sar clock divider values. energy calculations are for the adc subsystem only and do not include cpu current. modes in blue are only available on 'f912 and 'f902 devices.
c8051f91x-c8051f90x 77 rev. 1.3 sfr page = 0x0; sfr address = 0xe8; bit-addressable ; sfr definition 5.1. adc0cn: adc0 control bit 7 6 5 4 3 2 1 0 name ad0en bursten ad0int ad0busy ad0wint adc0cm type r/w r/w r/w w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ad0en adc0 enable. 0: adc0 disabled (low-power shutdown). 1: adc0 enabled (active and re ady for data conversions). 6 bursten adc0 burst mode enable. 0: adc0 burst mode disabled. 1: adc0 burst mo de enabled. 5 ad0int adc0 conversion complete interrupt flag. set by hardware upon completion of a data conversion (bursten=0), or a burst o f conversions (bursten=1). can trigger an interrupt. must be cleared by soft - ware. 4 ad0busy adc0 busy. writing 1 to this bit initiates an adc conversion when adc0cm[2:0] = 000. 3 ad0wint adc0 window compare interrupt flag. set by hardware when the contents of adc0h:adc0l fall within the window speci - fied by adc0gth:adc0gtl and adc0lth:adc0ltl. can trigger an interrupt. mu st be cleared by software. 2:0 adc0cm[2:0] adc0 start of conversion mode select. specifies the adc0 start of conversion source. 000: adc0 conversion initiat ed on write of 1 to ad0busy. 001: adc0 conversion initiated on overflow of timer 0. 010: adc0 conversion initiated on overflow of timer 2. 011: adc0 conversion initiated on overflow of timer 3. 1xx: adc0 conversion initiated on rising edge of cnvstr. note:
c8051f91x-c8051f90x rev. 1.3 78 sfr page = 0x0; sfr address = 0xbc sfr definition 5.2. adc0cf: adc0 configuration bit 7 6 5 4 3 2 1 0 name ad0sc[4:0] ad08be ad0tm amp0gn type r/w r/w r/w r/w reset 1 1 1 1 1 0 0 0 bit name function 7:3 ad0sc[4:0] adc0 sar conversion clock divider. sar conversion clock is derived from fclk by the following equation, where ad0sc re fers to the 5-bit value held in bits ad0sc[4:0]. sar conversion clock requirements are given in ta b l e 4.10 . bursten = 0: fclk is the current system clock. bursten = 1: fclk is the 20 mhz low power oscillator, independent of the s ystem clock. 2 ad08be adc0 8-bit mode enable. 0: adc0 operates in 10-bit mode (normal operation). 1: adc0 operates in 8-bit mode. 1 ad0tm adc0 track mode. selects between normal or delayed tracking modes. 0: normal track mode: when adc0 is enabled, conversion begins immediately fol - lowing the start-of-conversion signal. 1: delayed track mode: when adc0 is e nabled, conversion begins 3 sar clock cycles following the start-of-conversion signal. the adc is allowed to track during this time. 0 amp0gn adc0 gain control. 0: the on-chip pga gain is 0.5. 1: the on-chip pga gain is 1. * *round the result up. or ad0sc fclk clk sar -------------------- 1? = clk sar fclk ad 0 sc 1+ ---------------------------- =
c8051f91x-c8051f90x 79 rev. 1.3 sfr page = 0x0; sfr address = 0xba sfr definition 5.3. adc0ac: adc0 accumu lator configuration bit 7 6 5 4 3 2 1 0 name ad012be ad0ae ad0sjst ad0rpt type r/w w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ad012be adc0 12-bit mode enable . enables 12-bit mode. only available on ?f912 and ?f902 devices. 0: 12-bit mode disabled. 1: 12-bit mode enabled. 6 ad0ae adc0 accumulate enable. enables multiple conversions to be accumulated when burst mode is disabled. 0: adc0h:adc0l contain the result of the latest conversion when burst mode is d isabled. 1: adc0h:adc0l contain the accumulated conversion results when burst mode is disable d. software must write 0x00 00 to adc0h:adc0l to clear the accumu - lated result. this bit is write-only. always reads 0b. 5:3 ad0sjst[2:0] adc0 accumulator shift and justify. specifies the format of data read from adc0h:adc0l. 000: right justified. no shif ting applied. 001: right justified. shifted right by 1 bit. 010: right justified. shifted right by 2 bits. 011: right justified. shifted right by 3 bits. 100: left justified. no shifting applied. all remaining bit combinations are reserved. 2:0 ad0rpt[2:0] adc0 repeat count. selects the number of conversions to per form and accumulate in burst mode. this bit field must be set to 000 if burst mode is disabled. 000: perform and accumulate 1 conversion. 001: perform and accumulate 4 conversions. 010: perform and accumulate 8 conversions. 011: perform and accumulate 16 conversions. 100: perform and accumulate 32 conversions. 101: perform and accumulate 64 conversions. all remaining bit combinations are reserved.
c8051f91x-c8051f90x rev. 1.3 80 sfr page = 0xf; sfr address = 0xba sfr definition 5.4. adc0pwr: adc0 burst mode power-up time bit 7 6 5 4 3 2 1 0 name ad0lpm ad0pwr[3:0] type r/w r r r r/w reset 00001111 bit name function 7 ad0lpm adc0 low power mode enable. enables low power mode operation. only availa ble on ?f912 and ?f902 devices. 0: low power mode disabled. 1: low power mode enabled. 6:4 unused unused. read = 0000b; write = don?t care. 3:0 ad0pwr[3:0] adc0 burst mode power-up time. sets the time delay required for adc0 to power up from a low power state. for bursten = 0: adc0 power state controlled by ad0en. for bursten = 1 and ad0en = 1: adc0 remains enabled and does not enter a low power state after all co nversions are complete. conversions can begin immediately following the start-of-conversion signal. for bursten = 1 and ad0en = 0: adc0 enters a low power state after all conversions are complete. conversions can begin a programmed delay after the start-of-conversion signal. the adc0 burst mode power-up time is programmed according to the following e quation: note: setting ad0pwr to 0x04 provides a typical tracking time of 2 us for the first sa mple taken after the start of conversion. or ad0pwr tstartup 400 ns ---------------------- 1? = tstartup ad0pwr 1+ () 400 ns =
c8051f91x-c8051f90x 81 rev. 1.3 sfr page = 0xf; sfr address = 0xbd sfr definition 5.5. adc0tk: adc0 burst mode track time bit 7 6 5 4 3 2 1 0 name reserved ad0tk[5:0] type r r r/w reset 0 0011110 bit name function 7:6 reserved reserved. read = 0b; write = must write 0b. 6 unused unused. read = 0b; write = don?t care. 5:0 ad0tk[5:0] adc0 burst mode track time. sets the time delay between consecutiv e conversions performed in burst mode. the adc0 burst mode track time is programmed according to the following equa - tion: notes: 1. if ad0tm is set to 1, an additional 3 sar clock cycles of track time will be inserted prior to starting the conversion. 2. th e burst mode track delay is not inserted prior to the fi rst conversion. the required tracking time for the first conversion should be met by the burst mode power-up time. or ad0tk 63 ttrack 50 ns ---------------- - 1? ?? ?? ?= ttrack 64 ad0tk ? () 50 ns =
c8051f91x-c8051f90x rev. 1.3 82 sfr page = 0x0; sfr address = 0xbe sfr page = 0x0; sfr address = 0xbd; sfr definition 5.6. adc0h: adc0 data word high byte bit 7 6 5 4 3 2 1 0 name adc0[15:8] type r/w reset 00000000 bit name description read write 7:0 adc0[15:8] adc0 data word high byte. most significant byte of the 16 -bit adc0 accumulator formatted according to the settings in ad0sjst[2:0]. set the most significant byte of th e 16-bit adc0 accumulator to the value written. note: if accumulator shifting is enabled, the most significant bits of the value read will be zeros. this register should not be written when the sync bit is set to 1. sfr definition 5.7. adc0l: adc0 data word low byte bit 7 6 5 4 3 2 1 0 name adc0[7:0] type r/w reset 00000000 bit name description read write 7:0 adc0[7:0] adc0 data word low byte. least significant byte of the 16 -bit adc0 accumulator formatted according to the settings in ad0sjst[2:0]. set the least significant byte of th e 16-bit adc0 accumulator to the value written. note: if accumulator shifting is enabled, the most significant bi ts of the value read will be the least significant bits of the accumulator high byte. this register should not be written when the sync bit is set to 1.
c8051f91x-c8051f90x 83 rev. 1.3 5.6. programmable window detector the adc programmable window detector continuously compares the adc0 output registers to user- programmed limits, and notifies the system when a desired condition is detected. this is especially effective in an interrupt-driven system, saving c ode space and cpu bandwidth while delivering faster system response times. t he window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison values. the window detector flag can be programmed to indicate when measured data is inside or outside of the user-p rogrammed limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. sfr page = 0x0; sfr address = 0xc4 sfr page = 0x0; sfr address = 0xc3 sfr definition 5.8. adc0gth: adc0 greater-than high byte bit 7 6 5 4 3 2 1 0 name ad0gt[15:8] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 ad0gt[15:8] adc0 greater-than high byte. most significant byte of the 16-bit greater-than window compare register. sfr definition 5.9. adc0gtl: adc0 great er-than low byte bit 7 6 5 4 3 2 1 0 name ad0gt[7:0] type r/w reset 1 1 1 1 1 1 1 1 bit name function 7:0 ad0gt[7:0] adc0 greater-than low byte. least significant byte of the 16-bit greater-than window compare register. note: in 8-bit mode, this register should be set to 0x00.
c8051f91x-c8051f90x rev. 1.3 84 sfr page = 0x0; sfr address = 0xc6 sfr page = 0x0; sfr address = 0xc5 sfr definition 5.10. adc0lth: adc0 l ess-than high byte bit 7 6 5 4 3 2 1 0 name ad0lt[15:8] type r/w reset 00000000 bit name function 7:0 ad0lt[15:8] adc0 less-than high byte. most significant byte of the 16-bit less-than window compare register. sfr definition 5.11. adc0ltl: adc0 less-than low byte bit 7 6 5 4 3 2 1 0 name ad0lt[7:0] type r/w reset 00000000 bit name function 7:0 ad0lt[7:0] adc0 less-than low byte. least significant byte of the 16-bit le ss-than window compare register. note: in 8-bit mode, this register should be set to 0x00.
c8051f91x-c8051f90x 85 rev. 1.3 5.6.1. window detector in single-ended mode figure 5.5 shows two example window comparisons for right-justified data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth:adc0gtl = 0x0040 (64d). the input voltage can r ange from 0 to vref x (1023/1024) with respect to gnd, and is represented by a 10-bit unsigned integer value. in the left example, an ad0wint interrup t will be generated if the adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080). in the ri ght example, and ad 0wint interrupt will be generated if the adc0 conversion word is outside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080). figure 5.6 shows an example using left- justified data with the sa me comp arison values. figure 5.5. adc window compare example: right-justified single-ended data figure 5.6. adc window compare exampl e: lef t-justified single-ended data 5.6.2. adc0 specifications see ?4. electrical characteristics? on page 42 for a detailed listing of adc0 specifications. 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl
c8051f91x-c8051f90x rev. 1.3 86 5.7. adc0 analog multiplexer adc0 on c8051f91x-c8051f90x has an analog multiplexer, referred to as amux0. amux0 selects the positive inputs to the single-ended adc0. any of the following may be selected as the po sitive input: port i/o pins, the on-chip temperature sensor, the vbat power supply, regulated digital supply voltage (output of vreg0), vdd/dc+ supply, or the positive input may be connected to gnd. the adc0 input channels are selected in the adc0mx register described in sfr definition 5.12 . figure 5.7. adc0 multip lexer block diagram important note about adc0 input configuration: port pins selected as adc0 inputs should be configured as analog inputs, and should be skipped by the digital crossbar. to configure a port pin for analog input, set to 0 the corresponding bit in regist er pnmdin and disable the digital driver (pnmdout = 0 and port latch = 1). to force the crossbar to skip a port pin, set to 1 the corresponding bit in register pnskip. see section ?21. port input/output? on page 210 for more port i/o configuration details. adc0 temp sensor amux vbat adc0mx ad0mx4 ad0mx3 ad0mx2 ad0mx1 am0mx0 ain+ p0.0 p1.6* digital supply vdd/dc+ programmable attenuator gain = 0.5 or 1 adc0 temp sensor amux vbat adc0mx ad0mx4 ad0mx3 ad0mx2 ad0mx1 am0mx0 ain+ p0.0 p1.6* digital supply vdd/dc+ programmable attenuator gain = 0.5 or 1
c8051f91x-c8051f90x 87 rev. 1.3 sfr page = 0x0; sfr address = 0xbb sfr definition 5.12. adc0mx: adc0 input channel select bit 7 6 5 4 3 2 1 0 name ad0mx type r r r r/w r/w r/w r/w r/w reset 00011111 bit name function 7:5 unused unused. read = 000b; write = don?t care. 4:0 ad0mx amux0 positive input selection. selects the positive input channel for adc0. 00000: p0.0 10000: reserved. 00001: p0.1 10001: reserved. 00010: p0.2 10010: reserved. 00011: p0.3 10011: reserved. 00100: p0.4 10100: reserved. 00101: p0.5 10101: reserved. 00110: p0.6 10110: reserved. 00111: p0.7 10111: reserved. 01000: p1.0 11000: reserved. 01001: p1.1 11001: reserved. 01010: p1.2 11010: reserved. 01011: p1.3 11011: temperature sensor* 01100: p1.4 11100: vbat supply voltage (0.9?1.8 v) or (1.8?3.6 v) 01101: p1.5 01110: p1.6 11101: digital supply voltage (vreg0 output, 1.7 v typical) 01111: reserved, 11110: vdd/dc+ supply voltage (1.8?3.6 v) 11111: ground *note: before switching the adc multiplexer from another channel to the temperature sensor, the adc mux should select the 'ground' channel as an intermediate step. the intermediate 'ground' channel selection step will discharge any voltage on the adc sampling capacitor from the previous channel selection. this will prevent the possibility of a high voltage (> 2v) being presented to the temperature sensor circuit, which can otherwise impact its long-term reliability.
c8051f91x-c8051f90x rev. 1.3 88 5.8. temperature sensor an on-chip temperature sensor is included on the c8051f91x-c8051f90x which c an be directly accessed via the adc multiplexer in single-e nded configuration. to use the adc to measure the temperature sensor, the adc mux channel should select the temperature sensor. the temperature sens or transfer function is shown in figure 5.8 . the output voltage (v temp ) is the positive adc input wh en the adc multiplexer is set correctly. the tempe bit in register ref0cn enables/disab les the temperature sensor, as described in sfr definition 5.15 . while disabled, the temperature sensor defaults to a high impedance state and any adc measurements performed on the sens or will result in meaningless data. refer to ta b l e 4.11 for the slope and offset parameters o f the temperature sensor. important note : before sw itching the adc mu ltiplexer from another channel to the temperature sensor, the adc mux should select the 'ground' channel as an intermediate step. the intermediate 'ground' chan - nel selection step will discharge any voltage on the adc s ampling capacitor from the previous channel selection. this will prevent the possibility of a high voltage (> 2v) being presente d to the temperature sen - sor circuit, which can otherwise imp act its long-term reliability. figure 5.8. temperature sensor transfer function temperature voltage v temp = slope x (temp c offset ( v at 25 celsius) slope ( v / deg c) temp c = 25 + ( - 25) + offset v temp - offset ) / slope
c8051f91x-c8051f90x 89 rev. 1.3 5.8.1. calibration the uncalibrated temperature sensor output is extrem ely linear and suitable for relative temperature mea - surements (see ta b l e 4.11 for linearity specifications). for abso lute tem perature measurements, offset and/or gain calibration is recommended. t ypically a 1-point (offset) calibration includes the following steps: 1. control/measure the ambient temperature (this temperature must be known). 2. power the device, and delay for a few seconds to allow for self-heating. 3. perform an adc conversion with the temperature sensor selected as the positive input and gnd se lected as the negative input. 4. calculate the offset characteristics, and store this v alue in non-volatile memory for use with subsequent temperature sensor measurements. figure 5.9 shows the typical temperature sensor error assuming a 1-point calibration at 25 c. par ame - ters that affect adc measurement, in p articular the voltage refere nce value, will al so affect tem - perature measurement. a single-point offset measurement of the temper atur e sensor is performed on each device during produc - tion test. the measurement is performed at 25 c 5 c, using the adc with the internal high speed refer - ence buffer selected as the voltage reference. the direct adc result of the measurement is stored in the sfr re gisters toffh and toffl, shown in sfr definition 5.13 and sfr definition 5.14 . figure 5.9. temperature sensor error with 1-point calibration (v ref = 1.68 v) -40.00 -20.00 0.00 20.00 40.00 60.00 80.00 temperature (degrees c) error (degrees c) -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00 -5.00 -4.00 -3.00 -2.00 -1.00 0.00 1.00 2.00 3.00 4.00 5.00
c8051f91x-c8051f90x rev. 1.3 90 sfr page = 0xf; sfr address = 0x86 sfr page = 0xf; sfr address = 0x85 sfr definition 5.13. toffh: temperature sensor offset high byte bit 7 6 5 4 3 2 1 0 name toff[9:2] type rrrrrrrr reset varies varies varies varies varies varies varies varies bit name function 7:0 toff[9:2] temperature sensor offset high bits. most significant bits of the 10-bit temperature sensor offset measurement. sfr definition 5.14. toffl: temperature sens or offset low byte bit 7 6 5 4 3 2 1 0 name toff[1:0] type rr reset variesvaries000000 bit name function 7:6 toff[1:0] temperature sensor offset low bits. least significant bits of the 10-bit temp erature sensor offset measurement. 5:0 unused unused. read = 0; write = don't care.
c8051f91x-c8051f90x 91 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 91 5.9. voltage and ground reference options the voltage reference mux is configurable to use an externally connected voltage reference, one of two internal voltage references, or one of two power supply voltages (see figure 5.10 ). the ground reference mux allows the ground reference for adc0 to be selected between the ground pin (gnd) or a port pin dedicated to analog ground (p0.1/agnd). the voltage and ground reference options are configured using the ref0cn sfr described on page 93 . electrical specifications are can be found in the electrical s pecifications chapter. important note about the v ref and agnd inputs: port pins are used as the external v ref and agnd inputs. when using an external voltage reference or th e internal precision reference, p0.0/vref should be configured as an analog input and skipped by the di gital crossbar. when using agnd as the ground reference to adc0, p0.1/agnd should be configured as an analog input and skipped by the digital crossbar. refer to section ?21. port input/output? on page 210 for complete port i/ o c onfiguration details. the external reference voltage must be within the range 0 v ref vdd/dc+ and the external ground r eference must be at the same dc voltage potential as gnd. figure 5.10. voltage reference functional block diagram vref (to adc) adc input mux p0.0/vref r1 vdd external voltage reference circuit gnd temp sensor en 00 01 10 11 ref0cn refsl0 tempe refoe refsl1 refgnd internal 1.68v reference recommended bypass capacitors + 4.7 f0.1 f internal 1.8v regulated digital supply en vdd/dc+ internal 1.65v high speed reference gnd p0.1/agnd 0 1 ground (to adc) refoe refgnd
c8051f91x-c8051f90x 92 rev. 1.3 5.10. external voltage references to use an external voltage reference, refsl[1:0] should be set to 00 and the internal 1.68 v precision ref - erence should be disabled by setting refoe to 0. byp ass capacitors should be added as recommended by the manufacturer of the external voltage reference. 5.11. internal voltage references for applications requiring the maximum number of po rt i/o pins, or very short vref turn-on time, the 1.65 v high-speed reference will be the best internal refere nce option to c hoose. th e high speed internal reference is selected by setting refsl[1:0] to 11. when selected , the high speed intern al reference will be automatically enabled/disabled on an as-needed basis by adc0. for applications requiring the highest absolute accuracy, the 1.68 v precision voltage reference will be the b est internal reference option to choose. the 1.68 v precision reference may be enabled and selected by setting refoe to 1 a nd refsl[1:0] to 00. an external capacitor of at least 0.1 f is recommended when u sing the precision voltage reference. in applications that leave the prec ision internal oscillator always runn ing, there is no additional power required to use the precision voltage reference. in all other applications, using the high speed reference will result in lower overall pow er consumption due to its minimal startup time and the fact that it remains in a low power state when an adc conversion is not taking place. note: when using the precision internal oscillator as the system clock source, the precision voltage reference should not be enabled from a disabled state. to use the precision oscillator and the precision voltage reference simultaneously, the precision volt age reference should be enabled first and allowed to settle to its final value (charging the external capa citor) before the precision oscillator is started and selected as the system clock. for applications with a non-varying power supply voltag e, using the power supply as the voltage reference can provide adc0 with added dynamic range at the cost of reduced power supply noise rejection. to use the 1.8 to 3.6 v power supply voltage (v dd /dc+) or the 1.8 v regulated digital supply voltage as the re ference source, refsl[1:0] should be set to 01 or 10, respectively. 5.12. analog ground reference to prevent ground noise generated by switching digital logic from affecting sensitive analog measurements, a separate analog ground reference op tion is available. when enabled, the ground reference for adc0 during both the tracking/sampli ng and the conversion periods is taken from the p0.1/agnd pin. any external sensors sampled by adc0 should be referenced to the p0.1/agnd pin. this pin should be connected to the ground terminal of any external sensors sampled by adc0. if an external voltage reference is used, the p0.1/agnd pin should be connected to the ground of the external reference and its associated decoupling capacitor. if the 1.68 v precision internal referenc e is used, then p0.1/agnd should be connected to the ground terminal of its external decoupling capacitor. the separate analog ground reference option is enabled by setting refgnd to 1. note that when sampling the internal temperature sensor, the internal chip ground is always used for the sampling operation, regardless of the setting of the refgnd bit. simila rly, whenever the internal 1.65 v high-speed reference is selected, the in ternal chip ground is always used during the conversion period, regardless of the setting of the refgnd bit. 5.13. temperature sensor enable the tempe bit in register ref0cn enables/disables the temperature sensor. while disabled, the temperature sensor defaults to a high impedance st ate and any adc0 measurements performed on the sensor result in meaningless data. see section ?5.8. temperature sensor? on page 88 for details on temperature sensor characteri stic s when it is enabled.
c8051f91x-c8051f90x rev. 1.3 93 sfr page = 0x0; sfr address = 0xd1 5.14. voltage reference electrical specifications see ta b l e 4.12 on page 63 for detailed voltage reference electrical specifications. sfr definition 5.15. ref0cn: voltage reference control bit 7 6 5 4 3 2 1 0 name refgnd refsl tempe refoe type r r r/w r/w r/w r/w r r/w reset 00011000 bit name function 7:6 unused unused. read = 00b; write = don?t care. 5 refgnd analog ground reference. selects the adc0 ground reference. 0: the adc0 ground reference is the gnd pin. 1: the adc0 ground reference is the p0.1/agnd pin. 4:3 refsl voltage reference select. selects the adc0 voltage reference. 00: the adc0 voltage reference is the p0.0/vref pin. 01: the adc0 voltage reference is the vdd/dc+ pin. 10: the adc0 voltage reference is the internal 1.8 v digital supply voltage. 11: the adc0 voltage reference is the internal 1.65 v high speed voltage reference. 2 tempe temperature sensor enable. enables/disables the internal temperature sensor. 0: temperature sensor disabled. 1: temperature sensor enabled. 1 unused unused. read = 0b; write = don?t care. 0 refoe internal voltage refe rence output enable. connects/disconnects the internal vo lt age reference to the p0.0/vref pin. 0: internal 1.68 v precision voltage reference disabled and not connected to p0.0/vref . 1: internal 1.68 v precision voltage reference enabled and connected to p0.0/vref .
c8051f91x-c8051f90x 94 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 94 6. programmable current reference (iref0) c8051f91x-c8051f90x devices include an on-chip prog rammable current reference (source or sink) with two output current settings: low power mode and high current mode. the maximum current output in low power mode is 63 a (1 a steps) and the maximum current output in high current mode is 504 a (8 a step s). the current source/sink is controlled though the iref0c n sp ecial function register. it is enabled by setting the desired output current to a non-zero value. it is di sabled by writing 0x00 to iref0cn. the port i/o pin associated with isrc0 should be configured as an analog input and skipped in the crossbar. see section ?21. port input/output? on page 210 for more details. sfr page = 0x0; sfr address = 0xb9 6.1. pwm enhanced mode on ?f912 and ?f902 devices, the precision of the current reference can be increased by fine tuning the iref0 output using a pwm signal gen erated by the pca. this mode allows the iref0dat bits to perform a course adjustment on the iref0 output. any avail able pca channel can perform a fine adjustment on the iref0 output. when enabled (pwmen = 1), the cex signal selected using the pwmss bit field is internally routed to iref0 to control the on time of a current source having the weight of 2 lsbs. with the two least significant bits of iref 0dat set to 00b, applying a 100% duty cycle on the cex signal will be equivalent to setting the two lsbs of iref0dat to 10b. pwm enhanced mode is enabled and setup using the iref0cf register. sfr definition 6.1. iref0cn: current reference control bit 7 6 5 4 3 2 1 0 name sink mode iref0dat type r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 sink iref0 current sink enable. selects if iref0 is a current source or a current sink. 0: iref0 is a current source. 1: iref0 is a current sink. 6 mdsel iref0 output mode select. selects low power or high current mode. 0: low power mode is selected (step size = 1 a). 1: high current mode is selected (step size = 8 a). 5:0 iref0dat[5:0] iref0 data word. specifies the number of steps required to achieve the desired output current. output current = direction x step size x iref0dat. iref0 is in a low power state wh en i ref0dat is set to 0x00.
c8051f91x-c8051f90x 95 rev. 1.3 sfr page = 0xf; sfr address = 0xb9 6.2. iref0 specifications see ta b l e 4.13 on page 64 for a detailed listing of iref0 specifications. sfr definition 6.2. iref0cf: current reference configuration bit 7 6 5 4 3 2 1 0 name pwmen pwmss[2:0] type r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 pwmen pwm enhanced mode enable. enables the pwm enhanced mode. only available on ?f912 and ?f902 devices. 0: pwm enhanced mode disabled. 1: pwm enhanced mode enabled. 6:3 unused unused. read = 00b, write = don?t care. 2:0 pwmss[2:0] pwm source select. selects the pca channel to use for the fi ne- tuning control signal. only available on ?f912 and ?f902 devices. 000: cex0 selected as fine-tuning control signal. 001: cex1 selected as fine-tuning control signal. 010: cex2 selected as fine-tuning control signal. 011: cex3 selected as fine-tuning control signal. 100: cex4 selected as fine-tuning control signal. 101: cex5 selected as fine tuning control signal. all other values: reserved.
c8051f91x-c8051f90x rev. 1.3 96 7. comparators c8051f91x-c8051f90x devices include two on-chip programmable voltage comparators: comparator 0 ( cpt0) is shown in figure 7.1 ; comparator 1 (cpt1) is shown in figure 7.2 . the two comparators operate identically, but may differ in their ability to be us ed as reset or wake -up sources. see the reset sources chapter and the power management chapter for details on reset sources and low power mode wake-up sources, respectively. the comparator offers programmable response time a nd hysteresis, an analog in put multiplexer, and two outputs that are optionally available at the port pins : a digital synchronous ?latched? output (cp0, cp1), or a digital asynchronous ?raw? output (cp0a, cp1a). the asynchronous cp0a signal is available even when the system clock is not active. this allows the comp arator to operate and gener ate an output when the device is in some low power modes. 7.1. comparator inputs each comparator performs an analog comparison of th e voltage levels at its positive (cp0+ or cp1+) and negative (cp0- or cp1-) input. both comparators suppo rt multiple port pin inpu ts multiplexed to their positive and negative comparator inputs using analog in put multiplexers. the analog input multiplexers are completely under software control and configured using sfr registers. see section ?7.6. comparator0 and comparator1 analog multiplexers? on page 103 for details on how to select and configure comparator inputs. important note about comparator inputs: t he port pins selected as comparator inputs should be configured as analog inputs and skipped by the crossbar. see the port i/o chapter for more details on how to configure port i/o pins as analog inputs. the comparator may also be used to compare the logic level of digital signals, however, port i/o pins configured as digital inputs must be driven to a valid logic state (high or low) to avoid increased power consumption. figure 7.1. comparator 0 functional block diagram vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp0 + px.x cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 rising-edge cp0 falling-edge cp0 interrupt px.x px.x px.x cp0 - (asynchronous) analog input multiplexer
c8051f91x-c8051f90x 97 rev. 1.3 7.2. comparator outputs when a comparator is enabled, its output is a logic 1 if the voltage at the positive input is higher than the volt age at the negative input. when disa bled, the comparator output is a logic 0. the comparator output is synchronized with the sys te m clock as shown in figure 7.2 . the synchronous ?latched? output (cp0, cp1) can be polled in software (cpnout bit), used as an interrupt source, or routed to a port pin (configured for d igital i/o) through the crossbar. the asynchronous ?raw? comparator output (cp0a, cp 1a) is used by the low power mode wake-up logic and reset decision logic. see the power options chapter and the reset sources chapter for more details on how the asynchronous comparator outputs are used to make wake-up and reset decisions. the asynchronous comparator output can also be routed directly to a port pin through the crossbar, and is available for use outside the device even if the system clock is stopped. when using a comparator as an interrupt source, comparator interrupts can be generated on rising-edge and/or falling-edge co mparator output transitions. two indepe ndent interrupt flags (cpnrif and cpnfif) allow software to determine which edge caused the comparator interrupt. the comparator rising-edge and falling-edge interrupt flags are set by hardware when a corr esponding edge is detected rega rdless of the interrupt enable state. once set, these bits remain set until cleared by software. the rising-edge and falling-edge interrupts can be in dividually enabled using the cpnrie and cpnfie interrupt enable bits in the cptnmd register. in or der for the cpnrif and/or cpnfif interrupt flags to generate an interrupt request to the cpu, the comparator must be enabled as an interrupt source and global interrupts must be enabled. see the interrupt handler chapter for additional information. figure 7.2. comparator 1 functional block diagram vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp1 + px.x cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 cpt0md cp1rie cp1fie cp1md1 cp1md0 cp1 cp1a cp1 rising-edge cp1 falling-edge cp1 interrupt px.x px.x px.x cp1 - (asynchronous) analog input multiplexer
c8051f91x-c8051f90x rev. 1.3 98 7.3. comparator response time comparator response time may be configured in software via the cptnmd registers described on ?cpt0md: comparator 0 mode selection? on page 100 and ?cpt1md: comparator 1 mode selection? on page 102 . four response time settings are available: mode 0 (fastest response time), mode 1, mode 2, and mode 3 (lowest power). selecting a longer response time reduces the comparator active supply cur rent. the comparators also have low power shutdown state, which is entered any time the comparator is disabled. comparator rising edge and falling edge re sponse times are typically not equal. see ta b l e 4.14 on page 65 for complete comparator timing and supply current specifications. 7.4. comparator hysteresis the comparators fe ature software-progra mmable hysteresis that can be used to stab ilize the comparator output while a transition is occurr ing on the input. using the cptncn registers, the user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and negative-going symmetry of this hysteresis around the threshold voltage (i.e., the comparator negative input). figure 7.3 shows that when positive hysteresis is enabled, the comp arator output does not transition from logic 0 to logic 1 until the comparator positive input voltage has exceeded the threshold voltage by an a mount equal to the programmed hysteresis. it also show s that when negative hysteresis is enabled, the comparator output does not transition from logic 1 to logic 0 until the comparator positive input voltage has falle n below the threshold voltage by an amount equal to the programmed hysteresis. the amount of positive hysteresis is de termined by the settings of the cpnhyp bits in the cptncn register and the amount of negative hy steresis voltage is determined by t he settings of the cpnhyn bits in the same register. settings of 20, 10, 5, or 0 mv can be programmed for both positive and negative h ysteresis. see section ?table 4.14. comparator electrical characteristics? on page 65 for complete comparator hysteresis specifications. figure 7.3. comparator hysteresis plot positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cpn+ cpn- cpn vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol
c8051f91x-c8051f90x 99 rev. 1.3 7.5. comparator register descriptions the sfrs used to enable and configure the comp arators are described in the following register descriptions. a comparator must be enabled by setting the cpnen bit to logic 1 before it can be used. fr om an enabled state, a comparator can be disabled and placed in a low power state by clearing the cpnen bit to logic 0. important note about comparator settings: false rising and falling edges can be detected by the comparator while powering on or if changes are made to the hysteresis or response time control bits. therefore, it is recommended that the rising-edge and falling-edge flags be explicitly cleared to logic 0 a sho rt time after the comparator is enabled or its mode bits have been changed. the comparator power up time is specified in section ?table 4.14. comparator electrical characteristics? on page 65 . sfr page= 0x0; sfr address = 0x9b sfr definition 7.1. cpt0cn: comparator 0 control bit 7 6 5 4 3 2 1 0 name cp0en cp0out cp0rif cp0fif cp0hyp[1:0] cp0hyn[1:0] type r/w r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 cp0en comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. 6 cp0out comparator0 output state flag. 0: voltage on cp0+ < cp0 ? . 1: voltage on cp0+ > cp0 ? . 5 cp0rif comparator0 rising-edge flag. must be cleared by software. 0: no comparator0 rising edge has occu rr ed since this flag was last cleared. 1: comparator0 rising edge has occurred. 4 cp0fif comparator0 falling-edge flag. must be cleared by software. 0: no comparator0 falling-e dge has occurred since this flag was last cleared. 1: comparator0 falling-edge has occurred. 3-2 cp0hyp[1:0] comparator0 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = hysteresis 1. 10: positive hysteresis = hysteresis 2. 11: positive hysteresis = hysteresis 3 (maximum). 1:0 cp0hyn[1:0] comparator0 negative hy st eresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = hysteresis 1. 10: negative hysteresis = hysteresis 2. 11: negative hysteresis = hysteresis 3 (maximum).
c8051f91x-c8051f90x rev. 1.3 100 sfr page = all pages; sfr address = 0x9d sfr definition 7.2. cpt0md: comparator 0 mode selection bit 7 6 5 4 3 2 1 0 name cp0rie cp0fie cp0md[1:0] type r/w r r/w r/w r r r/w reset 1 0 0 0 0 0 1 0 bit name function 7 reserved reserved. read = 1b, must write 1b. 6 unused unused. read = 0b, write = don?t care. 5 cp0rie comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. 4 cp0fie comparator0 falling-edge interrupt enable. 0: comparator0 falling-edge interrupt disabled. 1: comparator0 falling-edge interrupt enabled. 3:2 unused unused. read = 00b, write = don?t care. 1:0 cp0md[1:0] comparator0 mode select these bits affect the response time and power consumption for comparator0. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
c8051f91x-c8051f90x 101 rev. 1.3 sfr page= 0x0; sfr address = 0x9a sfr definition 7.3. cpt1cn: comparator 1 control bit 7 6 5 4 3 2 1 0 name cp1en cp1out cp1rif cp1fif cp1hyp[1:0] cp1hyn[1:0] type r/w r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 cp1en comparator1 enable bit. 0: comparator1 disabled. 1: comparator1 enabled. 6 cp1out comparator1 output state flag. 0: voltage on cp1+ < cp1 ? . 1: voltage on cp1+ > cp1 ? . 5 cp1rif comparator1 rising-edge flag. must be cleared by software. 0: no comparator1 rising edge has occu rr ed since this flag was last cleared. 1: comparator1 rising edge has occurred. 4 cp1fif comparator1 falling-edge flag. must be cleared by software. 0: no comparator1 falling-e dge has occurred since this flag was last cleared. 1: comparator1 falling-edge has occurred. 3:2 cp1hyp[1:0] comparator1 positive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = hysteresis 1. 10: positive hysteresis = hysteresis 2. 11: positive hysteresis = hysteresis 3 (maximum). 1:0 cp1hyn[1:0] comparator1 negative hy st eresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = hysteresis 1. 10: negative hysteresis = hysteresis 2. 11: negative hysteresis = hysteresis 3 (maximum).
c8051f91x-c8051f90x rev. 1.3 102 sfr page = 0x0; sfr address = 0x9c sfr definition 7.4. cpt1md: comparator 1 mode selection bit 7 6 5 4 3 2 1 0 name cp1rie cp1fie cp1md[1:0] type r/w r r/w r/w r r r/w reset 1 0 0 0 0 0 1 0 bit name function 7 reserved reserved. read = 1b, must write 1b. 6 unused unused. read = 0b, write = don?t care. 5 cp1rie comparator1 rising-edge interrupt enable. 0: comparator1 rising-edge interrupt disabled. 1: comparator1 rising-edge interrupt enabled. 4 cp1fie comparator1 falling-edge interrupt enable. 0: comparator1 falling-edge interrupt disabled. 1: comparator1 falling-edge interrupt enabled. 3:2 unused unused. read = 00b, write = don?t care. 1:0 cp1md[1:0] comparator1 mode select these bits affect the response time and power consumption for comparator1. 00: mode 0 (fastest response time, highest power consumption) 01: mode 1 10: mode 2 11: mode 3 (slowest response time, lowest power consumption)
c8051f91x-c8051f90x 103 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 103 7.6. comparator0 and comparator1 analog multiplexers comparator0 and comparator1 on c8051f91x-c8051f90x devices have analog input multiplexers to connect port i/o pins and internal signals the comparator inputs; cp0+ /cp0- are the positive and negative input multiplexers for comparator0 and cp1+/cp1- are the positive and negative input multiplexers for comparator1. the comparator input multip lexers direct ly support capacitive touc h switches. when the capacitive touch sense compare input is selected on the positive or neg ative multiplexer, any port i/o pin connected to the other multiplexer can be directly connected to a capacitive touch switch with no additional external components. the capacitive touch sense compare prov ides the appropriate reference level for detecting when the capacitive touch switches have charged or discharged through the on-chip rsense resistor. the comparator outputs can be routed to timer2 or timer3 for capturing sense capacitor?s charge and discharge time. see section ?25. timers? on page 274 for details. any of the following may be sele cted as comparator inputs: port i/o pins, capacitive touch sense compare, vdd/dc+ supply voltage, regulated digital supply voltage (output of vreg0), the vbat supply voltage or ground. the comparator?s supply volt age divided by 2 is also available as an input; the resistors used to divide the voltage only draw current when this setting is selected. the comparator input multiplexers are configured using the cpt0mx and cpt1mx registers described in sfr definition 7.5 and sfr definition 7.6 . figure 7.4. cpn multiplexer block diagram important note about comparator input configuration: port pins selected as comparator inputs should be configured as analog inputs, and should be skipped by the digital crossbar. to configure a port pin for analog input, set to 0 the corresponding bit in regist er pnmdin and disable the digital driver (pnmdout = 0 and port latch = 1). to force the crossbar to skip a port pin, set to 1 the corresponding bit in register pnskip. see section ?21. port input/output? on page 210 for more port i/o configuration details. cpn- input mux digital supply p0.1 vdd/dc+ + - gnd vdd/dc+ p0.3 p0.5 p0.7 p1.1 p1.3 p1.5 vdd/dc+ r r vdd/dc+ r r cpnout r ? x vdd/dc+ (1/3 or 2/3) x vdd/dc+ capacitive touch sense compare cpn+ input mux vbat cptnmx cmxnn3 cmxnn2 cmxnn1 cmxnn0 cmxnp3 cmxnp2 cmxnp1 cmxnp0 p0.0 p0.2 p0.4 p0.6 p1.0 p1.2 p1.4 p1.6 vdd/dc+ r r vdd/dc+ r r cpnout r ? x vdd/dc+ (1/3 or 2/3) x vdd/dc+ cpnout rsense only enabled when capacitive touch sense compare is selected on cpn+ input mux. cpnout rsense capacitive touch sense compare only enabled when capacitive touch sense compare is selected on cpn- input mux. gnd
c8051f91x-c8051f90x 104 rev. 1.3 sfr page = 0x0; sfr address = 0x9f sfr definition 7.5. cpt0mx: comparator0 input channel select bit 7 6 5 4 3 2 1 0 name cmx0n[3:0] cmx0p[3:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 bit name function 7:4 cmx0n comparator0 negative input selection. selects the negative input channel for comparator0. 0000: p0.1 1000: reserved 0001: p0.3 1001: reserved 0010: p0.5 1010: reserved 0011: p0.7 1011: reserved 0100: p1.1 1100: capacitive touch sense compare 0101: p1.3 1101: vdd/dc+ divided by 2 0110: p1.5 1110: digital supply voltage 0111: reserved 1111: ground 3:0 cmx0p comparator0 positive input selection. selects the positive input channel for comparator0. 0000: p0.0 1000: reserved 0001: p0.2 1001: reserved 0010: p0.4 1010: reserved 0011: p0.6 1011: reserved 0100: p1.0 1100: capacitive touch sense compare 0101: p1.2 1101: vdd/dc+ divided by 2 0110: p1.4 1110: vbat supply voltage 0111: p1.6 1111: vdd/dc+ supply voltage
c8051f91x-c8051f90x rev. 1.3 105 sfr page = 0x0; sfr address = 0x9e sfr definition 7.6. cpt1mx: comparator1 input channel select bit 7 6 5 4 3 2 1 0 name cmx1n[3:0] cmx1p[3:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 11111111 bit name function 7:4 cmx1n comparator1 negative input selection. selects the negative input channel for comparator1. 0000: p0.1 1000: reserved 0001: p0.3 1001: reserved 0010: p0.5 1010: reserved 0011: p0.7 1011: reserved 0100: p1.1 1100: capacitive touch sense compare 0101: p1.3 1101: vdd/dc+ divided by 2 0110: p1.5 1110: digital supply voltage 0111: reserved 1111: ground 3:0 cmx1p comparator1 positive input selection. selects the positive input channel for comparator1. 0000: p0.0 1000: reserved 0001: p0.2 1001: reserved 0010: p0.4 1010: reserved 0011: p0.6 1011: reserved 0100: p1.0 1100: capacitive touch sense compare 0101: p1.2 1101: vdd/dc+ divided by 2 0110: p1.4 1110: vbat supply voltage 0111: p1.6 1111: vdd/dc+ supply voltage
c8051f91x-c8051f90x 106 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 106 8. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the mcu family has a superset of all the peripherals included with a standard 8051. the cip-51 also includes on-chip debug hardware (see description in section 27 ), and interfaces directly with the analog and digital subsystems providing a complete da t a acquisition or control-system solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional c ustom peripherals and func tions to extend its capability (see figure 8.1 for a block diagram). the cip-51 includes the following features: 8.1. performance the cip-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051 architecture. in a standard 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute, and usua lly have a maximum system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its inst ructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. figure 8.1. cip-51 block diagram - fully compatible wit h mcs-51 instruction set - 25 mips peak throughput with 25 mhz clock - 0 to 25 mhz clock frequency - extended interrupt handler - reset input - power management modes - on-chip debug logic - program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8
c8051f91x-c8051f90x 107 rev. 1.3 with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a total of 109 instructions. the table below shows the total number of instructions that require each execution time. 8.2. programming a nd debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is accomplished via the silicon l abs 2-wire development interface (c2). the on-chip debug support logic facilitates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, and reading/writing the contents of registers and memory. this method of on-chip debugging is complete ly non-intrusive, requiri ng no ram, stack, timers, or other on-chip resources. c2 details can be found in section ?27. c2 interface? on page 316 . the cip-51 is supported by development tools from silicon labs and third part y vendors. silicon labs provides an integrated development environment (ide ) including editor, debugger and programmer. the ide's debugger and programmer interface to the cip-51 via the c2 interface to provide fast and efficient in-system device programming and debugging. third party macro assemblers and c compilers are also available. 8.3. instruction set the instruction set of the cip-51 system controlle r is fully compatible wit h the standard mcs-51? instruction set. standard 8051 development tools can be used to develop software for the cip-51. all cip- 51 instructions are the binary and functional equiva lent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, instruction timing is di fferent than that of the standard 8051. 8.3.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instruction timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most in structions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. table 8.1 is the cip-51 instruction set summary, which includes the mn emonic, number of bytes, and number of clock cycles for each instruction. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1
c8051f91x-c8051f90x rev. 1.3 108 table 8.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3
c8051f91x-c8051f90x 109 rev. 1.3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 table 8.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles
c8051f91x-c8051f90x rev. 1.3 110 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 4/5 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not eq ual 3 3/4 cjne @ri, #data, rel compare immediate to indirect and jump if not eq ual 3 4/5 djnz rn, rel decrement register and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 8.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles
c8051f91x-c8051f90x 111 rev. 1.3 notes on registers, operands and addressing modes: rn ?register r0?r7 of the currently selected register bank. @ri ?data ram location addressed indirectly through r0 or r1. rel ?8-bit, signed (twos complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct ?8-bit internal data location?s address. this could be a direct-access data ram location (0x00?0x7f) or an sfr (0x80?0xff). #data ?8-bit constant #data16 ?16-bit constant bit ?direct-accessed bit in data ram or sfr addr11 ?11-bit destination address used by acall and ajmp. the destination must be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 ?16-bit destination address used by lcall an d ljmp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980.
c8051f91x-c8051f90x rev. 1.3 112 8.4. cip-51 regist er descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should not be set to logic l. future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default st ate. detailed descriptions of the remaining sfrs are included in the sections of the data sheet associated with their corresponding system function. sfr page = all pages; sfr address = 0x82 sfr page = all pages; sfr address = 0x83 sfr definition 8.1. dpl: data pointer low byte bit 7 6 5 4 3 2 1 0 name dpl[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 dpl[7:0] data pointer low. the dpl register is the low byte of the 16 -bit dptr. dptr is used to access indi - rectly addressed flash memory or xram. sfr definition 8.2. dph: data pointer high byte bit 7 6 5 4 3 2 1 0 name dph[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 dph[7:0] data pointer high. the dph register is the high byte of the 16-bit dp tr. dptr is used to access indi - rectly addressed flash memory or xram.
c8051f91x-c8051f90x 113 rev. 1.3 sfr page = all pages; sfr address = 0x81 sfr page = all pages; sfr ad dress = 0xe0; bit-addressable sfr page = all pages; sfr ad dr ess = 0xf0; bit-addressable sfr definition 8.3. sp: stack pointer bit 7 6 5 4 3 2 1 0 name sp[7:0] type r/w reset 0 0 0 0 0 1 1 1 bit name function 7:0 sp[7:0] stack pointer. the stack pointer holds the location of the t op of the stack. the stack pointer is incre - mented before every push operation. the sp register defaults to 0x07 after reset. sfr definition 8.4. acc: accumulator bit 7 6 5 4 3 2 1 0 name acc[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 acc[7:0] accumulator. this register is the accumulator for arithmetic operations. sfr definition 8.5. b: b register bit 7 6 5 4 3 2 1 0 name b[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 b[7:0] b register. this register serves as a second accumu la tor for certain arithmetic operations.
c8051f91x-c8051f90x rev. 1.3 114 sfr page = all pages; sfr ad dress = 0xd0; bit-addressable sfr definition 8.6. psw: program status word bit 7 6 5 4 3 2 1 0 name cy ac f0 rs[1:0] ov f1 parity type r/w r/w r/w r/w r/w r/w r reset 0 0 0 0 0 0 0 0 bit name function 7 cy carry flag. this bit is set when the last arithmetic oper a tion resulted in a carry (addition) or a bor - row (subtraction). it is cleared to logi c 0 by all other arithmetic operations. 6 ac auxiliary carry flag. this bit is set when the last arithmetic operat ion resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arith - metic operations. 5 f0 user flag 0. this is a bit-addressable, general purp ose fla g for use under software control. 4:3 rs[1:0] register bank select. these bits select which register bank is used during register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2 ov overflow flag. this bit is set to 1 under the following circumstances: ? an add, addc, or subb instruction causes a sign-change overflow. ? a mul instruction results in an overflow (result is greater than 255). ? a div instruction causes a divide -by-zero condition. the ov bit is cleared to 0 by the add, a ddc, sub b, mul, and div instructions in all other cases. 1 f1 user flag 1. this is a bit-addressable, general purp ose fla g for use under software control. 0 parity parity flag. this bit is set to logic 1 if the sum of the ei gh t bits in the accumulator is odd and cleared if the sum is even.
c8051f91x-c8051f90x 115 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 115 9. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. the memory organization of the c8051f91x-c8051f90x device family is shown in figure 9.1 figure 9.1. c8051f91x-c8051f90x memory map program/data memory (flash) (direct and indirect addressing) upper 128 ram (indirect addressing only) special function registers (direct addressing only) data memory (ram) general purpose registers bit addressable lower 128 ram (direct and indirect addressing) internal data address space external data address space f 0 0x0000 0x3fff reserved 0x3c00 0x3bff scratchpad memory (data only) 0x01ff 0x0000 c8051f912/11 8kb flash (in-system programmable in 512 byte sectors) 0x0000 0x1fff scratchpad memory (data only) 0x01ff 0x0000 c8051f902/1 xram - 512 bytes (accessable using movx instruction) 0x0000 0x01ff unpopulated address space 0x0200 0x1fff c8051f912/11/02/01 16kb flash (in-system programmable in 512 byte sectors) note: code compatible devices with up to 64 kb flash and 4 kb ram are available as the c8051f93x-92x family.
c8051f91x-c8051f90x 116 rev. 1.3 9.1. program memory the cip-51 core has a 64 kb program memory space. the c805 1f9 1x-c8051f90x devices implement 16 kb (c8051f912/1) or 8 kb (c8051f902/1) of this program memory space as in-system, re- p rogrammable flash memory, organized in a contiguous block from addresses 0x0000 to 0x3bff (c8051f912/1) or 0x1fff (c8051f902/1). the last byte of this contiguous block of addresses serves as the security lock byte for the device. any addresses above the lock byte are reserved. figure 9.2. flash program memory map 9.1.1. movx instruction and program memory the movx instruction in an 8051 device is typica lly used to access external data memory. on the c8051f91x-c8051f90x devices, the movx instruction is normally used to read and write on-chip xram, but can be re-configured to write and erase on-chip flash memory space. movc instructions are always used to read flash memory, while movx write instructions are used to erase and write flash. this flash access feature provides a mechanism for the c8051f91x-c8051f90x to update program code and use the program memory space for non-volatile data storage. refer to section ?13. flash memory? on page 139 for further details. 9.2. data memory the c8051f91x-c8051f90x device family include 768 bytes of ram data memory. 256 bytes of this memory is mapped into the internal ram space of the 8051. the remainder of this memory is on-chip ?external? memory. the data memory map is shown in figure 9.1 for reference. 9.2.1. internal ram there are 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general pu rp ose registers and scratch pad memory. either direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0x00 thr ough 0x1f are addressable as four banks of gene ral purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, ma y eithe r be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by i ndir ect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines lock byte 0x0000 flash memory organized in 512-byte pages flash memory space lock byte page lock byte flash memory space lock byte page reserved area 0x0000 0x3bfe 0x3c00 0x3a00 0xffff 0x3bff 0x1fff 0x1ffe 0x1e00 0x1bff 0x39ff scratchpad (data only) unpopulated address space (reserved) 0xffff 0x8000 0x0000 0x01ff c8051f912/1 (sfle=0) c8051f902/1 (sfle=0) c8051f912/1 c8051f902/1 (sfle=1)
c8051f91x-c8051f90x rev. 1.3 117 whether the cpu accesses the upper 128 bytes of data memory space or th e sfrs. in structions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 9.1 illustrates the data memory or ganization of the c8051f91x - c8051f90x. 9.2.1.1. general purpose registers the lower 32 bytes of data memory, locations 0x00 th rough 0x1f, may be addressed as four banks of general-purpose registers. each bank consists of eight byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. tw o bits in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in sfr definition 8.6 ). this allows fast context switching when entering subrouti nes and interrupt service ro utines. indirect addressing modes use registers r0 and r1 as index registers. 9.2.1.2. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x 00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0 x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destin ation operands as opposed to a byte source or destination). the mcs-51? assembly language allows an alternate no tation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 9.2.1.3. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is designated using the stack po inter (sp) sfr. the sp will point to th e last location us ed. the next value pushed on the stack is placed at sp +1 and then sp is incremented. a re set initializes the stack pointer to location 0x07. therefore, the first value pushed on the st ack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. 9.2.2. external ram there are 512 bytes of on-chip ram mapped into the external data memory space. all of these address locations may be accessed using the external move instruction (movx) and the data pointer (dptr), or using movx indirect addressing mode (such as @r 1) in combinat ion with the emi0cn register.
c8051f91x-c8051f90x 118 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 118 10. on-chip xram the c8051f91x-c8051f90x mcus include on-chip ram mapped into the external data memory space (xram). the external memory space may be accessed using the external move instruction (movx) with the target address specified in either the data pointer (dptr), or with the target address low byte in r0 or r1 and the target address high byte in the external memory interface control re gister (emi0cn, shown in sfr definition 10.1 ). when using the movx instruction to access on-chip ra m, no additional initialization is required and the movx instruction execution time is as specified in the cip-51 chapter. important note : movx wr ite operations can be configured to target flash memory, instead of xram. see section ?13. flash memory? on page 139 for more details. the movx in st ruction accesses xram by default. 10.1. accessing xram the xram memory space is accessed using the mo vx instruction. the movx instruction has two forms, both of which use an indirect addressing method. th e first method uses the data pointer, dptr, a 16-bit register which contains the effect ive address of the xram location to be read from or written to. the second method uses r0 or r1 in combination with th e emi0cn register to generate the effective xram address. examples of both of these methods are given below. 10.1.1. 16-bit movx example the 16-bit form of the movx instructi on accesses the memory location po inted to by the contents of the dptr register. the following series of instructions reads the value of the byte at address 0x1234 into the accumulator a: mov dptr, #1234h ; load dptr with 16-bit address to read (0x1234) movx a, @dptr ; load contents of 0x1234 into accumulator a the above example uses the 16-bit immed iate mov instruction to set th e contents of dptr. alternately, the dptr can be accessed through the sfr registers dph, which contains the upper 8-bits of dptr, and dpl, which contains the lower 8-bits of dptr. 10.1.2. 8-bit movx example the 8-bit form of the movx instruction uses the content s of the emi0cn sfr to determine the upper 8-bits of the effective address to be accessed and the contents of r0 or r1 to determine the lower 8-bits of the effective address to be accessed. the following series of instructions read the contents of the byte at address 0x1234 into the accumulator a. mov emi0cn, #12h ; load high byte of address into emi0cn mov r0, #34h ; load low byte of address into r0 (or r1) movx a, @r0 ; load contents of 0x1234 into accumulator a
c8051f91x-c8051f90x 119 rev. 1.3 10.2. special function registers the special function register used fo r configuring xram access is emi0cn. sfr page = 0x0; sfr address = 0xaa sfr definition 10.1. emi0cn: external memory interface control bit 7 6 5 4 3 2 1 0 name pgsel type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:1 unused unused. read = 0000000b; write = don?t care 0 pgsel xram page select. the emi0cn register provides the high byte of the 16-bit external data memory add ress when using an 8-bit movx command, effectively selecting a 256-byte page of ram. since the upper (unused) bits of the register are always zero, the pgsel determines which page of xram is accessed. for example: if emi0cn = 0x01, addresses 0x 0100 through 0x01ff will be accessed. if emi0cn = 0x00, addresses 0x 0000 through 0x00ff will be accessed.
c8051f91x-c8051f90x rev. 1.3 120 11. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data excha nge with the c8051f91x-c8051f90x's resources and peripherals. the cip-51 controller core duplicates the sfrs found in a typical 8051 implementation as well as implementing additional sfrs used to confi gure and access the sub-systems unique to the c8051f91x-c8051f90x. this allows th e addition of new functionality wh ile retaining compatibility with the mcs-51? instruction set. ta b l e 11.1 an d ta b l e 11.2 list the sfrs implemented in the c8051f91x- c8051f90x device family. the sfr registers are accessed anytime the direct ad dr essing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g., p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing t hese areas will have an indeterminate effect and should be avoided. refer to the corres ponding pages of the data sheet, as indicated in ta b l e 11.3 , for a detailed description of each register. table 11.1. special function register (sfr) memory map (page 0x0) f8 spi0cn pca0l pca0h pca0cpl0 pca0cph0 pca0cpl4 pca0cph4 vdm0cn f0 b p0mdin p1mdin smb0adr smb0adm eip1 eip2 e8 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 pca0cpl3 pca0cph3 rstsrc e0 acc xbr0 xbr1 xbr2 it01cf flwr eie1 eie2 d8 pca0cn pca0md pca0cpm0 pca0cpm1 pca0cpm2 pca0cpm3 pca0cpm4 pca0pwm d0 psw ref0cn pca0cpl5 pca0cph5 p0skip p1skip p0mat c8 tmr2cn reg0cn tmr2rll tmr2rlh tmr2l tmr2h pca0cpm5 p1mat c0 smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth p0mask b8 ip iref0cn adc0ac adc0mx adc0cf adc0l adc0h p1mask b0 spi1cn oscxcn oscicn oscicl pmu0cf flscl flkey a8 ie clksel emi0cn rtc0adr rtc0dat rtc0key a0 p2 spi0cfg spi0ckr spi0dat p0mdout p1mdout p2mdout sfrpage 98 scon0 sbuf0 cpt1cn cpt0cn cpt1md cpt0md cpt1mx cpt0mx 90 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h dc0cf dc0cn 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph spi1cfg spi1ckr spi1dat pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable)
c8051f91x-c8051f90x 121 rev. 1.3 11.1. sfr paging to accommodate more than 128 sfrs in the 0x80 to 0xff address space, sfr paging has been implemented. by default, all sfr accesses target sfr pa ge 0x0 to allow access to the registers listed in ta b l e 11.1 . during device initialization, so me sfrs located on sfr page 0xf may need to be accessed. ta b l e 11.2 lists the sfrs accessible from sfr page 0x0f. some sfrs are accessible from both pages, including the sfrpage register. sfrs only accessible from page 0xf are in bo ld . sfrs only available on the ?f912 and ?f902 devices are in blue . the following procedure should be used when accessing sfrs on page 0xf: 1. save the current interr upt state (ea_save = ea). 2. disable interrupts (ea = 0). 3. set sfrpage = 0xf. 4. access the sfrs located on sfr page 0xf. 5. set sfrpage = 0x0. 6. restore interrupt state (ea = ea_save). table 11.2. special function register (sfr) memory map (page 0xf) f8 f0 b eip1 eip2 e8 e0 acc flwr eie1 eie2 d8 d0 psw c8 c0 b8 iref0cf adc0pwr adc0tk b0 pmu0md a8 ie clksel a0 p2 p0drv p1drv p2drv sfrpage 98 90 p1 crc0dat crc0cn crc0in dc0md crc0flip crc0auto crc0cnt 88 80 p0 sp dpl dph toffl toffh pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable)
c8051f91x-c8051f90x rev. 1.3 122 sfr page = all pages; sfr address = 0xa7 sfr definition 11.1. sfr page: sfr page bit 7 6 5 4 3 2 1 0 name sfrpage[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 sfrpage[7:0] sfr page. specifies the sfr page used when reading, writing, or modifying special function r egisters. table 11.3. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved. sfrs highlighted in blue are only available on ?f912 and ?f902 devices. register address sfr page description page acc 0xe0 all accumulator 113 adc0ac 0xba 0x0 adc0 accumulator configuration 79 adc0cf 0xbc 0x0 adc0 configuration 78 adc0cn 0xe8 0x0 adc0 control 77 adc0gth 0xc4 0x0 adc0 greater-than compare high 83 adc0gtl 0xc3 0x0 adc0 greater-than compare low 83 adc0h 0xbe 0x0 adc0 high 82 adc0l 0xbd 0x0 adc0 low 82 adc0lth 0xc6 0x0 adc0 less-than compare word high 84 adc0ltl 0xc5 0x0 adc0 less-than compare word low 84 adc0mx 0xbb 0x0 amux0 channel select 87 adc0pwr 0xba 0xf adc0 burst mode power-up time 80 adc0tk 0xbd 0xf adc0 tracking control 81 b 0xf0 all b register 113 ckcon 0x8e 0x0 clock control 275 clksel 0xa9 all clock select 190 cpt0cn 0x9b 0x0 comparator0 control 100 cpt0md 0x9d 0x0 comparator0 mode selection 100 cpt0mx 0x9f 0x0 comparator0 mux selection 104 cpt1cn 0x9a 0x0 comparator1 control 101
c8051f91x-c8051f90x 123 rev. 1.3 cpt1md 0x9c 0x0 comparator1 mode selection 102 cpt1mx 0x9e 0x0 comparator1 mux selection 105 crc0auto 0x96 0xf crc0 automatic control 164 crc0cn 0x92 0xf crc0 control 162 crc0cnt 0x97 0xf crc0 automatic flash sector count 164 crc0dat 0x91 0xf crc0 data 163 crc0flip 0x95 0xf crc0 flip 165 crc0in 0x93 0xf crc0 input 163 dc0cf 0x96 0x0 dc0 (dc-dc converte r ) configuration 174 dc0cn 0x97 0x0 dc0 (dc-dc converter) control 173 dc0md 0x94 0xf dc0 (dc-dc converter) mode 175 dph 0x83 all data pointer high 112 dpl 0x82 all data pointer low 112 eie1 0xe6 all extended interrupt enable 1 133 eie2 0xe7 all extended interrupt enable 2 135 eip1 0xf6 0x0 extended interrupt priority 1 134 eip2 0xf7 0x0 extended interrupt priority 2 136 emi0cn 0xaa 0x0 emif control 119 flkey 0xb7 0x0 flash lock and key 147 flscl 0xb6 0x0 flash scale 147 ie 0xa8 all interrupt enable 131 ip 0xb8 0x0 interrupt priority 132 iref0cn 0xb9 0x0 current reference iref control 94 iref0cf 0xb9 0xf current reference iref configuration 95 it01cf 0xe4 0x0 int0 / int1 configuration 138 oscicl 0xb3 0x0 internal oscilla tor c alibration 191 oscicn 0xb2 0x0 internal oscillator control 191 oscxcn 0xb1 0x0 external oscillator control 192 p0 0x80 all port 0 latch 223 p0drv 0xa4 0xf port 0 drive strength 225 p0mask 0xc7 0x0 port 0 mask 220 p0mat 0xd7 0x0 port 0 match 220 p0mdin 0xf1 0x0 port 0 input mode configuration 224 table 11.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. sfrs highlighted in blue are only available on ?f912 and ?f902 devices. register address sfr page description page
c8051f91x-c8051f90x rev. 1.3 124 p0mdout 0xa4 0x0 port 0 output mode configuration 224 p0skip 0xd4 0x0 port 0 skip 223 p1 0x90 all port 1 latch 226 p1drv 0xa5 0xf port 1 drive strength 228 p1mask 0xbf 0x0 port 1 mask 221 p1mat 0xcf 0x0 port 1 match 221 p1mdin 0xf2 0x0 port 1 input mode configuration 227 p1mdout 0xa5 0x0 port 1 output mode configuration 227 p1skip 0xd5 0x0 port 1 skip 226 p2 0xa0 all port 2 latch 228 p2drv 0xa6 0xf port 2 drive strength 229 p2mdout 0xa6 0x0 port 2 output mode configuration 229 pca0cn 0xd8 0x0 pca0 control 310 pca0cph0 0xfc 0x0 pca0 capture 0 high 315 pca0cph1 0xea 0x0 pca0 capture 1 high 315 pca0cph2 0xec 0x0 pca0 capture 2 high 315 pca0cph3 0xee 0x0 pca0 capture 3 high 315 pca0cph4 0xfe 0x0 pca0 capture 4 high 315 pca0cph5 0xd3 0x0 pca0 capture 5 high 315 pca0cpl0 0xfb 0x0 pca0 capture 0 low 315 pca0cpl1 0xe9 0x0 pca0 capture 1 low 315 pca0cpl2 0xeb 0x0 pca0 capture 2 low 315 pca0cpl3 0xed 0x0 pca0 capture 3 low 315 pca0cpl4 0xfd 0x0 pca0 capture 4 low 315 pca0cpl5 0xd2 0x0 pca0 capture 5 low 315 pca0cpm0 0xda 0x0 pca0 module 0 mode register 313 pca0cpm1 0xdb 0x0 pca0 module 1 mode register 313 pca0cpm2 0xdc 0x0 pca0 module 2 mode register 313 pca0cpm3 0xdd 0x0 pca0 module 3 mode register 313 pca0cpm4 0xde 0x0 pca0 module 4 mode register 313 pca0cpm5 0xce 0x0 pca0 module 5 mode register 313 pca0h 0xfa 0x0 pca0 counter high 314 pca0l 0xf9 0x0 pca0 counter low 314 table 11.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. sfrs highlighted in blue are only available on ?f912 and ?f902 devices. register address sfr page description page
c8051f91x-c8051f90x 125 rev. 1.3 pca0md 0xd9 0x0 pca0 mode 311 pca0pwm 0xdf 0x0 pca0 pwm configuration 312 pcon 0x87 0x0 power control 157 pmu0cf 0xb5 0x0 pmu0 configuration 155 pmu0md 0xb5 0xf pmu0 mode 156 psctl 0x8f 0x0 program store r/w control 146 psw 0xd0 all program status word 114 ref0cn 0xd1 0x0 voltage reference control 93 reg0cn 0xc9 0x0 voltage regulator (vreg0) control 176 rstsrc 0xef 0x0 reset source configuration/status 184 rtc0adr 0xac 0x0 rtc0 address 198 rtc0dat 0xad 0x0 rtc0 data 198 rtc0key 0xae 0x0 rtc0 key 197 sbuf0 0x99 0x0 uart0 data buffer 258 scon0 0x98 0x0 uart0 control 257 sfrpage 0xa7 all sfr page 122 smb0adm 0xf5 0x0 smbus slave address mask 242 smb0adr 0xf4 0x0 smbus slave address 242 smb0cf 0xc1 0x0 smbus configuration 237 smb0cn 0xc0 0x0 smbus control 239 smb0dat 0xc2 0x0 smbus data 243 sp 0x81 all stack pointer 113 spi0cfg 0xa1 0x0 spi0 configuration 268 spi0ckr 0xa2 0x0 spi0 clock rate control 270 spi0cn 0xf8 0x0 spi0 control 269 spi0dat 0xa3 0x0 spi0 data 270 spi1cfg 0x84 0x0 spi1 configuration 268 spi1ckr 0x85 0x0 spi1 clock rate control 270 spi1cn 0xb0 0x0 spi1 control 269 spi1dat 0x86 0x0 spi1 data 270 tcon 0x88 0x0 timer/counter control 280 th0 0x8c 0x0 timer/counter 0 high 283 th1 0x8d 0x0 timer/counter 1 high 283 table 11.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. sfrs highlighted in blue are only available on ?f912 and ?f902 devices. register address sfr page description page
c8051f91x-c8051f90x rev. 1.3 126 tl0 0x8a 0x0 timer/counter 0 low 282 tl1 0x8b 0x0 timer/counter 1 low 282 tmod 0x89 0x0 timer/counter mode 281 tmr2cn 0xc8 0x0 timer/counter 2 control 287 tmr2h 0xcd 0x0 timer/counter 2 high 289 tmr2l 0xcc 0x0 timer/counter 2 low 289 tmr2rlh 0xcb 0x0 timer/counter 2 reload high 288 tmr2rll 0xca 0x0 timer/counter 2 reload low 288 tmr3cn 0x91 0x0 timer/counter 3 control 293 tmr3h 0x95 0x0 timer/counter 3 high 295 tmr3l 0x94 0x0 timer/counter 3 low 295 tmr3rlh 0x93 0x0 timer/counter 3 reload high 294 tmr3rll 0x92 0x0 timer/counter 3 reload low 294 toffh 0x86 0xf temperature offset high 90 toffl 0x85 0xf temperature offset low 90 vdm0cn 0xff 0x0 vdd monitor control 181 xbr0 0xe1 0x0 port i/o crossbar control 0 217 xbr1 0xe2 0x0 port i/o crossbar control 1 218 xbr2 0xe3 0x0 port i/o crossbar control 2 219 table 11.3. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. sfrs highlighted in blue are only available on ?f912 and ?f902 devices. register address sfr page description page
c8051f91x-c8051f90x 127 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 127 12. interrupt handler the c8051f91x-c8051f90x microcontroller family includes an extended interrupt system supporting multiple interrupt sources and two priority levels. the allocation of interrupt sources between on-chip peripherals and external input pins varies accordin g to the specific version of the device. refer to ta b l e 12.1, ?interrupt summary,? on page 129 for a detailed listing of all interrupt sources supported by the device. refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). each interrupt source has one or more associated interrupt-pending flag(s) located in an sfr or an in direct register. when a peripheral or external s ource meets a valid interrupt condition, the associated interrupt-pending flag is set to logic 1. if both global interrupts and the spe cific interrupt source is enabled, a cpu interrupt request is generated when the interrupt-pending flag is set. as soon as execution of the cu rr ent instruction is complete, the cpu generates an lcall to a predetermined address to begin execution of an interrup t service routine (isr). each isr must end with an reti instruction, which re turns program execution to the next instru ction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as no rmal. (the interrupt-pending flag is set to logic 1 r egardless of the interrupt's enable/disable state.) some interrupt-pending flags are automatically cleared by hardware when the cpu vectors to the isr. howeve r, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of th e next instruction. 12.1. enabling interrupt sources each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in the interrupt enable and extended interrupt enable sfrs. however, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are r ecognized. setting the ea bit to logic 0 disables all in terrupt sources regardless of the individual interrupt- enable settings. note that interrupts which occur wh en the ea bit is set to logic 0 will be held in a pending state, and will not be serviced until the ea bit is set back to logic 1. 12.2. mcu interrupt sources and vectors the cpu services interrupts by generating an lca ll to a predetermined address (the interrupt vector address) to begin execution of an interrupt service routine (isr). the interrupt vector addresses associated with each interrupt source are listed in ta b l e 12.1 on page 129 . software should ensure that the interrupt vector for each enabled interrupt source contains a valid interrupt service routine. software can simulate an interrupt by setting any interrupt-pending flag to logic 1. if interrupts are enabled for the flag, an interrupt request will be gene rated and the cpu will vector to the isr address associated with the interrupt-pending flag.
c8051f91x-c8051f90x 128 rev. 1.3 12.3. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low priority interrupt service routine can be preempted by a high priority interrupt. a high priority interrupt cannot be preempted. if a high priority interrupt preempts a low priority interrupt, the low priority interrupt will finish execution after the high pr iority interrupt completes. each in terrupt has an asso ciated interrupt priority bit in in the interrupt priority and extended in terrupt priority registers used to configure its priority level. low priority is the default. if two interrupts are recognized simultaneously, the interrup t with th e higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate. see ta b l e 12.1 on page 129 to determine the fixed priority order used to arbitrate between simultaneously recognized interrupts. 12.4. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 7 system clock cycles: 1 clock cycle to detect the interrupt, 1 clock cycle to execute a single instruction, and 5 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is executed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) oc curs when the cpu is performing an re ti instruction followed by a div as the next instruction. in this case, the response time is 19 system clock cycles: 1 clock cycle to detect the int errupt, 5 clock cycles to execute the reti, 8 clock cycles to complete the div instruction and 5 clock cycle s to execute the lcall to the isr. if the cpu is executing an isr for an interrupt with equal or higher priority, the new interrupt will not be serviced until the current isr co mpletes, includi ng the reti and following instruction.
c8051f91x-c8051f90x rev. 1.3 129 table 12.1. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 to p none n/a n/a always en abled always hi ghest external interrupt 0 ( int0 ) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip.0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 ( int1 ) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip.2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip.4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) wcol (spi0cn.6) modf (spi0cn.5) rxovrn (spi0cn.4) y n espi0 (ie.6) pspi0 (ip.6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (ei e1.0) psmb0 (ei p1.0) smartclock alarm 0x0043 8 alrm (rtc0cn.2) 2 n n eartc0 (ei e1.1) partc0 (ei p1.1) adc0 window comparator 0x004b 9 ad0wint (adc0cn.3) y n ewadc0 (ei e1.2) pwadc0 (ei p1.2) adc0 end of conversion 0x0053 10 ad0int (adc0sta.5) y n eadc0 (ei e1.3) padc0 (ei p1.3) programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) y n epca0 (ei e1.4) ppca0 (ei p1.4) comparator0 0x0063 12 cp0fif (cpt0cn.4) cp0ri f (cpt0cn.5) n n ecp0 (ei e1.5) pcp0 (ei p1.5) comparator1 0x006b 13 cp1fif (cpt1cn.4) cp1rif (cpt1cn.5) n n ecp1 (ei e1.6) pcp1 (ei p1.6) timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) n n et3 (eie1.7) pt3 (ei p1.7) supply monitor early wa rning 0x007b 15 vddok (vdm0cn.5) 1 vbatok (vdm0cn.4) 1, 3 ewarn (eie2.0) pwarn (ei p2.0) port match 0x0083 16 none emat (ei e2.1) pmat (ei p2.1) smartclock oscillator fail 0x008b 17 oscfail (rtc0cn.5) 2 n n ertc0f (ei e2.2) pfrtc0f (ei p2.2) spi1 0x0093 18 spif (spi1cn.7) wcol (spi1cn.6) modf (spi1cn.5) rxovrn (spi1cn.4) n n espi1 (ei e2.3) pspi1 (ei p2.3) notes: 1. indicates a read-only interrupt pending flag. the interrupt enable may be used to prevent software from vectoring to the associated interrupt service routine. 2. indicates a register located in an indirect memory space. 3. blue text indicates a bit only available on ?f912 and ?f902 devices.
c8051f91x-c8051f90x 130 rev. 1.3 12.5. interrupt register descriptions the sfrs used to enable the interrupt sources and se t their priority level ar e described in the following register descriptions. refer to the data sheet sectio n associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).
c8051f91x-c8051f90x rev. 1.3 131 sfr page = all pages; sfr ad dress = 0xa8; bit-addressable sfr definition 12.1. ie: interrupt enable bit 7 6 5 4 3 2 1 0 name ea espi0 et2 es0 et1 ex1 et0 ex0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ea enable all interrupts. globally enables/disables all interrupts. it ov err ides individual interrupt mask settings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. 6 espi0 enable serial peripheral interface (spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. 5 et2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. 4 es0 enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. 3 et1 enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. 2 ex1 enable external interrupt 1. this bit sets the masking of ex ternal interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the int1 input. 1 et0 enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. 0 ex0 enable external interrupt 0. this bit sets the masking of ex ternal interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input.
c8051f91x-c8051f90x 132 rev. 1.3 sfr page = 0x0; sfr addres s = 0xb8; bit-addressable sfr definition 12.2. ip: interrupt priority bit 7 6 5 4 3 2 1 0 name pspi0 pt2 ps0 pt1 px1 pt0 px0 type r r/w r/w r/w r/w r/w r/w r/w reset 1 0 0 0 0 0 0 0 bit name function 7 unused unused. read = 1b, write = don't care. 6 pspi0 serial peripheral interface (spi 0) interrupt priori ty control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. 5 pt2 timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. 4 ps0 uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupt set to high priority level. 3 pt1 timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupt set to high priority level. 2 px1 external interrupt 1 priority control. this bit sets the priority of the external interrupt 1 interrupt. 0: external interrupt 1 se t to low priority level. 1: external interrupt 1 se t to high priority level. 1 pt0 timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. 0 px0 external interrupt 0 priority control. this bit sets the priority of the external interrupt 0 interrupt. 0: external interrupt 0 se t to low priority level. 1: external interrupt 0 se t to high priority level.
c8051f91x-c8051f90x rev. 1.3 133 sfr page = all pages; sfr address = 0xe6 sfr definition 12.3. eie1: extended interrupt enable 1 bit 7 6 5 4 3 2 1 0 name et3 ecp1 ecp0 epca0 eadc0 ewadc0 ertc0a esmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 et3 enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. 6 ecp1 enable comparator1 (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by the cp1rif or cp1fif flags. 5 ecp0 enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. 4 epca0 enable programmable counte r ar ray (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pc a0 interrupts. 1: enable interrupt requests generated by pca0. 3 eadc0 enable adc0 conversion complete interrupt. this bit sets the masking of the adc0 conversion complete interrupt. 0: disable adc0 conversi on complete interrupt. 1: enable interrupt requests generated by the ad0int flag. 2 ewadc0 enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comp arison interrupt. 1: enable interrupt requests generated by adc0 wind ow compare flag (ad0wint). 1 ertc0a enable smartclock alarm interrupts. this bit sets the masking of the smartclock alarm interrupt. 0: disable smartclo ck ala rm interrupts. 1: enable interrupt requests generated by a smartclock alarm. 0 esmb0 enable smbus (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0.
c8051f91x-c8051f90x 134 rev. 1.3 sfr page = all pages; sfr address = 0xf6 sfr definition 12.4. eip1: extended interrupt priority 1 bit 7 6 5 4 3 2 1 0 name pt3 pcp1 pcp0 ppca0 padc0 pwadc0 prtc0a psmb0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 pt3 timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts set to low priority level. 1: timer 3 interrupts set to high priority level. 6 pcp1 comparator1 (cp1) interru pt priority control. this bit sets the priority of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. 5 pcp0 comparator0 (cp0) interru pt priority control. this bit sets the priority of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. 4 ppca0 programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. 3 padc0 adc0 conversion complete interrupt priority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt s et to low priority level. 1: adc0 conversion complete interrupt set to high priority level. 2 pwadc0 adc0 window comparator interrupt priority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt se t to low priority level. 1: adc0 window interrupt set to high priority level. 1 prtc0a smartclock alarm interr upt priority control. this bit sets the priority of the smartclock alarm interrupt. 0: smartclock alarm interrup t s et to low priority level. 1: smartclock alarm interrupt s et to high priority level. 0 psmb0 smbus (smb0) interrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level.
c8051f91x-c8051f90x rev. 1.3 135 sfr page = all pages;sfr address = 0xe7 sfr definition 12.5. eie2: extended interrupt enable 2 bit 7 6 5 4 3 2 1 0 name espi1 ertc0f emat ewarn type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:4 unused unused. read = 0000b. write = don?t care. 3 espi1 enable serial peripheral in t erface (spi1) interrupt. this bit sets the masking of the spi1 interrupts. 0: disable all spi1 interrupts. 1: enable interrupt requests generated by spi1. 2 ertc0f enable smartclock oscillator fail interrupt. this bit sets the masking of the smartclock alarm interrupt. 0: disable smartclock alarm interrupt s. 1: enable interrupt requests generated by smartclock alarm. 1 emat enable port match interrupts. this bit sets the masking of the port match event interrupt. 0: disable all port match interrupts. 1: enable interrupt requests generated by a port match. 0 ewarn enable supply monitor early warning interrupt. this bit sets the masking of the supply monitor early warning interrupt. 0: disable the supply monitor early warning interrupt. 1: enable interrupt requests generated by the supply monitor(s). ?f912 and ?f902 d evices can provide an early warning for both vbat and the vdd/dc+ supply. all other devices only provide an early warning for the vdd/dc+ supply.
c8051f91x-c8051f90x 136 rev. 1.3 sfr page = all pages; sfr address = 0xf7 sfr definition 12.6. eip2: extended interrupt priority 2 bit 7 6 5 4 3 2 1 0 name pspi1 prtc0f pmat pwarn type rrrrr/wr/wr/wr/w reset 0 0 0 0 0 0 0 0 bit name function 7:4 unused unused. read = 0000b. write = don?t care. 3 pspi1 serial peripheral interface (spi 1) interrupt pr iority control. this bit sets the priority of the spi1 interrupt. 0: sp1 interrupt set to low priority level. 1: spi1 interrupt set to high priority level. 2 prtc0f smartclock oscillator fail in terrupt priority contr ol. this bit sets the priority of the smartclock alarm interrupt. 0: smartclock alarm interrupt set to low priority level. 1: smartclock alarm interrupt set to high priority level. 1 pmat port match interrupt priority control. this bit sets the priority of the port match event interrupt. 0: port match interrupt se t to low priority level. 1: port match interrupt se t to high priority level. 0 pwarn supply monitor early warning interrupt priori ty control. this bit sets the priority of the vdd/dc+ supply monitor early warning interrupt. 0: supply monitor early warning in terrupt set to low priority level. 1: supply monitor early warning inte rrupt set to high priority level.
c8051f91x-c8051f90x rev. 1.3 137 12.6. external interrupts int0 and int1 the int0 and int1 external interrupt sources are configurable as active high or low, edge or level sensitive. the in0pl ( int0 polarity) and in1pl ( int1 polarity) bits in the it01cf register select active high or active low; the it0 and it1 bits in tcon ( section ?25.1. timer 0 and timer 1? on page 276 ) select level or edge sensitive. the table be low lis ts the possible configurations. int0 and int1 are assigned to port pins as defined in the it01cf register (see sfr definition 12.7 ). note that int0 and int0 port pin assignments are independent of any crossbar assignments. int0 and int1 will monitor their assigned port pins wit hout disturbing the peripheral that was assigned the port pin via the crossbar. to assign a port pin only to int0 and/or int1 , configure the crossbar to skip the selected pin(s). this is accomplished by setting the associated bit in register xbr0 (see section ?21.3. priority crossbar decoder? on page 214 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interrupt-pending flags for the int0 and int1 external interrupts, respectively. if an int0 or int1 external interrupt is configured as edge-sensitive, the corresponding interrupt-pending flag is automatically cleared by the hardware when the cpu vectors to the isr. when configured as level sensitiv e, the interrupt-pending flag remains logic 1 while the input is active as defined by the corresponding pola rity bit (in0pl or in1pl); the flag remains logic 0 while the input is inactive. the external interrupt source must hold the i nput active until the interrupt request is recognized. it must then deactivate the interrup t request before execution of the isr completes or another interrupt request will be generated. it0 in0pl int0 interrupt it1 in1pl int1 interrupt 10 active low, edge sensitive 10 active low, edge sensitive 11 active high, edge sensitive 11 active high, edge sensitive 00 active low, level sensitive 00 active low, level sensitive 01 active high, level sensitive 01 active high, level sensitive
c8051f91x-c8051f90x 138 rev. 1.3 sfr page = 0x0; sfr address = 0xe4 sfr definition 12.7. it01cf: int0 / int1 configuration bit 7 6 5 4 3 2 1 0 name in1pl in1sl[2:0] in0pl in0sl[2:0] type r/w r/w r/w r/w reset 0 0 0 0 0 0 0 1 bit name function 7 in1pl int1 polarity. 0: int1 input is active low. 1: int1 input is active high. 6:4 in1sl[2:0] int1 port pin se lection bits. these bits select which port pin is assigned to int1 . note that this pin assignment is independent of the crossbar; int1 will monitor the assigned port pin without disturb - ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7 3 in0pl int0 polarity. 0: int0 input is active low. 1: int0 input is active high. 2:0 in0sl[2:0] int0 port pin se lection bits. these bits select which port pin is assigned to int0 . note that this pin assignment is independent of the crossbar; int0 will monitor the assigned port pin without disturb - ing the peripheral that has been assigned t he port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is configured to skip the selected pin. 000: select p0.0 001: select p0.1 010: select p0.2 011: select p0.3 100: select p0.4 101: select p0.5 110: select p0.6 111: select p0.7
c8051f91x-c8051f90x rev. 1.3 139 13. flash memory on-chip, re-programmable flash memory is included fo r program code and non-volatile data storage. the flash memory can be programmed in-system through the c2 interface or by software using the movx write instruction. once cleared to logic 0, a flash bit must be erased to set it back to logic 1. flash bytes wou ld typically be erased (set to 0xff) before be ing reprogrammed. the write and erase operations are automatically timed by hard ware for proper execution; data polling to determine the end of th e write/erase operations is not required. code execution is sta lled during flash write/erase operations. refer to ta b l e 4.6 for complete flash memory electrical characteristics. 13.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon laboratories or a th ird party vendor. this is the only means for programming a non-initialized device. for details on the c2 commands to program flash memory, see section ?27. c2 interface? on page 316 . the flash memory can be programmed by software using the movx write instruction with the address and data byte to be programmed provided as normal operands. before programming flash memory using movx, flash programming operations must be enabled by: (1) setting the pswe program store write enable bit (psctl.0) to logic 1 (this directs the movx writes to target flash memory); and (2) writing the flash key codes in sequence to the flash lock register (flkey). the pswe bit remains set until cleared by software. for detailed guidelines on programming flash from firmware, please see section ?13.5. flash write and erase guidelines? on page 143 . to ensure the integrity of the flash contents, the on - chip vdd monitor must be enabled and enabled as a reset source in any system that includes code that writes and/or erases flash memory from software. furthermore, there should be no delay between enabling the v dd monitor and enabling the v dd monitor as a reset source. any attempt to write or erase flash memory while the v dd monitor is disabled, or not enabled as a reset source, will ca use a flash error device reset. 13.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. the flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, be fore flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and eras es will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be performed. the flkey register is detailed in sfr definition 13.2 .
c8051f91x-c8051f90x 140 rev. 1.3 13.1.2. flash erase procedure the flash memory is organized in 512-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an entire flash page, perform the following steps: 1. save current interrupt state and disable interrupts. 2. set the psee bit (register psctl). 3. set the pswe bit (register psctl). 4. write the first key code to flkey: 0xa5. 5. write the second key code to flkey: 0xf1. 6. using the movx instruction, wr ite a dat a byte to any location within the page to be erased. 7. clear the pswe and psee bits. 8. restore previous interrupt state. steps 4?6 must be repeated for each 512-byte page to be erased. notes: 1. to maintain code compatibility with the ?f93x-?f92x product family, the erase pr ocedure should be performed on two consecutive 512-byte sections of memory at a ti me. this allows the same so ftware to run on devices with 1024-byte or 512-byte flash pages. using this te chnique, devices with 1024-byte flash pages will have each flash page erased twice. 2. flash security settings may prevent erasure of some flash pages, such as the reserved area and the page containing the lock bytes. for a summary of flash security settings and restrictions affecting flash erase operations, please see section ?13.3. security options? on page 141 . 3. 8-bit movx instructions cannot be used to erase or write to flash memory at addresses higher than 0x00ff. 13.1.3. flash write procedure a write to flash memory can clear bits to logic 0 but cannot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed should be erased before a new value is written. the recommended procedure for writing a si ngle byte in flas h is as follows: 1. save current interrupt state and disable interrupts. 2. ensure that the flash byte has been erased (has a value of 0xff). 3. set the pswe bit (register psctl). 4. clear the psee bit (register psctl). 5. write the first key code to flkey: 0xa5. 6. write the second key code to flkey: 0xf1. 7. using the movx instruction, write a single data byte to the desired location within the 1024- byte sector. 8. clear the pswe bit. 9. restore previous interrupt state. steps 5?7 must be repeated for each byte to be written. notes: 1. flash security settings may prevent writes to some areas of flash, such as the reserved area. for a summary of flash security settings and restrictions affecting flash write operations, please see section ?13.3. security options? on page 141 . 2. 8-bit movx instructions cannot be used to erase or write to flash memory at addresses higher than 0x00ff. 13.2. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read using th e movc instruction. movx read instructions always target xram. an additional 512-byte scratchpad is available for no n- volatile data storage. it is accessible at addresses 0x0000 to 0x01ff when sfle is set to 1. the scratchpad area cannot be used for code execution.
c8051f91x-c8051f90x rev. 1.3 141 13.3. security options the cip-51 provides security options to protect th e flash memory from inad vertent modification by software as well as to prevent the viewing of prop rietary program code and constants. the program store write enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to 1 before software can modify the flash me mory; both pswe and psee must be set to 1 before software can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of fl ash user space offers protection of the flash program memory from access (reads, writes, or erases) by unpr otected code or the c2 inte rface. the flash security mechanism allows the user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x 01ff), where n is the 1s complement number repres ented by the security lock byte. note that the page containing the flash security lock byte is unlocked when no other flash pages are locked (all bits of the lock byte are 1) and locked when any other flash pages are locked (any bit of the lock byte is 0). figure 13.1. flash program memory map (16 kb and 8 kb devices) the level of flash security depends on the flash ac cess method. the three flash access methods that can be restricted are reads, writes, an d erases from the c2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. ta b l e 13.1 summarizes the flash security features of the c8051f91x-c8051f90x devices. security lock byte: 1111 1011b o nes complement: 0000 0100b flash pages locked: 5 (first four flash pages + lock byte page) addresses locked: 0x0000 to 0x07ff (first four flash pages) and 0x3a00 to 0x3bff (lock byte page) lock byte page access limit set according to the flash security lock byte 0x0000 0x1fff lock byte 0x1ffe 0x2000 flash memory organized in 512-byte pages 0x1e00 unlocked flash pages locked when any other flash pages are locked lock byte page 0x0000 0x3bff lock byte reserved 0x3bfe 0x3c00 0x3a00 unlocked flash pages 16kb flash device (sfle = 0) 8kb flash device (sfle = 0) 0x0000 scratchpad area (data only) 0x01ff 16/8 kb flash device (sfle = 1) 0xffff reserved 0xffff
c8051f91x-c8051f90x 142 rev. 1.3 table 13.1. flash security summary action c2 debug interface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages ( except page with lock byte) permitted permitted permitted read, write or erase locked pages ( except page with lock byte) not permitted fedr permitted read or write page containing lock byte ( if no pages are locked) permitted permitted permitted read or write page containing lock byte (if an y page is locked) not permitted fedr permitted read contents of lock byte (if no pages are locked) permitted permitted permitted read contents of lock byte (if any page is locked) not permitted fedr permitted erase page containing lock byte ( if no pages are locked) permitted fedr fedr erase page containing lock byte - unlock all pages (if an y page is locked) only by c2de fedr fedr lock additional pages (cha nge 1s to 0s in the lock byte) not permitted fedr fedr unlock individual pages (change 0s to 1s in the lock byte) not permitted fedr fedr read, write or erase reserved area not permitted fedr fedr c2de?c2 device erase (erases all flash pages including the page containing the lock byte) fedr?not permitted; causes flash error device reset (ferror bit in rs tsrc is 1 after reset) ? all prohibited operations that are performed via th e c2 inter face are ignored (do not cause device reset). ? locking any flash page also locks the page containing the lock byte. ? once written to, the lock byte cannot be modifi e d except by performing a c2 device erase. ? if user code writes to the lock byte, the lock doe s not take effect until the next device reset. ? the scratchpad is locked when all other flash pages are locked. ? the scratchpad is erased when a flash device erase command is performed.
c8051f91x-c8051f90x rev. 1.3 143 13.4. determining the device part number at run time in many applications, user software may need to determine the mcu part number at run time in order to determine the hardware capabilities. the part number can be determined by reading the value of the flash byte at address 0x3ffe. the value of the flash byte at address 0x3ffe can be decoded as follows: 0xd0?c8051f901 0xd1?c8051f902 0xd2?c8051f911 0xd3?c8051f912 13.5. flash write and erase guidelines any system which contains routines which write or er ase flash memory from software involves some risk that the write or erase ro utines will execute unin tentionally if the cpu is op erating outside its specified operating range of vdd, system clock frequency, or temperature. this accid ental execution of flash modifying code can result in alteration of flash memo ry contents causing a system failure that is only recoverable by re-flashing the code in the device. to help prevent the accidental modi fica tion of flash by firmware, the vdd monitor must be enabled and enabled as a reset source on c8051f91x-c8051f90x devices for the flash to be successfully modified. if either the vdd monitor or the vdd monitor reset source is not enabled, a flash error device reset will be generated when the firmwar e attempts to modify the flash. the following guidelines are recomme nded f or any system that contains routines which write or erase flash from code. 13.5.1. vdd maintenance and the vdd monitor 1. if the system power supply is subject to volta ge or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the maximum vb a t ramp time specification of 3 ms is met. this specifica - tion is outlined in ta b l e 4.4 on page 59 . on silicon revision c and later revisions, if the system cannot meet this rise time specification, t hen add an external vdd brownout circuit to the rst pin of the device that holds the device in reset until vdd reaches the minimum device operat - ing voltage and re-asserts rst if vdd drops below the minimum device operating voltage. 3. keep the on-chip vdd monitor enabled and en able the vdd monitor as a reset source as early in code as possible. this should be the fi rst set of instructions executed after the reset vector. for c-based systems, this will involve mo difying the startup code added by the c com - piler. see your compiler documentation for more details. make certain that there are no delays in software between enabling the vdd monitor and enabling the vdd monitor as a reset source. code examples showing this can be found in ?an201: writing to flash from firm - ware," available from the silicon laboratories website. note: on c8051f91x-c8051f90x devices, both the vdd monitor and the vdd monitor reset source must be enabled to write or erase flash without generating a flash error device reset. note: on c8051f91x-c8051f90x devices, both the vdd monitor and the vdd monitor reset source are enabled by hardware after a power-on reset. 4. as an added precaution, explicitly enable the vdd monitor and enable the vdd monitor as a r eset source inside the functions that write and erase flash memory. the vdd monitor enable instructions should be placed just after the inst ruction to set pswe to a 1, but before the flash write or erase operation instruction.
c8051f91x-c8051f90x 144 rev. 1.3 5. make certain that all writes to the rstsrc (r eset sources) register use direct assignment operators and explicitly do not use the bit- wise operators (such as and or or). for exam - ple, "rstsrc = 0x02" is correct, but "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to the rstsrc regi st er explicitly set the porsf bit to a 1. areas to check are initialization code which enables ot her reset sources, such as the missing clock detector or comparator, for example, and instru ctions which force a so ftware reset. a global search on "rstsrc" can quickly verify this. 13.5.2. pswe maintenance 7. reduce the number of places in code where the pswe bit (b0 in psctl) is set to a 1. there should be exactly one routine in code that se ts pswe to a 1 to write flash bytes and one rou - tine in code that sets both pswe and psee both to a 1 to erase flash pages. 8. minimize the number of variable accesses while pswe is set to a 1. handle pointer address u pdates and loop maintenance outside the "p swe = 1;... pswe = 0;" area. code examples showing this can be found in an201, "writing to flash from firmware" , available from the sili - con laboratories web site. 9. disable interrupts prior to setting pswe to a 1 and leave them disabled until after pswe has been reset to 0. any interrupts posted during the flash write or erase operation will be ser - viced in priority order after the flash operation has been completed and interrupts have been r e-enabled by software. 10. make certain that the flash write and erase pointer variables are not located in xram. see you r compiler documentation for instructions regard ing how to explicitly lo cate variables in dif - ferent memory areas. 11. add address bounds checking to the routines th at write or erase flash memory to ensure that a routine called with an illegal address does not re sult in modification of the flash. 13.5.3. system clock 12. if operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noi sy environment, use the internal oscillator or use an external cmos clock. 13. if operating from the ex ternal osc illator, switch to the internal oscillator during flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after th e flash operation has completed. additional flash recommendations and example code ca n be found in ?an201: writing to flash from firmware", available from the silicon laboratories web site.
c8051f91x-c8051f90x rev. 1.3 145 13.6. minimizing flash read current the flash memory in the c8051f91x-c8051f90x devices is responsible for a substantial portion of the total digital supply current when the device is execut ing code. below are suggestions to minimize flash read current. 1. use idle, suspend, or sleep mo des while waiting for an interrup t, rather than polling the inter - rupt flag. idle mode is particularly well-suited for u se in implementing short pauses, since the wake-up time is no more than three system clock cycles. se e the power management chapter for details on the various low-power operating modes. 2. c8051f91x-c8051f90x devices have a one-shot timer that saves power when operating at system clock frequencies of 14 mhz or less. the one-shot ti m er generates a minimum-dura - tion enable signal for the flash sense amps on eac h clock cycle in which the flash memory is accessed. this allows the flash to remain in a low power state for the remainder of the long clock cycle. at clock frequencies above 14 mhz, the system clock cycle be comes short enough that the one-shot timer no longer provides a power benefi t. disabling the one-shot timer at higher fre - quencies reduces power consumption. the one-s hot is ena bled by default, and it can be dis - abled (bypassed) by setting the bypass bit (flscl.6) to logic 1. to re-enable the one-shot, clear the byp ass bit to logic 0. 3. flash read current depends on the number of address lines that toggle between sequential fla sh read operations. in most cases, the differen ce in power is relative ly small (on the order of 5%). the flash memory is organized in rows of 64 bytes. a substantial current increase can be detected when the read address jumps from one row in the flash memory to another. con - sider a 3-cycle loop (e.g., sjmp $, or while(1 );) w hich straddles a fl ash row bound ary. the flash address jumps from one row to another on two of every three clock cycles. this can result in a current increase of up 30% when compared to the same 3-cycle loop contained entirely within a single row. to minimize the power consumption of sm all loops, it is best to locate them within a single row, if possible. to check if a loop is contained withi n a flash row, divide the starting address of the first instruction in the loop by 64. if the remainder (result of modulo operation) plus the length of the loop is less than 63, then the loop fits inside a single flash row. otherwise, the loop will be straddling two adjacent flash rows. if a loop executes in 20 or more clock cycles, then the transitions from one row to another will occur on relatively few clock cycles, and any resulting increase in operating cu rrent will be negligible. to write software that is compatible with a ll devices in the ?f93x- ?f92x and ?f91x-?f90x product families, the flash row size should be considered 64 bytes.
c8051f91x-c8051f90x 146 rev. 1.3 sfr page =0x0; sfr address = 0x8f sfr definition 13.1. psctl: program store r/w control bit 7 6 5 4 3 2 1 0 name sfle psee pswe type r r r r r r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:3 unused unused. read = 00000b, write = don?t care. 2 sfle scratchpad flash memory access enable. when this bit is set, flash movc reads and movx writes from user software are d irected to the scratchpad flash sector. flash accesses outside the address range 0x0000-0x01ff should not be attempted and may yield undefined results when sfle is set to 1. 0: flash access from user software dir ected to the program/data flash sector. 1: flash access from user software directed to the scratchpad sector. 1 psee program store erase enable. setting this bit (in combination with pswe) allows an entire page of flash program mem ory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx instruction will erase the entire page that contains the location addressed by the movx instruction. the value of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. 0 pswe program store write enable. setting this bit allows writing a byte of data to the flash program memory using the movx wr ite instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabl ed; th e movx write instruction targets flash memory.
c8051f91x-c8051f90x rev. 1.3 147 sfr page = 0x0; sfr address = 0xb6 sfr definition 13.2. flkey: flash lock and key bit 7 6 5 4 3 2 1 0 name flkey[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 flkey[7:0] flash lock and key register. write: this register provides a lock and key func tion for flash erasures and writes. flash writes and erases are enabled by writing 0xa5 follo wed by 0xf1 to the flkey regis - ter. flash writes and erases are automatically disable d after the next write or erase is complete. if any writes to flkey are performed incorrectly, or if a flash write or erase operation is attempted while these operations are disa bled, the flash will be perma - nently locked from writes or erasures unt il th e next device reset. if an application never writes to flash, it can intentionally lock the flash by writing a non-0xa5 value to flkey from software. read: when read, bits 1?0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases disabled until the next reset.
c8051f91x-c8051f90x 148 rev. 1.3 sfr page = 0x0; sfr address = 0xb6 sfr page = 0x0; sfr address = 0xe5 sfr definition 13.3. flscl: flash scale bit 7 6 5 4 3 2 1 0 name bypass type r r/w r r r r r r reset 0 0 0 0 0 0 0 0 bit name function 7 reserved reserved. always write to 0. 6 bypass flash read timing one-shot bypass. 0: the one-shot determines t he flash read time. this setting should be used for oper - ating frequencies less than 10 mhz. 1: the system clock determines the flash rea d time. this setting should be used for frequencies greater than 10 mhz. 5:0 reserved reserved. always write to 000000. note: operations which clear the bypass bit do not need to be immediately follow ed by a benign 3-byte instruction on c8051f912/11/02/01 devices. for code compatibility with c8051f930/31/20/21 devices, a benign 3-byte instruction whose third byte is a don't care should follow the clear operation. see the c8051f93x-c8051f92x data sheet for more details. sfr definition 13.4. flwr: flash write only bit 7 6 5 4 3 2 1 0 name flwr[7:0] type w reset 0 0 0 0 0 0 0 0 bit name function 7:0 flwr[7:0] flash write only. all writes to this register have no effect on system operation.
c8051f91x-c8051f90x rev. 1.3 149 14. power management c8051f91x-c8051f90x devices support 5 power modes: normal, idle, stop, suspend, and sleep. the power management unit (pmu0) allows the device to enter and wake-up from the available power modes. a brief description of each power mode is provided in ta b l e 14.1 . detailed descriptions of each mode can be found in the following sections. in battery powered systems, the system sh ould spend as much time as possible in sleep mode in order to preserve battery life. when a task with a fixed number of clock cycles needs to be performed, the device should switch to normal mode, finish the task as quickly as possible, and return to sleep mode. idle mode and suspend modes provide a very fa st wake-up time; however, the power savings in these modes will not be as much as in sleep mode. stop mode is included for legacy reas ons; the system will be more power efficient and easier to wake up when idle, suspend, or sleep mode are used. although switching power modes is an integral part of power management, enabling/disabling individual peri pherals as needed will help lower power consumption in all power modes. each analog peripheral can be disabled when not in use or placed in a low power mode. digital peripherals such as timers or serial busses draw little power whenever they are not in us e. digital peripherals draw no power in sleep mode. table 14.1. power modes power mode description wake-up so urces power savings normal device fully functional n/a excellent mips/mw idle all peripherals fully functional. very easy to wake up. any interrupt. good no code execution stop legacy 8051 low power mode. a reset is required to wake up. any reset. good no code execution precision oscillator disabled suspend similar to stop mode, but very fast wa ke-up time and code resumes execution at the next instruction. smartclock, port match, comp arator0, rst pin. very good no code execution all internal oscillators disabled system clock gated sleep ultra low power and flexible wake-up sources . code resumes execution at the next instruction. comparator0 only functional in two-cell mode. smartclock, port match, comp arator0, rst pin. excellent power supply gated all oscillators except smart - clock disabled
c8051f91x-c8051f90x 150 rev. 1.3 14.1. normal mode the mcu is fully functional in normal mode. figure 14.1 shows the on-chip power distribution to various peripherals. there are three supply voltages powering various s ections of the chip: vbat, vdd/dc+, and the 1.8 v internal core supply. vreg0, pm u0 and the smartclock are always powered directly from the vbat pin. all analog peripherals are directly powered fr om the vdd/dc+ pin, which is an output in one-cell mode and an input in two-cell mode. all digital peripherals and the cip-51 core are powered from the 1.8 v internal core supply. the ram is also powe red from the core supply in normal mode. figure 14.1. c8051f91x-c8051f90x power distribution ram vreg0 pmu0 sleep active/idle/ stop/suspend vbat vdd/dc+ one-cell: 0.9 to 1.8 v two-cell: 1.8 to 3.6 v one-cell or two-cell: 1.8 to 3.6 v analog peripherals 10-bit 300 ksps adc temp sensor a m u x voltage comparators + - iref0 + - vref digital peripherals flash cip-51 core uart spi smbus timers gpio 1.8 v dc0 smartclock one-cell active/ idle/stop/suspend one-cell sleep 1.9 v typical note: vdd/dc+ must be > vbat one-cell: 0.9 to 3.6 v (f912/02 devices only)
c8051f91x-c8051f90x rev. 1.3 151 14.2. idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes executio n. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. note: to ensure the mcu enters a low power state upon entry into idle mode, the one-shot circuit should be enabled by clearing the bypass bit (flscl.6). idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction immedi ately following the one that se t the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset and thereby termi - nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event o f an inadvertent write to the pcon register. if this behavior is not desired, th e wdt may be disabled by software prior to entering th e idle mode if the wdt was initially config ured to allow this operation. this pro - vides the opportunity for additional power savings, allo win g the system to remain in the idle mode indefi - nitely, waiting for an external stimulus to wake up the system. refer to section ?18.6. pca watchdog timer reset? on page 182 for more information on the use and configuration of the wdt. 14.3. stop mode setting the stop mode select bit (pcon.1) causes th e cip-51 to enter stop mode as soon as the instruc - tion that sets the bit co mpletes execution. in stop mode the precision internal o scillator and cpu are stopped; the state of the low power oscillator and the exte rnal oscillator circuit is not affected. each analog peripheral (including the external oscillator circuit) may be shut do wn individually prior to entering stop mode. stop mode can only be terminated by an internal or external reset. on re set, the cip-51 performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout. stop mode is a legacy 8051 power mo de; it will not result in optimal power savings. sleep or suspend mode will provide more power savings if the mcu need s to be inactive for a long period of time. note: to ensure the mcu enters a low power state upon en try into stop mode, the on e-shot circuit should be enabled by clearing the bypass bit (flscl.6).
c8051f91x-c8051f90x 152 rev. 1.3 14.4. suspend mode setting the suspend mode select bit (pmu0cf.6) causes the system clock to be gated off and all internal oscillators disabled. the system cloc k source must be set to the low po wer internal oscillator or the preci - sion oscillator prior to entering su spend mode. all digital logic (timers, communica tion peripher als, inter - rupts, cpu, etc.) stops func tion ing until one of the enabled wake-up sources occurs. the following wake-up sources can be configured to wake the device from suspend mode: ? smartclock oscillator fail ? smartclock alarm ? port match event ? comparator0 rising edge note: upon wake-up from suspend mode, pmu0 requires tw o system clocks in order to update the pmu0cf wake- up flags. all flags will re ad back a value of '0' during the first two system clocks following a wake-up from suspend mode. in addition, a noise glitch on rst that is not long enough to reset the device will cause the device to exit suspend. in order for the mcu to respond to the pin reset event, software must not place the device back into suspend mode for a period of 15 s. the pmu0cf register may be checked to determine if the wake- up w as due to a falling edge on the /rst pin. if the wake-up source is not due to a falling edge on rst , there is no time restriction on how soon software may place the device back into suspend mode. a 4.7 kw pu llup resistor to vd d/dc+ is recommend for rst to prevent noise glitches from waking the device. 14.5. sleep mode setting the sleep mode select bit (pmu0cf.6) turns off the internal 1.8 v regulator (vreg0) and switches the power supply of all on-chip ram to the vbat pin (see figure 14.1 ). power to most digital logic on the chip is disconnected; only pmu0 and the smartclock remain powered. analog peripherals remain pow - ered in two-cell mode and lose their supply in one-cell mo de because the dc-dc converter is disabled. in two-cell mode, only the comparators remain functional when the device enters sleep mode. all other ana - log peripherals (adc0, iref0, external oscillator, etc.) should be disabl ed prior to ente ring sleep mode. the system clock source must be set to the low power internal oscillator or the pr ecision oscillator prior to entering sleep mode. note: when exiting sleep mode, 4 nop instructions should be located immediately after the write to pmu0cf that placed the device in sleep mode. note: if the average active time (between successive entries into sleep mode) is less than 1 ms, peripherals tha t may cause a wake-up from sleep mode (smartclock, port match, and comparator0) or are enabled or configured in a way which may cause the wake-up flag to be set should be selected as wake-up sources. if these peripherals are not selecte d as wake-up sources, then it is recommended to bypass the flash one-shot (flscl.6=1) before entering into sleep mode. gpio pins configured as digital outputs will retain thei r output state du ring sleep mode. in two-cell mode, they will maintain the same current dr ive capability in sleep mode as they have in normal mode. in one-cell mode, the vdd/dc+ supply will drop to the level of vbat, which will reduce the output high-voltage level and the source and sink current drive capability. gpio pins configured as digital inputs can be used d uring sleep mode as wakeup sources using the port match feature. in two-cell mode, they will maintain the same input leve l specs in sleep mode as they have in normal mode. in one-cell mode , the vdd supply will drop to the level of vbat, which will lower the switching threshold and increase the propagation delay. c8051f912 and c8051f902 devices support a wakeup req uest for external devices. upon exit from sleep mode, the wake-up request signal is driven high, allowing other devices in the system to wake up from their low power modes. an example of a system that ma y benefit from this function is one that uses a high- power dc-dc converter (>65 mw of output power). the dc-dc conver ter may be disabled when the system is asleep, and can be awoken by the wake-up request signal from the mcu. the wakeup request signal is high when the mcu is awake and low when the mcu is asleep.
c8051f91x-c8051f90x rev. 1.3 153 note: by default, the vdd/dc+ supply is connected to vbat upon entry into sleep mode (one-cell mode). if the vddslp bit (dc0cf.1) is set to logic 1, the vdd/dc + supply will float in sleep mode. this allows the decoupling capacitance on the vdd/dc+ supply to maintain the supply rail until the capacitors are discharged. for relatively short sleep intervals, this can result in substantial power savings because the decoupling capacitance is not continuously charged and discharged. ram and sfr register contents are preserved in sleep mode as long as the voltage on vbat does not fall below v por . the pc counter and all other volatile state information is preserved allowing the device to resume code execution upon waking up from slee p mode. the following wake-up sources can be config - ured to wake the devi ce fr om sleep mode: ? smartclock oscillator fail ? smartclock alarm ? port match event ? comparator0 rising edge. the comparator0 rising edge wakeup is only valid in two-cell mode. the comparator requires a supply volt age of at least 1.8 v to operate properly. on ?f912 and ?f902 devices, the vbat supply monitor can be dis abled to save power by writing 1 to the mondis (pmu0md.5) bit. when the vbat supply monitor is disabled, all reset sources will trigger a full po r and will re-enable the vbat supply monitor. in addition, any falling edge on rst (due to a pin reset or a noise glit ch) will cause the device to exit sleep mode. in order for the mcu to respond to the pin reset event, software must not place the device back into sleep mode for a period of 15 s. the pmu0cf register may be checke d to determine if the wake-up was due to a falling edge on the rst pin. if the wake-up source is not due to a falling edge on rst , there is no time restriction on how soon software may place the device back into sleep mode. a 4.7 k pullu p resistor to vdd/dc+ is recommend for rst to prevent noise glitches from waking the device. 14.6. configuring wakeup sources before placing the device in a low power mode, one or more wakeup sources should be enabled so that the device does not remain in the lo w power mode indefinitely. for idle mode, this includes enabling any interrupt. for stop mode, this includes enabling any reset source or relying on the rst pin to reset the device. wake-up sources for suspend and sleep modes are configured through the pmu0cf register. wake-up sou rces are enabled by writing 1 to the corresponding wake-up source enable bit. wake-up sources must be re-enabled each time the device is placed in susp end or sleep mode, in the same write that places the device in the low power mode. the reset pin is always enabled as a wa ke-up s ource. on the falling edge of rst , the device will be awaken from sleep mode. the device must remain awake for more than 15 s in order for the reset to take p lace.
c8051f91x-c8051f90x 154 rev. 1.3 14.7. determining the event that caused the last wakeup when waking from idle m ode, the cpu will vector to th e interrupt which caused it to wake up. when wak - ing from stop mode, the rstsrc register may be re ad to determine the cause of the last reset. upon exit from suspend or sleep mode, the wake-up fl ags in the pmu0cf r egister can be read to deter - mine the event which caused the devi ce to wake up. after waking up, the wake-up flags will continue to be updated if any of the wake-up events occur. wake-up flags are always updated, even if they are not enabled as wake-up sources. all wake-up flags enabled as wake-up sources in pmu0cf must be cleared before the device can enter suspend or sleep mode. after clearing the wake-up flags, each of the enabled wake-up events should be checked in the individual peripherals to ensure that a wake-up event did not occur while the wake-up flags were being cleared.
c8051f91x-c8051f90x rev. 1.3 155 sfr page = 0x0; sfr address = 0xb5 sfr definition 14.1. pmu0cf: power management unit configuration 1,2 bit 7 6 5 4 3 2 1 0 name sleep suspend clear rstwk rtcfwk rtcawk pmatwk cpt0wk type w w w r r/w r/w r/w r/w reset 0 0 0 varies varies varies varies varies bit name description write read 7 sleep sleep mode select writing 1 places the de vice in sleep mode. n/a 6 suspend suspend mode select writing 1 places the de vice in suspend mode. n/a 5 clear wake-up flag clear writing 1 clears all wake- up flags. n/a 4 rstwk reset pin wake-up flag n/a set to 1 if a falling edge ha s been detected on rst . 3 rtcfwk smartclock oscillator fa il wake-up source enable and flag 0: disable wake-up on smar tclock osc. fail. 1: enable wake-up on smar tclock osc. fail. set to 1 if the smart - clock oscillator has failed. 2 rtcawk smartclock alarm w ake-up source enable and flag 0: disable wake-up on smar tclock alarm. 1: enable wake-up on smar tclock alarm. set to 1 if a smartclock alar m has occurred. 1 pmatwk port match wake-up sour ce enable and flag 0: disable wake-up on port match event. 1: enable wake-up on port match event. set to 1 if a port match even t has occurred. 0 cpt0wk comparator0 wake-up sour ce enable and flag 0: disable wake-up on comp arator0 rising edge. 1: enable wake-up on comp arator0 rising edge. set to 1 if comparator0 r ising edge caused the last wake-up. notes: 1. read-modify-write operations (orl, anl, etc.) should not be used on this register. wake-up sources must be re-enabled each time the sleep or suspend bits are written to 1. 2. the low power internal oscillator cannot be disabled and the mcu cannot be placed in suspend or sleep mode if any wake-up flags are set to 1. software should clear all wake-up sources after each reset and after each wake-up from suspend or sleep modes. 3. pmu0 requires two system clocks to update the wake-up source flags after waking from suspend mode. the wake-up source flags will read ?0? during the first tw o system clocks following the wake from suspend mode.
c8051f91x-c8051f90x 156 rev. 1.3 sfr page = 0xf; sfr address = 0xb5 sfr definition 14.2. pmu0md: power management unit mode bit 7 6 5 4 3 2 1 0 name rtcoe wakeoe mondis type r/w r/w r/w r/w r/w r/w r/w r/w reset 00 000000 bit name function 7 rtcoe buffered smartclock output enable. enables the buffered smartclock oscillato r output on p0.2. only available on ?f912 and ?f902 devices. 0: buffered smartclock output is not enabled. 1: buffered smartclock output is enabled. 6 wakeoe wakeup request output enable. enables the sleep mode wake-up request signal on p0.3. only available on ?f912 a nd ?f902 devices. 0: wake-up request signal is not enabled. 1: wake-up request signal is enabled. 5 mondis vbat supply monitor disable. writing a 1 to this bit disables the vbat supply monitor. writing a 0 to this bit when the vba t supply monitor is disabled will tr igger a power-on reset. only available on ?f912 and ?f902 devices. 4:0 unused unused. read = 00000b. write = don?t care.
c8051f91x-c8051f90x rev. 1.3 157 sfr page = all pages; sfr address = 0x87 14.8. power management specifications see ta b l e 4.5 on page 60 for detailed power management specifications. sfr definition 14.3. pcon: power manageme nt control register bit 7 6 5 4 3 2 1 0 name gf[5:0] stop idle type r/w w w reset 00 000000 bit name description write read 7:2 gf[5:0] general purpose flags sets the logic value. returns the logic value. 1 stop stop mode select writing 1 places the de vice in stop mode. n/a 0 idle idle mode select writing 1 places the devic e in idle mode. n/a
c8051f91x-c8051f90x 158 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 158 15. cyclic redundancy check unit (crc0) c8051f91x-c8051f90x devices include a cyclic redund ancy check unit (crc0) that can perform a crc using a 16-bit or 32-bit polynomial. crc0 accepts a stream of 8-bit data written to the crc0in register. crc0 posts the 16-bit or 32-bit result to an internal register. the internal result register may be accessed indirectly using the crc0pnt bits a nd crc0dat register, as shown in figure 15.1 . crc0 also has a bit reverse register for quick data manipulation. figure 15.1. crc0 block diagram 15.1. crc algorithm the c8051f91x-c8051f90x crc unit generates a crc result equivalent to the following algorithm: 1. xor the input with the most-significant bits of t he current crc result. if this is the first iteration of the crc unit, the current crc re sult will be the set initial value (0x00000000 or 0xffffffff). 2a. if the msb of the crc result is set, shift the c rc result and xor the re sult with the selected polynomial. 2b. if the msb of the crc result is not set, shift the crc result. repeat steps 2a/2b for the number of input bits (8). the algorithm is also described in the following ex ample. the 16-bit c8051f91x-c8051f90x crc algorithm can be described by the following code: unsigned short updatecrc (unsigned short crc_acc, unsigned char crc_input) { unsigned char i; // loop counter #define poly 0x1021 // create the crc "dividend" for polynomial arithmetic (binary arithmetic crc0in 8 crc0dat crc0cn crc0sel crc0init crc0val crc0pnt1 crc0pnt0 crc engine 4 to 1 mux result 32 8 8 8 8 8 crc0auto crc0cnt automatic crc controller flash memory 8 crc0flip write crc0flip read
c8051f91x-c8051f90x 159 rev. 1.3 // with no carries) crc_acc = crc_acc ^ (crc_input << 8); // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x8000) == 0x8000) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc << 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc << 1; } } // return the final remainder (crc value) return crc_acc; } ta b l e 15.1 lists several input values and the associated outputs using the 16-bit c8051f91x-c8051f90x crc algorithm: table 15.1. example 16-bit crc outputs input output 0x63 0xbd35 0x8c 0xb1f4 0x7d 0x4eca 0xaa, 0xbb, 0xcc 0x6cf6 0x00, 0x00, 0xaa, 0xbb, 0xcc 0xb166
c8051f91x-c8051f90x rev. 1.3 160 15.2. 32-bit crc algorithm the c8051f91x-c8051f90x crc unit calculates the 32-bit crc using a poly of 0x04c11db7. the crc- 32 algorithm is "reflected", meaning that all of the inpu t bytes and the final 32-bit output are bit-reversed in the processing engine. the following is a description of a simplified crc algorithm that produces results identical to the hardware: step 1. xor the least-significant by te of the current crc result with the input byte. if this is the first iteration of the crc un it, the current crc result w ill be the set initial value (0x00000000 or 0xffffffff). step 2. right-shift the crc result. step 3. if the lsb of the crc result is set, xor the crc result with the reflected polynomial (0xedb88320). step 4. repeat at step 2 for the number of input bits (8). for example, the 32-bit 'f91x/90x crc algo rithm can be described by the following code: unsigned long updatecrc (unsigned long crc_acc, unsigned char crc_input) { unsigned char i; // loop counter #define poly 0xedb88320 // bit-reversed version of the poly 0x04c11db7 // create the crc "dividend" for polynomial arithmetic (binary arithmetic // with no carries) crc_acc = crc_acc ^ crc_input; // "divide" the poly into the dividend using crc xor subtraction // crc_acc holds the "remainder" of each divide // // only complete this division for 8 bits since input is 1 byte for (i = 0; i < 8; i++) { // check if the msb is set (if msb is 1, then the poly can "divide" // into the "dividend") if ((crc_acc & 0x00000001) == 0x00000001) { // if so, shift the crc value, and xor "subtract" the poly crc_acc = crc_acc >> 1; crc_acc ^= poly; } else { // if not, just shift the crc value crc_acc = crc_acc >> 1; } } // return the final remainder (crc value) return crc_acc; } the following table lists several input values and the associated outputs using the 32-bit 'f91x/90x crc algorithm (an initial value of 0xffffffff is used):
c8051f91x-c8051f90x 161 rev. 1.3 15.3. preparing for a crc calculation to prepare crc0 for a crc calculati on, software should select the desired polynomial and set the initial value of the result. two polynomials are available: 0x1021 (16-bit) and 0x04c11db7 ( 32-bit). the crc0 result may be initialized to one of two values: 0x00000000 or 0xffffffff. the following steps can be used to initialize crc0. 1. select a polynomial (set crc0sel to 0 for 32-bit or 1 for 16-bit). 2. select the initial result value (set crc0val to 0 for 0x 00000000 or 1 for 0xffffffff). 3. set the result to its initia l v alue (write 1 to crc0init). 15.4. performing a crc calculation once crc0 is initialized, the input data stream is sequenti ally written to crc0in, one byte at a time. the crc0 result is automatically updated after each byte is written. the crc engine may also be configured to automatically perform a crc on one or more flas h sectors. the following steps can be used to automatically perform a crc on flash memory. 1. prepare crc0 for a crc calculation as shown above. 2. write the index of the starting page to crc0auto. 3. set the autoen bit in crc0auto. 4. write the number of flash sectors to perform in the crc ca lculation to crc0cnt. note: each flash sector is 512 bytes on ?f91x and ?f90x devices. 5. write any value to crc0cn (or or its contents with 0x00) to initiat e th e crc calculation. the cpu will not execute code any additional code until the crc operation completes. see the note in sfr definition 15.1. crc0cn: crc0 control for more information on how to properly initiate a crc calculation. 6. clear the autoen bit in crc0auto. 7. read the crc result using the procedure below. 15.5. accessing the crc0 result the internal crc0 result is 32-b its (crc0sel = 0b) or 16-bits (crc0sel = 1b). the crc0pnt bits select the byte that is targeted by read and write operations on crc0dat and increment after each read or write. the calculation result will remain in the internal cr0 result register until it is set, overwritten, or additional data is written to crc0in. table 15.2. example 32-bit crc outputs input output 0x63 0xf9462090 0xaa, 0xbb, 0xcc 0x41b207b3 0x00, 0x00, 0xaa, 0xbb, 0xcc 0x78d129bc
c8051f91x-c8051f90x rev. 1.3 162 sfr page = 0xf; sfr address = 0x92 sfr definition 15.1. crc0cn: crc0 control bit 7 6 5 4 3 2 1 0 name crc0sel crc0init crc0val crc0pnt[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:5 unused unused. read = 000b; write = don?t care. 4 crc0sel crc0 polynomial select bit. this bit selects the crc0 polynomial and result length (32-bit or 16-bit). 0: crc0 uses the 32-bit polynomial 0x 04c 11db7 for calcul ating the crc result. 1: crc0 uses the 16-bit polynomial 0x10 21 for calculating the crc result. 3 crc0init crc0 result init ializ ation bit. writing a 1 to this bit initializes th e entire cr c result based on crc0val. 2 crc0val crc0 set value initialization bit. this bit selects the set value of the crc result. 0: crc result is set to 0x00000000 on write of 1 to crc0init. 1: crc result is set to 0xfff fffff on write of 1 to crc0init. 1:0 crc0pnt[1:0] crc0 result pointer. specifies the byte of the crc result to b e read/written on the next access to crc0dat. the value of these bits will auto -increment upon ea ch read or write. for crc0sel = 0: 00: crc0dat accesses bits 7?0 of the 32-bit crc result. 01: crc0dat accesses bits 15?8 of the 32-bit crc result. 10: crc0dat accesses bits 23?16 of the 32-bit crc result. 11: crc0dat accesses bits 31?24 of the 32-bit crc result. for crc0sel = 1: 00: crc0dat accesses bits 7?0 of the 16-bit crc result. 01: crc0dat accesses bits 15?8 of the 16-bit crc result. 10: crc0dat accesses bits 7?0 of the 16-bit crc result. 11: crc0dat accesses bits 15?8 of the 16-bit crc result. note: upon initiation of an automatic crc calculation, the third opcode byte fetched from program memory is indeterminate. therefore, writes to crc0cn that initiate a crc operation must be immediately followed by a benign 3-byte instruction whose third byte is a don?t care . an example of such an instruction is a 3-byte mov that targets the crc0flip register. when programming in ?c?, the dummy value written to crc0flip should be a non-zero value to prevent the compiler from generating a 2-byte mov instruction.
c8051f91x-c8051f90x 163 rev. 1.3 sfr page = 0xf; sfr address = 0x93 sfr page = 0xf; sfr address = 0x91 sfr definition 15.2. crc0in: crc0 data input bit 7 6 5 4 3 2 1 0 name crc0in[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 crc0in[7:0] crc0 data input. each write to crc0in result s in the written data being computed into the existing crc result according to the crc algorithm described in section 15.1 sfr definition 15.3. crc0dat: crc0 data output bit 7 6 5 4 3 2 1 0 name crc0dat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 crc0dat[7:0] crc0 data output. each read or write performed on crc0dat targets the crc result bits pointed to by the crc0 result pointer (crc0pnt bits in crc0cn).
c8051f91x-c8051f90x rev. 1.3 164 sfr page = 0xf; sfr address = 0x96 sfr page = 0xf; sfr address = 0x97 sfr definition 15.4. crc0auto: crc0 automatic control bit 7 6 5 4 3 2 1 0 name autoen crcdone crc0st[5:0] type r/w r/w reset 0 1 0 0 0 0 0 0 bit name function 7 autoen automatic crc calc ulation enable. when autoen is set to 1, any write to c rc0cn will initiate an automatic crc starting at flash sector crc0st and continuing for crc0cnt sectors. 6 crcdone crcdone automatic crc calculation complete. set to 0 when a crc calculation is in pr ogress. code execution is stopped during a crc calculation; therefore, read s from firmware will always return 1. 5:0 crc0st[5:0] automatic crc calculation s tarting flash sector. these bits specify the flash sector to st art the automatic crc calculation. the starting address of the first flash sector included in the automatic crc calculation is crc0st x page size. note: ?f91x and ?f90x devices have a page size of 512 bytes. sfr definition 15.5. crc0cnt: crc0 automati c flash sector count bit 7 6 5 4 3 2 1 0 name crc0cnt[5:0] type r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:6 unused unused. read = 00b; write = don?t care. 5:0 crc0cnt[5:0] automatic crc calculation flash sector count. these bits specify the number of flash sector s to include in an automatic crc calculation. the starting address of the la st flash sector included in the automatic crc calculation is (crc0st+crc0cnt) x page size. note: ?f91x and ?f90x devices have a page size of 512 bytes.
c8051f91x-c8051f90x 165 rev. 1.3 15.6. crc0 bit reverse feature crc0 includes hardware to reverse the bit order of each bit in a byte as shown in figure 15.2 . each byte of data written to crc0flip is read back bit reversed. f or example, if 0xc0 is written to crc0flip, the data read back is 0x03. bit reversal is a useful mathem atical function used in algorithms such as the fft. figure 15.2. bit reverse register sfr page = 0xf; sfr address = 0x95 sfr definition 15.6. crc0flip: crc0 bit flip bit 7 6 5 4 3 2 1 0 name crc0flip[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 crc0flip[7:0] crc0 bit flip. any byte written to crc0flip is read back in a bit-rev ersed order, i.e. the written lsb becomes the msb. for example: if 0xc0 is written to crc0flip, the dat a read back will be 0x03. if 0x05 is written to crc0flip, the dat a read back will be 0xa0. crc0flip write crc0flip read
c8051f91x-c8051f90x rev. 1.3 166 16. on-chip dc-dc converter (dc0) c8051f91x-c8051f90x devices include an on-chip dc-dc converter to allow operat ion from a single cell battery with a supply voltage as low as 0.9 v. the dc-dc converter is a switching boost converter with an in put voltage range of 0.9 to 1.8 v (c8051f911/01) or 3.6 v (c8051f912/11) and a programmable output volt age range of 1.8 to 3.3 v. the default output voltage is 1.9 v when the input is less than 1.9 v. since the dc-dc converter uses a boost architecture, the output voltage will always be greater than or equal to the input voltage. the dc-d c converter can supply the system with up to 65 mw of regulated power (or up to 10 0 mw in some applications) and can be used for powe r ing other devices in the system. this allows the most flexibility when interfacing to sensors and other analog signals which typically require a higher supply voltage than a single-cell battery can provide. figure 16.1 shows a block diagram of the dc-d c converter. during normal operation in the first half of the switching cycle, the duty cycle cont rol s witch is closed and the diode bypass switch is open. since the output voltage is higher than the voltage at the dcen pin, no current flows through the diode and the load is powered from the output capacito r. during this stage, the dcen pin is connected to ground through the duty cycle control switch, generating a positive voltage across the inductor and forcing its current to ramp up. in the second half of the switching cycle, the duty cycle control switch is opened and the diode bypass switch is closed. this connects dc en directly to vdd/dc+ and forces the inductor current to charge the output capacitor. once the inductor transfers its stored energy to the output capacitor, the duty cycle con - trol switch is closed, the diode bypass switch is opened, and the cycle repeats. the dc-dc converter has a built in volt age reference and oscillator, and will automatically limit or turn off the switching activity in case the peak inductor current rises beyond a safe limit or the output voltage rises above the programmed target value. this allows the dc -dc converter output to be safely overdriven by a secondary power source (when available) in order to preserve battery life. the dc-dc converter?s settings can be modified using sfr registers which provide the ability to change the target output voltage, oscillator frequency or source, diode bypass sw itch resistance, peak inductor current, and minimum duty cycle. figure 16.1. dc-dc converter block diagram vbat vdd/dc+ dcen gnd/dc- gnd 1uf c load i load control logic duty cycle control diode bypass 0.68 uh dc/dc converter dc0cf dc0cn dc/dc oscillator voltage reference l parasitic 4.7 uf l parasitic dc0md
c8051f91x-c8051f90x 167 rev. 1.3 16.1. startup behavior on initial power-on, the dc-dc converter outputs a constant 50% duty cycle until there is sufficient voltage on the output capacitor to maintain regulation. the size of the output capacitor and the amount of load cur - rent present during startup will determine the length of time it take s to charge the output capacitor. during initial power-on reset, the maximum peak inductor cur rent threshold, which triggers the overcurrent protection circuit, is set to approximately 125 ma. this generates a ?soft-start? to limit the output voltage slew rate and prevent excessive in-rush current at the output capacitor. in order to ensure reliable startup of the dc-dc converter, the following restrictions have been imposed: ? the maximum dc load current allowed during startup is given in ta b l e 4.16 on page 67 . if the dc-dc converter is powering external sensors or device s thr ough the vdd/dc+ pin or through gpio pins, then the current supplied to these sensors or devices is counted towards this li mit. the in-rush current into capacitors does not count towards this limit. ? the maximum total output capacitance is given in ta b l e 4.16 on page 67 . this value includes the required 1 f ceramic output capacitor and any additional capacitance connected to the vdd/dc+ pin. once initial power-on is complete, the peak inductor cu rrent limit can be increased by software as shown in ta b l e 16.1 . limiting the peak inductor current can allow the de vice to start up near the battery?s end of life. . the peak inductor current is dependent on several fa ctors including the dc load current and can be esti - mated using following equation: efficiency = 0.80 inductance = 0.68 h frequency = 2.4 mhz table 16.1. ipeak inductor current limit settings swsel ilimit peak current (ma) normal power mode peak current (ma) low power mode 1 0 100 75 1 1 125 100 0 0 250 125 0 1 500 250 i pk 2 i load vdd/dc+ vbat ? () i nductance ------------------------------------------------------------------------------------------- =
c8051f91x-c8051f90x rev. 1.3 168 16.2. high power applications the dc-dc converter is designed to provide the system with 65 mw of output power, however, it can safely p rovide up to 100 mw of output power without any risk of damage to the device. for high power applica - tions, the system should be carefully designed to prevent unwanted vbat and vdd/dc+ supply monitor resets, which are more likely to occur when the dc-dc converter output power exceeds 65mw. in addition, output power above 65 mw causes the dc-dc converter to have relaxed output regulation, high output rip - ple and more analog noise. at high output power, an in ductor with low dc resistance should be chosen in order to minimize power loss and maximize efficiency. the combination of high output power and low inpu t voltage will result in ve ry high peak and average inductor currents. if the power supply has a high intern al resistance, the transient voltage on the vbat ter - minal could drop below 0.9 v and trigger a vbat supply monitor reset, even if the open-circuit voltage is well ab ove the 0.9 v threshold. while this proble m is most often associated wit h operation from very small batteries or batteries that are near the end of their useful life, it can also o ccur when using bench power supplies that have a slow transient response; the supply?s display may indicate a voltage above 0.9 v, but the minimum voltage on the vbat pin may be lower. a similar problem can occur at the output of the dc-dc converter: using the default low current limit setting (125 ma) can trigger v dd supply monitor resets if there is a high transient load current, particularly if the programmed output voltage is at or near 1.8 v. 16.3. pulse skipping mode the dc-dc converter allows the user to set the minimu m pulse width such that if the duty cycle needs to decrease below a cert ain width in order to maintain regulation , an entire "clock pulse" will be skipped. pulse skipping can provide substantial power savings, pa rtic ularly at low values of load current. the con - verter will continue to maintain a mi nimum output volt age at its programme d value when pulse skipping is employed, though the output voltage ripple can be high er. another consideration is that the dc-dc will oper - ate with pulse-frequency modulation rather than pulse -wid th modulation, which makes the switching fre - quency spectrum less predictable; this could be an iss ue if the dc-dc converter is used to power a radio. figure 4.5 and figure 4.6 on page 52 and 53 show the effect of pulse skipping on power consumption.
c8051f91x-c8051f90x 169 rev. 1.3 16.4. enabling the dc-dc converter on power-on reset, the state of th e dcen pin is sampled to determine if the device will power up in one- cell or two-cell mode. in two-cell mode, the dc-dc conv erter always remains disabled. in one-cell mode, the dc-dc converter remains disabled in sleep mode, and enabled in all other power modes. see section ?14. power management? on page 149 for complete details on available power modes. the dc-dc converter is enabled (one-cell mode) in hardware by placing a 0.68 h inductor between dcen a nd vbat. the dc-dc converter is disabled (two-cell m ode) by shorting dcen directly to gnd. the dcen pin should never be left floating. the device can on ly switch between one-cell and two-cell mode during a power-on reset. see section ?18. reset sources? on page 177 for more information regarding reset behav - ior. figure 16.2 shows the two dc-dc conver ter configuration options. figure 16.2. dc-dc converter configuration options when the dc-dc converter ?enabled? configuration (o ne-cell mode) is chosen, the following guidelines apply: ? in most cases, the gnd/dc? pin should not be e xternally connected to gnd. ? the 0.68 h inductor should be placed as close as po ssible to the dcen pin for maximum efficiency. ?the 4.7 f capacitor should be placed as close as possible to the inductor. ? the current loop including gnd, the 4.7 f capacitor, the 0.68 h inductor and the dcen pin should b e made as short as possible. ? the pcb traces connecting vdd/dc+ to the output ca pacitor and the output capacitor to gnd/dc? should be as short and as thick as possible in order to minimize parasitic inductance. vbat vdd/dc+ dcen gnd/dc- 1uf 0 . 68 uh gnd 4.7 uf vbat vdd/dc+ dcen gnd/dc- gnd dc-dc converter enabled 0.9 to 3.6 v (?f912/02) 0.9 to 1.8 v (?f911/01) supply voltage (one-cell mode) dc-dc converter disabled 1.8 to 3.6 v supply voltage (two-cell mode)
c8051f91x-c8051f90x rev. 1.3 170 16.5. minimizing power supply noise to minimize noise on the power supply lines, the gn d and gnd/dc- pins should be kept separate, as shown in figure 16.2 ; one or the other should be connected to the pc board ground plane. for applications in which the dc-dc converter is used only to power in tern al circuits, the gnd pin is normally connected to the board ground. the large decoupling capacitors in the input and output cir cuits ensure that each supply is relatively quiet with respect to its own ground. howe ver, connecting a circuit element "diagonally" (e.g. connecting an external chip between vdd/dc+ and gnd, or betwee n vbat and gnd/dc-) can result in high supply noise across that circuit element. for applications in which the dc-dc converter is used to power external analog circuitry, it is recommende d to connect the gnd/dc? pin to the board ground and connect the bat - tery?s negative terminal to the gnd pin only , which is not connected to board ground. to accommodate situations in which adc0 is sampling a sign al that is referenced to one of the external grounds, we recommend using the analog ground reference (p0.1/agnd) option described in section 5.12 . this option prevents any voltage differences bet wee n the internal chip ground and the external grounds from modulating the adc input signal. if this option is enabled, the p0.1 pin should be tied to the ground reference of the external analog input sig nal. when using the adc with the dc-dc converter, we also recommend enabling the sync bit in the dc0cn register to minimize interference. these general guidelines provide the best performanc e in most applications, though some situations may benefit from experimentation to eliminate any residu al noise issues. examples might include tying the grounds together, using additional low-inductance dec oupling caps in parallel wi th the recommended ones, investigating the effects of different dc-dc converter settings, etc. 16.6. selecting the optimum switch size the dc-dc converter has two built-in switches (the dio de bypass switch and duty cycle control switch). to maximize efficiency, one of two switch sizes may be selected. the large switches are ideal for carrying high currents and the small switches are ideal for low current applications. the ideal switchover point to switch from the small switches to the large switches varies with the programmed output voltage. at an out - put voltage of 2 v, the ideal switchover point is at approximately 4 ma total output current. at an output volt age of 3 v, the ideal switchover point is at approximately 8 ma total output current. 16.7. dc-dc converte r clocking options the dc-dc converter may be clocked from its internal oscillator, or from any system cl ock source, select - able by the clksel bit (dc0cf.0). the dc-dc conver ter internal oscillator fr equenc y is approximately 2.4 mhz. for a more accurate clock source, the system cl oc k, or a divided version of the system clock may be used as the dc-dc clock source. the dc-dc converter has a built in clock divider (configured using dc0cf[6:5]) which allo ws any system clock frequency over 1.6 mhz to generate a valid clock in the range o f 1.6 to 3.2 mhz. when the precision inte rnal oscillator is selected as the system clock source, the oscicl register may be used to fine tune the oscillator frequency and the dc-dc converter cl ock. the oscillator frequency should only be decreased since it is factory calibrated at its maximum frequency. the minimum frequency which can be reached by the oscillator after taking into acco unt process variations is approximately 16 mhz. the system clock routed to the dc-dc converter clock divider also may be inverted by setting the clkinv bit (dc0cf.3) to logic 1. these options can be used to mi nimize interference in noise sensitive applications.
c8051f91x-c8051f90x 171 rev. 1.3 16.8. dc-dc conver ter behavior in sleep mode when the c8051f91x-c8051f90x devices are placed in sleep mode, the dc-dc converter is disabled, and the vdd/dc+ output is internally connected to vbat by default. this behavior ensures that the gpio pins are powered from a low-impedance source during sleep mode. if the gpio pins are not used as inputs or outputs during sleep mode, then the vdd/dc+ output c an be made to float during sleep mode by setting the vddslp bit in the dc0cf register to 1. setting this bit can provide power savings in two ways. fi rst, if the sleep interval is relatively short and the vdd/dc+ load current (include le akage currents) is negligible, then the capacitor on vdd/dc+ will main - tain the output voltage n ear the programmed value, which means that the vd d/dc+ capacitor will not need to be recharged upon every wake up event. the second power advantage is that internal or external low- power circuits that require more than 1.8 v can continue to function during sleep mode without operating the dc-dc converter, powered by the energy stored in the 1 f output decoupling capacitor. for example, the c8051f91x-c8051f90x comparators require about 0.4 a when operating in th eir lowes t power mode. if the dc-dc converter output were increased to 3.3 v just before putting the device into sleep mode, then the comparator could be powered for more than 3 seconds before the output voltage dropped to 1.8 v. in this exam ple, the overall energy c onsumption would be much lower than if the dc-dc converter were kept running to power the comparator. if the load current on vdd/dc+ is high enough to di sch arge the vdd/dc+ capacitance to a voltage lower than vbat during the sleep interval , an internal diode will prevent vdd/ dc+ from dropping more than a few hundred millivolts below vbat. there may be some additional leakag e current from vbat to ground when the vdd/dc+ level falls below vbat, but this leakage current should be small compared to the cur - rent from vdd/dc+. the amount of time that it takes for a device configured in one-cell mode to wake up from sleep mode d epends on a number of factors, including the dc-dc converter clock speed, t he settings of the swsel, ilimit, and lpen bits, the battery internal resistance, the load current, and the difference between the vbat voltage level and the programmed output voltage. the wake up time can be as short as 2 s, though it is mo re commonly in the range of 5 to 10 s, and it can exceed 50 s under extreme conditions. see section ?14. power management? on page 149 for more information about sleep mode. 16.9. bypass mode (c8051f912/02 only) during normal operation, if the dc-dc converter input voltage exceeds the programmed output voltage, the converter will stop switching and the diode bypass switch will remain in th e ?on? state. th e output voltage will be equal to the input volt age minus any resistive loss in the switch and all of the converter?s analog cir - cuits will remain biased. the bypass feature automatic ally sh uts off the dc-dc converter when the input voltage is greater than the programmed output voltage by 150 mv. in bypass, the diode bypass switch and dc -dc converter bias currents are disabled except for the voltage comparison circuitry (~ 3 a, depending o n the configuration settings in the dc0md register). if the input voltage drops within 50 mv of the pro - grammed output value, then the dc-dc converter automatically st arts operating in the normal state. there is 100 mv voltage hysteresis built in the by p ass comparator to enhance stability. the bypass mode increases system operating time in systems which have a minimum operating voltage h igher than the battery end of life voltage. for instance , if an external chip requires a minimum supply volt - age of 2.7 v and a lithium coin cell battery is used as po wer source (end-of-life voltage is approximately 2 v), then the c8051f912/902?s dc-dc converter coul d b e configured for an output voltage of 2.7 v with by pass mode enabled. the dc-dc converter would be bypassed when the battery was fresh, but as soon as the battery voltage dropped below 2.75 v, the dc-dc converter would turn on to ensure that the external chip was provided with a minimum of 2.7 v for the remainder of the battery life.
c8051f91x-c8051f90x rev. 1.3 172 16.10. low power mode (c8051f912/02 only) setting the lpen bit in the dc0cf register will enable a low power mode for the dc-dc converter. in low power mode, the bias currents are substantially reduce d, which can lead to an efficiency improvement with light load currents (g enerally less than a few ma). the drawback to this mode is that the response time of the converter?s analog blocks is increased; larger de lay in the circuits controlling the diode bypass switch can lead to loss of efficiency at medium and high lo ad currents due to reverse leakage in the switch. the low power mode also reduces the peak inductor current limit as shown in table 16.1 . 16.11. passive diode mo de (c8051f912/02 only) setting the extden bit in dc0md enables the passive di ode mode. in this mode, the control circuits for the diode bypass switch are disabled, which reduce s the converter?s quiescent operating current. an external schottky diode may be connected between the dcen (ano de) and vdd/dc+ (cathode) pins. under light load conditions, an external diode is typically not required. there are two situations in which this mode can prove beneficial. first is with very light load currents, where the efficiency is dominated by the converter?s quiescent current. the converter will use an internal p-n junction diode to transfer current from the inductor to the output capacitor; although there is a larger voltage drop (and power loss) across a passive diode, the overall efficiency may be improved du e to the reduction in quiescent current. the sec - ond situation is when output power is very high. in tha t case, efficiency can suffer because some reverse current can flow in the diode bypass switch before t he control circuitry turns th e switch off. putting the device in passive diode mode and optionally connecti ng an external schottky diode between the dcen and vdd/dc+ pins (parallel to the internal diode) may provide higher efficiency in some applications than using the internal diode bypass switch.
c8051f91x-c8051f90x 173 rev. 1.3 16.12. dc-dc converter register descriptions the sfrs used to configure the dc-dc converter are de scribed in the following register descriptions. the reset values for these registers can be used as-is in most systems; therefore, no software intervention or initialization is required. sfr page = 0x0; sfr address = 0x97 sfr definition 16.1. dc0cn: dc-dc converter control bit 7 6 5 4 3 2 1 0 name minpw swsel reserved sync vsel type r/w r/w r/w r/w r/w reset 0 0 1 0 0 0 0 1 bit name function 7:6 minpw[1:0] dc - dc converter minimum pulse width. specifies the minimum pulse width. 00: no minimum duty cycle. 01: minimum pulse width is 20 ns. 10: minimum pulse width is 40 ns. 11: minimum pulse width is 80 ns. 5 swsel dc-dc converter switch select. selects one of two possible converter sw itch sizes to maximize efficiency. 0: the large switches are selected (best efficiency for high output currents). 1: the small switches are selected (best efficiency for low output currents). 4 reserved reserved. always write to 0. 3 sync adc0 synchronization enable. when synchronization is enabled, the adc0sc[4:0] bits in the adc0cf register mu st be set to 00000b. 0: the adc is not synchronized to the dc-dc converter. 1: the adc is synchronized to the dc-dc converter. adc0 tracking is performed d uring the longest quiet time of the dc-d c converter switching cycle and adc0 sar clock is also synchronized to th e dc-dc converter switching cycle. 2:0 vsel[2:0] dc - dc converter output voltage select. specifies the target output voltage. 000: target output voltage is 1.8 v. 001: target output voltage is 1.9 v. 010: target output voltage is 2.0 v. 011: target output voltage is 2.1 v. 100: target output voltage is 2.4 v. 101: target output voltage is 2.7 v. 110: target output voltage is 3.0 v. 111: target output voltage is 3.3 v.
c8051f91x-c8051f90x rev. 1.3 174 sfr page = 0x0; sfr address = 0x96 sfr definition 16.2. dc0cf: dc-dc conver ter configuration bit 7 6 5 4 3 2 1 0 name lpen clkdiv[1:0] ad0ckinv clkinv ilimit vddslp clksel type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 lpen low power mode enable. enables the dc-dc low power mode which reduces bias currents, reduces peak in ductor current, and increases efficiency for low load currents. only available on ?f912 and ?f902 devices. 0: low power mode disabled. 1: low power mode enabled. 6:5 clkdiv[1:0] dc - dc clock divider. divides the dc-dc converter clock when the s ystem clock is selected as the clock source for dc-dc converter. these bits are ignored when the dc-dc converter is clocked from its local oscillator. 00: the dc-dc converter clock is system clock divided by 1. 01: the dc-dc converter clock is system clock divided by 2. 10: the dc-dc converter clock is system clock divided by 4. 11: the dc-dc converter clock is system clock divided by 8. 4 ad0ckinv adc0 clock inversion (clo ck invert during sync). inverts the adc0 sar clock d erived from the dc-dc converter clock when the sync bit (dc0cn.3) is enab led. this bit is ignored when the sync bit is set to zero. 0: adc0 sar clock is inverted. 1: adc0 sar clock is not inverted. 3 clkinv dc - dc converter clock invert. inverts the system clock used as th e input to the dc-dc clock divider. 0: the dc-dc converter clock is not inverted. 1: the dc-dc converter clock is inverted. 2 ilimit peak current limit threshold. sets the threshold for the maximum allowe d pe ak inductor current according to ta b l e 16.1 . 1 vddslp vdd - dc+ sleep mode connection. specifies the power source for vdd/dc+ in sleep mode when the dc-dc converter is enabled. 0: vdd-dc+ connected to vbat in sleep mode. 1: vdd-dc+ is floating in sleep mode. 0 clksel dc - dc converter clock source select. specifies the dc-dc converter clock source. 0: the dc-dc converter is cloc k ed from its local oscillator. 1: the dc-dc converter is clocked from the system clock.
c8051f91x-c8051f90x 175 rev. 1.3 sfr page = 0xf; sfr address = 0x94 16.13. dc-dc conver ter specifications see ta b l e 4.16 on page 67 for a detailed listing of dc-dc converter specifications. sfr definition 16.3. dc0md: dc-dc mode bit 7 6 5 4 3 2 1 0 name bypflg bypsel[1:0] pasden type r/w r/w r/w r/w r r/w r/w reset 0 0 0 0 varies 0 0 0 bit name function 7:4 unused unused. read = 0000b, write = don?t care. 3 bypflg bypass indicator. indicates when the dc-dc converter is operating in bypass mode. only available on ?f9 12 and ?f902 devices. 0: dc0 is not operating in bypass mode. 1: dc0 is operating in bypass mode. 2:1 bypsel[1:0] bypass mode select. selects the bypass settings. only av aila ble on ?f912 and ?f902 devices. 00: bypass mode disabled (highest supply current when the input voltage exceeds the programmed output voltage). 01: bypass enabled (auto switch), dc-dc oscill ator enabled (fast response time) 10: bypass enabled (auto switch), dc-dc os cillator disabled (redu ced supply c urrent) 11: the dc-dc converter is forced into bypa ss mod e (lowest supply current when the input voltage exceeds the programmed output voltage). 0 pasden passive diode mode enable. passive external diode mode. only available on ?f912 and ?f902 devices. 0: passive diode mode disabled. 1: passive diode mode enabled.
c8051f91x-c8051f90x rev. 1.3 176 17. voltage regulator (vreg0) c8051f91x-c8051f90x devices include an internal volt age regulator (vreg0) to regulate the internal core supply to 1.8 v from a vdd/dc+ supply of 1.8 to 3.6 v. electrical characteristics for the on-chip r egulator are specified in the electrical specifications chapter. the reg0cn register allows the prec ision oscillator bias to be disabled , reducing supply current in all non-sleep power modes. this bias should only be disabl ed when the prec ision oscillator is not being used. the internal regulator (vreg0) is disabled when the device enters sleep mode and remains enabled wh en the device enters suspend mode. see section ?14. power management? on page 149 for complete details about low power modes. sfr page = 0x0; sfr address = 0xc9 17.1. voltage regulator el ectrical specifications see ta b l e 4.15 on page 66 for detailed voltage regulato r electrical s pecifications. sfr definition 17.1. reg0cn: voltage regulator control bit 7 6 5 4 3 2 1 0 name reserved reserved oscbias reserved type r r/w r/w r/w r r r r/w reset 00010000 bit name function 7 unused unused. read = 0b. write = don?t care. 6 reserved reserved. read = 0b. must write 0b. 5 reserved reserved. read = 0b. must write 0b. 4 oscbias precision oscillator bias. when set to 1, the bias used by the precisio n oscillator is forced on. if the precision oscillator is not being used, this bit may be cleared to 0 to save approximately 80 a o f supply current in all non-sleep power modes. if disabled then re-enabled, the pre - cision oscillator bias requires 4 s of settling time. 3:1 unused unused. read = 000b. write = don?t care. 0 reserved reserved. read = 0b. must write 0b.
c8051f91x-c8051f90x 177 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 177 18. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled all sfrs are reset to the predefined values noted in the sfr descriptions. the contents of ram are u naffected during a reset; any previously stored data is preserved as long as power is not lost. since the stack pointer sfr is reset, the stack is effectively lo st, even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. weak pullups are enabled d uring and after the reset. for power-on resets, the rst pin is high-impedance with the weak pull-up off until the device exits the reset state. for v dd monitor resets, the rst pin is driven low until the device exits the reset state. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to an internal os cillator. refer to section ?19. clocking sources? on page 185 for information on selecting and configuring the system clock source. the watchdog time r is e nabled with the system clock divided by 12 as its clock source ( section ?26.4. watchdog timer mode? on page 308 details the use of the watchdog timer). program execution begins at location 0x0000. figure 18.1. reset sources pca wdt missing clock detector (one- shot) (software reset) system reset reset funnel px.x px.x en swrsf system clock cip-51 microcontroller core extended interrupt handler en wdt enable mcd enable illegal flash operation rst '0' + - comparator 0 vdd/dc+ + - supply monitor enable smartclock rtc0re c0rsef power-on reset power management block (pmu0) system reset vbat power on reset reset
c8051f91x-c8051f90x 178 rev. 1.3 18.1. power-on (vbat supply monitor) reset during power-up, the device is held in a reset state and the rst pin is high-impedance with the weak pull- up off until v bat settles above v por . an additional delay occurs before th e device is released from reset; the delay decreases as the v bat ramp time increases (v bat ramp time is defined as how fast v bat ramps from 0 v to v por ). figure 18.3 plots the power-on and v dd monitor reset timing. for valid ramp times (less than 3 ms), the power-on reset delay (t pordelay ) is typically 3 ms (v bat = 0.9 v), 7 ms (v bat = 1.8 v), or 15 ms (v bat = 3.6 v). note: the maximum v dd ramp time is 3 ms; slower ramp times may cause the device to be released from reset bef ore v bat reaches the v por level. on exit from a power-on reset, the porsf fl ag (rstsrc.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000), software can read the porsf flag to determine if a power-up was the cause of reset. the contents of internal data memory should be assumed to be undefined after a power-on reset. on ?f912 and ?f902 devices, the vbat supply monitor ca n be disabled to save power by writing ?1? to the mondis (pmu0md.5) bit. when the vbat supply monito r is disabled, all reset sources will trigger a full por and will re-enable the vbat supply monitor. figure 18.2. power-fail reset timing diagram power-on reset power-on reset rst t volts logic high logic low t pordelay v b a t v por vbat see specification table for min/max voltages. t pordelay
c8051f91x-c8051f90x rev. 1.3 179 18.2. power-fail (vdd/dc+ supply monitor) reset c8051f91x-c8051f90x devices have a vdd/dc+ supply monitor that is enabled and selected as a reset source after each power-on or power-fail reset. when enabled and selected as a reset source, any power down transition or power irregularity that causes vdd/dc+ to drop below v rst will cause the rst pin to be driven low and the cip-51 will be held in a reset state (see figure 18.3 ). when vdd/dc+ returns to a level above v rst , the cip-51 will be released from the reset state. after a power-fail reset, the porsf flag reads 1, the contents of ra m invalid, and the vdd/dc+ supply monitor is enabled and selected as a reset source. the enable state of the vdd/dc+ supply monitor and its selection as a reset source is only altered by power-on and power-fail resets. for example, if the vdd/dc+ supply monitor is de-selected as a reset sour ce and disabled by software, then a software reset is performed, the vdd/dc+ supply monitor will re main disabled and de-selected after the reset. in battery-operated systems, the contents of ram c an be preserved near the end of the battery?s usable life if the device is placed in sleep mode prior to a power-fail reset occurring. when the device is in sleep mode, the power-fail reset is automatically disabled and the contents of ram are preserved as long as the vbat supply does not fall below v por . a large capacitor can be used to hold the power supply voltage above v por while the user is replacing the battery. upon waking from sleep mode, the enable and reset source select state of the vdd/dc+ supply monitor are restored to the value last set by the user. to allow software early notification that a power failure is about to occur, the vddok bit is cleared when the vdd /dc+ supply falls below the v warn threshold. the vddok bit can be configured to generate an interrupt. see section ?12. interrupt handler? on page 127 for more details. important note: t o protect the integrity of flash contents, the vdd/dc+ supply monitor must be enabled and selected as a reset source if software contains routines which erase or write flash memory. if the vdd/dc+ supply monitor is not enabled, any erase or write performed on flash memory will cause a flash error device reset. figure 18.3. power-fail reset timing diagram t volts v rst vdd/dc+ v por vdd warn vbat note: wakeup signal required after new battery insertion vddok sleep rst active mode power-fail reset sleep mode ram retained - no reset vbat warn
c8051f91x-c8051f90x 180 rev. 1.3 important notes: ? the power-on reset (por) delay is not incurred after a vdd/dc+ supply monitor reset. see section ?4. electrical characteristics? on page 42 for complete electrical characteristic s of the vdd/dc+ moni - tor. ? software should take care not to inadvertently disable the v dd monitor as a reset source when writing to rstsrc to enable other reset sources or to trigge r a software reset. all writes to rstsrc should explicitly set porsf to 1 to keep the v dd monitor enabled as a reset source. ? the vdd/dc+ supply monitor must be enab le d before sele cting it as a reset source . selecting the vdd/dc+ supply monitor as a reset source before it has stabilized may genera te a system reset. in systems where this reset would be undesirable, a delay should be introduced between enabling the vdd/dc+ supply monitor and selecting it as a reset source. see section ?4. electrical characteristics? on page 42 for minimum vdd/dc+ supply monitor turn-on time. no de lay should be introduced in systems where software contains routines that erase or write flash memory. t he procedure for enabling the vdd/dc+ supply mo nitor and selecting it as a reset source is shown below: 1. enable the vdd/dc+ supply monito r (v dmen bit in vdm0cn = 1). 2. wait for the vdd/dc+ supply monitor to s tabilize (optional). 3. select the vdd/dc+ supply monitor as a reset source (porsf bit in rstsrc = 1).
c8051f91x-c8051f90x rev. 1.3 181 sfr page = 0x0; sfr address = 0xff sfr definition 18.1. vdm0cn: vdd/dc+ suppl y monitor control bit 7 6 5 4 3 2 1 0 name vdmen vddstat vddok vbatok vddokie vbatokie type r/w r r r r/w r/w r/w r/w reset 1 varies varies varies 1 0 0 0 bit name function 7 vdmen vdd/dc+ supply monitor enable. this bit turns the vdd/dc+ supply monitor circuit on/off. the vdd/dc+ supply monitor cannot generate system resets until it is also selected as a reset source in register rstsrc ( sfr definition 18.2 ). 0: vdd/dc+ supply monitor disabled. 1: vdd/dc+ supply monitor enabled. 6 vddstat vdd/dc+ supply status. this bit indicates the current power supply status. 0: vdd/dc+ is at or below the v rst threshold. 1: vdd/dc+ is above the v rst threshold. 5 vddok vdd/dc+ supply status (early warning). this bit indicates the current vdd/dc+ power supply status. 0: vdd/dc+ is at or below the vdd warn threshold. 1: vdd/dc+ is above the vdd warn threshold. 4 vbatok vbat supply status (early warning). this bit indicates the current vbat power supply status. this bit is only present on ?f9 12 and ?f902 devices. 0: vbat is at or below the vbat warn threshold. 1: vbat is above the vbat warn threshold. 3 vddokie vdd/dc+ early warni ng in terrupt enable. enables the vdd/dc+ early warning interrupt. this bit only has an effect on ?f912 a nd ?f902 devices. all other devices behave as if this bit is set to 1. 0: vdd/dc+ early warning interrupt is disabled. 1: vdd/dc+ early warning interrupt is enabled. 2 vbatokie vbat early warning interrupt enable. enables the vbat early warning interrupt. this bit only has an effect on ?f912 and ?f9 02 devices. all other devices beh ave as if this bit is set to 0. 0: vbat early warning in terrupt is disabled. 1: vbat early warning interrupt is enabled. 1:0 unused unused. read = 00b. write = don?t care.
c8051f91x-c8051f90x 182 rev. 1.3 18.3. external reset the external rst pin provides a means for external circuitr y to force the device into a reset state. asserting an active-low signal on the rst pin generates a reset; an exte rnal pullup and/or decoupling of the rst pin may be necessary to avoid erroneous noise-induced resets. see ta b l e 4.4 for complete rst pin specifications. the external rese t remains functional even when the device is in the low power suspend and sleep modes. the pinrsf flag (rstsrc.0) is set on exit from an external reset. 18.4. missing clock detector reset the missing clock detector (mcd) is a one-shot circuit that is triggered by the syst em clock. if the system clock remains high or low for more than 100 s, the one-shot will time out an d generate a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read 1, signifying the mcd as the reset source; otherwise, this bit reads 0. writing a 1 to the mcdrsf bit enables the missing clock detector; writing a 0 disables it. the missing clock detector reset is automatically disabl ed when the device is in the low power suspend or sleep mode. upon exit from either low power state, the enabled/disabled state of this reset source is restored to its previous value. the state of the rst pin is unaffected by this reset. 18.5. comparator0 reset comparator0 can be configured as a reset source by writing a 1 to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is less than the inverting input voltage (on cp0?), the device is put into the reset state. after a compar ator0 reset, the c0rsef flag (rst src.5) will read 1 signifying comparator0 as the reset source; otherwise, this bit reads 0. the comparator0 reset source remains functional even when the device is in the low power suspend and sleep states as long as comparator0 is also enabled as a wake-up source. the state of the rst pin is unaffected by this reset. 18.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as described in section ?26.4. watchdog timer mode? on page 308 ; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is gen erated and the wdtrsf bit (rstsrc.5) is set to 1. the pca watchdog timer reset source is autom atically disabled when th e device is in the low power suspend or sleep mode. upon exit from either low power state, the enable d/disabled state of this reset source is restored to its previous value.the state of the rst pin is unaffected by this reset.
c8051f91x-c8051f90x rev. 1.3 183 18.7. flash error reset if a flash read/write/era se or program read targets an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to 1 and a movx wr ite operation targets an address above the lock byte address. ? a flash read is attempted above user code space. this occurs when a movc operation targets an address above the lock byte address. ? a program read is attempted above user code spac e. this occu rs when user code attempts to branch to an address above the lock byte address. ? a flash read, write or erase attempt is re stricted d ue to a flash security setting (see section ?13.3. security options? on page 141 ). ? a flash write or erase is attempted while the v dd monitor is disabled. the ferror bit (rstsrc.6) is set following a flash error reset. the state of the rst pin is unaffected by this reset. 18.8. smartclock (real time clock) reset the smartclock can generate a system reset on two events: smartclock oscillator fail or smartclock alarm. the smartclock oscillator fa il event occurs when the smartclock missing clock detector is enabled and the smartclo ck clock is below approximately 20 khz. a smartclock alarm ev ent occurs when the smartclock alarm is enab led and the smartclock timer value matches the alarmn registers. the smartclock can be configured as a reset source by writing a 1 to the rtc0re flag (rstsrc.7). the smartclock reset remains functional even when the device is in the low power suspend or sleep mode. the state of the rst pin is unaffected by this reset. 18.9. software reset software may force a reset by wr iting a 1 to the swrsf bit (rst src.4). the swrsf bit will read 1 following a software forced reset. the state of the rst pin is unaffected by this reset.
c8051f91x-c8051f90x 184 rev. 1.3 sfr page = 0x0; sfr address = 0xef. sfr definition 18.2. rstsrc: reset source bit 7 6 5 4 3 2 1 0 name rtc0re ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf type r/w r r/w r/w r r/w r/w r reset varies varies varies varies varies varies varies varies bit name description write read 7 rtc0re smartclock reset enable and flag 0: disable smartclock as a reset source. 1: enable smartclock as a r eset source. set to 1 if smartclock alarm or oscillator fail caused the last reset. 6 ferror flash error reset flag. n/a set to 1 if flash read/w rite/erase error caused the last reset. 5 c0rsef comparator0 reset enable and flag . 0: disable comparator0 as a r eset source. 1: enable comparator0 as a r eset source. set to 1 if comparator0 caus ed the last reset. 4 swrsf software reset force and flag. writing a 1 forces a sys - tem reset. set to 1 if last reset was cau sed by a write to swrsf. 3 wdtrsf watchdog timer reset flag. n/a set to 1 if watchdog timer o verflow caused the last reset. 2 mcdrsf missing clock detector (mcd) ena ble and flag. 0: disable the mcd. 1: enable the mcd. the mcd triggers a reset if a mis sing clock condition is detected. set to 1 if missing clock detector timeout caused the last reset. 1 porsf power-on / power-fail re set flag, and power-fail reset enable. 0: disable the vdd/dc+ sup ply monitor as a reset source. 1: enable the vdd/dc+ sup ply monitor as a reset source. 3 set to 1 anytime a power- on or v dd monitor reset occurs. 2 0 pinrsf hw pin reset flag. n/a set to 1 if rst pin caused the last reset. notes: 1. it is safe to use read-modify-write operations (orl, anl, etc.) to enable or disable specific interrupt sources. 2. if porsf read back 1, the value read from all other bits in this register are indeterminate. 3. writing a 1 to porsf before the vdd/dc+ supply monitor is stabilized may generate a system reset.
c8051f91x-c8051f90x rev. 1.3 185 19. clocking sources c8051f91x-c8051f90x devices include a programmable prec ision internal oscillator, an external oscillator drive circuit, a low power internal oscillator, and a smartclock real ti me clock oscillator. the precision internal oscillator can be enabled/disabled and calibrated using the oscicn and oscicl registers, as shown in figure 19.1 . the external oscillator can be config ured us ing the oscxcn register. the low power internal oscillator is automatic ally enabled and disabled when selected and dese lected as a clock source. smartclock operation is described in the smartclock oscillator chapter. the system clock (sysclk) can be der ived from the precision internal oscil lator, external oscillator, low power internal oscillator, or smartclock oscillator. the global clock divider can generate a system clock that is 1, 2, 4, 8, 16, 32, 64, or 128 times slower that the selected in put clock source. os cillator electrical specifications can be found in the electrical specif ications chapter. figure 19.1. clocking sources block diagram the proper way of changing the system clock when bo th the clock source and the clock divide value are being changed is as follows: if switching from a fast ?undivided? clock to a slower ?undivided? clock: a. change the clock divide value. b. poll for clkrdy > 1. c. change the clock source. if switching from a slow ?undivided? clock to a faster ?undivided? clock: a. change the clock source. b. change the clock divide value. c. poll for clkrdy > 1. external oscillator drive circuit xtal1 xtal2 option 2 vdd xtal2 option 1 10m option 4 xtal2 oscxcn xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 precision internal oscillator en oscicl oscicn ioscen ifrdy sysclk clksel clkdiv2 clkdiv1 clkdiv0 clkrdy clksl1 clksl0 smartclock oscillator clock divider n low power internal oscillator low power internal oscillator smartclock oscillator external oscillator precision internal oscillator clkrdy option 3 xtal2
c8051f91x-c8051f90x 186 rev. 1.3 19.1. programmable precisi on internal oscillator all c8051f91x-c8051f90x devices include a programma ble precision internal oscillator that may be selected as the system clock. oscicl is factory calibrate d to obtain a 24.5 mhz frequency. see section ?4. electrical characteristics? on page 42 for complete oscilla tor specifications. the precision oscillator supports a spread spectrum mode which modulates the out put frequency in order to reduce the emi generated by t he system. when enabled (sse = 1), the oscillator output frequency is modulated by a stepped triangle wave whose frequenc y is equal to the oscillato r frequency divided by 384 (63.8 khz using the factory calibration). the dev iation from the nominal oscillator frequen cy is +0%, ?1.6%, and the step size is typically 0.26% of the nominal fr equency. when using this mode, the typical average oscillator frequency is lowered from 24.5 mhz to 24.3 mhz. 19.2. low power internal oscillator all c8051f91x-c8051f90x devices in clude a low power internal oscilla tor that defaults as the system clock after a system reset. the low power internal oscillator frequency is 20 mhz 10% and is automati - cally enabled when selected as the system clock and disabled when not in use. see section ?4. electrical characteristics? on page 42 for complete oscillator specifications. 19.3. external oscill ator drive circuit all c8051f91x-c8051f90x devices include an external osc illator circuit that may dr ive an external crystal, ceramic resonator, capacitor, or rc network. a cmos clock ma y also provide a clock input. figure 19.1 shows a block diagram of the four external oscillator options. the extern al osc illator is enabled and config - ured using the oscxcn register. the external oscillato r output may be s elected as the system clock or used to clock some of the digital peripherals (e.g. timers, pca, etc.). see the data shee t chapters for each digital peripheral for details. see section ?4. electrical characte ristics? on page 42 for complete oscilla tor s pecifications. 19.3.1. external crystal mode if a crystal or ceramic resonator is used as the external oscillator, the crystal/resonator and a 10 m resis - tor must be wired across the xtal1 and xtal2 pins as shown in figure 19.1 , option 1. appropriate load - ing capacitors should be added to xtal1 and xtal2, and both pins should be configured for analog i/o with th e digital output drivers disabled. figure 19.2 shows the external oscillator circuit for a 20 mhz quartz crystal with a manufacturer recom - mended load capacitance of 12.5 pf. loading capacitors are "in series" as seen by the crystal and "in par - allel" with the stray capacitance of the xtal1 and xtal2 pins. the total value of the each loading cap acitor and the stray capacitance of each xtal pin should equal 12.5 pf x 2 = 25 pf. with a stray cap acitance of 10 pf per pin, the 15 pf capacitors yield an equivale nt se ries capacitance of 12.5 pf ac ross the crystal. note: the recommended load capacitance depends upon the crystal and the manufacturer. please refer to the crystal data sheet when completing these calculations.
c8051f91x-c8051f90x rev. 1.3 187 figure 19.2. 25 mhz external crystal example important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces which could introduce noise or interference. when using an external crystal, the external oscillator drive circuit must be configured by software for crys - tal oscillator mode or crystal oscillator mode with divide by 2 stage . the divide by 2 stage ensures that the clock derived from the external o scillator has a duty cycle of 50%. t he external oscillator frequency con - trol value (xfcn) must also be specified based on th e crystal frequency. the selection should be based on ta b l e 19.1 . for example, a 25 mhz crystal requires an xfcn setting of 111b. when the crystal oscillator is first enabled, the external osc illator valid detector allo ws software to deter - mine when the external system clock has stabilized. s witching to the external oscillator before the crystal oscillator has stabilized can result in unpredictable behavior . the recommended procedu re for starting the crystal is as follows: 1. configure xtal1 and xtal2 for analog i/o and disable the digital output drivers. 2. configure and enable the external oscillator. 3. poll for xtlvld => 1. 4. switch the system clock to the external oscillator . table 19.1. recommended xfcn settings for crystal mode xfcn crystal frequency bias current typical supply current (vdd = 2.4 v) 000 f 20 khz 0.5 a 3.0 a, f = 32.768 khz 001 20 khz < f 58 khz 1.5 a 4.8 a, f = 32.768 khz 010 58 khz < f 155 khz 4.8 a 9.6 a, f = 32.768 khz 011 155 khz < f 41 5 khz 14 a 28 a, f = 400 khz 100 415 khz < f 1.1 mhz 40 a 71 a, f = 400 khz 101 1.1 mhz < f 3. 1 mhz 120 a 193 a, f = 400 khz 110 3.1 mhz < f 8. 2 mhz 550 a 940 a, f = 8 mhz 111 8.2 mhz < f 25 mhz 2.6 ma 3.9 ma, f = 25 mhz 15 pf 15 pf 25 mhz xtal1 xtal2 10 mohm
c8051f91x-c8051f90x 188 rev. 1.3 19.3.2. external rc mode if an rc network is used as the external oscillator, the circuit should be configured as shown in figure 19.1 , option 2. the rc network should be added to xtal2, and xtal2 should be configured for analog i/o with the digital output drivers disabled. xtal1 is not affected in rc mode. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. the resistor should be no smaller than 10 k . the osc illation frequency can be de termined by the following equation: where f = frequency of clock in mhzr = pu ll-up resistor value in k v dd = power supply voltage in voltsc = capacitor value on the xtal2 pin in pf to determine the required external oscillator frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to produce the desired frequ ency of oscillation. for example, if the fre - quency desired is 100 khz, let r = 246 k an d c = 50 pf: where f = frequency of clock in mhz r = pull-up resistor value in k v dd = power supply voltage in volts c = capacitor value on the xtal2 pin in pf referencing table 19.2 , the recommended xfcn setting is 010. table 19.2. recommended xfcn settings for rc and c modes xfcn approximate fr equency range (rc and c mode) k factor (c mode) typical supply current/ actual me asured frequency (c mode, vdd = 2.4 v) 000 f 25 khz k factor = 0.87 3.0 a, f = 11 khz, c = 33 pf 001 25 khz < f 50 khz k factor = 2.6 5.5 a, f = 33 khz, c = 33 pf 010 50 khz < f 10 0 khz k factor = 7.7 13 a, f = 98 khz, c = 33 pf 011 100 khz < f 200 khz k factor = 22 32 a, f = 270 khz, c = 33 pf 100 200 khz < f 400 khz k factor = 65 82 a, f = 310 khz, c = 46 pf 101 400 khz < f 800 khz k factor = 180 242 a, f = 890 khz, c = 46 pf 110 800 khz < f 1.6 mhz k factor = 664 1.0 ma, f = 2.0 mhz, c = 46 pf 111 1.6 mhz < f 3.2 mhz k factor = 1590 4.6 ma, f = 6.8 mhz, c = 46 pf f 1.23 10 3 rc ------------------------ - = f 1.23 10 3 rc ------------------------ - 1.23 10 3 246 50 ------------------------ - 100 khz ===
c8051f91x-c8051f90x rev. 1.3 189 when the rc oscillator is first enabled , the external oscillator valid detect or allows software to determine when oscillation has stabilized. the recommended procedure fo r starting the rc oscillator is as follows: 1. configure xtal2 for analog i/o and disable the digital output drivers. 2. configure and enable the external oscillator. 3. poll for xtlvld => 1. 4. switch the system clock to the external oscillator . 19.3.3. external capacitor mode if a capacitor is used as the external oscillator, the circuit should be configured as shown in figure 19.1 , option 3. the capacitor should be added to xtal2, a nd xtal2 should be configured for analog i/o with the digital output drivers disabled. xtal1 is not affected in rc mode. the capacitor should be no greater than 100 pf; however, for very small cap acitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. the oscillation fr equency and th e required external oscillator frequency control value (xfcn) in the os cxcn register can be determined by the following equation: where f = frequency of clock in mhzr = pu ll-up resistor value in k v dd = power supply voltage in voltsc = capacitor value on the xtal2 pin in pf below is an example of selecting the capacitor an d fi nding the frequency of oscillation assume v dd = 3.0 v a nd f = 150 khz: since a frequency of roughly 150 khz is desired, select the k factor from ta b l e 19.2 as kf = 22: therefore, the xfcn value to use in this exam ple is 011 and c is approximately 50 pf. the recommended startup procedure for c mode is the same as rc mode. 19.3.4. external cmos clock mode if an external cmos clock is used as the external oscillator, the clock shou ld be directly routed into xtal2. the xtal2 pin should be configured as a digital input. xtal1 is not used in external cmos clock mode. the external oscillator valid detector will always return zero when the external oscilla tor is configured to external cmos clock mode. f kf cv dd --------------------- = f kf cv dd --------------------- = 0.150 mhz kf c3.0 ----------------- = 0.150 mhz 22 c 3.0 v ----------------------- = c 22 0.150 mhz 3.0 v ---------------------------------------------- - = c 48.8 pf =
c8051f91x-c8051f90x 190 rev. 1.3 19.4. special function register s for selecting and confi guring the system clock the clocking sources on c8051f91x-c8051f90x device s are enabled and configured using the oscicn, oscicl, oscxcn and the smartclo ck internal registers. see section ?20. smartclock (real time clock)? on page 193 for smartclock register descriptions. th e s ystem clock source for the mcu can be selected using the clksel register. to minimize active mode current, the oneshot timer which sets flash read time should by bypassed when the system clock is greater than 10 mhz. see the flscl register desc ription for details. the clock selected as the system cloc k can be divided by 1, 2, 4, 8, 16 , 32, 64, or 128. when switching between two clock divide values, the transition may ta ke up to 128 cycles of th e undivided clock source. the clkrdy flag can be polled to determine when the new clock divide value has been applied. the clock divider must be set to "divide by 1" when entering suspend or sleep mode. the system clock source may also be switched on-the -f ly. the switchover takes effect after one clock period of the sl ower oscillator. sfr page = all pages; sfr address = 0xa9 sfr definition 19.1. clksel: clock select bit 7 6 5 4 3 2 1 0 name clkrdy clkdiv[2:0] clksel[2:0] type r r/w r/w r/w r/w r/w r/w r/w reset 00110100 bit name function 7 clkrdy system clock divider clock ready flag. 0: the selected clock divide setting has no t been applied to the system clock. 1: the selected clock divide setting has been applied to the system clock. 6:4 clkdiv[2:0] system clock divider bits. selects the clock division to be applie d to the undivided system clock source. 000: system clock is divided by 1. 001: system clock is divided by 2. 010: system clock is divided by 4. 011: system clock is divided by 8. 100: system clock is divided by 16. 101: system clock is divided by 32. 110: system clock is divided by 64. 111: system clock is divided by 128. 3 unused unused. read = 0b. must write 0b. 2:0 clksel[2:0] system clock select. selects the oscillator to be used as the undivided system clock source. 000: precision internal oscillator. 001: external oscillator. 011: smartclock oscillator. 100: low power oscillator. all other values reserved.
c8051f91x-c8051f90x rev. 1.3 191 sfr page = 0x0; sfr address = 0xb2 note: read-modify-write operations such as orl and anl must be used to set or clear the enable bit of this register. sfr page = 0x0; sfr address = 0xb3 sfr definition 19.2. oscicn: internal os cillator control bit 7 6 5 4 3 2 1 0 name ioscen ifrdy reserved [5:0] type r/w r r/w r/w r/w r/w r/w r/w reset 0 0 varies varies varies varies varies varies bit name function 7 ioscen internal oscill at or enable. 0: internal oscillator disabled. 1: internal oscillator enabled. 6 ifrdy internal oscillator frequency ready flag. 0: internal oscillator is not r unning at its programmed frequency. 1: internal oscillator is runn ing at it s programmed frequency. 5:0 reserved reserved. must perform read-modify-write. sfr definition 19.3. oscicl: internal oscillator calibration bit 7 6 5 4 3 2 1 0 name sse oscicl [6:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 varies varies varies var ies varies varies varies bit name function 7 sse spread spectrum enable. 0: spread spectrum clock dithering disabled. 1: spread spectrum clock dithering enabled. 6:0 oscicl internal oscillator calibration. factory calibrated to obtain a frequency of 24.5 mhz. incrementing this register decreases the oscillator frequency and de crementing this regi ster increases the oscillator frequency. the step size is approximately 1% of the calibra ted frequency. the recommended calibration frequency range is between 16 and 24.5 mhz.
c8051f91x-c8051f90x 192 rev. 1.3 sfr page = 0x0; sfr address = 0xb1 sfr definition 19.4. oscxcn: external oscillator control bit 7 6 5 4 3 2 1 0 name xclkvld xoscmd[2:0] reserved xfcn[2:0] type r r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 xclkvld external oscilla tor v alid flag. provides external oscillator status and is valid at all times for a ll modes of operation except external cmos clock mode and external cmos clock mode with divide by 2. in these modes, xclkvld always returns 0. 0: external oscillator is unus ed or not yet stable. 1: external oscillator is running and stable. 6:4 xoscmd external oscillator mode bits. configures the external oscillato r circuit to the selected mode. 00x: external oscillat or circuit disabled. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mode w ith divide by 2 stage. 3 reserved reserved. read = 0b. must write 0b. 2:0 xfcn external oscillator frequency control bits. controls the external oscillator bias current. 000-111: see ta b l e 19.1 on page 187 (crystal mode) or ta b l e 19.2 on page 188 (rc or c mode) for recommended settings.
c8051f91x-c8051f90x rev. 1.3 193 20. smartclock (real time clock) c8051f91x-c8051f90x devices include an ultra lo w power 32-bit smartclock peripheral (real time clock) with alarm. the smartclock has a dedicated 32 khz oscillator that can be configured for us e with or without a crystal. no external resistor or loading capacitors are required. the on-chip loading capacitors are programmable to 16 discrete levels allowing compatibility with a wide range of crystals. the smartclock can operate directly from a 0.9?3.6 v battery voltage and remains operational even when the de vice goes into its lowest power down mode. on ?f912 and ?f902 devices, the smartclock output can be buffered and routed to a gpio pin to provide an accurate, low frequency clock to other devices while the mcu is in its lowe st power down mode ( see ?pmu0md: power management unit mode? on page 156 for more details). ?f912 and ?f902 devices also support an ultra low power internal lfo that reduces sleep mo de current. the smartclock allows a maximum of 36 hour 32-bit independent time-keeping when used with a 3 2.768 khz watch crystal. the smartclock provides an alarm and missing smartclock events, which cou ld be used as reset or wakeup sources. see section ?18. reset sources? on page 177 and section ?14. power management? on page 149 for details on reset sources and low power mode wake-up sources, respectively. figure 20.1. smartclock block diagram smartclock oscillator smartclock cip-51 cpu xtal4 xtal3 rtc0cn capturen rtc0xcf rtc0xcn alarmn rtc0key rtc0adr rtc0dat interface registers internal registers smartclock state machine wake-up 32-bit smartclock timer programmable load capacitors power/ clock mgmt interrupt rtc0pin rtcout buffered clock output and lfo only available on ?f912 and ?f902 devices. lfo
c8051f91x-c8051f90x 194 rev. 1.3 20.1. smartclock interface the smartclock interface consists of three re gisters: rtc0key, rtc0adr, and rtc0dat. these interface registers are located on the cip-51?s sfr map and provide access to the smartclock internal registers listed in ta b l e 20.1 . the smartclock internal registers can only be accessed indirectly through the smartclock interface. 20.1.1. smartclock lock and key functions the smartclock interface is protected with a lock and key function. the smartclock lock and key register (rtc0key) must be writte n with the correct key co des, in sequence , before writes and reads to rtc0adr and rtc0dat may be performed. the key codes are: 0xa5, 0xf1. there are no timing restrictions, but the key codes must be written in order. if the key codes are written out of order, the wrong codes are written, or an indirect register read or write is attempted while th e interface is locked, the smartclock interface will be disabled, and th e rtc0adr and rtc0dat registers will become inaccessible until the next system reset. once th e smartclock interface is unlocked, software may perform any number of accesses to the smartclock registers until the inte rface is re-locked or the device is reset. any write to rtc0key wh ile the smartclock inte rface is unlock ed will re-lock the interface. reading the rtc0key regist er at any time will provide the smar tclock inte rface status and will not interfere with the sequen ce that is being wr itten. the rtc0key regi ster description in sfr definition 20.1 lists the definition of each status code. table 20.1. smartclock internal registers smartclock address smartclock register register name description 0x00?0x03 capturen smartclock capture r egisters four registers used for setting the 32-bit smar tclock timer or reading its current value. 0x04 rtc0cn smartclock control re gister controls the operation of the sma rtclock state machine. 0x05 rtc0xcn smartclock oscillator c ontrol register controls the operation of the smartclock oscillator . note: some bits in this register are only available on ?f912 and ?f902 devices. 0x06 rtc0xcf smartclock oscillator co nfiguration register controls the value of the progammable osci llator load capacitance and enables/disables autostep. 0x07 rtc0pin smartclock pin co nfiguration register forces xtal3 and xtal4 to be internally sh orted. note: this register also contains other reserved bits which should not be modified. 0x08?0x0b alarmn smartclock alarm r egisters four registers used for setting or reading the 32- bit smartclock alarm value.
c8051f91x-c8051f90x rev. 1.3 195 20.1.2. using rtc0adr and rtc0dat to access smartclock internal registers the smartclock internal registers can be read and written using rtc0adr and rtc0dat. the rtc0adr register selects the smartclo ck internal register th at will be targeted by subsequent reads or writes. recommended instruction timing is provided in this section. if the recommended instruction timing is not followed, then busy (rtc0adr.7) should be checked prior to each read or write operation to make sure the smartclock interface is not busy perfor ming the previous read or write operation. a smartclock write operation is init iated by writing to the rtc0dat register. below is an example of writing to a smartclock internal register. 1. poll busy (rtc0adr.7) until it returns 0 or follow recommended instruction timing. 2. write 0x05 to rtc0adr. this selects the in te rnal rtc0cn register at smartclock address 0x05. 3. write 0x00 to rtc0dat. this operation wr ites 0x00 to the inter nal rtc0cn register. a smartclock read operation is initiated by setting the smar tclock interface busy bit. this transfers the contents of the internal register selected by rtc0adr to rtc0dat. the tr ansferred data will remain in rtc0dat until the next read or write operation. below is an example of reading a smartclock internal register. 1. poll busy (rtc0adr.7) until it returns 0 or follow recommended instruction timing. 2. write 0x05 to rtc0adr. this selects the in te rnal rtc0cn register at smartclock address 0x05. 3. write 1 to busy. this initiates the tr ansfer of data from rtc0cn to rtc0dat. 4. poll busy (rtc0adr.7) until it returns 0 or follow recommend in struction timing. 5. read data from rtc0dat. this data is a copy of the rtc0cn register. note: the rtc0adr and rtc0dat registers will retain their state upon a device reset. 20.1.3. rtc0adr short strobe feature reads and writes to indirect smart clock registers normally take 7 system clock cycles. to minimize the indirect register access time, the short strobe feat ure decreases the read and write access time to 6 system clocks. the short strobe feature is automat ically enabled on reset and can be manually enabled/disabled using the short (rtc0adr.4) control bit. recommended instruction timing for a single re gister read with short strobe enabled: mov rtc0adr, #095h nop nop nop mov a, rtc0dat recommended instruction timing for a single register write with short strobe enabled: mov rtc0adr, #095h mov rt c0dat, #000h nop 20.1.4. smartclock interface autoread feature when autoread is enabled, each read from rtc0dat initiates the next indirect read operation on the smartclock internal register selected by rtc0adr. software should set the busy bit once at the beginning of each series of consecutive reads. softwa re should follow recommended instruction timing or check if the smartclock interface is busy prior to reading rtc0dat. autoread is enabled by setting autord (rtc0adr.6) to logic 1.
c8051f91x-c8051f90x 196 rev. 1.3 20.1.5. rtc0adr autoincrement feature for ease of reading and writing the 32-bit c apture and alarm values, rtc0adr automatically increments after each read or write to a capturen or alarmn register. this speeds up the process of setting an alarm or reading the current smartclock timer value. autoincrement is always enabled. recommended instruction timing for a multi-byte regist er read with short strobe and auto read enabled: mov rtc0adr, #0d0h nop nop nop mov a, rtc0dat nop nop mov a, rtc0dat nop nop mov a, rtc0dat nop nop mov a, rtc0dat recommended instruction timing for a multi-by te re gister write with short strobe enabled: mov rtc0adr, #010h mov rt c0dat, #05h nop mov rtc0dat, #06h nop mov rtc0dat, #07h nop mov rtc0dat, #08h nop
c8051f91x-c8051f90x rev. 1.3 197 sfr page = 0x0; sfr address = 0xae sfr definition 20.1. rtc0key: smartclock lock and key bit 7 6 5 4 3 2 1 0 name rtc0st[7:0] type r/w reset 00000000 bit name function 7:0 rtc0st smartclock interface lock/key and status. locks/unlocks the smartclock interface when written. pro vides lock status when read. read: 0x00: smar tclock interface is locked. 0x01: smar tclock interface is locked. first key code (0xa5) has been written, waiting for second key code. 0x02: smar tclock interface is unlocked. first and second key codes (0xa5, 0xf1) have been written. 0x03: smar tclock interface is disabled until the next system reset. write: when rtc0st = 0x00 (locked), writing 0xa5 followed by 0xf1 unlocks the sm artclock interface. when rtc0st = 0x01 (waiting for second key code), writing any value other than the sec ond key code (0xf1) will change rtc0state to 0x03 and disable the smartclock interface until the next system reset. when rtc0st = 0x02 (unlocked), an y write to rtc0key will lock the smart - clock interface. when rtc0st = 0x03 (disabled), writes to rtc0key have no effect.
c8051f91x-c8051f90x 198 rev. 1.3 sfr page = 0x0; sfr address = 0xac sfr page= 0x0; sfr address = 0xad sfr definition 20.2. rtc0adr: smartclock address bit 7 6 5 4 3 2 1 0 name busy autord short addr[3:0] type r/w r/w r r/w r/w reset 00000000 bit name function 7 busy smartclock interface busy indicator. indicates smartclock interface status. writin g 1 to this bit initiates an indirect read. 6 autord smartclock interface autoread enable. enables/disables autoread. 0: autoread disabled. 1: autoread enabled. 5 unused unused. read = 0b; write = don?t care. 4 short short strobe enable. enables/disables the short strobe feature. 0: short strobe disabled. 1: short strobe enabled. 3:0 addr[3:0] smartclock indirect register address. sets the currently selected smartclock register. see ta b l e 20.1 for a listing of all smartclock indirect registers. note: the addr bits increment after each indirect read/write operation that targets a capturen or alarmn internal smartclock register. sfr definition 20.3. rtc0dat: smartclock data bit 7 6 5 4 3 2 1 0 name rtc0dat[7:0] type r/w reset 00000000 bit name function 7:0 rtc0dat smartclock data bits. holds data transferred to/from the internal smartclock register selected by r tc0adr. note: read-modify-write instructions (orl, anl, etc.) should not be used on this register.
c8051f91x-c8051f90x rev. 1.3 199 20.2. smartclock clocking sources the smartclock peripheral is clocked from its ow n timebase, independent of the system clock. the smartclock timebase can be derived from an external cmos clock, the internal lfo (?f912 and ?f902 devices only), or the smartclock o scillator circuit, which has two mode s of operation: crystal mode, and self-oscillate mode. the osc illation frequency is 32.768 khz in crystal mode and can be programmed in th e range of 10 khz to 40 khz in self-oscillate mode. the internal lfo frequency is 16.4 khz 20%. the frequency of the smar tclock oscilla tor can be measured with respect to another oscillator using an on- chip timer. see section ?25. timers? on page 274 for more information on how this can be accomplished. note: the smartclock timebase can be selected as the system clock and routed to a port pin. see section ?19. clocking sources? on page 185 for information on selecting the system clock sour ce and section ?21. port input/output? on page 210 for information on how to route the system clock to a port pin. on ?f912 and ?f902 devices, the smartclock timebase can be routed to a port pin while the device is in its ultra low power sleep mode. see the pmu0md register description for details. 20.2.1. using the smartclock oscillator with a crystal or external cmos clock when using crystal mode, a 32.768 khz crystal should be connected between xtal3 and xtal4. no o ther external components are required. the following steps show how to start the smartclock crystal oscillator in software: 1. set smartclock to crystal mode (xmode = 1). 2. disable automatic gain contro l (agcen) and enable bias doub ling (biasx2) for fast crystal startup. 3. set the desired loading capacitance (rtc0xcf). 4. enable power to the smartclock oscillato r circuit (rtc0en = 1). 5. wait 20 ms. 6. poll the smartclock clock valid bit (clkvl d) until the crystal oscillator stabilizes. 7. poll the smartclock load capacitance ready bit (loadr dy) until the load capacitance reaches its programmed value. 8. enable automatic gain cont rol (agcen) and disable bias doubling (biasx2) for maximum power savings. 9. enable the smartclock missing clock detector . 10. wait 2 ms. 11. clear the pmu0cf wake-up source flags. in crystal mode, the smartclock osc illator may be driven by an extern al cmos clock. the cmos clock should be applied to xtal3. xtal4 should be left floating. the input low voltage (vil) and input high voltage (vih) for xtal3 when used with an external cmos clock are 0.1 and 0.8 v, respectively. the smar tclock oscillator should be conf igured to its lowest bias settin g with agc disabled. the clkvld bit is indeterminate when using a cmos clock, however, the oscfail bit may be checked 2 ms after smar tclock oscillator is powered on to ensu re that there is a valid clock on xtal3.
c8051f91x-c8051f90x 200 rev. 1.3 20.2.2. using the smartclock oscillator in self-oscillate mode when using self-oscillate mode, the xtal3 and xtal 4 pins should be short ed together. the rtc0pin register can be used to internally short xtal3 and xtal4. the following steps show how to configure smartclock for use in self-oscillate mode: 1. set smartclock to self-osc illate mode (xmode = 0). 2. set the desired oscillation frequency: for oscillation at about 20 khz, set biasx2 = 0. for oscillation at about 40 khz, set biasx2 = 1. 3. the oscillator starts oscillating instantaneously. 4. fine tune the oscillation frequency by adjusting the load cap acitance (rtc0xcf). 20.2.3. using the low frequency oscillator (lfo) the low frequency oscillator provides an ultra low power, on-chip clo ck source to the smartclock. the typical frequency of oscillation is 16.4 khz 20%. no external components are required to use the lfo and the xtal3 and xtal4 pins do not need to be shorted together. the lfo is only available on ?f912 and ?f902 devices. the following steps show how to configure smartclock for use with the lfo: 1. enable and select the low fr equenc y oscillator (lfoen = 1). 2. the lfo starts oscillating instantaneously. when the lfo is enabled, the smartclock oscillator increm ent s bit 1 of the 32-bit timer (instead of bit 0). this effectively multiplies the lfo frequency by 2, making the rtc timebase behave as if a 32.768 khz cr ystal is connected at the output.
c8051f91x-c8051f90x rev. 1.3 201 20.2.4. programmable load capacitance the programmable lo ad capacitance has 16 values to support crystal oscillators with a wide range of recommended load capacitance. if automatic load capacitance stepping is enabled, the crystal load capacitors start at the smallest se tting to allow a fast startup time, then slowly increase the capacitance until the final programmed value is reached. the final programmed loading capacitor value is specified using the loadcap bits in the rtc0xcf register. th e loadcap setting specifies the amount of on-chip load capacitance and does not include any stray pc b capacitance. once the final programmed loading capacitor value is reached, the loadrdy fl ag will be set by hardware to logic 1. when using the smartclock oscillato r in self-oscillate mode, the prog rammable load capacitance can be used to fine tune the oscillation fr equency. in most cases, increasing the load capacitor value will result in a decrease in oscillation frequency. ta b l e 20.2 shows the crystal load capaci t ance for various settings of loadcap. table 20.2. smartclock load capacitance settings loadcap crystal load capacitance equivalent capacitance seen on xtal3 and xtal4 0000 4.0 pf 8.0 pf 0001 4.5 pf 9.0 pf 0010 5.0 pf 10.0 pf 0011 5.5 pf 11.0 pf 0100 6.0 pf 12.0 pf 0101 6.5 pf 13.0 pf 0110 7.0 pf 14.0 pf 0111 7.5 pf 15.0 pf 1000 8.0 pf 16.0 pf 1001 8.5 pf 17.0 pf 1010 9.0 pf 18.0 pf 1011 9.5 pf 19.0 pf 1100 10.5 pf 21.0 pf 1101 11.5 pf 23.0 pf 1110 12.5 pf 25.0 pf 1111 13.5 pf 27.0 pf
c8051f91x-c8051f90x 202 rev. 1.3 20.2.5. automatic gain control (crystal mode only) and smartclock bias doubling automatic gain control allows the sm artclock oscillator to trim the osc illation amplitude of a crystal in order to achieve the lowest possible power consumpt ion. automatic gain control automatically detects when the oscillation amplitude has r eached a point where it safe to redu ce the drive current, therefore, it may be enabled during crystal startup. it is reco mmended to enable automatic gain control in most systems which use the smartclock oscillator in crystal mode. the following are recommended crystal specifications and operating conditions when automatic gain control is enabled: ? esr < 50 k ? load capacitance < 10 pf ? supply voltage < 3.0 v ? temperature > ?20 c when using automatic gain control, i t is recommended to perform an osc illation robustness test to ensure that the chosen crystal will oscillate under the worst case condition to which th e system will be exposed. the worst case condition that shou ld result in the least robust os cillation is at the following system conditions: lowest temperature, highest supply voltag e, highest esr, highest load capacitance, and lowest bias current (agc enabled, bias double disabled). to perform the oscillation robustness test, the smartc loc k oscillator should be enabled and selected as the system clock source. next, the sysclk signal should be routed to a po rt pin configured as a push-pull digital output. the positive duty cy cle of the output cloc k can be used as an indicator of oscillation robustness. as shown in figure 20.2 , duty cycles less than 55% indicate a robust oscillation. as the duty cycle approaches 60%, oscillation beco mes less reliable and the risk of cl ock failure increases. increasing the bias current (by disabling agc) will always improve oscilla tion robustness and w ill reduce the output clock?s duty cycle. this test should be performed at th e worst case system conditions, as results at very low temperatures or high supply voltage will vary from results taken at room temperature or low supply voltage. figure 20.2. interpreting oscillation robustness (duty cycle) test results as an alternative to performing the oscilla tion robustness test, automatic ga in control may be disabled at the cost of increased power consumption (approximately 200 na). disabling automatic gain control will provide the cry stal oscillator with higher immunity against exte rnal factors which may lead to clock failure. automatic gain control must be di sabled if using the smartclock os cillator in self-oscillate mode. ta b l e 20.3 shows a summary of the oscillator bias settings . the smar tclock bias doubling feature allows the self-oscillation frequency to be inc reased (alm ost doubled) and allo ws a higher crystal drive strength in crystal mode. high crystal drive strength is re commended when the crystal is exposed to poor environmental conditions such as excessive moistu re. smartclock bias doublin g is enabled by setting biasx2 (rtc0xcn.5) to 1. duty cycle 25% 55% 60% safe operating zone low risk of clock failure high risk of clock failure
c8051f91x-c8051f90x rev. 1.3 203 . table 20.3. smartclock bias settings mode setting power co nsumption crystal bias double off, agc on lowest 600 na bias double off, agc off low 800 na bias double on, agc on high bias double on, agc off highest self-oscillate bias double off low bias double on high
c8051f91x-c8051f90x 204 rev. 1.3 20.2.6. missing smartclock detector the missing smartclock detector is a one-shot circ uit enabled by setting mc lken (rtc0cn.6) to 1. when the smartclock missing clock detector is enabled, oscfail (rtc 0cn.5) is set by hardware if smartclock oscillator remains high or low for more than 100 s. a smartclock missing clock detector timeout can trigger an interrupt, wake the device from a low power mo de, or reset the device. see section ?12. interrupt hand le r? on page 127 , section ?14. power management? on page 149 , and section ?18. reset sources? on page 177 for more information. note: the smartclock missing clock detector should be disabled when making changes to the oscillator settings in rtc0xcn. 20.2.7. smartclock oscillator crystal valid detector the smartclock oscillator crystal valid detector is an oscillation amplit ude detector circuit used during crystal startup to dete rmine when oscillation has started and is ne arly stable. the output of this detector can be read from the clkvld bit (rtx0xcn.4). notes: ? the clkvld bit has a blanking interval of 2 ms. during the first 2 ms after turning on the crystal oscillator, the out - put of clkvld is not valid. ? this smartclock crystal valid detector (clkvld) is not intended for detecting an oscillator failure. the missing smartclock detector (clkfail) should be used for this purpose . 20.3. smartclock timer and alarm function the smartclock timer is a 32-bit counter that, when running (rtc0tr = 1), is incremented every smartclock oscillator cycle. the timer has an alarm f unction that can be set to generate an interrupt, wake the device from a low power mode, or reset the device at a specific time. see section ?12. interrupt handler? on page 127 , section ?14. power management? on page 149 , and section ?18. reset sources? on page 177 for more information. the smartclock timer includes an auto reset feature, which automatically resets the timer to zero one smartclock cycle after the alarm signal is deassert ed. when using auto reset, the alarm match value should always be set to 2 counts less than the desired match value. when using the lfo in combination with auto reset, the right-justified alarm match value should be set to 4 counts less than the desired match value. auto reset can be enabled by writing a 1 to alrm (rtc0cn.2). 20.3.1. setting and reading the smartclock timer value the 32-bit smartclock timer can be set or read using the six capturen internal registers. note that the timer does not need to be stopped before reading or setting its value. the following steps can be used to set the timer value: 1. write the desired 32-bit set value to the capturen registers. 2. write 1 to rtc0set. this will transfer the co ntent s of the capturen registers to the smart - clock timer. 3. operation is complete when rtc0set is cleared to 0 by hardware. the following steps can be used to read the current timer value: 1. write 1 to rtc0cap. this will tr ansfer the content s of the timer to the capturen registers. 2. poll rtc0cap until it is cle ared to 0 by hardware. 3. a snapshot of the timer value can be read from the capturen registers
c8051f91x-c8051f90x rev. 1.3 205 20.3.2. setting a smartclock alarm the smartclock alarm function compares the 32-bit value of smartclock timer to the value of the alarmn registers. an alarm event is triggered if the sm artclock timer is equal to the alarmn registers. if auto reset is enabled, the 32-b it timer will be cleared to zero o ne smartclock cycle after the alarm event. the smartclock alarm event can be configured to reset the mcu, wake it up from a low power mode, or ge nerate an interrupt. see section ?12. interrupt hand ler? on page 127 , section ?14. power management? on page 149 , and section ?18. reset sources? on page 177 for more information. the following steps can be used to set up a smartclock alarm: 1. disable smartclock alarm events (rtc0aen = 0). 2. set the alarmn registers to the desired value. 3. enable smartclock alar m events (rtc0aen = 1). notes: ? the alrm bit, which is used as the smartclock alar m event flag, is cleared by disabling smartclock alarm events (rtc0aen = 0). ? if autoreset is disabled, disabling (rtc0aen = 0) then re-enabling alarm events (rtc0aen = 1) after a smar tclock alarm without modifying alarmn registers will automatically schedule the next alarm after 2^32 smartclock cycles (approximately 36 hours using a 32.768 khz crystal). ? the smartclock alarm event flag will remain asserted for a maximum of one smartclock cycle. see section ?14. power management? on page 149 for information on how to capture a smartclock alarm event using a flag which is not automatically cleared by hardware. 20.3.3. software considerations for using the smartclock timer and alarm the smartclock timer and alarm have two operating modes to suit varying applications. the two modes are described below: mode 1: the first mode uses the smartclock timer as a perpet ual tim ebase which is never reset to zero. every 36 hours, the timer is allowed to overflow without being stopped or disrupted. the alarm interval is software managed and is added to the alrmn registers by software after each alarm. this allows the alarm match value to always stay ahead of the timer by one software managed interval. if software uses 32-bit unsigned addition to increment the alarm match value, then it does not need to handle ov erflows since both the timer and the alarm match value will overflow in the same manner. this mode is ideal for applications which have a long alarm interval (e.g., 24 or 36 hours) and/or have a n eed for a perpetual timebase. an example of an application that needs a perpetual timebase is one whose wake-up interval is constant ly changing. for these applications, software can keep track of the number of timer overflows in a 16-bit variable, extendi ng the 32-bit (36 hour) timer to a 48-bit (272 year) perpetual timebase. mode 2: the second mode uses the smartclock timer as a general pu rpose up counter which is auto reset to zero by hardware after each alarm. the alarm interval is managed by hardware and stored in the alrmn registers. software only needs to set the alarm interval once during device initializ ation. after each alarm, software should keep a count of the number of alarms that have occurred in order to keep track of time. this mode is ideal for applications that require minimal software intervention and/or have a fixed alarm interval. this mode is the most power effici ent since it requires less cpu time per alarm.
c8051f91x-c8051f90x 206 rev. 1.3 smartclock address = 0x04 internal register definition 20.4. rtc0cn: smartclock control bit 7 6 5 4 3 2 1 0 name rtc0en mclken oscfail rtc0tr rtc0aen alrm rtc0set rtc0cap type r/w r/w r/w r/w r/w r/w r/w r/w reset 00varies00000 bit name function 7 rtc0en smartclock enable. enables/disables the smartclock osc illator and associat ed bias current s. 0: smartclock oscillator disabled. 1: smartclock oscillator enabled. 6 mclken missing smartclock detector enable. enables/disables the missing smartclock detector. 0: missing smartclock detector disabled. 1: missing smartclock detector enabled. 5 oscfail smartclock oscillator fail event flag. set by hardware when a missing smartclock detector timeout occurs. must be clea red by software. the value of this bit is not defined when the smartclock oscillator is disabled. 4 rtc0tr smartclock timer run control. controls if the smartclock timer is running or stopped (holds current value). 0: smartclock timer is stopped. 1: smartclock timer is running. 3 rtc0aen smartclock alarm enable. enables/disables the smartclock alarm fu nction. also clears the alrm flag. 0: smartclock alarm disabled. 1: smartclock alarm enabled. 2 alrm smartclock alarm event flag and auto reset enable. reads return the state of the ala rm event flag. writes enable/disable the auto reset function. read: 0: smartclock alarm eve nt flag is de-asserted. 1: smartclock alarm event flag is asserted. write: 0: disable auto reset. 1: enable auto reset. 1 rtc0set smartclock timer set. writing 1 initiates a smartclock timer set oper atio n. this bit is cleared to 0 by hard - ware to indicate that the ti me r set operation is complete. 0 rtc0cap smartclock timer capture. writing 1 initiates a smartclock timer capture op eration. this bit is cleared to 0 by hardware to indicate that the timer capture operation is complete. note: the alrm flag will remain asserted for a maximum of one smartc lock cycle. see section ?power management? on page 149 for information on how to capture a smartclock alarm event using a flag which is not automatically cleared by hardware.
c8051f91x-c8051f90x rev. 1.3 207 smartclock address = 0x05 internal register definition 20.5. rtc0xcn: smartclock oscillator control bit 7 6 5 4 3 2 1 0 name agcen xmode biasx2 clkvld lfoen type r/wr/wr/wrrrrr reset 00000000 bit name function 7 agcen smartclock oscillator automatic gain control (agc) enable. 0: agc disabled. 1: agc enabled. 6 xmode smartclock oscillator mode. selects crystal or self oscillate mode. 0: self-oscillate mode selected. 1: crystal mode selected. 5 biasx2 smartclock oscillator b ias double enable. enables/disables the bia s double feature. 0: bias double disabled. 1: bias double enabled. 4 clkvld smartclock oscillator crystal valid indicator. indicates if oscillation amplitude is su f ficient for maintaining oscillation. 0: oscillation has not s tarted or oscillation amplitude is too low to maintain oscillation. 1: sufficient oscillati on amplitude detected. 3 lfoen low frequency oscillator enable and select. overrides xmode and selects the internal low frequenc y oscillator (lfo) as the smartclock oscillator sour ce. only available on ?f912 and ?f902 devices. 0: xmode determines smartclock oscillator source. 1: lfo enabled and selected as s martclock oscillator source. 2:0 unused unused. read = 000b; write = don?t care.
c8051f91x-c8051f90x 208 rev. 1.3 smartclock address = 0x06 smartclock address = 0x07 internal register definition 20.6. rtc0xcf: smartclock osc illator configuration bit 7 6 5 4 3 2 1 0 name autostp loadrdy loadcap type r/w r r r r/w reset 0 0 0 0 varies varies varies varies bit name function 7 autostp automatic load capacitance stepping enable. enables/disables automatic load capacitance stepping. 0: load capacitance stepping disabled. 1: load capacitance stepping enabled. 6 loadrdy load capacitance ready indicator. set by hardware when the load capacitance matches the programmed value. 0: load capacitance is currently stepping. 1: load capacitance has reached it programmed value. 5:4 unused unused. read = 00b; write = don?t care. 3:0 loadcap load capacitance programmed value. holds the user?s desired value of the load capacitance. see ta b l e 20.2 on page 201 . internal register definition 20.7. rtc0pin: smartclock pin configuration bit 7 6 5 4 3 2 1 0 name rtc0pin type w r/w r/w r/w r/w r/w r/w r/w reset 0 varies varies varies var ies varies varies varies bit name function 7 rtc0pin smartclock pin configuration. 0: xtal3 and xtal4 in their normal configuration. 1: xtal3 and xtal4 internally short ed for use with self oscillate mode. 6:0 reserved reserved. read = varies. software should not modify the value of these bits. to change the r tc0pin setting, the entire regi ster contents should be read, modified, then rewritten.
c8051f91x-c8051f90x rev. 1.3 209 smartclock addresses: capture0 = 0x00; capture1 = 0x01; capture2 =0x02; capture3: 0x03. smartclock addresses: alarm0 = 0x08; alarm1 = 0x09; alarm2 = 0x0a; alarm3 = 0x0b internal register definition 20.8. capturen: smartclock timer capture bit 7 6 5 4 3 2 1 0 name capture[31:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 capture[31:0] smartclock timer capture. these 4 registers (capture3?capture0) are used to read or set the 32-bit smar tclock timer. data is transferred to or from the smartclock timer when the rtc0set or rtc0cap bits are set. note: the least significant bit of the timer capture value is in capture0.0. internal register definition 20.9. alarmn: smartclock al arm programmed v alue bit 7 6 5 4 3 2 1 0 name alarm[31:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 alarm[31:0] smartclock alarm programmed value. these 4 registers (alarm3?alarm0) are use d to set an alarm event for the smartclock timer. the smartclock alarm should be disabled (rtc0aen=0) when updating these registers. note: the least significant bit of the alarm programmed value is in alarm0.0.
c8051f91x-c8051f90x 210 rev. 1.3
c8051f91x-c8051f90x rev. 1.3 210 21. port input/output digital and analog resources are available through 16 i/o pins. port pins are organized as three byte-wide ports. port pins p0.0?p1.6 can be de fined as digital or analog i/o. digital i/o pins can be assigned to one of the internal digital resources or used as general purpose i/o (gpio). analog i/o pins are used by the internal analog resources. p2.7 can be used as gpio and is shared with the c2 interface data signal (c2d). see section ?27. c2 interface? on page 316 for more details. the designer has complete control over which digital an d analog functions are as signed to individual port pins, limited only by the nu mber of physical i/o pins. this resour ce assignment flexibility is achieved through the use of a priority crossbar decoder. see section 21.3 for more information on the crossbar. all port i/os are 5 v tolerant when used as digital inputs or open-d rain outputs. for port i/os configured as push-pull outputs, current is sourced from the vdd/dc+ supply. port i/os used for analog functions can operate up to the vdd/dc+ supply voltage. see section 21.1 for more information on port i/o operating modes and the electrical specifications chap ter for detailed electrical specifications. figure 21.1. port i/o functional block diagram xbr0, xbr1, xbr2, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 port match p0mask, p0mat p1mask, p1mat uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 7 pca 4 cp0 cp1 outputs spi0 spi1 4 p1 i/o cells p1.0 p1.6 7 (port latches) p0 (p0.0-p0.7) (p1.0-p1.6) 8 7 p1 p2 i/o cell p2 (p2.7) 1 1 pnmdout, pnmdin registers p2.7 to analog peripherals (adc0, cp0, and cp1 inputs, vref, iref0, agnd) external interrupts ex0 and ex1
c8051f91x-c8051f90x 211 rev. 1.3 21.1. port i/o modes of operation port pins p0.0?p1.6 use the port i/o cell shown in figure 21.2 . each port i/o cell can be configured by software for analog i/o or digital i/o using the pnmdin re g isters. on reset, all port i/o cells default to a dig - ital high impedance state with weak pull-ups enabled. 21.1.1. port pins configured for analog i/o any pins to be used as comparator or adc input, external oscillator input/output, or agnd, vref, or cur - rent reference output should be co nfigu red for analog i/o (pnmdin.n = 0). when a pin is configured for a nalog i/o, its weak pullup and digital receiver are disa bled. in most cases, software should also disable the digital output drivers. port pins configured for analog i/o will always read back a value of 0 regardless of the actual voltage on the pin. configuring pins as analog i/o saves power and isolates th e port pin from digital interference. port pins configured as digital inputs may still be used by analog peripherals; howe ver, this practice is not recom - mended and may result in measurement errors. 21.1.2. port pins configured for digital i/o any pins to be used by digital peripherals (uart, sp i, smbus, etc.), external digital event capture func - tions, or as gpio should be co nfigu red as digital i/o (pnmdin.n = 1). for digital i/o pins, one of two output mo des (push-pull or open-drain) must be selected using the pnmdout registers. push-pull outputs (pnmdout.n = 1) drive the port pad to the vdd/dc+ or gnd supply rails based on the o utput logic value of the port pin. open-drain output s have the high side driver disabled; therefore, they only drive the port pad to gnd wh en the output logic value is 0 and become high impedance inputs (both high and low drivers turned off) when the output logic value is 1. when a digital i/o cell is placed in the high impedance st at e, a weak pull-up transistor pulls the port pad to the vdd/dc+ supply voltage to ensure the digital input is at a defined logic state. weak pull-ups are dis - abled when the i/o ce ll is driven to gnd to minimize power c onsumption and may be globally disabled by setting weakpud to 1. the user must en sure that digital i/o are always in ternally or externally pulled or driven to a valid logic state. port pins configured for digital i/o always read back the logic state of the port pad, regardless of the output logic value of the port pin. figure 21.2. port i/o cell block diagram gnd vdd/dc+ vdd/dc+ (weak) port pad to/from analog peripheral pnmdin.x (1 for digital) (0 for analog) pn.x ? output logic value (port latch or crossbar) xbare (crossbar enable) pn.x ? input logic value (reads 0 when pin is configured as an analog i/o) pnmdout.x (1 for push-pull) (0 for open-drain) weakpud (weak pull-up disable)
c8051f91x-c8051f90x rev. 1.3 212 21.1.3. interfacing port i/o to 5 v and 3.3 v logic all port i/o configured for digital, open-drain operation are capable of interfacing to digital logic operating at a supply voltage higher than 4.5 v and less than 5.25 v. when the supply voltage is in the range of 1.8 to 2. 2 v, the i/o may also interface to digital logic operating between 3.0 to 3.6 v if the input signal frequency is less than 12.5 mhz or less than 25 mhz if the signal rise time (10% to 90%) is less than 1.2 ns. when op erating at a supply voltage above 2.2 v, the device should not interface to 3.3 v logic; however, interfac - ing to 5 v logic is permitted. an external pull-up resistor to the higher supply voltage is typically required for most systems. important note: ? when interfacing to a signal that is between 4.5 and 5.25 v, the maximum clock frequency that may be input on a gpio pin is 12.5 mhz. the exception to th is rule is when routing an external cmos clock to p0.3, in which case, a signal up to 25 mhz is valid as long as the rise time (10% to 90%) is shorter than 1.8 ns. ? when the supply voltage is less than 2.2 v and interf acing to a signal that is between 3.0 and 3.6 v, the maximum clock frequency that may be input on a gpio pin is 3.125 mhz. the exception to this rule is when routing an external cmos clock to p0.3, in which case, a signal up to 25 mhz is valid as long as the rise time (10% to 90%) is shorter than 1.2 ns. ? in a multi-voltage interface, the external pull-up resi stor should be sized to allow a current of at least 150 a to flow into the port pin when the suppl y voltage is between (vdd/dc+ plus 0.4 v) and (vdd/dc+ plus 1.0 v). once the port pad voltage in creases beyond this range, the current flowing into the port pin is minimal. ? these guidelines only apply to multi-voltage interfac es. port i/os may always interface to digital logic operating at the same supply voltage. 21.1.4. increasing port i/o drive strength port i/o output drivers support a high and low drive st rength; the default is low drive strength. the drive strength of a port i/o can be configured using the pndrv registers. see section ?4. electrical characteris - tics? on page 42 for the difference in output drive strength between the two modes. 21.2. assigning port i/o pins to analog and digital functions port i/o pins p0.0?p1.6 can be assigned to various a nalog, digital, and external interrupt functions. the port pins assuaged to analog functions should be conf igured for analog i/o and port pins assuaged to dig - ital or external interrupt functions should be configured for digital i/o. 21.2.1. assigning port i/o pins to analog functions ta b l e 21.1 shows all available analog function s that need port i/o assignments. port pins selected for these analog functions should have their digital dr iv ers disabled (pnmdout.n = 0 and port latch = 1) and their corresponding bit in pnskip set to 1. this reserves the pin for use by the analog function and does not allow it to be claimed by the crossbar. ta b l e 21.1 shows the potential mapping of port i/o to each analog function. table 21.1. port i/o assignment for analog functions analog function potentially as signable port pins sfr(s) used for assignme nt adc input p0.0?p1.6 adc0mx, pnskip comparator0 input p0.0?p1.6 cpt0mx, pnskip comparator1 input p0.0?p1.6 cpt1mx, pnskip
c8051f91x-c8051f90x 213 rev. 1.3 21.2.2. assigning port i/o pins to digital functions any port pins not assigned to analog functions may be assigned to digital functi ons or used as gpio. most digital functions rely on the crossbar for pin assi gnment; however, some digital functions bypass the crossbar in a manner similar to the analog functions listed above. port pins used by these digital func - tions and any port pins selected for use as gpio should have their corresponding bit in pnskip set to 1. ta b l e 21.2 shows all available digital functions and the potential mapping of port i/o to each digital function. 21.2.3. assigning port i/o pins to external digital event capture functions external digital event captur e functions can be used to trigger an interrupt or wake the device from a low power mode when a transition occurs on a digital i/o pin. the digital event capture functions do not require dedicated pins and will function on both gpio pins (pnskip = 1) and pi ns in use by the crossbar (pnskip = 0). external digital even capture functions cannot be used on pins configured for analog i/o. ta b l e 21.3 shows all available external digital event capture functions. voltage reference (vref0) p0.0 ref0cn, pnskip analog ground reference (agnd) p0.1 ref0cn, pnskip current reference (iref0) p0.7 iref0cn, pnskip external oscillator input (xtal1) p0.2 oscxcn, pnskip external oscillato r output (xtal2) p0.3 oscxcn, pnskip table 21.2. port i/o assignment for digital functions digital function potentially assignable port pins sfr(s) used for as signment uart0, spi1, spi0, smbus, cp0 an d cp1 outputs, sys - tem clock output, pca0, t imer0 and timer1 external inputs. any port pin available for assignment by the cro ssbar. this includes p0.0?p1.6 pins which have their pnskip bit set to 0. note: th e crossbar will always assign uart0 and spi1 pins to fixed locations. xbr0, xbr1, xbr2 any pin used for gpio p0.0?p1.6, p2.7 p0skip, p1skip table 21.3. port i/o assignment for external digital event capture functions digital function potentially assignable port pins sfr(s) used for as signment external interrupt 0 p0.0?p0.7 it01cf external interrupt 1 p0.0?p0.7 it01cf port match p0.0?p1.6 p0mask, p0mat p1mask, p1mat table 21.1. port i/o assignment for analog functions (continued) analog function potentially assignable port pins sfr(s) used for assignment
c8051f91x-c8051f90x rev. 1.3 214 21.3. priority crossbar decoder the priority crossbar decoder assigns a port i/o pin to each software selected digital function using the fixed peripheral priority order shown in figure 21.3 . the registers xbr0, xbr1, and xbr2 defined in sfr definition 21.1 , sfr definition 21.2 , and sfr definition 21.3 are used to select digital functions in the crossbar. the port pins available for assignment by th e crossbar include all port pins (p0.0?p1.6) which have their corresponding bit in pnskip set to 0. from figure 21.3 , the highest priority peripheral is uart0. if uart0 is selected in the crossbar (using the xbrn registers), then p0.4 and p0.5 will be ass igned to uart0. the next highest priority peripheral is spi1. if spi1 is selected in the cros sbar, then p1.0?p1.3 will be assigned to spi1. the user should ensure that the pins to be assigned by the crossbar have their pnskip bits set to 0. for all remaining digital functions selected in the crossbar, starting at the top of figure 21.3 going down, the least-significant unskipped, unassigned port pin(s) ar e assigne d to that function. if a port pin is already assigned (e.g. uart0 or spi1 pins), or if its pnskip bit is set to 1, then the crossbar will skip over the pin and find next available unskipped, unas signed port pin. all port pins used for analog functions, gpio, or dedicated digital functions such as the emif should have their pnskip bit set to 1. figure 21.3 shows the crossbar decoder priority with no po rt pins skipped (p0 skip, p1skip = 0x00); figure 21.4 shows the crossbar decoder priority with th e external oscillator pins (xtal1 and xtal2) skipped (p0skip = 0x0c). notes: ? the crossbar must be enabl ed (xbare = 1) before any port pin is used as a digital output. port output drivers are disabled while the crossbar is disabled. ? when smbus is selected in the crossbar, the pins associated with sda and scl will automatically be forced into ope n-drain output mode regardless of the pnmdout setting. ? spi0 can be operated in either 3-wire or 4-wire modes , depending on the state of the nssmd1-nssmd0 bits in register spi0cn. the nss signal is only routed to a po rt pin when 4-wire mode is selected. when spi0 is selected in the crossbar, the spi0 mode (3-wire or 4-wire) wi ll affect the pinout of all digital functions lower in pri - ority than spi0. ? for given xbrn, pnskip, and spincn register settings, one can determine the i/o pin-out of the device using figure 21.3 and figure 21.4 .
c8051f91x-c8051f90x 215 rev. 1.3 figure 21.3. crossbar priority decoder with no pins skipped vref agnd xtal1 xtal2 cnvstr iref0 c2d 012345670123456 7 sck (spi1) miso (spi1) mosi (spi1) nss* (spi1) (*4-wire spi only) sck (spi0) miso (spi0) mosi (spi0) nss* (spi0) (*4-wire spi only) cp0 cp0a cp1 cp1a /sysclk cex0 cex1 cex2 cex3 cex4 cex5 eci t0 t1 000000000000000x sda p0skip[0:7] scl rx0 sf signals pin i/o tx0 p2 p0 p1 p1skip[0:7]
c8051f91x-c8051f90x rev. 1.3 216 figure 21.4. crossbar priority decoder with crystal pins skipped vref agnd xtal1 xtal2 cnvstr iref0 c2d 012345670123456 7 sck (spi1) miso (spi1) mosi (spi1) nss* (spi1) (*4-wire spi only) sck (spi0) miso (spi0) mosi (spi0) nss* (spi0) (*4-wire spi only) cp0 cp0a cp1 cp1a /sysclk cex0 cex1 cex2 cex3 cex4 cex5 eci t0 t1 001100000000000x p2 p0 p1 p1skip[0:7] rx0 sf signals pin i/o tx0 sda p0skip[0:7] scl
c8051f91x-c8051f90x 217 rev. 1.3 sfr page = 0x0; sfr address = 0xe1 sfr definition 21.1. xbr0: port i/o crossbar register 0 bit 7 6 5 4 3 2 1 0 name cp1ae cp1e cp0ae cp0e syscke smb0e spi0e urt0e type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 cp1ae comparator1 asynchronous output enable. 0: asynchronous cp1 output unavailable at port pin. 1: asynchronous cp1 output routed to port pin. 6 cp1e comparator1 output enable. 0: cp1 output unavailable at port pin. 1: cp1 output routed to port pin. 5 cp0ae comparator0 asynchronous output enable. 0: asynchronous cp0 output unavailable at port pin. 1: asynchronous cp0 output routed to port pin. 4 cp0e comparator0 output enable. 0: cp1 output unavailable at port pin. 1: cp1 output routed to port pin. 3 syscke sysclk output enable. 0: sysclk output unavailable at port pin. 1: sysclk output routed to port pin. 2 smb0e smbus i/o enable. 0: smbus i/o unavailable at port pin. 1: sda and scl routed to port pins. 1 spi0e spi0 i/o enable. 0: spi0 i/o unavailable at port pin. 1: sck, miso, and mosi (for spi0) routed to port pins. nss (for spi0) routed to port pin only if spi0 is configured to 4-wire mode. 0 urt0e uart0 output enable. 0: uart i/o unavailable at port pin. 1: tx0 and rx0 routed to port pins p0.4 and p0.5. note: spi0 can be assigned either 3 or 4 port i/o pins.
c8051f91x-c8051f90x rev. 1.3 218 sfr page = 0x0; sfr address = 0xe2 sfr definition 21.2. xbr1: port i/o crossbar register 1 bit 7 6 5 4 3 2 1 0 name spi1e t1e t0e ecie pca0me[2:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 unused unused. read = 0b; write = don?t care. 6 spi1e spi1 i/o enable. 0: spi0 i/o unavailable at port pin. 1: sck (for spi1) routed to p1.0. miso (for spi1) routed to p1.1. mosi (for spi1) routed to p1.2. nss (for spi1) routed to p1.3 only if spi1 is configured to 4-wire mode. 5 t1e timer1 input enable. 0: t1 input unavailable at port pin. 1: t1 input routed to port pin. 4 t0e timer0 input enable. 0: t0 input unavailable at port pin. 1: t0 input routed to port pin. 3 ecie pca0 external counter input (eci) enable. 0: pca0 external counter input unavailable at port pin. 1: pca0 external counter input routed to port pin. 2:0 pca0me pca0 module i/o enable. 000: all pca0 i/o unavailable at port pin. 001: cex0 routed to port pin. 010: cex0, cex1 routed to port pins. 011: cex0, cex1, cex2 routed to port pins. 100: cex0, cex1, cex2 cex3 routed to port pins. 101: cex0, cex1, cex2, cex3, c ex4 routed to port pins. 110: cex0, cex1, cex2, cex3, cex4 , cex5 routed to port pins. 111: reserved. note: spi1 can be assigned either 3 or 4 port i/o pins.
c8051f91x-c8051f90x 219 rev. 1.3 sfr page = 0x0; sfr address = 0xe3 sfr definition 21.3. xbr2: port i/o crossbar register 2 bit 7 6 5 4 3 2 1 0 name weakpud xbare type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0000000 bit name function 7 weakpud port i/o weak pullup disable. 0: weak pullups enabled (except for port i/o pins configured for analog mode). 6 xbare crossbar enable. 0: crossbar disabled. 1: crossbar enabled. 5:0 unused unused. read = 000000b; write = don?t care. note: the crossbar must be enabled (xbare = 1) to use any port pin as a digital output.
c8051f91x-c8051f90x rev. 1.3 220 21.4. port match port match functionality allows system events to be tr iggered by a logic value change on p0 or p1. a soft - ware controlled value stored in the pnmat registers sp e cifies the expected or normal logic values of p0 and p1. a port mismatch event occurs if the logic levels of the port?s input pins no longer match the soft - ware controlled value. this allows software to be notified if a certain change or pattern occurs on p0 or p1 in put pins regardless of the xbrn settings. the pnmask registers can be used to individually select which p0 a nd p1 pins should be compared against the pnmat registers. a port mismatch event is generated if (p0 & p0mask) does not equal (pn mat & p0mask) or if (p1 & p1mask) does not equal (pnmat & p1mask). a port mismatch event may be used to generate an interrupt or wake the device from a low power mode. see section ?12. interrupt handler? on page 127 and section ?14. power management? on page 149 for more details on interrupt and wake-up sources. sfr page= 0x0; sfr address = 0xc7 sfr page= 0x0; sfr address = 0xd7 sfr definition 21.4. p0mask: port0 mask register bit 7 6 5 4 3 2 1 0 name p0mask[7:0] type r/w reset 00000000 bit name function 7:0 p0mask[7:0] port0 mask value. selects the p0 pins to be compared with the corresponding bits in p0mat. 0: p0.n pin pad logic value is ignored an d cannot cause a port mismatch event. 1: p0.n pin pad logic value is compared to p0mat.n. sfr definition 21.5. p0mat: port0 match register bit 7 6 5 4 3 2 1 0 name p0mat[7:0] type r/w reset 11111111 7 : 0 p0mat[7:0] port 0 match value. match comparison value used on port 0 for bit s in p0mask which are set to 1. 0: p0.n pin logic value is compared with logic low. 1: p0.n pin logic value is compared with logic high.
c8051f91x-c8051f90x 221 rev. 1.3 sfr page= 0x0; sfr address = 0xbf sfr page = 0x0; sfr address = 0xcf sfr definition 21.6. p1mask: port1 mask register bit 7 6 5 4 3 2 1 0 name p1mask[7:0] type r/w reset 00000000 bit name function 7:0 p1mask[7:0] port 1 mask value. selects p1 pins to be compared to the corresponding bits in p1mat. 0: p1.n pin logic value is ignored and ca nnot cause a port mismatch event. 1: p1.n pin logic value is compared to p1mat.n. sfr definition 21.7. p1mat: port1 match register bit 7 6 5 4 3 2 1 0 name p1mat[7:0] type r/w reset 11111111 bit name function 7:0 p1mat[7:0] port 1 match value. match comparison value used on port 1 for bit s in p1mask which are set to 1. 0: p1.n pin logic value is compared with logic low. 1: p1.n pin logic value is compared with logic high.
c8051f91x-c8051f90x rev. 1.3 222 21.5. special function registers for accessing and configuring port i/o all port i/o are accessed through corresponding specia l function registers (sfrs) that are both byte addressable and bit addressable. wh en writing to a port, the value written to the sfr is latched to main - tain the output data value at each pin. when reading, the logic levels of the port's input pins are returned r egardless of the xbrn settings (i.e., even when the pi n is assigned to another signal by the crossbar, the port register can always read its corresponding port i/ o pin). the exception to this is the execution of the read-modify-write instructio ns that target a port latch register as the destination. the read-modify-write instructions when operating on a port sfr are the fo llowing: anl, orl, xrl, jb c, cpl, inc, dec, djnz and mov, clr or setb, when the destination is an indi vidual bit in a port sfr. for these instructions, the value of the latch register (not the pin) is read, modified, and written back to the sfr. each port has a corresponding pnskip register which allo ws it s individual port pins to be assigned to dig - ital functions or skipped by the crossbar. all port pins used for analog functions, gpio, or dedicated digital func tions such as the emif shou ld have their pnskip bit set to 1. the port input mode of the i/o pins is defined usi ng the port input mode registers (pnmdin). each port cell can be configured for analog or digital i/o. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. th e only exception to this is p2.7, which can only be used for digital i/o. the output driver characteristics of the i/o pins ar e d efined using the port output mode registers (pnmd - out). each port output driver can be configured as either open drain or push- pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. the drive strength of the output driv ers a re controlled by the port drive strength (pndrv) registers. the default is low drive strength. see section ?4. electrical characteristics? on page 42 for the difference in out - put drive strength between the two modes.
c8051f91x-c8051f90x 223 rev. 1.3 sfr page = all pages; sfr address = 0x80; bit-addressable sfr page= 0x0; sfr address = 0xd4 sfr definition 21.8. p0: port0 bit 7 6 5 4 3 2 1 0 name p0[7:0] type r/w reset 11111111 bit name description write read 7:0 p0[7:0] port 0 data. sets the port latch logic valu e or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic lo w. 1: set output latch to logic high. 0: p0.n port pin is logic low . 1: p0.n port pin is logic hi gh. sfr definition 21.9. p0skip: port0 skip bit 7 6 5 4 3 2 1 0 name p0skip[7:0] type r/w reset 00000000 bit name function 7:0 p0skip[7:0] port 0 crossbar skip enable bits. these bits select port 0 pins to be skippe d b y the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar.
c8051f91x-c8051f90x rev. 1.3 224 sfr page= 0x0; sfr address = 0xf1 sfr page = 0x0; sfr address = 0xa4 sfr definition 21.10. p0mdin: port0 input mode bit 7 6 5 4 3 2 1 0 name p0mdin[7:0] type r/w reset 11111111 bit name function 7:0 p0mdin[7:0] analog configuration bits for p0.7?p0.0 (respectively). port pins configured for analog mode have their weak pullup, and digital receiver disabled. the digital driver is not explicitly disabled. 0: corresponding p0.n pin is configured for analog mode. 1: corresponding p0.n pin is not configured for analog mode. sfr definition 21.11. p0mdout: port0 output mode bit 7 6 5 4 3 2 1 0 name p0mdout[7:0] type r/w reset 00000000 bit name function 7:0 p0mdout[7:0] output configuration bits for p0.7?p0.0 (respectively). these bits control the digital driver even when the corresponding bit in register p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull.
c8051f91x-c8051f90x 225 rev. 1.3 sfr page = 0xf; sfr address = 0xa4 sfr definition 21.12. p0drv: port0 drive strength bit 7 6 5 4 3 2 1 0 name p0drv[7:0] type r/w reset 00000000 bit name function 7:0 p0drv[7:0] drive strength configuration bits for p0.7?p0.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p0.n output has low output drive strength. 1: corresponding p0.n output has high output drive strength.
c8051f91x-c8051f90x rev. 1.3 226 sfr page = all pages; sfr address = 0x90; bit-addressable sfr page = 0x0; sfr address = 0xd5 sfr definition 21.13. p1: port1 bit 7 6 5 4 3 2 1 0 name p1[6:0] type r/w reset 01111111 bit name description write read 7 unused unused. read =0b; write = don?t care. 6:0 p1[6:0] port 1 data. sets the port latch logic valu e or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic lo w. 1: set output latch to logic high. 0: p1.n port pin is logic low . 1: p1.n port pin is logic hi gh. sfr definition 21.14. p1skip: port1 skip bit 7 6 5 4 3 2 1 0 name p1skip[6:0] type r/w reset 00000000 bit name function 7 unused unused. read =0b; write = don?t care. 6:0 p1skip[6:0] port 1 crossbar skip enable bits. these bits select port 1 pins to be skippe d b y the crossbar decoder. port pins used for analog, special functions or gpio should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar.
c8051f91x-c8051f90x 227 rev. 1.3 sfr page = 0x0; sfr address = 0xf2 sfr page = 0x0; sfr address = 0xa5 sfr definition 21.15. p1mdin: port1 input mode bit 7 6 5 4 3 2 1 0 name p1mdin[6:0] type r/w reset 11111111 bit name function 7 unused unused. read =0b; write = don?t care. 6:0 p1mdin[6:0] analog configuration bits for p1.6?p1.0 (respectively). port pins configured for analog mode have their weak pullup and digital receiver disabled. the digital driver is not explicitly disabled. 0: corresponding p1.n pin is configured for analog mode. 1: corresponding p1.n pin is not configured for analog mode. sfr definition 21.16. p1mdout: port1 output mode bit 7 6 5 4 3 2 1 0 name p1mdout[6:0] type r/w reset 00000000 bit name function 7 unused unused. read =0b; write = don?t care. 6:0 p1mdout[6:0] output configuration bits for p1.6?p1.0 (respectively). these bits control the digital driver even when the corresponding bit in register p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull.
c8051f91x-c8051f90x rev. 1.3 228 sfr page = 0xf; sfr address = 0xa5 sfr page = all pages; sfr ad dress = 0xa0; bit-addressable sfr definition 21.17. p1drv: port1 drive strength bit 7 6 5 4 3 2 1 0 name p1drv[6:0] type r/w reset 00000000 bit name function 7 unused unused. read =0b; write = don?t care. 6:0 p1drv[6:0] drive strength configuration bits for p1.6?p1.0 (respectively). configures digital i/o port cells to high or low output drive strength. 0: corresponding p1.n output has low output drive strength. 1: corresponding p1.n output has high output drive strength. sfr definition 21.18. p2: port2 bit 7 6 5 4 3 2 1 0 name p2 type r/w reset 10000000 bit name description write read 7 p2 port 2 data. sets the port latch logic valu e or reads the port pin logic state in port cells con - figured for digital i/o. 0: set output latch to logic lo w. 1: set output latch to logic high. 0: p2.7 port pin is logic low . 1: p2.7 port pin is logic hi gh. 6:0 unused unused. read = 0000000b; write = don?t care.
c8051f91x-c8051f90x 229 rev. 1.3 sfr page = 0x0; sfr address = 0xa6 sfr page = 0x0f; sfr address = 0xa6 sfr definition 21.19. p2mdout: port2 output mode bit 7 6 5 4 3 2 1 0 name p2mdout type r/w reset 00000000 bit name function 7 p2mdout output configuration bits for p2.7. these bits control the digital driver. 0: p2.7 output is open-drain. 1: p2.7 output is push-pull. 6:0 unused unused. read = 0000000b; write = don?t care. sfr definition 21.20. p2drv: port2 drive strength bit 7 6 5 4 3 2 1 0 name p2drv type r/w reset 00000000 bit name function 7 p2drv drive strength configuration bits for p2.7. configures digital i/o port cells to high or low output drive strength. 0: p2.7 output has low output drive strength. 1: p2.7 output has high output drive strength. 6:0 unused unused. read = 0000000b; write = don?t care.
c8051f91x-c8051f90x rev. 1.3 230 22. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i 2 c serial bus. reads and writes to the interface by the system contro ller are byte oriented with the smbu s interface autonom ously controlling the serial transfer of the data. data can be transferre d at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or sla ve, and may function on a bus with multiple mas - ters. the smbus provides control of sda (serial data), scl ( serial clock) generation and synchronization, arbitration logic, and start/stop control and genera tion. the smbus peripheral can be fully driven by software (i.e. software accepts/re jects slave addresses, and generate s acks), or hardware slave address recognition and automatic ack gener ation can be enabled to minimize software overhead. a block dia - gram of the smbus peripheral and the associated sfrs is shown in figure 22.1 . figure 22.1. smbus block diagram data path control smbus control logic c r o s s b a r scl filter n sda control scl control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n smb0adr s l v 4 s l v 2 s l v 1 s l v 0 g c s l v 5 s l v 6 s l v 3 smb0adm s l v m 4 s l v m 2 s l v m 1 s l v m 0 e h a c k s l v m 5 s l v m 6 s l v m 3 arbitration scl synchronization hardware ack generation scl generation (master mode) sda control hardware slave address recognition irq generation
c8051f91x-c8051f90x 231 rev. 1.3 22.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including specifications), ph ilips semiconductor. 2. the i 2 c-bus specification?version 2.0, philips semiconductor. 3. system management bus specification?v ersion 1.1, sbs implementers forum. 22.2. smbus configuration figure 22.2 shows a typical smbus configuration. the smbu s s pecification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. the bi-direc - tional scl (serial clock) and sda (serial data) lines mu st b e connected to a positive power supply voltage through a pullup resistor or similar circuit. every devi ce connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. figure 22.2. typical smbus configuration vdd = 5 v master device slave device 1 slave device 2 vdd = 3 v vdd = 5 v vdd = 3 v sda scl
c8051f91x-c8051f90x rev. 1.3 232 22.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitr ation. note that it is not necessary to specify one device as the master in a system ; any device who transmits a star t and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond itio n followed by an address byte (bits7?1: 7-bit slave address; bit0: r/w direction bit), one or more bytes of data, and a stop condition. bytes that are received (by a master or slave) are acknowledg ed (ack) with a low sda during a high scl (see figure 22.3 ). if the receiving device does not ack, the transmitting device will read a nack (not acknowl - edge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit po sition of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation. all transactions are initiated by a master, with one or more addressed slave devices as the target. the ma ster generates the start condition and then transmits the slave address and direction bit. if the trans - action is a write operation from the ma ster to the slave, the master tr ansmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transaction and free the bus. figure 22.3 illustrates a typical smbus transaction. figure 22.3. smbus transaction 22.3.1. transmitter vs. receiver on the smbus communications interface, a device is the ?transmitter? when it is sending an address or data byte to another device on the bus. a device is a ?receiver? when an ad dress or data byte is being sent to it from another device on the bus. the transmitter controls the sda line during the address or data byte. after each byte of address or data information is sent by the transmitter, the receiver sends an ack or nack bit during the ack phase of the transfer, dur ing which time the receiver controls the sda line. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop
c8051f91x-c8051f90x 233 rev. 1.3 22.3.2. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?22.3.5. scl high (smbus free) timeout? on page 233 ). in the event that two or more devices attempt to begin a transfer at the same time, an arbitra - tion scheme is employed to force one master to give u p the bus. the master devices continue transmitting until one attempts a high while the other transmits a low. since the bus is open-drain, the bus will be pulled low. the master attempting th e high will detect a low sda and lo se the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destru ctive: one device always wins, and no data is lost. 22.3.3. clock low extension smbus provides a clock synchron ization mechanism, similar to i 2 c, which allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 22.3.4. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi - cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to r eload when scl is high, and allowed to count when scl is low. with timer 3 enabled and configured to ov erflow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable a nd re-enable) the smbus in the event of an scl low timeout. 22.3.5. scl high (smbus free) timeout the smbus specification stipulates that if the scl and sda lines remain high for more that 50 s, the bus is des ignated as free. when the sm bfte bit in smb0cf is set, the bu s will be considered free if scl and sda remain high for more than 10 smbus clock source periods (as defined by the timer configured for the smbus clock source). if the smbus is waiting to generate a master start, the start will be generated following this timeout. note that a clock source is required for free timeout detection, even in a slave-only implementation.
c8051f91x-c8051f90x rev. 1.3 234 22.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con - trol for serial transfers; higher level protocol is dete rm ined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as define d by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information ? optional hardware recognition of slave address and automatic acknowledgement of address/data smbus interrupts are generated for each data byte or slave address that is transferred. when hardware acknowledgment is disabled, the point at which the interrupt is generated depends on whether the hard - ware is acting as a data transmitter or receiver. when a transmitter (i.e. sending address/data, receiving an ack), this interrupt is generated after the ack cycle so that software may read the received ack value; when receiving data (i.e. receiving address/data, sending an ack), this interrupt is generated before the ack cycle so that software may define the outgoing ack value. if hardware acknowledgment is enabled, these interrupts are always generated after the ack cycle. see section 22.5 for more details on transmis - sion sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus inte rrupt. the smb0cn register is described in section 22.4.2 ; ta b l e 22.5 provides a quick smb0cn decoding reference.
c8051f91x-c8051f90x 235 rev. 1.3 22.4.1. smbus configuration register the smbus configuration register (s mb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options . when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer). the smbcs1?0 bits select th e smbus clock source, which is used only when operating as a master or when the free timeout detection is enabled. when op erating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 22.1 . note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uar t baud rates simultaneously. timer configuration is covered in section ?25. timers? on page 274 . equation 22.1. minimum scl high and low times the selected clock source should be configured to establish the minimum scl high and low times as per equation 22.1 . when the interface is operating as a master ( and scl is not driven or extended by any other devices on the bus), the typica l smbus bit rate is app roximated by equation 22.2 . equation 22.2. typical smbus bit rate figure 22.4 shows the typical scl generation described by equation 22.2 . notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will never exce ed the limits defined by equation equation 22.1 . figure 22.4. typical smbus scl generation table 22.1. smbus clock source selection smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow t highmin t lowmin 1 f clocksourceoverflow ---------------------------------- ----------- - == bitrate f clocksourceoverflow 3 --------------- ------------------------------ - = scl timer source overflows scl high timeout t low t high
c8051f91x-c8051f90x rev. 1.3 236 setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. ta b l e 22.2 shows the min - imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mhz. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low time outs (see section ?22.3.4. scl low timeout? on page 233 ). the smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count when scl is low. the timer 3 interrupt service routine sho uld be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is s et, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 22.4 ). table 22.2. minimum sda setup and hold times exthold minimum sda setup time minimum sda hold time 0 t low ? 4 system clocks or 1 system clock + s/w delay* 3 system clocks 1 11 system clocks 12 system clocks *note: setup time for ack bit transmissions and the msb of all data transfers. when using software acknowledgement, the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same write that defines the outgoing ack value, s/w delay is zero.
c8051f91x-c8051f90x 237 rev. 1.3 sfr page = 0x0; sfr address = 0xc1 sfr definition 22.1. smb0cf: smbus clock/configuration bit 7 6 5 4 3 2 1 0 name ensmb inh busy exthold smbtoe smbfte smbcs[1:0] type r/w r/w r r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 ensmb smbus enable. this bit enables the smbus interface when set to 1. when enabled, the interface constantly monitors the sda and scl pins. 6 inh smbus slave inhibit. when this bit is set to logic 1, the smbu s d oes not generate an interrupt when slave events occur. this effectively removes the smbus slave from the bus. master mode interrupts are not affected. 5 busy smbus busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. 4 exthold smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to ta b l e 22.2 . 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. 3 smbtoe smbus scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus forces ti mer 3 to reload while scl is high and allows timer 3 to count when scl goes low. if timer 3 is configured to split mode, only the high byte of the timer is held in reload while scl is high. timer 3 should be programmed to generate interrupts at 25 ms, an d the timer 3 interrupt service routine should reset smbus communication. 2 smbfte smbus free timeout detection enable. when this bit is set to logic 1, the bus will be considered free if sc l and sda remain high for more than 10 smbus clock source periods. 1 : 0 smbcs[1:0] smbus clock source selection. these two bits select the smbus clock sour ce, which is used to generate the smbus bit rate. the selected device should be configured according to equation 22.1 . 00: timer 0 overflow 01: timer 1 overflow 10:timer 2 high byte overflow 11: timer 2 low byte overflow
c8051f91x-c8051f90x rev. 1.3 238 22.4.2. smb0cn control register smb0cn is used to control the interface and to provide status information (see sfr definition 22.2 ). the higher four bits of smb0cn (master, txmode, sta, and sto) form a status vector that can be used to ju mp to service routines. master indicates whether a device is the master or slave during the current transfer. txmode indicates whether the device is tr ansmitting or receiving data for the current byte. sta and sto indicate that a start and/or stop ha s been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas - ter. writing a 1 to sta will cause the smbus interface to enter master mode and generate a start when th e bus becomes free (sta is not cleared by hardwar e after the start is generated). writing a 1 to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitratio n while operating as a slave indicates a bus error condi - tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see ta b l e 22.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. 22.4.2.1.software ack generation when the ehack bit in register smb0 adm is clear ed to 0, the firmware on the device must detect incom - ing slave addresses and ack or nack the slave addres s and incoming dat a bytes. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received during the last ack cycle. ackrq is set each ti me a byte is received, indi cating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be g enerated if software does not write the ack bit before clearing si. sda will reflect the defined ack value immediately following a write to the ack bit; however scl will remain low until si is cleared. if a received slave address is not acknowledged, further slave events will be ignored until the next start is detected. 22.4.2.2.hardwar e ack generation when the ehack bit in register smb0adm is set to 1, au tomatic slave address recognition and ack gen - eration is enabled. more detail about automatic slave address recognition can be found in section 22.4.3 . as a receiver, the value currently specified by the ac k bit will be automatically sent on the bus during the ack cycle of an incoming data byte. as a transmitter, reading the ack bit indicates the value received on the last ack cycle. the ackrq bit is not used when hardware ack generation is enabled. if a received slave address is nacked by hardware, further sl ave events will be ignored un til the next start is detected, and no interrupt will be generated. ta b l e 22.3 lists all sources for hardware changes to the smb0cn bits. refer to ta b l e 22.5 for smbus sta - tus decoding using the smb0cn register.
c8051f91x-c8051f90x 239 rev. 1.3 sfr page = 0x0; sfr addres s = 0xc0; bit-addressable sfr definition 22.2. smb0cn: smbus control bit 7 6 5 4 3 2 1 0 name master txmode sta sto ackrq arblost ack si type rrr/wr/wrrr/wr/w reset 00000000 bit name description read write 7 master smbus master/slave in dicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mo de. 1: smbus operating in ma ster mode. n/a 6 txmode smbus transmit mode in dicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mo de. 1: smbus in transmitter mo de. n/a 5 sta smbus start flag. 0: no start or repeated s tart detected. 1: start or repeated start detect ed. 0: no start generated. 1: when configured as a mas ter, initiates a start or repeated start. 4 sto smbus stop flag. 0: no stop condition detect ed. 1: stop condition detected ( if in slave mode) or pend - ing (if in master mode). 0: no stop condition is transmitt ed. 1: when configured as a ma ster, causes a stop condition to be transmit - ted after the next ack cy cle. cleared by hardware. 3 ackrq smbus acknowledge re quest. 0: no ack requested 1: ack requested n/a 2 arblost smbus arbitration lost in dicator. 0: no arbitration error. 1: arbitration lost n/a 1 ack smbus acknowledge. 0: nack received. 1: ack received. 0: send nack 1: send ack 0 si smbus interrupt flag. this bit is set by hardware und er the conditions listed in table 15.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. 0: no interrupt pending 1: interrupt pending 0: clear interrupt, and initi - ate next state machine even t. 1: force interrupt.
c8051f91x-c8051f90x rev. 1.3 240 table 22.3. sources for hardware changes to smb0cn bit set by hardware when: cleared by hardware when: master ? a s tart is generated. ? a st op is generated. ? ar bitration is lost. txmode ? st art is generated. ? sm b0dat is written before the start of an smbus frame. ? a st art is detected. ? ar bitration is lost. ? smb 0dat is not written before the start of an smbus frame. sta ? a st art followed by an address byte is received. ? m ust be cleared by software. sto ? a stop is detected while addressed as a slave. ? ar bitration is lost due to a detected stop. ? a pe nding stop is generated. ackrq ? a byte ha s been received and an ack response value is needed (only when hard - ware ack is not enabled). ? af ter each ack cycle. arblost ? a repeated start is detected as a master when sta is low (unwanted repeated start). ? scl is sensed low while attempting to gener - ate a stop or repeated start condition. ? s da is sensed low wh ile transmitting a 1 (excluding ack bits). ? each time si is clea red. ack ? the incoming ack value is low (acknowledge). ? the incoming ack value is high (not acknowledge). si ? a st art has been generated. ? l ost arbitration. ? a byte ha s been transmitted and an ack/nack received. ? a byte ha s been received. ? a st art or repeated start followed by a slave address + r/w has been received. ? a stop has been received. ? m ust be cleared by software.
c8051f91x-c8051f90x 241 rev. 1.3 22.4.3. hardware slave address recognition the smbus hardware has the capability to automatically recognize incoming slav e addresses and send an ack without software intervention. automatic slave address recognition is enabled by setting the ehack bit in register smb0adm to 1. this will enable both automatic slave address recognition and automatic hardware ack generation for received bytes (as a mast er or slave). more detail on automatic hardware ack generation can be found in section 22.4.2.2 . the registers used to define which address(es) ar e r ecognized by the hardware are the smbus slave address register ( sfr definition 22.3 ) and the smbus slave address mask register ( sfr definition 22.4 ). a single address or range of addresses (including the general call address 0x00) can be specified using th ese two registers. the most-significant seven bits of the two registers are used to define which addresses will be acked. a 1 in bit pos itions of the slave address mask slvm[6:0] enable a comparison between the received slave address and the hardware?s sl ave address slv[6:0] for those bits. a 0 in a bit of the slave address mask means that bit will be treated as a ?don?t care ? for comparison purposes. in this case, either a 1 or a 0 value are acceptable on the in coming slave address. additionally, if the gc bit in register smb0adr is set to 1, hardware will recognize the genera l call address (0x00). ta b l e 22.4 shows some example parameter settings and the slave ad dress es that will be recogni zed by hardware under those conditions. table 22.4. hardware address recognition examples (ehack = 1) hardware slave address slv[6:0] slave address mask slvm[6:0] gc bit slave addresses recognized by hardware 0x34 0x7f 0 0x34 0x34 0x7f 1 0x34, 0x00 (general call) 0x34 0x7e 0 0x34, 0x35 0x34 0x7e 1 0x34, 0x35, 0x00 (general call) 0x70 0x73 0 0x70, 0x74, 0x78, 0x7c
c8051f91x-c8051f90x rev. 1.3 242 sfr page = 0x0; sfr address = 0xf4 sfr page = 0x0; sfr address = 0xf5 sfr definition 22.3. smb0adr: smbus slave address bit 7 6 5 4 3 2 1 0 name slv[6:0] gc type r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 : 1 slv[6:0] smbus hardware slave address. defines the smbus slave address(es) for automatic hardware acknowledgement. on ly address bits which have a 1 in the corresponding bit position in slvm[6:0] are checked against the incoming address. this allows multiple addresses to be recognized. 0 gc general call address enable. when hardware address reco gnition is enabled (ehack = 1), this bit will deter - mine whether the general call address (0 x0 0) is also recognized by hardware. 0: general call ad dr ess is ignored. 1: general call address is recognized. sfr definition 22.4. smb0adm: smbus slave address mask bit 7 6 5 4 3 2 1 0 name slvm[6:0] ehack type r/w r/w reset 1111111 0 bit name function 7 : 1 slvm[6:0] smbus slave address mask. defines which bits of register smb0adr are compared with an incoming address b yte, and which bits are ignored. any bit set to 1 in slvm[6:0] enables compari - sons with the corresponding bit in slv[6:0]. bit s set to 0 are ignored (can be either 0 or 1 in the incoming address). 0 ehack hardware acknowledge enable. enables hardware acknowledgement of slave address and received data bytes. 0: firmware must manually acknowledge all incoming address and data bytes. 1: automatic slave address recognition and hardware acknowledge is enabled.
c8051f91x-c8051f90x 243 rev. 1.3 22.4.4. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, a s the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted ou t msb first. after a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi - tration, the transition from master transmitter to slave r eceiver is made with the correct data or address in smb0dat. sfr page = 0x0; sfr address = 0xc2 sfr definition 22.5. smb0dat: smbus data bit 7 6 5 4 3 2 1 0 name smb0dat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7 : 0 smb0dat[7:0] smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus ser ial interface or a byte that has just b een received on the smbus serial interface. the cpu can read from or write to this regi ster whenever the si serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu shou ld not attempt to access this register.
c8051f91x-c8051f90x rev. 1.3 244 22.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames. note that the position of the ack interrupt when operating as a receiver depends on whether hardware ack generation is enabled . as a receiver, the inte rrupt for an ack occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack genera - tion is enabled. as a transmitter, interrupts occur af ter the ack, regardless of whether hardware ack gen - eration is enabled or not. 22.5.1. write sequence (master) during a write sequence, an smbus master writes data to a slave device. the master in this transfer will be a transmitter during the address byte, and a transmitter during all data bytes. the smbus interface gener - ates the start condition and transmits the first byte cont aining the address of the target slave and the data direction bit. in this case th e data direction bit (r/w) will be logic 0 (write). the master then trans - mits one or more bytes of serial data. after each byte is tr ansmitted, an acknowledge bit is generated by the slave. the transfer is ended wh en the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not written following a master transm itter interrupt. figure 22.5 shows a typical master write sequence. two tr a nsmit data bytes are shown, though any num - ber of bytes may be transmitted. notice that all of th e ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 22.5. typical master write sequence a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
c8051f91x-c8051f90x 245 rev. 1.3 22.5.2. read sequence (master) during a read sequence, an smbus ma ster reads data from a slave devic e. the master in this transfer will be a transmitter during the address byte, and a receiv er during all data bytes. the smbus interface gener - ates the start condition and transmits the first byte cont aining the address of the target slave and the data direction bit. in this case t he data direction bit (r/w) will be logic 1 (read). serial data is then r eceived from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardw are will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. writing a 1 to the ack bit generates a n ack; writing a 0 generates a nack. software should write a 0 to the ack bit for the last data transfer, to transmit a nack. the interface exits master receiver mode after the sto bit is set and a stop is generated. the inte rface will switch to master transmitter mode if smb0 - dat is written while an active master receiver. figure 22.6 shows a typical master read sequence. two received data bytes are shown, though any number of by tes may be received. notice that the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack gen - eration is enabled. the interrupt occurs be fore the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 22.6. typical master read sequence data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
c8051f91x-c8051f90x rev. 1.3 246 22.5.3. write sequence (slave) during a write sequence, an smbus ma ster writes data to a slave device. the slave in this transfer will be a receiver during the address byte, and a receiver during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direc - tion bit (write in this case) is r eceived. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ac krq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generation is enabled, the hardware will apply the ac k for a slave address which matches the criteria set up by smb0adr and smb0adm. the inte rrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are received. if hardware ack generation is disabled, the ackrq is set to 1 and an interrupt is generated after each received byte. software must writ e the ack bit at that time to ack or nack the received byte. with hardware ack generation enab led, the smbus hardw are will autom atically generate the ack/nack, and then post the interrupt. it is important to note that the appropriate ack or nack value should be set up by the software prior to receiving the byte when hardware ack generation is enabled. the interface exits slave re ceiver mode after receiving a stop. note that the interface will switch to slave transmitter mode if smb0 dat is written while an active slave receiver. figure 22.7 shows a typical slave write sequence. two received data bytes are shown, though any number of bytes may be received. notice tha t the ?data byte transferred? interrupts occur at different places in the sequence, depending on whether hardware ack generation is enabled. the interrupt occurs before the ack with hardware ack generation disabled, and after the ack when hardware ack generation is enabled. figure 22.7. typical slave write sequence p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
c8051f91x-c8051f90x 247 rev. 1.3 22.5.4. read sequence (slave) during a read sequence, an smbus ma ster reads data from a slave device. the slave in this transfer will be a receiver during the address byte, and a transm itter during all data bytes. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to receive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. if hardware ack generation is disabled, upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. the software must respond to the received slave address with an ack, or ignore the received slave address with a nack. if hardware ack generat ion is enabled, the hardware will apply the ack for a slave address which matches the criteria set up by smb0adr and smb0adm. the interrupt will occur after the ack cycle. if the received slave address is ignore d (by software or hardware), slav e interrupts will be inhibited until the next start is detected. if the received slave address is acknowledged, zero or more data bytes are trans - mitted. if the received slave address is acknowledged, data should be written to smb0dat to be transmit - ted. the interface enters slave transmitter mode, and tr a nsmits one or more bytes of data. after each byte is transmitted, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be written with the next data byte. if the acknowle dge bit is a nack, smb0dat should not be written to before si is cleared (note: an error condition may be generated if smb0dat is wr itten following a received nack while in slave transmitter mo de). the interface exits slave transmitter mode after receiving a stop. note that the interface will switch to slav e receiver mode if smb0dat is not written following a slave transmitter interrupt. figure 22.8 shows a typical slave read sequence. two transmitted data bytes are shown, though any number of byte s ma y be transmitted. notice that all of the ?data byte transferred? interrupts occur after the ack cycle in this mode, regardless of whether hardware ack generation is enabled. figure 22.8. typical slave read sequence 22.6. smbus status decoding the current smbus status can be easily decoded usin g the smb0cn register. the appropriate actions to take in response to an smbus event depend on whether hardware slave address recognition and ack generation is enabled or disabled. ta b l e 22.5 describes the typical actions when hardware slave address recognition and ack generation is disabled. ta b l e 22.6 describes the typical actions when hardware slave address recognition and ack generation is enabled. in the t ables, status vector refers to the four upper bits of smb0cn: master, tx mode, sta, and sto. the shown response options are only the typ - ical responses; application-specific procedures are allowed as long as they conform to the smbus specifi - cation. highlighted responses are allowed by hardwar e bu t do not conform to the smbus specification. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupts with hardware ack disabled (ehack = 0) interrupts with hardware ack enabled (ehack = 1)
c8051f91x-c8051f90x rev. 1.3 248 table 22.5. smbus status decoding with hardware ack generation disabled (ehack = 0) mode values read current smbus state typical response options values to wr ite next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener - ated. load slave address + r/w into smb 0dat. 00x1100 11 00 000 a master data or address byte w as transmitted; nack received. set sta to restart transfer. 10x1110 abort transfer. 01x - 001 a master data or address byte was transmitted; ack received. load next data byte into smb0 - dat. 00x1100 end transfer with stop. 01x - end transfer with stop and start an other transfer. 11x - send repeated start. 10x1110 switch to master receiver mode ( clear si without writing new data to smb0dat). 0 0 x 1000 master receiver 1000 1 0 x a master data byte was r eceived; ack requested. acknowledge received byte; read smb0da t. 0 0 1 1000 send nack to indi ca te last byte, and send stop. 010 - send nack to indi ca te last byte, and send stop followed by start. 1101110 send ack followed by repeated st art. 1011110 send nack to indi ca te last byte, and send repeated start. 1001110 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 1100 send nack and switch to mas - ter transmitter mode (write to smb0dat before clearing si). 0 0 0 1100
c8051f91x-c8051f90x 249 rev. 1.3 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting st op condition). 0 0 x 0001 001 a slave byte was transmitted; ac k received. load smb0dat with next data by te to transmit. 0 0 x 0100 01 x a slave byte was transmitted; err or detected. no action required (expecting m aster to end transfer). 0 0 x 0001 01 01 0 x x an illegal stop or bus error wa s detected while a slave transmission was in progress. clear sto. 00x - slave receiver 0010 10x a slave address + r/w was r eceived; ack requested. if write, acknowledge received ad dress 0 0 1 0000 if read, load smb0dat with d ata byte; ack received address 0 0 1 0100 nack received address. 000 - 11 x lost arbitration as master; s lave address + r/w received; ack requested. if write, acknowledge received ad dress 0 0 1 0000 if read, load smb0dat with d ata byte; ack received address 0 0 1 0100 nack received address. 000 - reschedule failed transfer; nack received addres s. 1001110 00 01 00x a stop was detected while a ddressed as a slave trans - mitter or slave receiver. clear sto. 00x - 11 x lost arbitration while attempt - ing a stop. no action required (transfer com plete/aborted). 000 - 00 00 1 0 x a slave byte was received; ack re quested. acknowledge received byte; read smb0da t. 0 0 1 0000 nack received byte. 000 - bus error condition 0010 0 1 x lost arbitration while attempt - ing a repeated start. abort failed transfer. 00x - reschedule failed transfer. 10x1110 00 01 0 1 x lost arbitration due to a detected st op. abort failed transfer. 00x - reschedule failed transfer. 10x1110 00 00 1 1 x lost arbitration while transmit - ting a data byte as master. abort failed transfer. 000 - reschedule failed transfer. 1001110 table 22.5. smbus status decoding with hardware ack generation disabled (ehack = 0) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
c8051f91x-c8051f90x rev. 1.3 250 table 22.6. smbus status decoding with hardware ack generation enabled (ehack = 1) mode values read current smbus state typical response options values to wr ite next status vector expected status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was gener - ated. load slave address + r/w into smb 0dat. 00x1100 11 00 000 a master data or address byte w as transmitted; nack received. set sta to restart transfer. 10x1110 abort transfer. 01x - 001 a master data or address byte was transmitted; ack received. load next data byte into smb0 - dat. 00x1100 end transfer with stop. 01x - end transfer with stop and start an other transfer. 11x - send repeated start. 10x1110 switch to master receiver mode ( clear si without writing new data to smb0dat). set ack for initial data byte. 0 0 1 1000 master receiver 1000 001 a master data byte was received; ack sent. set ack for next data byte; read smb0dat. 0 0 1 1000 set nack to indicate next data by te as the last data byte; read smb0dat. 0 0 0 1000 initiate repeated start. 1001110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100 000 a master data byte was received; nack sent (last byte). read smb0dat; send stop. 010 - read smb0dat; send stop follo wed by start. 1101110 initiate repeated start. 1001110 switch to master transmitter mode (write to smb0dat before clearing si). 0 0 x 1100
c8051f91x-c8051f90x 251 rev. 1.3 slave transmitter 0100 000 a slave byte was transmitted; nack received. no action required (expecting st op condition). 0 0 x 0001 001 a slave byte was transmitted; ac k received. load smb0dat with next data by te to transmit. 0 0 x 0100 01 x a slave byte was transmitted; err or detected. no action required (expecting m aster to end transfer). 0 0 x 0001 01 01 0 x x an illegal stop or bus error wa s detected while a slave transmission was in progress. clear sto. 00x - slave receiver 0010 00x a slave address + r/w was received; ack sent. if write, set ack for first data by te. 0 0 1 0000 if read, load smb0dat with da ta byte 0 0 x 0100 01 x lost arbitration as master; s lave address + r/w received; ack sent. if write, set ack for first data by te. 0 0 1 0000 if read, load smb0dat with da ta byte 0 0 x 0100 reschedule failed transfer 10x1110 00 01 00x a stop was detected while a ddressed as a slave trans - mitter or slave receiver. clear sto. 00x - 01 x lost arbitration while attempt - ing a stop. no action required (transfer com plete/aborted). 000 - 00 00 0 0 x a slave byte was received. set ack for next data byte; read smb0dat. 0 0 1 0000 set nack for next data byte; read smb0dat. 0 0 0 0000 bus error condition 0010 0 1 x lost arbitration while attempt - ing a repeated start. abort failed transfer. 00x - reschedule failed transfer. 10x1110 00 01 0 1 x lost arbitration due to a detected st op. abort failed transfer. 00x - reschedule failed transfer. 10x1110 00 00 0 1 x lost arbitration while transmit - ting a data byte as master. abort failed transfer. 00x - reschedule failed transfer. 10x1110 table 22.6. smbus status decoding with hardware ack generation enabled (ehack = 1) (continued) mode values read current smbus state typical response options values to write next status vector expected status vector ackrq arblost ack sta sto ack
c8051f91x-c8051f90x rev. 1.3 252 23. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?23.1. enhanced baud rate generation? on page 253 ). received data buffering allows uart0 to start reception of a second incoming data byte be fore software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generated each time a transmit is completed (ti0 is set in scon0) , or a data byte has been received (ri0 is set in scon0). the uart0 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). figure 23.1. uart0 block diagram uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set qd clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch)
c8051f91x-c8051f90x 253 rev. 1.3 23.1. enhanced baud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl 1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 23.2 ), which is not user- accessible. both tx and rx timer overflows are divid ed b y two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is de t ected on the rx pin. th is allows a receive to begin any time a start is detected, independent of the tx timer state. figure 23.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload (see section ?25.1.3. mode 2: 8-bit counter/timer with auto-reload? on page 278 ). the timer 1 reload value should be set so that overflows will occur at two times the desired uart ba ud rate frequenc y. note that timer 1 may be clocked by one of six sources: sysclk, sysclk / 4, sysclk / 12, sysclk / 48, the external oscillator clock / 8, or an ex ternal input t1. for any given timer 1 clock source, the uart0 baud rate is determined by equation 23.1 -a and equation 23.1 -b. equation 23.1. uart0 baud rate where t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is sele cte d as described in section ?25.1. timer 0 and timer 1? on page 276 . a quick reference for typical baud rates and system clock frequencies is given in ta b l e 23.1 through ta b l e 23.2 . note that the internal osc illator may still generate the s ystem clock when the external oscillator is driving timer 1. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart uartbaudrate 1 2 -- - t1_overflow_rate = t1_overflow_rate t1 clk 256 th1 ? ------------------------- - = a) b)
c8051f91x-c8051f90x rev. 1.3 254 23.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown below. figure 23.3. uart interconnect diagram 23.2.1. 8-bit uart 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit . data are transmitted lsb first from the tx0 pin a nd received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins wh en s oftware writes a data byte to th e sbuf0 register. the ti0 transmit inter - rupt flag (scon0.1) is set at the end of the transmi ssion ( the beginning of the stop-bit time). data recep - tion can begin any time after the ren0 rece ive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the dat a byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over - run, the first received 8 bits are latched into the sbuf0 receive register and the following overrun data bits ar e lost. if these conditions are met, the eight bits of data is stor ed in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. figure 23.4. 8-bit uart timing diagram or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space
c8051f91x-c8051f90x 255 rev. 1.3 23.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma - ble ninth data bit, and a stop bit. the state of the nint h transmit dat a bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg - ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit g oes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a d ata byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive enab le bit (scon0.4) is set to 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the st ate of the ninth data bit is unimportant). if these cond itions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 flag is set to 1. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to 1. a uart 0 interrupt will occur if enabled when either ti0 or ri0 is set to 1. figure 23.5. 9-bit uart timing diagram 23.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of t he ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select th e target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor co n figures its uart such that when a stop bit is received, the uart will gener ate an interrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address by te has been received. in the uart interrupt handler, software will compare the received address with the slave's own assigned 8-bit addre ss. if the addresses match, the slav e will clear its mce0 bit to enable interrupts on the reception of the following data byte (s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addres sed slave resets its mce0 bit to ignore all transmis - sions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and /or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8
c8051f91x-c8051f90x rev. 1.3 256 figure 23.6. uart multi-pr ocessor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
c8051f91x-c8051f90x 257 rev. 1.3 sfr page = 0x0; sfr address = 0x98; bit-addressable sfr definition 23.1. scon0: serial port 0 control bit 7 6 5 4 3 2 1 0 name s0mode mce0 ren0 tb80 rb80 ti0 ri0 type r/w r r/w r/w r/w r/w r/w r/w reset 01000000 bit name function 7 s0mode serial port 0 operation mode. selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. 6 unused unused. read = 1b. write = don?t care. 5 mce0 multiprocessor comm unic ation enable. for mode 0 (8-bit uart): ch ecks for vali d stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. for mode 1 (9-bit uart): multip rocessor communica tions e nable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is gene ra ted only when the ninth bit is logic 1. 4 ren0 receive enable. 0: uart0 reception disabled. 1: uart0 reception enabled. 3 tb80 ninth transmission bit. the logic level of this bit will be sent as th e ninth transmission bi t in 9-bit uart mode (mode 1). unused in 8-bit mode (mode 0). 2 rb80 ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th da ta bit in mode 1. 1 ti0 transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8- bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting this bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. 0 ri0 receive interrupt flag. set to 1 by hardware when a byte of data has been received by uart0 (set at the st op bit sampling time). when the uart0 in terrupt is enabled, setting this bit to 1 causes the cpu to vector to the uart0 in terrupt service routine. this bit must be cleared manually by software.
c8051f91x-c8051f90x rev. 1.3 258 sfr page = 0x0; sfr address = 0x99 sfr definition 23.2. sbuf0: serial (uart0) port data buffer bit 7 6 5 4 3 2 1 0 name sbuf0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 sbuf0 serial data buffer bits 7:0 (msb?lsb). this sfr accesses two registers; a transmit shif t register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmission. writing a byte to sbuf0 initiates the transm ission. a read of sbuf0 returns the contents of the receive latch.
c8051f91x-c8051f90x 259 rev. 1.3 table 23.1. timer settings for standard baud rates using the internal 24.5 mhz oscillator frequency: 24.5 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from internal osc. 230400 ?0.32% 106 sysclk xx 2 1 0xcb 115200 ?0.32% 212 sysclk xx 1 0x96 57600 0.15% 426 sysclk xx 1 0x2b 28800 ?0.32% 848 sysclk/4 01 0 0x96 14400 0.15% 1704 sysclk/12 00 0 0xb9 9600 ?0.32% 2544 sysclk/12 00 0 0x96 2400 ?0.32% 10176 sysclk/48 10 0 0x96 1200 0.15% 20448 sysclk/48 10 0 0x2b notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 25.1 . 2. x = don?t care. table 23.2. timer settings for standard baud rates using an external 22.1184 mhz oscillator frequency: 22.1184 mhz target baud rate (bps) baud rate % error oscilla- tor divide factor timer clock source sca1?sca0 (pre-scale select) 1 t1m 1 timer 1 reload value (hex) sysclk from external osc. 230400 0.00% 96 sysclk xx 2 10xd0 115200 0.00% 192 sysclk xx 1 0xa0 57600 0.00% 384 sysclk xx 1 0x40 28800 0.00% 768 sysclk / 12 00 0 0xe0 14400 0.00% 1536 sysclk / 12 00 0 0xc0 9600 0.00% 2304 sysclk / 12 00 0 0xa0 2400 0.00% 9216 sysclk / 48 10 0 0xa0 1200 0.00% 18432 sysc lk / 48 10 0 0x40 sysclk from internal osc. 230400 0.00% 96 extclk / 8 11 0 0xfa 115200 0.00% 192 extclk / 8 11 0 0xf4 57600 0.00% 384 extclk / 8 11 0 0xe8 28800 0.00% 768 extclk / 8 11 0 0xd0 14400 0.00% 1536 extclk / 8 11 0 0xa0 9600 0.00% 2304 extclk / 8 11 0 0x70 notes: 1. sca1 ? sca0 and t1m bit definitions can be found in section 25.1 . 2. x = don?t care.
c8051f91x-c8051f90x rev. 1.3 260 24. enhanced serial peripheral interface (spi0 and spi1) the enhanced serial peripheral interf aces (spi0 and spi1) provide access to two identical, flexible, full- duplex synchronous serial busses. both spi0 and spi1 will be referred to collectively as spin. spin can operate as a master or slave devic e in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single spi bus. the slave-select (nss) signal can be configured as an input to select spin in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts si multaneous data transfers. nss can also be config - ured as a chip-select output in master mode, or di sable d for 3-wire operation. additional general purpose port i/o pins can be used to select multiple slave devices in master mode. figure 24.1. spi block diagram sfr bus data path control sfr bus write spi0dat receive data buffer spindat 0 1 2 3 4 5 6 7 shift register spi control logic spinckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spincfg spincn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spin irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssnmd1 nssnmd0 spibsy msten nssin srmt rxbmt spifn wcoln modfn rxovrnn txbmtn spinen
c8051f91x-c8051f90x 261 rev. 1.3 24.1. signal descriptions the four signals used by each spin (mosi, miso, sck, nss) are described below. 24.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spin is operat - ing as a master anspind an input when spin is operatin g as a slave. data is tr ansferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 24.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spin is operat - ing as a master and an output when spin is operating a s a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance stat e when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not select ed. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 24.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mast er device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spin gen - erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is n ot selected (nss = 1) in 4-wire slave mode. 24.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssnmd1 and nssnmd0 bits in the spincn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spin operates in 3-wire mode, and nss is disabled. when operating as a slave dev ice, spin is always selected in 3-wire mode. since no select signal is present, spin must be the only slave on the bus in 3-wire mode. this is intended for point-to-point communica tion between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-ma ster mode: spin operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spin device. when operating as a master, a 1-to-0 transition of th e nss signal disables t he master function of spin so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spin oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssm d0 determines what logic leve l the nss pin will output. this configuration should only be used wh en operating spin as a master device. see figure 24.2 , figure 24.3 , and figure 24.4 for typical connection diagra m s of the various operational modes. the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the cro ssbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ?21. port input/output? on page 210 for general purpose port i/ o and crossbar information.
c8051f91x-c8051f90x rev. 1.3 262 24.2. spi master mode operation a spi master device initiates all data transfers on a spi bus. spin is placed in master mode by setting the master enable flag (mstenn, spincn.6). writing a byte of data to the spin data register (spindat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spin master immediately shifts out the data serially on the mosi line wh ile providing the serial clock on sck. t he spifn (spincn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spin master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb-fi rst into the master's shift register. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spindat. when configured as a master, spin can operate in one of thr ee different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssnmd1 (spincn.3) = 0 and nssnmd0 (spincn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spin when anothe r master is accessing the bus. when nss is pulled low in this mode, mstenn (spi ncn.6) and spienn (spincn.0) are set to 0 to disable the spi master device, and a mode fault is generated (modfn, spincn.5 = 1). mode f ault will generate an interrupt if enabled. spin must be manually re-enabled in software under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-master mode, slave devices can be address ed individually (if needed) using general-purpose i/o pins. figure 24.2 shows a connection diagram between two master devices in multiple-master mode. 3-wire single-master mode is active when nssnmd1 ( spincn.3) = 0 and nssnmd0 (spincn.2) = 0. in this mode, nss is not used, and is not mapped to an external port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 24.3 shows a connection diagram between a master de vice in 3-wire master mode and a slave device. 4-wire single-master mode is active when nssnmd1 (spi nc n.3) = 1. in this mode, nss is configured as an output pin, and can be used as a slave-select signal for a single spi device. in this mode, the output value of nss is controlled (in software) with the bit nssnmd0 (spincn.2). addition al slave devices can be addressed using general-purpose i/o pins. figure 24.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices.
c8051f91x-c8051f90x 263 rev. 1.3 figure 24.2. multiple-master mode connection diagram figure 24.3. 3-wire single master and 3-wire single slave mode connection diagram figure 24.4. 4-wire single master mode and 4-wire slave mode connection diagram master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio slave device master device mosi miso sck miso mosi sck slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss
c8051f91x-c8051f90x rev. 1.3 264 24.3. spi slave mode operation when spin is enabled and not confi gured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig - nal. a bit counter in the spin logic counts sck edges. when 8 bits have been shifted through the shift reg - ister, the spif flag is set to logic 1, and the byte is co pied into the receive buffer. data is read from the receive buffer by reading spindat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spindat. writes to spindat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edg e of the next (or current) spi transfer. when configured as a slave, spin can be configured fo r 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssnmd1 (spincn.3) = 0 and nssnmd0 (spincn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spin is enabl ed when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a falling edge of n ss. note that the nss sig - nal must be driven low at least 2 system clocks before th e first active edge of sck for each byte transfer. figure 24.4 shows a connection diagram between two slav e de vices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssnmd1 (spincn. 3) = 0 and nssnmd0 (spincn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spin must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spin with the spien bit. figure 24.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 24.4. spi interrupt sources when spin interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: all of the following bits must be cleared by software. 1. the spi interrupt flag, spifn (spincn.7) is set to logic 1 at the end of each byte transfer. t his flag can occur in all spin modes. 2. the write collision flag, wcoln (spincn.6) is s et to logic 1 if a write to spindat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spindat w ill be ignored, and the transmit buffer will not be written.this flag can occur in all spin modes. 3. the mode fault flag modfn (spincn.5) is set to logic 1 when spin is configured as a ma ster, and for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the mstenn and spienn bits in spi0cn are set to logic 0 to disable spin and allow another master device to access the bus. 4. the receive overrun flag rxovrnn (spincn.4) is set to log ic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost.
c8051f91x-c8051f90x 265 rev. 1.3 24.5. serial clock phase and polarity four combinations of serial clock phase and polarity ca n be selected using the clock control bits in the spi configuration register (spincfg). the ckpha bit (spincfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spincfg.4) se lects between an active-high or active-low clock. both master and slave devices must be configured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spienn bit, spincn.0) w hen changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 24.5 . for slave mode, the clock and data relationships are shown in figure 24.6 and figure 24.7 . note that ckpha must be set to 0 on both the master and slave spi when communicating between two of the following devices: c8051f04x, c80 51f06x, c8051f12x, c8051f31x, c8051f32x, and c8051f33x. the spin clock rate register (spinckr) a s shown in sfr definition 24.3 controls the master mode serial clock frequency. this register is ignored when o perating in slave mode. when the spi is configured as a master, the maximum data transfer rate (bits/sec) is one-half the s ystem clock frequency or 12.5 mhz, whichever is slower. when the spi is configured as a sl ave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency , provided that the master issues sck, nss (in 4- wire slave mode), and the serial input data synchrono usly with the slave?s system clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfer rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master i ssues sck, nss, and the serial inpu t data synchronously with the slave?s system clock. figure 24.5. master mode data/clock timing sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode)
c8051f91x-c8051f90x rev. 1.3 266 figure 24.6. slave mode data/clock timing (ckpha = 0) figure 24.7. slave mode data/clock timing (ckpha = 1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi
c8051f91x-c8051f90x 267 rev. 1.3 24.6. spi special function registers spi0 and spi1 are accessed and controlled through four sp ecial function registers (8 registers total) in the system controller: spincn control re gister, spindat data register, spincfg configuration register, and spinckr clock rate register. the special function registers related to the operation of the spi0 and spi1 bus are described in the following figures.
c8051f91x-c8051f90x rev. 1.3 268 sfr addresses: spi0cfg = 0xa1, spi1cfg = 0x84 sfr pages: spi0cfg = 0x0, spi1cfg = 0x0 sfr definition 24.1. spincfg: spi configuration bit 7 6 5 4 3 2 1 0 name spibsy msten ckpha ckpol slvsel nssin srmt rxbmt type r r/w r/w r/w r r r r reset 0000011 1 bit name function 7 spibsy spi busy. this bit is set to logic 1 when a spi transf er is in progress (master or slave mode). 6 msten master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. 5 ckpha spi clock phase. 0: data centered on first edge of sck period. * 1: data centered on second edge of sck period. * 4 ckpol spi clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. 3 slvsel slave selected flag. set to logic 1 whenever the nss pin is low in dicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (s lave not selected). this bit does not indi - cate the instantaneous value at the nss pin, but rather a de-glitched version of the p in input. 2 nssin nss instantaneous pin input. this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. 1 srmt shift register empty (valid in slave mode only). set to logic 1 when data has been transferred in/out of the shift register, and there is no data is available to read from the transmit buffer or write to the receive buffer. set to logic 0 when a data byte is transferred to the shift register from the transmit bu ffer or by a transition on sck. note: srmt = 1 in master mode. 0 rxbmt receive buffer empty (valid in slave mode only). set to logic 1 when the receive buffer has been read and contains no new informa - tion. if there is new inform ation available in the receive buffer that has not been read, this bit will return to logic 0. note: rxbmt = 1 in master mode. *note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum settling time for the slave device. see table 24.1 for timing parameters.
c8051f91x-c8051f90x 269 rev. 1.3 sfr addresses: spi0cn = 0xf8, bit-addre ssable; spi1cn = 0xb0, bit-addressable sfr pages: spi0cn = 0x0, spi1cn = 0x0 sfr definition 24.2. spincn: spi control bit 7 6 5 4 3 2 1 0 name spifn wcoln modfn rxovrnn nssnmd1 nssnmd0 txbmtn spinen type r/w r/w r/w r/w r/w r/w r r/w reset 000 0 0 1 1 0 bit name function 7 spifn spin interrupt flag. this bit is set to logic 1 by hardware at th e end of a data transfer. if interrupts are enabled, setting this bit causes the cpu to vector to the spin interrupt service routine. this bit is not aut omatically cleared by hardwar e. it must be cleared by software. 6 wcoln write collision flag. this bit is set to logic 1 by hardware (and generates a spi0 interrupt) to indicate a write to the spi0 data register was attempted while a data transfer was in progress. it must be cleared by software. 5 modfn mode fault flag. this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when a mas - ter mode collision is detected (nss is lo w , msten = 1, and nssmd[1:0] = 01). this bit is not automatically cleared by hardware. it must be cleared by software. 4 rxovrnn receive overrun flag (valid in slave mode only). this bit is set to logic 1 by hardware (and generates a spin interrupt) when the receive buf fer still holds unread data from a previous transf er and the last bit of the current transfer is shifted in to the spi shift register. this bit is not automatically cleared by hardware. it must be cleared by software. 3:2 nssnmd[1:0] slave select mode. selects between the following nss operation modes: (see section 24.2 and section 24.3 ). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (d efau lt). nss is an input to the device. 1x: 4-wire single-master mode. nss sign al is ma pped as an output from the device and will assume the value of nssmd0. 1 txbmtn transmit buffer empty. this bit will be set to logic 0 when new da t a has been written to the transmit buffer. when data in the transmit buffer is transfer red to the spi shift register, this bit will be set to logic 1, indicating that it is safe to write a new byte to the transmit buffer. 0 spinen spin enable. 0: spin disabled. 1: spin enabled.
c8051f91x-c8051f90x rev. 1.3 270 sfr addresses: spi0ckr = 0xa2, spi1ckr = 0x85 sfr pages: spi0ckr = 0x 0, spi1ckr = 0x0 sfr addresses: spi0dat = 0xa3, spi1dat = 0x86 sfr pages: spi0dat = 0x0, spi1dat = 0x0 sfr definition 24.3. spinckr: spi clock rate bit 7 6 5 4 3 2 1 0 name scrn[7:0] type r/w reset 0000000 0 bit name function 7:0 scrn spi clock rate. these bits determine the frequency of the sck output when the spi module is co nfigured for master mode operation. the sck clock frequency is a divided version of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spinckr is the 8-bit value held in the spinckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spinckr = 0x04, sfr definition 24.4. spindat: spi data bit 7 6 5 4 3 2 1 0 name spindat[7:0] type r/w reset 0000000 0 bit name function 7:0 spindat spin transmit and receive data. the spindat register is used to transmit and receive spin data. writing data to spinda t places the data into the transmi t buffer and initiates a transfer when in master mode. a read of spindat returns the contents of the receive buffer. f sck sysclk 2 spinckr[7:0] 1 + () ------------------- --------------------------------------- - = f sck 2000000 241 + () -------------------------- = f sck 200 khz =
c8051f91x-c8051f90x 271 rev. 1.3 figure 24.8. spi master timing (ckpha = 0) figure 24.9. spi master timing (ckpha = 1) sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis
c8051f91x-c8051f90x rev. 1.3 272 figure 24.10. spi slave timing (ckpha = 0) figure 24.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz
c8051f91x-c8051f90x 273 rev. 1.3 table 24.1. spi slave timing parameters parameter description min max units master mode timing * (see figure 24.8 and figure 24.9 ) t mckh sck high time 1 x t sysclk ? ns t mckl sck low time 1 x t sysclk ? ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing * (see figure 24.10 and figure 24.11 ) t se nss falling to first sck edge 2 x t sysclk ? ns t sd last sck edge to nss rising 2 x t sysclk ? ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ? ns t ckl sck low time 5 x t sysclk ? ns t sis mosi valid to sck sample edge 2 x t sysclk ? ns t sih sck sample edge to mosi change 2 x t sysclk ? ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to miso change (ckpha = 1 only) 6 x t sysclk 8 x t sysclk ns *note: t sysclk is equal to one period of the device system clock (sysclk).
c8051f91x-c8051f90x rev. 1.3 274 25. timers each mcu includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer fo r use with the adc, smbus, or for general purpose use. these timers can be used to measure time inte rvals, count external even ts and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four primary modes of operation. ti mer 2 and timer 3 offer 16-bit and split 8-bit timer functionality with auto-reload. additionally, timer 2 and ti mer 3 have a capture mode that can be used to me asur e the smartclock or a comparator period with respect to another os cillator. this is particularly useful when using capacitive touch switches. timers 0 and 1 may be clocked by one of five sources, determined by the timer mode select bits (t1m ? t0m) and the clock scale bits (sca1?sca0). the clock scale bits define a pre- scaled clock from which timer 0 and/or timer 1 may be clocked (see sfr definition 25.1 for pre-scaled cl ock s election). timer 0/1 may then be configured to use this pre-sc ale d clock signal or th e system clock. timer 2 and t imer 3 may be clocked by the system clock, the system clock divided by 12. timer 2 may additionally be clocked b y the smartclock divided by 8 or the comparator0 output. timer 3 may additionally be clocked by the external oscillator clock source divided by 8 or the comparator 1 output. timer 0 and timer 1 may also be operated as counters. when fun ctioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a frequency of up to one-fourth the system clock frequency can be counted. the input signal need not be periodic, but it should be held at a given level for at least two full system clock cycles to ensure the level is properly sampled. timer 0 and timer 1 modes: ti mer 2 modes: timer 3 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto- reload two 8-bit timers with auto-reload t wo 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only)
c8051f91x-c8051f90x 275 rev. 1.3 sfr page = 0x0; sfr address = 0x8e sfr definition 25.1. ckcon: clock control bit 7 6 5 4 3 2 1 0 name t3mh t3ml t2mh t2ml t1m t0m sca[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 t3mh timer 3 high byte clock select. selects the clock supplied to the timer 3 high byte (split 8-bit timer mode only). 0: timer 3 high byte uses the clock defin ed by th e t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. 6 t3ml timer 3 low byte clock select. selects the clock supplied to timer 3. selects the clock supplie d to the lower 8-bit timer in split 8-bit timer mode. 0: timer 3 low byte uses the clock defined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. 5 t2mh timer 2 high byte clock select. selects the clock supplied to the timer 2 high byte (split 8-bit timer mode only). 0: timer 2 high byte uses the clock defin ed by th e t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. 4 t2ml timer 2 low byte clock select. selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, th is bit selects the clock supp lied to the lower 8-bit timer. 0: timer 2 low byte uses the clock defined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. 3 t1m timer 1 clock select. selects the clock source supplied to timer 1. ignored when c/t1 is set to 1. 0: timer 1 uses the clock defined by the prescale bits sca[1:0]. 1: timer 1 uses the system clock. 2 t0m timer 0 clock select. selects the clock source supplied to timer 0. ignored when c/t0 is set to 1. 0: counter/timer 0 uses the clock defined by th e prescale bits sca[1:0]. 1: counter/timer 0 uses the system clock. 1:0 sca[1:0] timer 0/1 prescale bits. these bits control the timer 0/1 clock prescaler: 00: system clock divided by 12 01: system clock divided by 4 10: system clock divided by 48 11: external clock divided by 8 (synchronized with the system clock)
c8051f91x-c8051f90x rev. 1.3 276 25.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer co ntrol register (tcon) is used to enable timer 0 and ti mer 1 as well as indicate status. timer 0 interrupts can be enabled by setting the et0 bit in the ie regis - ter ( section ?12.5. interrupt register descriptions? on page 130 ); timer 1 interrupts can be enabled by set - ting the et1 bit in the ie register ( section ?12.5. interrupt register descriptions? on page 130 ). both counter/timers operate in one of four primary m ode s selected by setting the mode select bits t1m1 ? t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 25.1.1. mode 0: 13-bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration a nd operation of timer 0. however, both timers operate identically, and timer 1 is configured in the same ma nner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c oun ter/timer. tl0 holds the five lsbs in bit positions tl0.4 ? tl0.0. the three upper bits of tl0 (tl0.7 ? tl0.5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf0 (tcon.5) is set and an interr upt will occur if timer 0 interrupts are e nabled. the c/t0 bit (tmod.2) selects the counter/time r's clock source. when c/t0 is set to logic 1, high-to-low tra nsitions at the selected timer 0 input pin (t0) increment the timer register (refer to section ?21.3. priority crossbar decoder? on page 214 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckcon (see sfr definition 25.1 ). setting the tr0 bit (tcon.4) enables the ti mer when either gate0 (tmod.3) is logic 0 or the input signal int0 is active as defined by bit in 0pl in register it01cf (see sfr definition 12.7 ). setting gate0 to 1 allows the timer to be controlled by the external input signal int0 (see section ?12.5. interrupt register descriptions? on page 130 ), facilitating pulse width measurements setting tr0 does not force the timer to re set. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. ti mer 1 is configured and controlled using the releva nt tcon and tmod bits just as with timer 0. the inp ut signal int1 is used with timer 1; the int1 polarity is defined by bit in1pl in register it01cf (see sfr definition 12.7 ). table 25.1. timer 0 running modes tr0 gate0 int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 1 1 1 enabled note: x = don't care
c8051f91x-c8051f90x 277 rev. 1.3 figure 25.1. t0 mode 0 block diagram 25.1.2. mode 1: 16-bit counter/timer mode 1 operation is the same as mode 0, except that the counte r /timer registers use all 16 bits. the cou nter/timers are enabled and configured in mode 1 in the same manner as for mode 0. tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 int0 t0 crossbar it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor
c8051f91x-c8051f90x rev. 1.3 278 25.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start valu e. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer over flow flag tf0 (tcon.5) is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enabled, an interr upt will occ ur when the tf0 flag is set. the reload value in th0 is not changed. tl0 must be initialized to the desired va lue before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or when the input signal int0 is active as defined by bit in 0pl in register it01cf (see section ?12.6. external interrupts int0 and int1? on page 137 for details on the external input signals int0 and int1 ). figure 25.2. t0 mode 2 block diagram tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock it01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
c8051f91x-c8051f90x 279 rev. 1.3 25.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit co un ter/timers held in tl0 and th0. the counter/timer in tl0 is controlled using the timer 0 control/status bits in tcon and tmod: tr0, c/t0, ga te0 and tf0. tl0 can use either the system clock or an external input signal as its timebase. the th0 register is restricted to a timer function sourced by the system clock or prescaled clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 overflow flag tf1 on overflow and thus controls the t imer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operating in mode 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud rates for the smbus and/or uart, and/or initiate adc conv ersions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode set - tings. to run timer 1 while timer 0 is in mode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, con figure it for mode 3. figure 25.3. t0 mode 3 block diagram tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m
c8051f91x-c8051f90x rev. 1.3 280 sfr page = 0x0; sfr address = 0x88; bit-addressable sfr definition 25.2. tcon: timer control bit 7 6 5 4 3 2 1 0 name tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf1 timer 1 overflow flag. set to 1 by hardware when timer 1 overflows. this flag can be cleared by software bu t is automatically cleared when the cpu vectors to the timer 1 interrupt service ro utine. 6 tr1 timer 1 run control. timer 1 is enabled by setting this bit to 1. 5 tf0 timer 0 overflow flag. set to 1 by hardware when timer 0 overflows. this flag can be cleared by software bu t is automatically cleared when the cpu vectors to the timer 0 interrupt service ro utine. 4 tr0 timer 0 run control. timer 0 is enabled by setting this bit to 1. 3 ie1 external interrupt 1. this flag is set by hardware when an edge/l evel o f type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 1 service routine in edge-triggered mode. 2 it1 interrupt 1 type select. this bit selects whether the configured int1 interrupt will be edge or level sensitive. int1 is configured active low or high by the in1pl bit in the it01cf register (see sfr definition 12.7 ). 0: int1 is level triggered. 1: int1 is edge triggered. 1 ie0 external interrupt 0. this flag is set by hardware when an edge/l evel o f type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external interrupt 0 service routine in edge-triggered mode. 0 it0 interrupt 0 type select. this bit selects whether the configured int0 interrupt will be edge or level sensitive. int0 is configured active low or high by the in0pl bit in register it01cf (see sfr definition 12.7 ). 0: int0 is level triggered. 1: int0 is edge triggered.
c8051f91x-c8051f90x 281 rev. 1.3 sfr page = 0x0; sfr address = 0x89 sfr definition 25.3. tmod: timer mode bit 7 6 5 4 3 2 1 0 name gate1 c/t1 t1m[1:0] gate0 c/t0 t0m[1:0] type r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 gate1 timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of int1 logic level. 1: timer 1 enabled only when tr1 = 1 and int1 is active as defined by bit in1pl in register it01cf (see sfr definition 12.7 ). 6 c/t1 counter/timer 1 select. 0: timer: timer 1 incremented by clock defined by t1m bit in register ckcon. 1: counter: timer 1 incremented by high-to-low transitions on external pin (t1). 5:4 t1m[1:0] timer 1 mode select. these bits select the timer 1 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, timer 1 inactive 3 gate0 timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of int0 logic level. 1: timer 0 enabled only when tr0 = 1 and int0 is active as defined by bit in0pl in register it01cf (see sfr definition 12.7 ). 2 c/t0 counter/timer 0 select. 0: timer: timer 0 incremented by clock defined by t0m bit in register ckcon. 1: counter: timer 0 incremented by high-to-low transitions on external pin (t0). 1:0 t0m[1:0] timer 0 mode select. these bits select the timer 0 operation mode. 00: mode 0, 13-bit counter/timer 01: mode 1, 16-bit counter/timer 10: mode 2, 8-bit counter/timer with auto-reload 11: mode 3, two 8-bit counter/timers
c8051f91x-c8051f90x rev. 1.3 282 sfr page = 0x0; sfr address = 0x8a sfr page = 0x0; sfr address = 0x8b sfr definition 25.4. tl0: timer 0 low byte bit 7 6 5 4 3 2 1 0 name tl0[7:0] type r/w reset 00000000 bit name function 7:0 tl0[7:0] timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. sfr definition 25.5. tl1: timer 1 low byte bit 7 6 5 4 3 2 1 0 name tl1[7:0] type r/w reset 00000000 bit name function 7:0 tl1[7:0] timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1.
c8051f91x-c8051f90x 283 rev. 1.3 sfr page = 0x0; sfr address = 0x8c sfr page = 0x0; sfr address = 0x8d sfr definition 25.6. th0: timer 0 high byte bit 7 6 5 4 3 2 1 0 name th0[7:0] type r/w reset 00000000 bit name function 7:0 th0[7:0] timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. sfr definition 25.7. th1: timer 1 high byte bit 7 6 5 4 3 2 1 0 name th1[7:0] type r/w reset 00000000 bit name function 7:0 th1[7:0] timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1.
c8051f91x-c8051f90x rev. 1.3 284 25.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may o perate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t2split bit (tmr2cn.3) defines the timer 2 operation mode. timer 2 can also be used in capture mode to measure the smartclock or the comparator 0 period with respect to anot her oscillator . the ability to measure the comparator 0 period with res pect to the system clock is make s using touch sense switches very easy. timer 2 may be clocked by the system cl ock, the system clock divided by 12, smartclock divided by 8, or comparator 0 output. note that the smartclock divided by 8 and comparator 0 output is synchronized with t he system clock. 25.2.1. 16-bit timer with auto-reload when t2split (tmr2cn. 3) is zero, timer 2 operates as a 16-bit time r with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, smar tclock divided by 8, or comparator 0 output. as the 1 6-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is loaded into the timer 2 register as shown in figure 25.4 , and the timer 2 high byte overflow flag (tmr2cn.7) is set. if timer 2 interrupts are enabled (if ie.5 is set), an interrupt will be gen erated on each timer 2 overflow. additionally, if timer 2 interrupts are enabled and the tf2len bit is set (tmr2cn. 5), an interr upt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. figure 25.4. timer 2 16-bit mode block diagram sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split tf2cen tf2l tf2h t2xclk tr2 interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m smartclock / 8 sysclk / 12 00 t2xclk[1:0] 01 11 comparator 0
c8051f91x-c8051f90x 285 rev. 1.3 25.2.2. 8-bit timers with auto-reload when t2split is set, timer 2 operates as two 8-bit timers (tmr2h an d tmr2l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 25.5 . tmr2rll holds the reload va lue for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr 2 bit in tmr2cn handles the run control for tmr2h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be configur ed to use sysclk, sysclk divided by 12, smartclock divided by 8 or comparator 0 output. the timer 2 clock select bits (t2mh and t2ml in ckc on) select either sysclk or the clock defined by the timer 2 external clock select bits (t2x c lk[1:0] in tmr2 cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00 ; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tm r2h overflows. if timer 2 interrupts are enabled and tf2len (tmr2cn.5) is set, an interrupt is gener - ated each time either tmr2l or tmr2h overflows. wh en tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags a re not cleared by hardware and must be manually cleared by software. figure 25.5. timer 2 8-bit mode block diagram t2mh t2xclk[1:0] tmr2h clock source t2ml t2xclk[1:0] tmr2l clock source 0 00 sysclk / 12 0 00 sysclk / 12 0 01 smartclock / 8 0 01 smartclock / 8 0 10 reserved 0 10 reserved 0 11 comparator 0 0 11 comparator 0 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr2 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split tf2cen tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m smartclock / 8 sysclk / 12 00 t2xclk[1:0] 01 11 comparator 0
c8051f91x-c8051f90x rev. 1.3 286 25.2.3. comparator 0/smartclock capture mode the capture mode in timer 2 allows either comparator 0 or the smartclock period to be measured agains t the system clock or the system clock divided by 12. comparator 0 and the smartclock period can a lso be compared against each other. timer 2 capture mode is enabled by setting tf2cen to 1. timer 2 sho uld be in 16-bit auto-reload mode when using capture mode. when capture mode is enable d, a c apture event will be gener ated either ev ery comparator 0 rising edge o r every 8 smartclock clock cycles, depending on th e t2xclk1 setting. when the capture event occurs, the contents of timer 2 (tmr2h:tmr2l) are loaded into the timer 2 reload registers ( tmr2rlh:tmr2rll) and the tf2h flag is set (triggering an interrupt if timer 2 interrupts are enabled). by re cording the difference between two succ essive timer capture values, the comparator 0 or smart - clock period can be determined with respect to the timer 2 clock. the timer 2 clock should be much faster than the capture clock to achieve an accurate reading. for example, if t2ml = 1b, t2xclk1 = 0b, and tf2cen = 1b, timer 2 will clock every sysclk and cap - ture every smartclock clock divided by 8. if the sysclk is 24.5 mh z and the difference between two successive captures is 5984, then t he smartclock clock is as follows: 24.5 mhz/(5984/8) = 0.032754 mhz or 32.754 khz. this mode allows software to de termine the exact smartclock freque ncy in self-oscillate mode and the time between consecutive comparator 0 rising edges, which is useful fo r detecting changes in the capaci - tance of a touch sense switch. figure 25.6. timer 2 capture mode block diagram smartclock / 8 sysclk 0 1 t2xclk1 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr2l tmr2h tclk tr2 tmr2rll tmr2rlh capture tmr2cn t2split t2xclk1 tf2cen tf2l tf2h t2xclk0 tr2 tf2len tf2cen interrupt sysclk / 12 x0 t2xclk[1:0] 01 11 comparator 0 0 1 smartclock / 8 comparator 0
c8051f91x-c8051f90x 287 rev. 1.3 sfr page = 0x0; sfr addres s = 0xc8; bit-addressable sfr definition 25.8. tmr2cn: timer 2 control bit 7 6 5 4 3 2 1 0 name tf2h tf2l tf2len tf2cen t2split tr2 t2xclk[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf2h timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 overflows from 0xffff to 0x0000. when the ti mer 2 interrupt is enabled, setting this bit causes the cpu to vector to the ti mer 2 interrupt service routine. this bit is not auto matically cleared by hardware. 6 tf2l timer 2 low byte overflow flag. set by hardware when the timer 2 low byte overflows from 0xff to 0x00. tf2l will be set when the low byte over flows regardless of the timer 2 mode. this bit is not a utomatically cleared by hardware. 5 tf2len timer 2 low byte interrupt enable. when set to 1, this bit enables timer 2 low byte interrupts. if timer 2 interrupts are als o enabled, an interr upt will be generat ed when the low byte of timer 2 over - flows. 4 tf2cen timer 2 capture enable. when set to 1, this bit enables timer 2 capture mode. 3 t2split timer 2 split mode enable. when set to 1, timer 2 operates as two 8-bit timers w ith auto-reload. otherwise, timer 2 operates in 16-bit auto-reload mode. 2 tr2 timer 2 run control. timer 2 is enabled by setting this bit to 1. in 8-bit mode, t his bit enables/disables tmr2h only; tmr2l is always enabled in split mode. 1:0 t2xclk[1:0] timer 2 external clock select. this bit selects the ?external? and ?capture trigger? clock sources for timer 2. if ti mer 2 is in 8-bit mode, this bit selects the ?external? clock source for both timer by tes. timer 2 clock select bits (t2mh and t2ml in register ckcon) may s till be used to select between the ?external? clock and the system clock for either timer. note: external clock sources are sy n chronized with the system clock. 00: external clock is sysclk/12. ca pture trigger is smartclock/8. 01: external clock is comparator 0. capture trigger is smartclock/8. 10: external clock is sysclk/12. capture trigger is comparator 0. 11: external clock is smartclock/8 . capture trigger is comparator 0.
c8051f91x-c8051f90x rev. 1.3 288 sfr page = 0x0; sfr address = 0xca sfr page = 0x0; sfr address = 0xcb sfr definition 25.9. tmr2rll: timer 2 relo ad register low byte bit 7 6 5 4 3 2 1 0 name tmr2rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rll[7:0] timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2. sfr definition 25.10. tmr2rlh: timer 2 relo ad register high byte bit 7 6 5 4 3 2 1 0 name tmr2rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rlh[7:0] timer 2 reload register high byte. tmr2rlh holds the high byte of the reload value for timer 2.
c8051f91x-c8051f90x 289 rev. 1.3 sfr page = 0x0; sfr address = 0xcc sfr page = 0x0; sfr address = 0xcd sfr definition 25.11. tmr2l: timer 2 low byte bit 7 6 5 4 3 2 1 0 name tmr2l[7:0] type r/w reset 00000000 bit name function 7:0 tmr2l[7:0] timer 2 low byte. in 16-bit mode, the tmr2l register contains th e low byte of the 16-bit timer 2. in 8- bit mode, tmr2l contains the 8-bit low byte timer value. sfr definition 25.12. tmr2h timer 2 high byte bit 7 6 5 4 3 2 1 0 name tmr2h[7:0] type r/w reset 00000000 bit name function 7:0 tmr2h[7:0] timer 2 high byte. in 16-bit mode, the tmr2h register contains the high byte of the 16-bit timer 2. in 8- b it mode, tmr2h contains the 8-bit high byte timer value.
c8051f91x-c8051f90x rev. 1.3 290 25.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may o perate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. the t3split bit (tmr2cn.3) defines the timer 3 operation mode. timer 3 can also be used in c apture mode to measure the exte rnal oscillator source or the comparator 1 period with respect to another os c illator. the ability to measure the comparator 1 period with respect to the system clock is makes using touch sense switches very easy. timer 3 may be clocked by the system clock, the system c lock divided by 12, external oscillator source divided by 8, or comparator 1 output. the external oscillator so urc e divided by 8 and comparator 1 output is synch ronized with the system clock. 25.3.1. 16-bit timer with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, external oscillator clock sour ce divided by 8, or comparator 1 o utput. as the 16-bit timer register increments and overflows from 0xffff to 0x 0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tmr3rll) is loaded into the timer 3 register as shown in figure 25.7 , and the timer 3 high byte overflow flag (tmr3cn. 7 ) is set. if timer 3 interrupts are enabled (if eie1.7 is set), an interrupt will be generated on each t imer 3 overflow. additionally, if timer 3 interrupts are enabled and the tf3len bit is set (tmr3cn.5), an interrupt will be generated each ti me the lower 8 bits (tmr3l) overflow from 0xff to 0x00. figure 25.7. timer 3 16-bit mode block diagram sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split t3xclk1 tf3cen tf3l tf3h t3xclk0 tr3 interrupt tf3len to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m external clock / 8 sysclk / 12 01 t3xclk[1:0] 10 11 comparator 1 sysclk / 12 00
c8051f91x-c8051f90x 291 rev. 1.3 25.3.2. 8-bit timers with auto-reload when t3split is set, timer 3 operates as two 8-bi t timers (tmr3h and tmr3l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 25.8 . tmr3rll holds the reload va lue for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr 3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be configured to use sysclk, sysc lk divided by 12, the external oscillator clock source divided by 8, or comparator 1. the timer 3 clock select bits (t3mh and t3ml in ckcon) select either sysclk or the clock defined by the timer 3 exte rnal clock select bits (t3xclk[1:0] in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00 ; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over - flows. if timer 3 interrupts are enabled and tf3len (tm r3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3le n is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. figure 25.8. timer 3 8-bit mode block diagram t3mh t3xclk[1:0] tmr3h clock source t3ml t3xclk[1:0] tmr3l clock source 0 00 sysclk / 12 0 00 sysclk / 12 0 01 external clock / 8 0 01 external clock / 8 0 10 sysclk / 12 0 10 sysclk / 12 0 11 comparator 1 0 11 comparator 1 1 x sysclk 1 x sysclk sysclk tclk 0 1 tr3 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split t3xclk1 tf3cen tf3len tf3l tf3h t3xclk0 tr3 to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m external clock / 8 sysclk / 12 01 t3xclk[1:0] 10 11 comparator 1 sysclk / 12 00
c8051f91x-c8051f90x rev. 1.3 292 25.3.3. comparator 1/external oscillator capture mode the capture mode in timer 3 allows either comparator 1 or the external oscillator period to be measured a gainst the system clock or the system clock divided by 12. comparator 1 and the external oscillator p eriod can also be compared against each other. setting tf3cen to 1 enables the comparator 1/external oscillator ca pture mode for t imer 3. in this mo de, t3split should be set to 0, as the full 16-bit timer is used. when capture mode is enable d, a c apture event will be gener ated either ev ery comparator 1 rising edge o r every 8 external clock cycles, depending on the t3xclk1 setting. when the capture event occurs, the contents of timer 3 (tmr3h:tmr3l) are loaded into the timer 3 reload registers (tmr3rlh:tmr3rll) a nd the tf3h flag is set (triggering an interrupt if timer 3 interrupts are enabled). by recording the differ - ence between two successive timer capture values, the comparator 1 or external clock period can be de termined with re spect to the timer 3 clock. the timer 3 clock should be much faste r than the capture clock to achieve an accurate reading. for example, if t3ml = 1b, t3xclk1 = 0b, and tf3cen = 1b, timer 3 will clock every sysclk and cap - ture every comparator 1 rising edge. if sysclk is 24.5 mhz and the difference between two successive ca ptures is 350 counts, then the comparator 1 period is: 350 x (1 / 24.5 mhz) = 14.2 s. this mode allows software to determine the exact frequency of th e external oscillator in c and rc mode or the time between consecutive comparator 0 rising edges, which is useful for detecting changes in the capacitance of a touch sense switch. figure 25.9. timer 3 capture mode block diagram external clock / 8 sysclk 0 1 t3xclk1 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr3l tmr3h tclk tr3 tmr3rll tmr3rlh capture tmr3cn t3split t3xclk1 tf3cen tf3l tf3h t3xclk0 tr3 tf3len tf3cen interrupt 0 1 comparator 1 external clock / 8 sysclk / 12 01 t3xclk[1:0] 10 11 comparator 1 sysclk / 12 00
c8051f91x-c8051f90x 293 rev. 1.3 sfr page = 0x0; sfr address = 0x91 sfr definition 25.13. tmr3cn: timer 3 control bit 7 6 5 4 3 2 1 0 name tf3h tf3l tf3len tf3cen t3split tr3 t3xclk[1:0] type r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tf3h timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 3 overflows from 0xffff to 0x0000. when the ti mer 3 interrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt s ervice routine. this bit is not automatically cleared by hardware. 6 tf3l timer 3 low byte overflow flag. set by hardware when the timer 3 low byte overflows from 0xff to 0x00. tf3l will be set when the low byte overflows regardless of the timer 3 mode. this bit is not au tomatically cleared by hardware. 5 tf3len timer 3 low byte interrupt enable. when set to 1, this bit enables timer 3 low byte inte rrupt s. if timer 3 interrupts are also enabled, an interrupt will be ge nerated when the lo w byte of timer 3 overflows. 4 tf3cen timer 3 comparator 1/external oscillator capture enable. when set to 1, this bit enables timer 3 capture mode. 3 t3split timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as two 8-bi t auto- reload timers. 2 tr3 timer 3 run control. timer 3 is enabled by setting this bit to 1. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is alwa ys enabled in split mode. 1:0 t3xclk[1:0] timer 3 external clock select. this bit selects the ?external? and ?capture trigger? clock sources for timer 3. if ti mer 3 is in 8-bit mode, this bit selects the ?external? cloc k source for both timer bytes. timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the ?external? cl ock and the system cloc k for either timer. note: external clock sources are sy n chronized with the system clock. 00: external clock is sysclk /12. capture trig ger is comparator 1. 01: external clock is external oscilla tor/8. capture trig ger is comparator 1. 10: external clock is sysclk/12. capt ure trigger is exte rnal oscillator/8. 11: external clock is comparator 1. capture trigger is external oscillator/8.
c8051f91x-c8051f90x rev. 1.3 294 sfr page = 0x0; sfr address = 0x92 sfr page = 0x0; sfr address = 0x93 sfr definition 25.14. tmr3rll: timer 3 relo ad register low byte bit 7 6 5 4 3 2 1 0 name tmr3rll[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rll[7:0] timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3. sfr definition 25.15. tmr3rlh: timer 3 relo ad register high byte bit 7 6 5 4 3 2 1 0 name tmr3rlh[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rlh[7:0] timer 3 reload register high byte. tmr3rlh holds the high byte of the reload value for timer 3.
c8051f91x-c8051f90x 295 rev. 1.3 sfr page = 0x0; sfr address = 0x94 sfr page = 0x0; sfr address = 0x95 sfr definition 25.16. tmr3l: timer 3 low byte bit 7 6 5 4 3 2 1 0 name tmr3l[7:0] type r/w reset 00000000 bit name function 7:0 tmr3l[7:0] timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8- bit mode, tmr3l contains the 8-bit low byte timer value. sfr definition 25.17. tmr3h timer 3 high byte bit 7 6 5 4 3 2 1 0 name tmr3h[7:0] type r/w reset 00000000 bit name function 7:0 tmr3h[7:0] timer 3 high byte. in 16-bit mode, the tmr3h register contains the high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value.
c8051f91x-c8051f90x rev. 1.3 296 26. programmable counter array the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and six 16-bit capture/compare modules. each capt ure/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled. the counter/timer is driven by a programmable timebase that can select between seve n sources: system clock, system clock divided by four, system clock divided by twelve, the external osc illator clock source divided by 8, smartclock divided by 8 ('f912 and 'f902 devices only), timer 0 overflows, or an external clock sig nal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge- triggered capture, software timer, high-speed output, frequency output, 8 to 11-bit pwm, or 16-bit pwm (each mode is described in se ction ?26.3. capture/compare modules? on page 300). the external oscillator clock option is ideal for real-time clock (r tc) functionality, allowing the pca to be clocked by a precision external oscillator while the internal oscillator drives the system clock. the pca is configured and controlled through the system controller's special func tion registers. the pca block diagram is shown in figure 26.1. important note: the pca module 5 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled . see section 26.4 for details. figure 26.1. pca block diagram capture/compare module 1 capture/compare module 0 capture/compare module 2 cex1 eci crossbar cex2 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 capture/compare module 4 capture/compare module 3 capture/compare module 5 / wdt cex4 cex5 cex3 smartclock/8* * only available on ?f912 and ?f902 devices.
c8051f91x-c8051f90x 297 rev. 1.3 26.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the lo w byte (lsb). reading pc a0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counter operation. the cps2 ? cps0 bits in the pca0md register select the timebase for the counter/timer as shown in table 26.1. when the counter/timer overflows from 0xffff to 0x0 000, the counter overflow fl ag (cf) in pca0md is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the in terrupt service routine, and must be cleared by software. clearing the cidl bit in the pca0md register allows the pca to continue normal operation while the cpu is in idle mode. table 26.1. pca timebase input options cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 100system clock 101 external oscillator source divided by 8 1 110 smartclock oscillator source divided by 8 2 111reserved notes: 1. external oscillator source divided by 8 is synchronized with the system clock. 2. smartclock oscillator source divided by 8 is synchronized with the syst em clock and is only available on 'f912 and 'f902 devices. this setting is reserved on all other devices.
c8051f91x-c8051f90x rev. 1.3 298 figure 26.2. pca counter/timer block diagram 26.2. pca0 interrupt sources figure 26.3 shows a diagram of the pca interrupt tr ee. there are eight independent event flags that can be used to generate a pca0 interrupt. they are: the main pca counter overflow flag (cf), which is set upon a 16-bit overflow of the pca0 counter, an inte rmediate overflow flag (covf), which can be set on an overflow from the 8th, 9th, 10th, or 11th bit of t he pca0 counter, and the individual flags for each pca channel (ccf0, ccf1, ccf2, ccf3, ccf4, and ccf5), which are set according to the operation mode of that module. these event flags are always set when the trigger condition occurs. each of these flags can be individually selected to genera te a pca0 interrupt, using the corr esponding interrupt enable flag (ecf for cf, ecov for covf, and eccfn for each ccfn). pc a0 interrupts must be globally enabled before any individual interrupt sources are recognized by the processor. pca0 interrupts are globally enabled by setting the ea bit and the epca0 bit to logic 1. pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 110 smartclock/8* * only available on ?f912 and ?f902 devices.
c8051f91x-c8051f90x 299 rev. 1.3 figure 26.3. pca interrupt block diagram pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 5 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 pca counter/timer 16- bit overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 5) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0pwm a r s e l c o v f c l s e l 0 c l s e l 1 e c o v pca counter/timer 8, 9, 10 or 11-bit overflow 0 1 set 8, 9, 10, or 11 bit operation 0 1 pca module 3 (ccf3) pca module 4 (ccf4) eccf4 0 1 pca module 5 (ccf5) eccf5 eccf3 0 1
c8051f91x-c8051f90x rev. 1.3 300 26.3. capture/compare modules each module can be configured to operate independent ly in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8 to 11-bit pulse width modulator, or 16-bit pulse width modulator. each module has special function registers (sfrs) associated with it in the cip-51 system controller. these registers are used to exch ange data with a module and configure the module's mode of operation. table 26.2 summarizes the bit settings in the pca0cpmn and pca0pwm registers used to select the pca capture/compare module?s oper ating mode. note that all modules set to use 8, 9, 10, or 11-bit pwm mode must use the same cycle length (8-11 bits). setting the eccfn bit in a pca0cpmn register enables the module's ccfn interrupt. table 26.2. pca0cpm and pca0pwm bit settings for pca capture/compare modules operational mode pca0cpmn pca0pwm bit number76543210765 4-2 1?0 capture triggered by positive edge on cexn xx10000a0xbxxx xx capture triggered by negative edge on cexn xx01000a0xbxxx xx capture triggered by any transition on cexn xx11000a0xbxxx xx software timer xc00100a0xbxxx xx high-speed output xc00110a0xbxxx xx frequency output xc00011a0xbxxx xx 8-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a 0 x b xxx 00 9-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 01 10-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 10 11-bit pulse width modulator (note 7) 0 c 0 0 e 0 1 a d x b xxx 11 16-bit pulse width modulator 1 c 0 0 e 0 1 a 0 x b xxx xx notes: 1. x = don?t care (no functional difference for individual module if 1 or 0). 2. a = enable interrupts for this module (pca interrupt triggered on ccfn set to 1). 3. b = enable 8th, 9th, 10th or 11th bit overfl ow interrupt (depends on setting of clsel[1:0]). 4. c = when set to 0, the digital comparator is off. for high speed and frequency output modes, the associated pin will not toggle. in any of the pwm modes, this generates a 0% duty cycle (output = 0). 5. d = selects whether the capture/compare register (0) or the auto-reload register (1) for the associated channel is accessed via addresses pca0cphn and pca0cpln. 6. e = when set, a match event will cause the ccfn flag for the associated channel to be set. 7. all modules set to 8, 9, 10 or 11-bit pw m mode use the same cycle length setting.
c8051f91x-c8051f90x 301 rev. 1.3 26.3.1. edge-triggered capture mode in this mode, a valid transition on the cexn pi n causes the pca to capture the value of the pca counter/timer and load it into the corresponding mo dule's 16-bit capture/compar e register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cp mn register are used to select the type of transition that triggers the capture: low-to-high transi tion (positive edge), high -to-low transition (negative edge), or either transition (positive or negative ed ge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by soft ware. if both cappn and capnn bi ts are set to logic 1, then the state of the port pin associated with cexn can be read directly to determi ne whether a rising-edge or falling-edge caused the capture. figure 26.4. pca capture mode diagram note: the cexn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hard ware. pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt x000x x
c8051f91x-c8051f90x rev. 1.3 302 26.3.2. software timer (compare) mode in software timer mode, the pca c ounter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 26.5. pca software timer mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt
c8051f91x-c8051f90x 303 rev. 1.3 26.3.3. high-speed output mode in high-speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1. an interrupt request is generated if the ccfn interrupt for that module is enabled. the ccfn bit is not automatically cleared by hardware when the cpu vect ors to the interrupt service routine, and must be cleared by software. setting the togn, matn, and ecomn bits in the pca0cpmn register enables the high-speed output mode. if ecomn is cleared, the associated pin will retain its state, and not toggle on the next match event. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. figure 26.6. pca high-speed output mode diagram match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 pca interrupt
c8051f91x-c8051f90x rev. 1.3 304 26.3.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte hol ds the number of pca clocks to count before the output is toggled. the frequency of the s quare wave is then defined by equation 26.1. equation 26.1. square wave frequency output where f pca is the frequency of the clock selected by the cps2 ? 0 bits in the pca mode register, pca0md. the lower byte of the capture/compare modu le is compared to the pca counter low byte; on a match, cexn is toggled and the offset held in the hi gh byte is added to the matched value in pca0cpln. frequency output mode is enabled by setting the ecomn, togn, and pwmn bits in the pca0cpmn register. note that the matn bit should normally be set to 0 in this mode. if the ma tn bit is set to 1, the ccfn flag for the channel will be set when the 16-bit pca0 counter and the 16-bit capture/compare register for the channel are equal. figure 26.7. pca frequency output mode f cexn f pca 2 pca0 cphn note: a value of 0x00 in the pca0cphn register is equal to 256 for this equation. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset
c8051f91x-c8051f90x 305 rev. 1.3 26.3.5. 8-bit, 9-bit, 10-bit and 11-bit pulse width modulator modes each module can be used independently to gener ate a pulse width modulated (pwm) output on its associated cexn pin. the frequency of the output is dependent on the timebase for the pca counter/timer, and the setting of the pwm cycle length (8, 9, 10 or 11-bits). for backwards- compatibility with the 8-bit pwm mode available on other devices, the 8-bit pwm mode operates slightly different than 9, 10 and 11- bit pwm modes. it is important to note that all channels configured for 8/9/10/11-bit pwm mode will use the same cycle length. it is not possible to configure one channel for 8-bit pwm mode and another for 11-bit mode (for example). however, other pca channels can be configured to pin capture, high- speed output, software timer, frequency output, or 16-bit pwm mode independently. 26.3.5.1. 8-bit pulse width modulator mode the duty cycle of the pwm output signal in 8-bit pw m mode is varied using the module's pca0cpln capture/compare register. when the value in the low by te of the pca counter/timer (pca0l) is equal to the value in pca0cpln, the output on th e cexn pin will be set. when the coun t value in pca0l overflows, the cexn output will be reset (see figure 26.8). also, when the counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically with the value stored in the module?s capture/compare high byte (pca0cphn) without software intervention. setting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to 00b enables 8-bit pulse width modulator mode. if the matn bit is se t to 1, the ccfn flag for the modu le will be set each time an 8-bit comparator match (rising edge) occurs. the covf flag in pca0pwm can be used to detect the overflow (falling edge), which will occur every 256 pca clock cycles. the duty cycle for 8-bit pwm mode is given in equation 26.2. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 26.2. 8-bit pwm duty cycle using equation 26.2, the largest duty cycle is 100 % (pca0cphn = 0), and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 26.8. pca 8-bit pwm mode diagram duty cycle 256 pca0 cphn ? () 256 ----------------------------------- ---------------- = 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l c l s e l 0 c l s e l 1 e c o v x0 0 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset covf c o v f
c8051f91x-c8051f90x rev. 1.3 306 26.3.5.2. 9/10/11-bit pulse width modulator mode the duty cycle of the pwm output signa l in 9/10/11-bit pwm mode should be varied by writing to an ?auto- reload? register, which is dual-mapped into the pc a0cphn and pca0cpln register locations. the data written to define the duty cycle should be right-just ified in the registers. the auto-reload registers are accessed (read or written) when the bit arsel in pca0pwm is set to 1. the capture/compare registers are accessed when arsel is set to 0. when the least-significant n bits of the pca0 co unter match the value in the associated module?s capture/compare register (pca0cpn), the output on cexn is asserted high. when the counter overflows from the nth bit, cexn is asserted low (see figure 26 .9). upon an overflow from the nth bit, the covf flag is set, and the value stored in the module?s auto-r eload register is loaded into the capture/compare register. the value of n is determined by the clsel bits in register pca0pwm. the 9, 10 or 11-bit pwm mode is selected by se tting the ecomn and pwmn bits in the pca0cpmn register, and setting the clsel bits in register pca0pwm to the desired cycle length (other than 8-bits). if the matn bit is set to 1, the ccfn flag for the mo dule will be set each time a comparator match (rising edge) occurs. the covf flag in pc a0pwm can be used to detect the overflow (falling edge), which will occur every 512 (9-bit), 1024 (10-bit) or 2048 (11-bi t) pca clock cycles. the duty cycle for 9/10/11-bit pwm mode is given in equation 26.2, where n is the number of bits in the pwm cycle. important note about pca0cphn and pca0cpln registers : when writing a 16-bit value to the pca0cpn registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 26.3. 9, 10, and 11-bit pwm duty cycle a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 26.9. pca 9, 10 and 11-bit pwm mode diagram duty cycle 2 n pca0 cpn ? () 2 n -------------------------------- ----------- - = n-bit comparator pca0h:l (capture/compare) pca0cph:ln (right-justified) (auto-reload) pca0cph:ln (right-justified) cexn crossbar port i/o enable overflow of n th bit pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 pca0pwm a r s e l c l s e l 0 c l s e l 1 e c o v x enb enb 0 1 write to pca0cpln write to pca0cphn reset r/w when arsel = 1 r/w when arsel = 0 set ?n? bits: 01 = 9 bits 10 = 10 bits 11 = 11 bits c o v f
c8051f91x-c8051f90x 307 rev. 1.3 26.3.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. 16-bit pwm mode is independent of the other (8/9/10/11-bit) pwm modes. in this mode, the 16-bit capture/compare module defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the module contents, the output on cexn is asserted high; when the 16-bit counter overflows, cexn is asserted low. to output a varying duty cycle, new value writes should be synchronized with pca ccfn match interrupts. 16-bit pwm mode is enabled by setting the ecomn, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/compar e register writes. if the matn bit is set to 1, the ccfn flag for the module will be set each time a 16-bit comparator match (rising edge) oc curs. the cf flag in pca0cn can be used to detect the overflow (falling edge). the duty cycle for 16-bit pwm mode is given by equation 26.4. important note about capture/compare registers : when writing a 16-bit value to the pca0 capture/compare registers, the low byte should always be written first. writing to pca0cpln clears the ecomn bit to 0; writing to pca0cphn sets ecomn to 1. equation 26.4. 16-bit pwm duty cycle using equation 26.4, the largest duty cycle is 100% (pca0cpn = 0), and the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to 0. figure 26.10. pca 16-bit pwm mode duty cycle 65536 pca0 cpn ? () 65536 ---------------------------------------------------- - = pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset
c8051f91x-c8051f90x rev. 1.3 308 26.4. watchdog timer mode a programmable watchdog timer (wdt) function is avai lable through the pca module 5. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph5) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte bit set in the pca0md register, mo dule 5 operates as a watchdog timer (wdt). the module 5 high byte is compared to the pca counter high byte; the module 5 low byte holds the offset to be used when wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled. the wdt will generate a reset shortly after code begins execution. to avoid this reset, the wdt should be explicitly disabled (and optionally re-configured and re-enabled if it is used in the system). 26.4.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2 ? cps0) ar e frozen. ? pca idle control bi t ( cidl) is frozen. ? module 5 is forced in to sof tware timer mode. ? writes to the module 5 mode register (pca0cpm5) are disabled. while the wdt is enabled, writes to the cr bit will not c hange the pca counter state; the counter will run until the wdt is disabled. the pca counter run control bit (cr) will re ad zero if the wdt is enabled but user software has not enabled th e pca counter. if a match occurs between pca0cph5 and pca0h while the wdt is enabled, a reset will be generated. to pr event a wdt reset, the wd t may be up dated with a write of any value to pca0cph5. up on a pca0cph5 write, pca0h plus the offset held in pca0cpl5 is loaded into pca0cph5 (see figure 26.11). figure 26.11. pca module 5 with watchdog timer enabled pca0h enable pca0l overflow reset pca0cpl5 8-bit adder pca0cph5 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph5 8-bit comparator
c8051f91x-c8051f90x 309 rev. 1.3 the 8-bit offset held in pca0cph5 is compared to th e upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a re set. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the value of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 26.5 , where pca0l is the value of the pca0l register at the time of the update. equation 26.5. watchdog timer offset in pca clocks the wdt reset is generated when pca0l overflow s while there is a match between pca0cph5 and pca0h. software may force a wdt reset by writing a 1 to the ccf5 flag (pca0cn.5) while the wdt is enabled. 26.4.2. watchdog timer usage to configure the wdt, perform the following tasks: ? disable the wdt by writing a 0 to the wdte bit. ? select the desired pca clo ck source (with the cps2 ? cps0 bits). ? load pca0cpl5 with the desi r ed wdt update offset value. ? configure the pca idle mode (set cidl if the wdt should be suspended while the cpu is in idle mode). ? enable the wdt by setting the wdte bit to 1. ? reset the wdt timer by writing to pca0cph5. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog time r is enabled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any rese t. the pca0 counter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl5 defaults to 0x00. using equation 26.5, this results in a wdt timeout interval of 256 pca clock cycles, or 3072 system clock cycles. table 26.3 lists some example timeout intervals for typical system clocks. table 26.3. watchdog timer timeout intervals system clock (hz) pca0cpl5 timeout interval (ms) 24,500,000 255 32.1 24,500,000 128 16.2 24,500,000 32 4.1 3,062,500 * 255 257 3,062,500 * 128 129.5 3,062,500 * 32 33.1 32,000 255 24576 32,000 128 12384 32,000 32 3168 *note: internal sysclk reset frequency = internal oscillator divided by 8. offset 256 pca0 cpl5 () 256 pca0 l ? () + =
c8051f91x-c8051f90x rev. 1.3 310 26.5. register descriptions for pca0 following are detailed descriptions of the special func tion registers related to the operation of the pca. sfr page = 0x0; sfr addres s = 0xd8; bit-addressable sfr definition 26.1. pca0cn: pca control bit 7 6 5 4 3 2 1 0 name cf cr ccf5 ccf4 ccf3 ccf2 ccf1 ccf0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 cf pca counter/timer overflow flag. set by hardware when the pca counter/timer overflows from 0xffff to 0x0000. w hen the counter/timer overflow (cf) interrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service r outine. this bit is not automatically cleared by hardware and must be cleared by software. 6 cr pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. 5:0 ccf[5:0] pca module n capture/compare flag. these bits are set by hardware when a matc h or capture occurs in the associated pca module n. when the ccfn interrupt is en abled, setting this bi t causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software.
c8051f91x-c8051f90x 311 rev. 1.3 sfr page = 0x0; sfr address = 0xd9 sfr definition 26.2. pca0md: pca mode bit 7 6 5 4 3 2 1 0 name cidl wdte wdlck cps2 cps1 cps0 ecf type r/w r/w r/w r r/w r/w r/w r/w reset 0 1 0 0 0 0 0 0 bit name function 7 cidl pca counter/timer idle control. specifies pca behavior when cpu is in idle mode. 0: pca continues to function normally while the system co ntroller is in idle mode. 1: pca operation is suspended while th e sys tem controller is in idle mode. 6 wdte watchdog timer enable. if this bit is set, pca module 2 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 2 enabled as watchdog timer. 5 wdlck watchdog timer lock. this bit locks/unlocks the watchdog timer e n able. when wdlck is set, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer enable unlocked. 1: watchdog timer enable locked. 4 unused read = 0b, write = don't care. 3:1 cps[2:0] pca counter/timer pulse select. these bits select the timebase source for the pca counter 000: system clock divided by 12 001: system clock divided by 4 010: timer 0 overflow 011: high-to-low transitions on eci (max rate = syste m clock divided by 4) 100: system clock 101: external clock divided by 8 (synchronized with the system clock) 110: smartclock divided by 8 (synchronized with the system clock and only avail - able on ?f912 and ?f902 devices -- this setting is reserved on all other devices) 111: reserved 0 ecf pca counter/timer overflow interrupt enable. this bit sets the masking of the pca co un ter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow in terrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to 1, the other bits in t he pca0md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled.
c8051f91x-c8051f90x rev. 1.3 312 sfr page = 0x0; sfr address = 0xdf sfr definition 26.3. pca0pwm: pca pwm configuration bit 7 6 5 4 3 2 1 0 name arsel ecov covf clsel[1:0] type r/w r/w r/w r r r r/w reset 0 0 0 0 0 0 0 0 bit name function 7 arsel auto-reload register select. this bit selects whether to read and write the normal pca capture/compare registers (pca0cpn) , or the auto-reload registers at the same sfr addresses. this function is used to define the reload value for 9, 10, and 11-bit pwm modes. in all other modes, the auto-reload registers have no function. 0: read/write capture/compare registers at pca0cphn and pca0cpln. 1: read/write auto-reload regi sters at pca0cphn and pca0cpln. 6 ecov cycle overflow interrupt enable. this bit sets the masking of the cycle overflow flag (covf) interrupt. 0: covf will not gene rate pca interrupts. 1: a pca interrupt will be ge nerated w hen covf is set. 5 covf cycle overflow flag. this bit indicates an overflow of the 8th, 9th, 10th, or 11th bit of the main pca counter (pca0) . the specific bit used for this flag depends on the setting of the cycle length select bits. the bit can be set by hardware or software, but must be cleared by soft - ware. 0: no overflow has occurred since th e last time this bit was cleared. 1: an overflow has occurred since t he last time this bit was cleared. 4:2 unused unused. read = 000b; write = don?t care. 1:0 clsel[1:0] cycle length select. when 16-bit pwm mode is not selected, th ese bits select the length of the pwm cycle, between 8, 9, 10, or 11 bits. this affects all channels configured for pwm which are not using 16-bit pwm mode. these bits are ignored for individual channels config - ured to16-bit pwm mode. 00: 8 bits. 01: 9 bits. 10: 10 bits. 11: 11 bits.
c8051f91x-c8051f90x 313 rev. 1.3 sfr address, page: pca0cpm0 = 0xda , 0x0; pca0cpm1 = 0xdb , 0x0; pca0cpm2 = 0xdc, 0x0 pca0cpm3 = 0xdd , 0x0; pca0cpm4 = 0xde , 0x0; pca0cpm5 = 0xce, 0x0 sfr definition 26.4. pca0cpmn: pca capture/compare mode bit 7 6 5 4 3 2 1 0 name pwm16n ecomn cappn capnn matn togn pwmn eccfn type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7 pwm16n 16-bit pulse width modulation enable. this bit enables 16-bit mode when pulse width modulation mode is enabled. 0: 8 to 11-bit pwm selected. 1: 16-bit pwm selected. 6 ecomn comparator function enable. this bit enables the comparator function for pca module n when set to 1. 5 cappn capture positive function enable. this bit enables the positive edge capture for pca module n when set to 1. 4 capnn capture negative function enable. this bit enables the negative edge capture for pca module n when set to 1. 3 matn match function enable. this bit enables the match function for pca module n when set to 1. when enabled, matches of the pca counter with a module's capture/compare regist er cause the ccfn bit in pca0md register to be set to logic 1. 2 togn toggle function enable. this bit enables the toggle function for pca module n when set to 1. when enabled, matches of th e pca counter with a module's capture/compare register cause the logic level on the cexn pin to toggle . if the pwmn bit is also set to logic 1, the module oper - ates in frequency output mode. 1 pwmn pulse width modulation mode enable. this bit enables the pwm function for pca module n when set to 1. when enabled, a pulse width modulated signal is output on the cexn pin. 8 to 11-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm1 6n is set to logic 1. if the togn bit is also set, the module operates in frequency output mode. 0 eccfn capture/compare flag interrupt enable. this bit sets the masking of the ca ptur e/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. note: when the wdte bit is set to 1, the pca0cpm5 register cannot be modified, and module 5 acts as the watchdog timer. to change the contents of the pca0cpm5 register or the function of module 5, the watchdog timer must be disabled.
c8051f91x-c8051f90x rev. 1.3 314 sfr page = 0x0; sfr address = 0xf9 sfr page = 0x0; sfr address = 0xfa sfr definition 26.5. pca0l: pca counter/timer low byte bit 7 6 5 4 3 2 1 0 name pca0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0[7:0] pca counter/timer low byte. the pca0l register holds the low byte (l sb) of the 16-bit pca counter/timer. note: when the wdte bit is set to 1, the pca0l register canno t be modified by software. to change the contents of the pca0l register, the watchdog timer must first be disabled. sfr definition 26.6. pca0h: pca counter/timer high byte bit 7 6 5 4 3 2 1 0 name pca0[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0[15:8] pca counter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. reads of this register will re ad the contents of a ?snapshot ? register, whose contents are updated only when the cont ents of pca0l are read (see section 26.1 ). note: when the wdte bit is set to 1, the pca0h register cannot be modified by software. to change the contents of the pca0h register, the watchdog timer must first be disabled.
c8051f91x-c8051f90x 315 rev. 1.3 sfr addresses: pca0cpl0 = 0xfb , pca0cpl1 = 0xe9 , pca0cpl2 = 0xeb, pca0cpl3 = 0xed , pca0cpl4 = 0xfd , pca0cpl5 = 0xd2 sfr pages: pca0cpl0 = 0x0 , pca0cpl1 = 0x0 , pca0cpl2 = 0x0, pca0cpl3 = 0x0 , pca0cpl4 = 0x0 , pca0cpl5 = 0x0 sfr addresses: pca0cph0 = 0xfc , pca0cph1 = 0xea , pca0cph2 = 0xec, pca0cph3 = 0xee , pca0cph4 = 0xfe , pca0cph5 = 0xd3 sfr pages: pca0cph0 = 0x0 , pca0cph1 = 0x0 , pca0cph2 = 0x0, pca0cph3 = 0x0 , pca0cph4 = 0x0 , pca0cph5 = 0x0 sfr definition 26.7. pca0cpln: pca capt ure module low byte bit 7 6 5 4 3 2 1 0 name pca0cpn[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0cpn[7:0] pca capture module low byte. the pca0cpln register holds the low byte (l sb) of the 16-bit capture module n. this register address also allows acce ss to the low byte of the corresponding pca channel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will clear the module?s ecomn bit to a 0. sfr definition 26.8. pca0cphn: pca capture module high byte bit 7 6 5 4 3 2 1 0 name pca0cpn[15:8] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 pca0cpn[15:8] pca capture module high byte. the pca0cphn register holds the high byte (m sb) of the 16-bit capture module n. this register address also allows access to the high byte of the corresponding pca ch annel?s auto-reload value for 9, 10, or 11-bit pwm mode. the arsel bit in register pca0pwm controls which register is accessed. note: a write to this register will set the module?s ecomn bit to a 1.
c8051f91x-c8051f90x rev. 1.3 316 27. c2 interface c8051f91x-c8051f90x devices includ e an on-chip silicon labs 2-wire (c2) debug interface to allow flash programming and in-system debugging with the produ ction part installed in the end application. the c2 interface uses a clock signal (c2ck) and a bi-direc tional c2 data signal (c2d) to transfer information between the device and a hos t system. see the c2 interface specificat ion for details on the c2 protocol. 27.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming through the c2 inter - face. all c2 registers are accessed through the c2 inte r face as described in the c2 interface specification. c2 register definition 27.1. c2add: c2 address bit 7 6 5 4 3 2 1 0 name c2add[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 c2add[7:0] c2 address. the c2add register is accessed via the c2 interface to select the target data register fo r c2 data read and data write commands. address description 0x00 selects the device id register for data read instructions 0x01 selects the revision id register for dat a read instructions 0x02 selects the c2 flash programming control register for data read/w rite instructions 0xb4 selects the c2 flash programm ing data register for data read/write instructions
c8051f91x-c8051f90x 317 rev. 1.3 c2 address: 0x00 c2 address: 0x01 c2 register definition 27.2. deviceid: c2 device id bit 7 6 5 4 3 2 1 0 name deviceid[7:0] type r/w reset 0 0 0 1 1 1 1 1 bit name function 7:0 deviceid[7:0] device id. this read-only register returns the 8-bit device id: 0x1f. c2 register definition 27.3. revid: c2 revision id bit 7 6 5 4 3 2 1 0 name revid[7:0] type r/w reset varies varies varies varies varies varies varies varies bit name function 7:0 revid[7:0] revision id. this read-only register returns the 8-bit revision id. for example: 0x03 = revision d
c8051f91x-c8051f90x rev. 1.3 318 c2 address: 0x02 c2 address: 0xb4 c2 register definition 27.4. fpctl: c2 flash programming control bit 7 6 5 4 3 2 1 0 name fpctl[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 fpctl[7:0] flash programming control register. this register is used to enable flash programming via the c2 interface. to enable c2 fla sh programming, the following codes must be written in order: 0x02, 0x01. note that once c2 flash programming is ena bled, a system reset must be issued to resume normal operation. c2 register definition 27.5. fpdat: c2 flash programming data bit 7 6 5 4 3 2 1 0 name fpdat[7:0] type r/w reset 0 0 0 0 0 0 0 0 bit name function 7:0 fpdat[7:0] c2 flash programming data register. this register is used to pass flash commands, addresses, and data during c2 flash a ccesses. valid commands are listed below. code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase
c8051f91x-c8051f90x 319 rev. 1.3 27.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming may be performed. this is possible because c2 communication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface ca n safely ?borrow? the c2ck ( rst ) and c2d pins. in most applications, external resistors are required to isolate c2 interface traffic from the user application. a typical isolation configuration is shown in figure 27.1 . figure 27.1. typical c2 pin sharing the configuration in figure 27.1 assumes the following: 1. the user input (b) cannot change stat e while the target device is halted. 2. the rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application. c2d c2ck rst (a) input (b) output (c) c2 interface master c8051fxxx
c8051f91x-c8051f90x rev. 1.3 320 d ocument c hange l ist revision 0.2 to revision 1.0 ? updated specification tables to remove tbds. ? updated power management section to indicate that the low power or precision oscillator must be selected when entering sleep or suspend mode. ? updated port i/o chapter with additional clarification on 5 v and 3.3 v tolerance. ? updated qfn-42 landing diagram and stencil recommendations. ? updated description of adc0 12-bit mode. revision 1.0 to revision 1.1 ? removed references to an338. revision 1.1 to revision 1.2 ? updated all part numbers in table 2.1, ?product selection guide,? on page 30. ? added package marking diagrams as figure 3.3 and fi gure 3.4 to help identify the silicon revision. ? clarified conditions that apply to ?vbat ramp time for power on? fo r one-cell mode vs two-cell mode in table 4.4, ?reset electrical characteristics,? on page 59. ? updated section ?5.2.3. burst mode? on page 72 and figure 5.3 to show difference in behavior between internal convert start signals and external cnvstr signal. ? added note about the need to ground the adc mux be fore switching to the temperature sensor in section ?5.8. temperature sensor? on page 88 and in sfr definition 5.12 ?adc0mx?. ? updated titles of sfr definition 5.13, ?t offh?, and sfr definition 5.14, ?toffl?. ? updated figure 7.4, ?cpn multiplexer block diagra m,? to correct the locations of vdd/dc+, vbat, digital supply, and gnd multiplexer inputs. ? updated table 8.1 to correct number of clock cycles for ?cjne a, direct, rel?. ? corrected vdd ramp time reference in item 2 of section ?13.5.1. vdd maintenance and the vdd monitor? on page 143. ? updated cpt0wk bit descr iption in sfr definition 14.1, ?pmu0cf?. ? added section ?15.2. 32-bit crc algorithm? on page 160 to illustrate the 32-bit crc algorithm. ? updated the second paragraph of section ?20.3. sm artclock timer and alarm function? on page 204. ? corrected clock sources associated with t3xclk settings in section ?25.3.2. 8-bit timers with auto- reload? on page 291, figure 25.7, figure 25.8, an d figure 25.9 to match the description in sfr definition 25.13. ? replaced incorrect pca channel references from pca0cph2 to pc a0cph5 in section ?26.4. watchdog timer mode? on page 308 and figure 26.11. ? updated revision listed in c2 register definition 27.3 to revision c. revision 1.2 to revision 1.3 ? updated part numbers to revision d in ?ordering information? on page 30. ? updated figure 7.4, ?cpn multiplexer block diagram,? to remove the bar over the cpnout signals. ? updated the ?reset sources? on page 177 chapt er to reflect the correct state of the rst pin during a power-on reset.
c8051f91x-c8051f90x 321 rev. 1.3 n otes :
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