pex 8733, pci express gen 3 switch, 32 lanes, 18 ports ? plx technology, www.plxtech.com page 1 of 5 22aug11, v ersion 1.0 highlights ? PEX8733 general features o 32 - lane, 18 - port pcie gen 3 switch - integrated 8 .0 gt/s serdes o 27 x 27 mm 2 , 676 - pin fcbga package o typical power: 6.4 watts ? PEX8733 key features o standards compliant - pci express base specification, r 3 .0 (compatible w/ pcie r1.0a/1.1 & 2.0 ) - pci power management spec, r1.2 - microsoft vista compliant - supports access control services - dynamic link - width control - dynamic serdes speed control o high performance ? performance pak ? read pacing (bandwidth throttling) ? multic ast ? dynamic bu ffer/fc credit pool - non - blocking switch fabric - full line rate on all ports - packet cut - thru with 1 32ns max packet latency (x8 to x8 ) - 2kb max payload size o integrated dma engine - four dma channels - internal descriptor support - dma function independent from tran sparent switch function - 64 - bit addressing - pre - fetch descriptor mode - stride mode o multi - host & fail - over support - 2 configurable n on - transparent port s - failover with n on - t ransparent port - up to 4 upstream/host ports with 1+1 or n+1 failover to other upstream po rts o quality of service (qos) - two virtual channels - eight traffic classes per port - weighted round - robin source port arbitration o reliability, availability, serviceability ? vision pak ? per port performance monitoring ? serdes eye capture ? pcie packet generator ? erro r injection and loopback - 3 hot - plug ports with native hp signals - all ports hot - plug capable thru i 2 c - ssc isolation on up to 8 ports - ecrc and poison bit support - data path parity - memory (ram) error correction - advanced error reporting - port status bits and g pio available - jtag ac/dc boundary scan the expresslane? PEX8733 device offers multi - host pci express switching capability enabling users to connect multiple hosts to their respective endpoints via scalable, high bandwidth, non - blocking interconnection to a wide variety of applications including servers, storage, communications, and graphics platforms. the PEX8733 i s well suited for fan - out , aggregation , and peer - to - peer traffic patterns . multi - host architecture the PEX8733 employs an enhanced version o f plxs field teste d pex 8 7 32 pcie switch architecture, which allows users to configure the device in legacy single - host mode or multi - host mode with up to four host ports capable of 1+1 (one active & one backup ) or n+1 (n active & one backup ) host failove r. this powerful architectural enhancement enables users to build pcie based systems to support high - avail ability, failover, redundant, or clustered systems. high performance & low packet latency the PEX8733 architecture supports packet cut - thru with a maximum latency of 1 32 ns (x 8 to x 8 ). this, combined with large packet memory, flexible common buffer/fc credit pool and non - blocking internal switch architecture, provides full line rate on all ports for performance - hungry applications such as servers an d switch fabrics . the low latency enables applications to achieve high throughput and performance. in addition to low latency, the device supports a packet payload size of up to 20 48 bytes, enabling the user to achieve even higher throughput. integrated d ma engine the PEX8733 boasts a versatile and powerful built - in dma engine . the dma engine removes the burden of having to move data between devices away from the processor C allowing the processor to perform computational tasks instead. the four dma chann els can support high data rate transfers between i/o devices connected to any of the switch s ports. additionally, the dma engine in the PEX8733 can be used to complement the dma engine in the processor by providing additional dma channels for higher perf ormance. data integrity the PEX8733 provides end - to - end crc (ecrc) protection and poison bit support to enable designs that require end - to - end data integrity . plx also supports data path parity and memory (ram) error correction circuitry throughout the i nternal data paths as packets pass through the switch. flexible configuration the PEX8733 s 18 ports can be configured to lane widths of x1, x2, x4, x8, or x16. flexible buffer allocation, along with the device's flexible packet flow control, maximizes throughput for applications where more traffic flows in the downstream, rather than upstream, direction. any port can be designated as the upstream port, which can be changed dynamically. figure 1 shows some of the PEX8733 s common port configurations in legacy single - host mode .
pex 8733, pci express gen 3 switch, 32 lanes, 18 ports ? plx technology, www.plxtech.com page 2 of 5 22aug11, v ersion 1.0 the PEX8733 can also be configured in multi - host mode where users can choose up to four ports as host/upstream ports and assign a desired number of downstream ports to each host. in multi - host mode, a virtual switch is created fo r each host port and its associated downstream ports inside the device. the traffic between the ports of a virtual switch is completely isolated from the traffic in other virtual switches. figure 2 illustrates some configurations of the PEX8733 in multi - h ost mode where each ellipse represents a virtual switch inside the device. the PEX8733 also provides several ways to configure its registers. the device can be configured through strapping pins, i 2 c interface , host software, or an optional serial eepro m. this allows for easy debug during the development phase, performance monitoring during the operation phase, and driver or software upgrade. dual - host & failover support in single - host mode, the PEX8733 supports 2 non - transparent (nt) port s , which en ables the implementation of dual - host systems for redundancy and host failover capability. the nt port allows systems to isolate host memory domains by presenting the processor subsystem as an endpoint rather than another memory system. base address regist ers are used to translate addresses; doorbell registers are used to send interrupts between the address domains; and scratchpad registers (accessible by both cpus) allow inter - processor communication (see figure 3). multi - host & failover support in multi - host mode, PEX8733 can be configured with up to four upstream host ports, each with its own dedicated downstream ports. the device can be configured for 1+1 redundancy or n+1 redundancy. the PEX8733 allows the hosts to communicate their status to each ot her via special door - bell registers. in failover mode, if a host fails, the host designated for failover will disable the upstream port attached to the failing host and program the downstream ports of that host to its own domain. figure 4a shows a two host system in multi - host mode with two virtual switches inside the device and figure 4b shows h ost 1 disabled after failure and h ost 2 having taken over all of h ost 1s end - points. hot - plug for high availability hot plug capability allows users to replace hardware modules and perform maintenance without powering down the system. the PEX8733 hot - plug capability feature makes it suitable for high availability (ha) applications . three downstream ports include a standard hot plug controller. if the PEX8733 is used in an application where one or more of its downstream ports connect to pci express slots, each ports hot - plug controller can be used to manage the hot - plug event of its associated slot. every port on the PEX8733 is equipped with a hot - plug control/ status register to support hot - plug capability through external logic via the i 2 c interface. serdes power and signal management the PEX8733 provides low power capability that is fully compliant with the pcie power management specification and supports so ftware control of the serdes outputs to allow optimization of power and signal strength in a system. furthermore, t he serdes block supports loop - back modes and advanced reporting of error conditions , which enables efficient management of the entire system. interoperability the PEX8733 is designed to be fully compliant with the p ci express base specification r3 .0, and is backwards compatible to p ci express base specification r2 . 0, r1.1,
PEX8733 , pci express gen 3 switch, 32 lanes, 18 ports ? plx technology, www.plxtech.com page 3 of 5 22aug11, v ersion 1.0 and r1.0a . additionally, it supports auto - negotiation , lane reversal , and polarity reversal . furthermore , the PEX8733 is tested for microsoft vista compliance as well . all plx switches undergo thorough interoperability testing in plxs interoperability lab and compliance testing at the pci - sig plug - fest . performance pak ? ex clusive to plx, performance pak is a suite of unique and innovative performance features which allows plxs gen 3 switches to be the highest performing gen 3 switches in the market today. the performance pak features consists of the read pacing, multicast, a nd dynamic buffer pool. read pacing the read pacing feature allows users to throttle the amount of read requests being made by downstream devices. when a downstream device requests several long reads back - to - back, the root complex gets tied up in serving t hat downstream port. if that port has a narrow link and is therefore slow in receiving these read packets from the root complex, then other downstream ports may become starved C thus, impacting performance. the read pacing feature enhances performances by allowing for the adequate servicing of all downstream devices. multicast the multica st feature enables the copying of data (packets) from one ingress port to multiple (up to 1 7 ) egress ports in one transaction allow ing for higher performance in dual - graphi cs, storage, security, and redundant applications , among others . multicast relieves the cpu from having to conduct multiple redundant transactions, resulting in higher system performance. dynamic buffer pool the PEX8733 employs a dynamic buffer pool for f low control (fc) management. as opposed to a static buffer scheme which assigns fixed, static buffers to each port, plxs dynamic buffer allocation scheme utilizes a common pool of fc credits which are shared by other ports. this shared buffer pool is full y programmable by the user, so fc credits can be allocated among the ports as needed. not only does this prevent wasted buffers and inappropriate buffer assignments, any unallocated buffers remain in the common buffer pool and can then be used for faster f c credit updates. vision pak ? another plx exclusive, vision pak is a deb ug diagnostics suite of integrated hardware and software instruments that users can use to help bring their systems to market faster. vision pak features consist of performance monitoring, serdes eye capture, error injection, serdes loopback, and more. performance monitoring the PEX8733 s real time performance monitoring allows users to literally see ingress and egress performance on each port as traffic passes through the switch using plxs software development kit (sdk). the monitoring is completely passive and therefore has no affect on overall system performance. internal counters provide extensive granularity down to traffic & packet type and even allows for the filtering of traffic (i.e. count only memory w rites). serdes eye capture users can evaluate their systems signal integrity at the physical layer using the PEX8733 s serdes eye capture feature. using plxs sdk, users can view the receiver eye of any lane on the switch. users can then modify serdes se ttings and see the impact on the receiver eye. figure 5 shows a screenshot of the serdes eye capture feature in the sdk. figure 5 . serdes eye capture pcie packet generator the PEX8733 features a full - fledged pcie packet generator capable of creating pr ogrammable pcie traffic running at up to gen 3 speeds and capable of saturating a x16 link . using plxs software development kit ( www.plxtech.com/sdk ), designers can create custom traffic scripts for system bring - up and debug. fully integrated into the PEX8733 , the packet generator proves to be a very convenient on - chip debug tool. furthermore, the packet generator can be used to create pcie traffic to test and debug other devices i n the system.
PEX8733 , pci express gen 3 switch, 32 lanes, 18 ports ? plx technology, www.plxtech.com page 4 of 5 22aug11, v ersion 1.0 error injection & serdes loopback using the PEX8733 s error injection feature, users can inject malformed packets and/or fatal errors into their system and evaluate a systems ability to detec t and recover from such errors . the PEX8733 also supports internal tx, external tx, recovered clock, and recovered data loopback modes. applications suitable for h ost - centric as well as peer - to - peer traffic patterns, the PEX8733 can be configured for a wide variety of form factors and applications. host centric fan - out the PEX8733 , with its symmetric or asymmetric lane configuration capability, allows user - specific tuning to a variety of host - centric applications. figure 6 shows a server design where, in a quad or multi processor system, users can assign endpoints/slots to cpu cores to distribute the system load. the packets directed to different cpu cores will go to different (user assigned) PEX8733 upstream ports, allowing better queuing and load balancing capability for higher performance. conversely, the PEX8733 can also be used in single - host mode to simply fan - out to endpoints. figure 6 . host centric dual upstream multi - host systems in multi - host mode, the PEX8733 can be shared by up to four hosts in a system. by creating four virtual switches, the PEX8733 allows fou r hosts to fan - out to their respective endpoints. this reduces the number figure 7 . multi - host system of switches required for fan - out, saving precious board space and power consumption. in f igure 7, the PEX8733 is being shared by four different servers (hosts) with each server is running its own applications (i/os). the PEX8733 assigns the endpoints to the appropriate host and isolates them from the other hosts. host fai lover the PEX8733 can also be utilized in applications where host failover is required. in the below application (figure 8) , two hosts may be active simultaneously and controlling their own domains while exchange status information through doorbell regi sters or i 2 c interface. the devices can be programmed to trigger fail - over if the heartbeat information is not provided. in the event of a failure, the surviving device will reset the endpoints connected to the failing cpu and enumerate them in its own dom ain without impacting the operation of endpoints already in its domain. figure 8 . host fail - over n+1 fail - over in storage systems the PEX8733 s multi - host feature can also be used to develop storage array clusters where each host manages a set o f storage devices independent of others (figure 9) . users can designate one of the hosts as the failover - host for all the other hosts while actively managing its own endpoints. the failover - host will communicate with other hosts for status/heartbeat inform ation and execute a failover event if/when it gets triggered. figure 9. n+1 failover
PEX8733 , pci express gen 3 switch, 32 lanes, 18 ports ? plx technology, www.plxtech.com page 5 of 5 22aug11, v ersion 1.0 software model from a system model viewpoint, each pci express port is a virtual pci to pci bridge device and has its own set of pci express configuration registers. i t is through the upstream port that the bios or host can configure the other ports using standard pci enumeration. the virtual pci to pci bridges within the PEX8733 are compliant to the pci and pci express system models. the configuration space registers (csrs) in a virtual primary/secondary pci to pci bridge are accessible by type 0 configuration cycles through the virtual primary bus interface (matching bus number, device number, and function number). interrupt sources/events the PEX8733 switch support s the intx interrupt message type (compatible with pci 2.3 interrupt signals) or message signaled interrupts (msi) when enabled. interrupts/messages are generated by PEX8733 for hot plug events, doorbell interrupts, baseline error reporting, and advanced error reporting. figure 10 . PEX8733 rdk development tools plx offers hardware and software tools to enable rapid customer design activity. these tools consist of a hardware module ( PEX8733 rdk), hardware documentation (available at www.plxtech.com ), and a software development kit (also available at www.plxtech.com ). expresslane PEX8733 rdk the PEX8733 rdk (see figure 10) is a hardware module containing the PEX8733 whic h plugs right into your system. the PEX8733 rdk can be used to test and validate customer software, or used as an evaluation vehicle for PEX8733 features and benefits. the PEX8733 rdk provides everything that a user needs to get their hardware and softw are development started. software development kit (sdk) plxs software development kit is available for download at www.plxtech.com/sdk . the software development kit includes drivers, source code, and gui inter faces to aid in configuring and debugging the PEX8733 . both performance pak and vision pak are supported by plxs rdk and sdk, the industrys most advanced hardware - and software - development kits . product ordering information part number description pe x 8733 - b a80bc g 32 - lane, 18 - port pci express switch, pb - free (27 x 27 mm 2 ) pex 8733 - b a rdk PEX8733 rapid development kit plx technology, inc. all rights reserved. plx , the plx logo, expresslane, read pacing and dual cast are tradema rks of plx technology, i nc . all other product names that appear in this material are for identification purposes only and are acknowledged to be tra demarks or registered trademarks of their respective companies. information supplied by plx is believed to be accurate and reliable, but plx assumes no responsibility for any errors that may appear in this material. plx reserves the right, without notice, to make changes in product design or specification. visit www.plxtech.com for more information.
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