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| september 2013 rev 3 1/42 1 tda7590 digital signal processing ic for speech and audio applications features ? 24-bit, fixed point, 120 mips dsp core ? large on-board memory (128kw-24 bit) ? host access to internal ram through expansion port ? access to external ram (16mw) through expansion port ? integrated stereo, 18-bit sigma-delta a/d and 20-bit d/a converters ? programmable codec sample rate up to 48 khz ? on-board pll for core clock and converters ? external flash/sram memory bank management ?i 2 c and sci serial interfac e for external control ? 2 enhanced synchronous serial interface (essi) ?jtag interface ? host interface ? 144-pin tqfp, 0.50 mm pitch ? automotive temperature range (from -40 c to +85 c) applications ? real time digital speech and audio processing: ? speech recognition ? speech synthesis ? speech compression ? echo canceling ? noise canceling ? mp3 decoding description the tda7590 is a high performances, fully programmable 24-bit, 120 mips. digital signal processor (dsp), designed to support several speech and audio applications, as automatic speech recognition, speech synthesis, mp3 decoding, echo and noise cancellation. nevertheless, the embedded codecs bandwidth and the generic processing engine allow to proceed also full-band audio signals. the large amount of on-chip memory (128 kwords), together with the 16 mw ords external memory addressable and the 32 general purpose i/o pins permit to build a dsp-system avoiding the usage of an additional microcontroller. the presence of serial and parallel interfaces allows easy connection with external devices including codecs, dsps, microprocessors and personal computers. in particular, the debug/jtag interface permits the on-chip emulation of the firmware developed. further, the presence of the timers and watchdog block makes tda7590 suitable for pwm processing and allows the integration of a system watchdog. tqfp144 table 1. device summary order code package packing E-TDA7590 tqfp144 (20x20x1.0 exposed pad down) (1) 1. in ecopack? package (see section 8: package information on page 22 ). tray E-TDA7590tr tape and reel www.st.com
contents tda7590 2/42 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1.1 codec (adc/dac) test description . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 electrical characteristics for i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 24 bit dsp core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7 dsp peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 serial audio interface (sai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 serial communication interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4 host interface (hi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.5 essi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.6 eoc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.7 timers and watchdog block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.8 pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.9 codec cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 appendix 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 tda7590 contents 3/42 9.1 benchmarking program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 list of tables tda7590 4/42 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 4. key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 6. recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7. general interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 tda7590 list of figures 5/42 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. tqfp144 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 block diagram tda7590 6/42 1 block diagram figure 1. block diagram mozart core 120mips, 32 gpios ebug interface prom pram 16k x 24 xram 4/8/16/14k x 24 yram 68/64/56/48k x 24 flex ram 40k x 24 expansion port pll clock oscillator 2 channel codec essi essi/12c sci host i/f triple timer ddb ydb dab ya b xdb xab pa b edb eab sai/cct rclk sclk tda7590 pin description 7/42 2 pin description 2.1 pin connection figure 2. pin connection (top view) 144 142 140 138 sc11 136 134 132 130 128 126 124 122 120 118 116 114 112 110 143 141 139 137 sc12 125 121 117 115 109 135 133 131 129 127 123 119 113 111 45 46 47 49 hreq 51 iovss 53 has 55 ha8 57 had6 59 had4 61 corevss 63 had2 65 67 aa3 69 xti 71 pll_vdd hds wen aa1 bg 48 hack 50 iovdd 52 hcs 54 had7 56 ha9 68 aa2 72 pll_vss iovss 58 had5 60 corevdd 62 had3 64 had1 66 70 hrw oen aa0 srd1 std1 srd0 db6 db5 db4 db3 corevss 102 corevss 101 corevdd 100 99 98 97 ab5 96 ab1 95 ab3 94 ab2 93 iovss corevdd db1 db2 ab19 ab18 ab17 ab16 rxd txd 108 ab13 107 ab12 106 iovss 105 iovdd 104 ab11 103 ab10 92 iovdd 91 iovss 90 iovdd 89 nmi 2 sc02 3 sc01 4 5 iovdd 6 iovss 7 std0 8 sc10 9 sc00 10 sclk 36 de_n testen 31 32 33 34 35 11 sck1 12 sck0 13 reset 14 scanen 15 corevdd 16 corevss 17 tio0 18 vsssub 19 dacop 20 ref0 21 codec_vdd 22 23 24 25 dac1 26 codec_vss 27 dacom 28 29 30 1 ab15 37 38 39 41 43 40 42 44 82 81 80 79 78 77 76 75 74 73 88 87 86 85 84 83 ab14 xto had0 adc1 adcom adcop iovdd iovss tdo tms tck trstn irqd irqc irqb irqa db23 db22 db21 db15 iovss iovss corevss corevdd db19 db18 db17 db16 iovdd db20 db14 db13 db12 db11 db10 db9 iovss iovdd db8 db7 tdi extdaclk br bb iovdd ab4 ab6 ab7 db0 ab0 iovdd ab9 ab8 pin description tda7590 8/42 2.2 pin function table 2. pin function n name type description 1 srd1/ti02 i/o serial receive data. serial in put data for receiver. timer 2 input/output. 2 std1 i/o serial transmit data. serial output data from transmitter. 3sc02i/o serial control 2.transmitter frame sync only in asynchronous mode, transmitter and receiver frame sync in synchronous mode. 4sc01i/o serial control 1. receive frame sync in asynchronous mode, output from transmitter 2 or serial flag 1 in synchronous mode. 5 de_n i/o test data output (input/output). debug request input and acknowledge output. 6nmi_ni non-maskable interrupt/ pinit. used to enable the pll during reset and as a non-maskable interrupt at all other times. 7 srd0 i/o serial receive data. serial input data for receiver. 8 iovdd i io power supply. 9 iovss i io ground. 10 std0 i/o serial transmit data. serial output data from transmitter. 11 sc10/scl i/o essi1 serial control 0. receive clo ck in asynchronous mode, output from transmitter or serial flag in synchronous mode. i 2 c scl serial clock line. 12 sc00 i/o serial control 0. receive clock in asynchronous mode, output from transmitter 1 or serial flag 0 in synchronous mode. 13 rxd i/o sci receive data. receives byte-oriented serial data. 14 txd i/o sci read enable. transmits serial data from sci transmit shift register. 15 sclk i/o sci serial clock. input or output clo ck from which data is transferred in synchronous mode and from which the tr ansmit and/or receive baud rate is derived in asynchronous mode. 16 sck1/ti01 i/o serial clock. serial bit clock for transmitter only in asynchronous mode, serial bit clock for both receiver and tr ansmitter in synchronous mode. timer 1 input/output. 17 sck0 i/o serial clock. serial bit clock for transmitter only in asynchronous mode, serial bit clock for both receiver and tr ansmitter in synchronous mode. 18 resetn i system reset. a low level appli ed to reset_n input initializes the ic. 19 scanen i scan enable. when active with testen also active, controls the shifting of the internal scan chains. 20 testen i test enable. when active, puts the chip into test mode and muxes the xti clock to all flip-flops. when scanen is also active, the scan chain shifting is enabled. 21 corevss i core ground. 22 corevdd i core power supply. 23 tio0 i/o timer 0 input/output. 24 vsssub i analog subs trate isolation. tda7590 pin description 9/42 25 dac1 o dac1 left single analog output. 26 dac0m o dac0 negative right differential analog output. 27 dac0p o dac0 positive right differential analog output. 28 codec_vss i voltage ground. 29 ref0 i codec power supply. 30 codec_vdd i codec reference. 31 adc1 i adc1 left single analog input. 32 adc0m i dac0 negative right differential analog inputs. 33 adc0p i dac0 positive right differential analog inputs. 36 extdaclk i external dac clock. optional external clock source from which lrclk and sclk can be generated. 37 xti i crystal oscillator input. external clock input or crystal connection. 38 xto o crystal oscillator output. crystal oscillator output drive. 39 pll_vdd i pll power supply. 40 pll_vss i pll ground input. 41 hds i/o host data strobe. polarity programmable host data strobe input for single strobe mode. polarity programmable host write strobe input for double strobe mode. 42 hrw i/o host read/write. host read/writ e for single strobe bus mode. polarity programmable host read data strobe for double strobe mode. 43 hack i/o host acknowledge. polarity programmable host interrupt acknowledge for single host request mode. polarity programmable host receive request interrupt for double host request mode. 44 hreq i/o host request. polarity programmable host request interrupt for single host request mode. polarity programmable host transfer request interrupt for double host request mode. 45 iovdd i io power supply. 46 iovss i io ground. 47 hcs i/o host chip select. polarity programmabl e host chip select for non-multiplexed mode. host address line 10 for multiplexed mode. 48 ha9 i/o host address 9. address line 9 in mu ltiplexed mode otherwise address line 2 in non-multiplexed mode. 49 ha8 i/o host address 8. address line 8 in mu ltiplexed mode otherwise address line 1 in non-multiplexed mode. 50 has i/o host address strobe. address strobe for multiplexed bus or address 0 for non multiplexed. 51 had[7] i/o host 8-bit data line 7. host data bus a nd/or address lines when in multiplexed mode. table 2. pin function (continued) n name type description pin description tda7590 10/42 52 had[6] i/o host 8-bit data line 6. host data bus a nd/or address lines when in multiplexed mode. 53 had[5] i/o host 8-bit data line 5. host data bus a nd/or address lines when in multiplexed mode. 54 had[4] i/o host 8-bit data line 4. host data bus a nd/or address lines when in multiplexed mode. 55 corevdd i core power supply. 56 corevss i core ground. 57 had[3] i/o host 8-bit data line 3. host data bus a nd/or address lines when in multiplexed mode. 58 had[2] i/o host 8-bit data line 2. host data bus a nd/or address lines when in multiplexed mode. 59 had[1] i/o host 8-bit data line 1. host data bus a nd/or address lines when in multiplexed mode. 60 had[0] i/o host 8-bit data line 0. host data bus a nd/or address lines when in multiplexed mode. 61 aa[3] o address attributes line 3.port a address attribut es/chip select pins with programmable polarity. 62 aa[2] o address attributes line 2.port a address attribut es/chip select pins with programmable polarity. 63 br_n o bus request. asserted when port a requires bus mastership to perform off- chip accesses. 64 bb_n i/o bus busy. asserted by port a when bus_busy_in_n is negated and bg_n is asserted. 65 iovdd i io power supply. 66 iovss i io ground. 67 wen_n o write enable. 68 oen_n o output enable. 69 aa[1] o address attributes line 1.port a address attribut es/chip select pins with programmable polarity. 70 aa[0] o address attributes line 0.port a address attribut es/chip select pins with programmable polarity. 71 bg_n i bus grant. when asserted, port a bec omes the bus master elect. bus mastership is attained when bus busy is negated by the current bus master. 72 ab[0] o address bus line 0. port a external address bus. 73 ab[1] o address bus line 1. port a external address bus. 74 iovdd i io power supply. 75 iovss i io ground. 76 ab[2] o address bus line 2. port a external address bus. table 2. pin function (continued) n name type description tda7590 pin description 11/42 77 ab[3] o address bus line 3. port a external address bus. 78 ab[4] o address bus line 4. port a external address bus. 79 ab[5] o address bus line 5. port a external address bus. 80 iovdd i io power supply. 81 iovss i io ground. 82 ab[6] o address bus line 6. port a external address bus. 83 ab[7] o address bus line 7. port a external address bus. 84 ab[8] o address bus line 8. port a external address bus. 85 ab[9] o address bus line 9. port a external address bus. 86 corevdd i core power supply. 87 corevss i core ground. 88 ab[10] o address bus line 10. port a external address bus. 89 ab[11] o address bus line 11. port a external address bus. 90 iovdd i io power supply. 91 iovss i io ground. 92 ab[12] o address bus line 12. port a external address bus. 93 ab[13] o address bus line 13. port a external address bus. 94 ab[14] o address bus line 14. port a external address bus. 95 ab[15] o address bus line 15. port a external address bus. 96 ab[16] o address bus line 16. port a external address bus. 97 ab[17] o address bus line 17. port a external address bus. 98 ab[18] o address bus line 18. port a external address bus. 99 ab[19] o address bus line 19. port a external address bus. 100 db[0] i/o address bus 0. port a external data bus. 101 db[1] i/o address bus 1. port a external data bus. 102 db[2] i/o address bus 2. port a external data bus. 103 corevdd i core power supply. 104 corevss i core ground. 105 db[3] i/o data bus line 3. port a external data bus. 106 db[4] i/o data bus line 4. port a external data bus. 107 db[5] i/o data bus line 5. port a external data bus. 108 db[6] i/o data bus line 6. port a external data bus. 109 db[7] i/o data bus line 7. port a external data bus. 110 db[8] i/o data bus line 8. port a external data bus. 111 iovdd i io power supply. table 2. pin function (continued) n name type description pin description tda7590 12/42 112 iovss i io ground. 113 db[9] i/o data bus line 9. port a external data bus. 114 db[10] i/o data bus line 10. port a external data bus. 115 db[11] i/o data bus line 11. port a external data bus. 116 db[12] i/o data bus line 12. port a external data bus. 117 db[13] i/o data bus line 13. port a external data bus. 118 db[14] i/o data bus line 14. port a external data bus. 119 iovdd i io power supply. 120 iovss i io ground. 121 db[15] i/o data bus line 15. port a external data bus. 122 db[16] i/o data bus line 16. port a external data bus. 123 db[17] i/o data bus line 17. port a external data bus. 124 db[18] i/o data bus line 18. port a external data bus. 125 db[19] i/o data bus line 19. port a external data bus. 126 corevdd i core power supply. 127 corevss i core ground. 128 db[20] i/o data bus line 20. port a external data bus. 129 iovdd i io power supply. 130 iovss i io ground. 131 db[21] i/o data bus line 21. port a external data bus. 132 db[22] i/o data bus line 22. port a external data bus. 133 db[23] i/o data bus line 23. port a external data bus. 134 irqa i interrupt request line/ mode control. used as mode control during reset and as interrupt request line at all other times. 135 irqb i interrupt request line/ mode control. used as mode control during reset and as interrupt request line at all other times. 136 irqc i interrupt request line/ mode control. used as mode control during reset and as interrupt request line at all other times. 137 irqd i interrupt request line/ mode control. used as mode control during reset and as interrupt request line at all other times. 138 trstn i test reset. jtag output pin for serial data out from debug interface. 139 tdi i test data input. jtag input pin for serial data input for debug interface. 140 tck i test clock. jtag input pin for clocking debug interface. 141 tms i test mode select. jtag input pin fo r control of tap controller of debug interface. 142 tdo o test data output. jtag output pi n for serial data out from debug interface. table 2. pin function (continued) n name type description tda7590 pin description 13/42 2.3 thermal data 143 sc12 i/o serial control 2.transmitter frame sync only in asynchronous mode, transmitter and receiver frame sync in synchronous mode. 144 sc11/sda i/o serial control 1. receive frame sync in asynchronous mode, output from transmitter 2 or seri al flag 1 in synchronous mode. i 2 c sda. serial data line. table 2. pin function (continued) n name type description table 3. thermal data symbol parameter value unit r th-j-pins thermal resistance junction to pins 32 c/w key parameters tda7590 14/42 3 key parameters 3.1 power consumption power consumption depends on applicat ion running and dsp clock frequency. supply current values are measured and guaranteed at testing level by adopting the benchmarking program reported in appendix 1. table 4. key parameters symbol parameter min. typ. max. unit general fosc crystal frequency 16 mhz core_vdd operating voltage 1.62 1.8 1.98 v codec_vdd operating voltage 3.0 3.3 3.6 v iovdd operating voltage 3.0 3.3 3.6 v pll_vdd operating voltage 3.0 3.3 3.6 v idd_1.8v supply current 150 ma idd_3.3v supply current 50 ma tamb operating temperature -40 85 c dsp core fdsp dsp clock frequency 120 mhz adc single ended vpp maximum input range at adc1 1.4 v thd/s total harmonics distortion to signal -71 db (thd+n)/s (thd + noise) to signal -70 db dr dynamic range 75 db icl interchannel isolation -100 db adc differential vpp maximum input range at adc0m-adc0p 2.8 v thd/s total harmonics distortion to signal -65 db (thd+n)/s (thd + noise) to signal -65 db dr dynamic range 84 db icl interchannel isolation -100 db dac single ended vpp maximum input range at adc1 1.4 v thd/s total harmonics distortion to signal -64 db (thd+n) (thd + noise) to signal -60 db tda7590 key parameters 15/42 3.1.1 codec (adc/dac) test description reported typical values (table 3. - adc and dac sections) have been measured at lab level during product evaluation phase. genera l definitions and procedures are separately defined in following dedicated paragraphs. total harmonic distortion with noise to signal (thd+n)/s thd+n is defined as the ratio of the total power of the second power and higher harmonic with noise components to the power of th e fundamental for that signal. for thd+n measurement, choose the dsp analyzer in digital analyzer with thd ratio as measurement option. measure the thd+n value at -3 db amp litude of the input signal. first measure the thd+n value at 1vrms which is 0 db reference and then measure the value at -3 db reference. dynamic range (dr) dr is defined as the level of thd+n measured when the input sine wave amplitude is so small that no harmonics apart from the fundam ental tone are present in the output signal. this way thd+n becomes practically the ratio between the whole signal and noise floor, being a different way to express snr. as a convention, at which no harmonics should be present in the output signal, it is fixed at -40db of the full scale amplitude. crosstalk or interchannel isolation a disturbance, caused by electromagnetic interf erence, along a circuit or a cable pair. an electric signal disrupts another signal in an adjacent circuit and can cause it to become confused and cross over each other. crosstalk is measured by applying a signal -3db amplitude of input signal at one channel (a ) and no signal at an other channel (b), measuring the effect on this channel (b) because of the channel (a). total harmonic distortion to signal (thd)/s thd is defined as the ratio of the sum of onl y those components of the output signal which are harmonic of system input, after having removed the f undamental tone co rresponding to the pure sine wave as input and the input signal.this measurement is done by using the harmonic analyzer which can isolate up to 15th harmonic components on the acquired signal and report the sum of all of them, centering the fundamental tone on the frequency provided by the input signal generator. these measurements are performed at -3db reference amplitude of input signal. dr dynamic range 89 db icl interchannel isolation -100 db dac differential vpp maximum input range at adc1 2.8 v thd/s total harmonics distortion to signal -58 db (thd+n)/s (thd + noise) to signal -57 db dr dynamic range 90 db icl interchannel isolation -85 db table 4. key parameters (continued) symbol parameter min. typ. max. unit electrical specification tda7590 16/42 4 electrical specification 4.1 absolute maximum ratings 4.2 electrical charact eristics for i/o pins table 5. absolute maximum ratings symbol parameter value unit pll_vdd 3.3v pll power supply voltage -0.5 to 4 v codec_vdd 3.3v codec analog power supply -0.5 to 4 v iovdd 3.3v io power supply -0.5 to 4 v core_vdd 1.8v core power supply -0.5 to 2.2 v io_max input or output voltage -0.5 to (iovdd +0.5) v table 6. recommended dc operating conditions symbol parameter value unit iovdd io power supply voltage 3 to 3.6 (1) v t j operating junction temperature -40 to 105 c 1. all the specification are valid only within these recommended operating conditions. table 7. general interface electrical characteristics symbol parameter test condition min. typ. max. unit iil low level input current without pull-up device 1 ? a iih high level input current without pull-down device 1 ? a ioz tri-state output leakage without pull up/down device 1 ? a iozft five volt tolerant tri-state output leakage without pull up/down device 1 ? a i latch-up i/o latch-up current v < 0v, v < vdd 200 ma vesd electrostatic protection (hbm) leakage < 1ma 2000 v vil low level input voltage (1) )0.8v vih high level input voltage (1) 2v vhyst schmitt trigger hysteresis (1) 0.4 v vol low level output voltage (1) (2) (3) iol = xma 0.15 v voh high level output voltage (1) (2) (3) ioh = -xma iovdd - 0.15 v 1. ttl specifications only apply to the supply voltage range vdd = 3.15v to 3.6v. 2. takes into account 200mv voltage drop in both supply lines. 3. x is the source/sink current under worst case conditions and is reflected in the name of the i/o cell according to the drive capability. tda7590 24 bit dsp core 17/42 5 24 bit dsp core the dsp core is a general purpose 24-bit dsp. the main feature of the dsp core are listed below: ? 120 mhz operating frequency (120 mips) ? fully pipelined 24 x 24 bit parallel multiplier-accumulator ? saturation/limiting logic ? 56-bit parallel barrel shifter ? linear, reverse carry and modulo addressing modes ? 24-bit address buses for program, x and y data spaces and dma ? memory-expandible hardware stack ? nested zero-overhead do loops ? fast interrupts ? powerful jtag emulation port ? software wait and stop low power standby modes ? program address tracing support ? two 24-bit data moves in pa rallel with arithmetic operations ? external interrupts including non-maskable interrupt ? interrupts may be independently masked and prioritized ? bit-manipulation instructions can access any register or memory location ? on board support for dma controller memories tda7590 18/42 6 memories 128 k x 24-bit ram divided into 4 areas, program ram(pram), x data ram(xram), y data ram(yram) and flexible a llocation ram(flex) as follows: ? 16 kb pram ? 40 kb flex ram. flex ram is accessed through the expansion port by the dsp core. ? external access to the flex ram is also supported. ? 72 kb ram is allocated as xram and yram. four configurations are supported: ? 4 kb xram and 68 kb yram ? 8 kb xram and 64 kb yram ? 16 kb xram and 56 kb yram ? 24 kb xram and 48 kb yram tda7590 dsp peripherals 19/42 7 dsp peripherals 7.1 serial audio interface (sai) the sai is used to communicate between the codec and the dsps. in addition, digital audio can be directly input for processing. there is only one sai found on the chip that can be accessed by either the d sp or the dma controller. the main features of this block are listed below: ? slave operating modes, all clock lines can be inputs or outputs ? transmit and receive interrupt logic triggers on left/right data pairs ? receive and transmit data registers have two locations to hold left and right data 7.2 serial communicati on interface (sci) the serial communication interface provides a full duplex port for serial communication to other dsps, microprocessors, and peripherals like modems. the interface supports the following features: ? no additional logic for connection to other ttl level peripherals ? asynchronous bit rates and protocols "high speed? synchronous data transmission. ? asynchronous protocol includes multidro p mode for master/slave operation with wake-up on idle line and wake -up on address bit capabilit y, permitting the sci to share a single line with multiple peripherals ? transmit and receive logic can operate asynchronously from each other. ? a programmable baud-rate generator wh ich provide the transmit and receive clocks or functions as a general purpose timer. 7.3 i 2 c interface the inter integrated-circuit bus is a simple bi-d irectional two-wire bus us ed for efficient inter ic control. all i 2 c bus compatible devices incorporat e an on-chip interface which allows them to communicate directly with each other via the i 2 c bus. every component connected to the i 2 c bus has it s own unique address whether it is a cpu, memory or some other complex function chip. each of these chips can act as a receiver and/or transmitter depending on it s functionality. 7.4 host interface (hi) the host interface is a system-on-chip module t hat permits connection to the data bus of a host processor. the hi is capable of drivi ng 16 programmable external pins which can be configured as an 8 bit parallel port for direct connection to a host processor. dsp peripherals tda7590 20/42 the key features of the host interface are: ? 8 bit parallel port "full-duplex" dedicated host register bank ? dedicated mozart? core dsp register core bank. ? register banks map directly into mozart x memory space ? 3 transfer modes: ? host command ? host to mozart core dsp ? mozart core dsp to host ? access protocols: ? software polled ? interrupt ? dma access by the mo zart core dsp core ? 2+ wait states clock cycles per transfer ? supported instructions: ? data transfer between mozart core and external host using mozart move instruction ? simple i/o service routine with bit addressing instructions ? io service using fast inte rrupts with movep instructions. 7.5 essi the essi peripheral enables serial-port co mmunication between the dsp core and external devices including codecs, dsp, microprocessors. the essi is capable of driving 12 programmable external pins which can be configured as gpio ports c and d or essi pins. the key features of the essi are: ? independent receiver and transmitter ? synchronous or asynchronous channel modes synchronous. receiver and transmitter use same clock/sync asynchronous. rece iver and transmitter may use separate clock/sync up to one transmitter enabled in asynchronous channel mode. ? up to three transmitters enabled in synchronous channel mode. ? normal mode. one word per period. ? network mode. up to 32 words per period. 7.6 eoc the salieri extended on-chip memory interfac e provides access to 40 kb of on-chip memory. the mozart core will treat this memory as if it were external. access by off-chip expansion bus masters is permitted. all ac cesses to the extended on-chip ram are controlled by the extended on-chip memory contro l register. this register determines which combinations of the address attribute pins shoul d be interpreted as accesses to the 40 kb of ram. tda7590 dsp peripherals 21/42 7.7 timers and watchdog block the timers and watchdog block consists of a common 21-bit prescaler and three independent and identical general-purpose 24-b it timer/event counters, each with its own register set. each timer has the fo llowing capabilities: ? uses internal or external clocking. ? interrupts the mozart after a specified number of events (clocks). ? signals an external device after counting internal events. ? triggers dma transfers after a specified number of events (clocks) occurs. ? connects to the external world through de signated pins tio[0-2] for timers 0-2. when tio is configured as an ? input: timer functions as an external even t counter. timer measures external pulse width/signal period. ? output: timer functions as a: ?timer ? watchdog timer ? pulse-width modulator. 7.8 pll the pll generates the following clocks: ? dclk: dsp core clock ? daclk: adc and dac clock ? lrclk: left/right clock for the sai and the codec ? sclk: shift serial clock for the sai and the codec 7.9 codec cell the main features of the codec cell are listed below: ? 20 bits stereo dac, and 18 bits adc ?i 2 s format ? oversampling ratio: 512 ? sampling rates of 8 khz to 48 khz the analog interface is in the form of differen tial signals for each channel. the interface on the digital side has the form of an sai interfac e and can interface directly to an sai channel and then to the dsp core. dclk can be supplied either by the internal pl l or by external, to allow synchronization with external anal digital sources. package information tda7590 22/42 8 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 3. tqfp144 mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.20 0.047 a1 0.05 0.15 0.002 0.006 a2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.003 0.008 d 21.80 22.00 22.20 0.858 0.866 0.874 d1 19.80 20.00 20.20 0.779 0.787 0.795 d2 2.00 0.079 d3 17.50 0.689 e 21.80 22.00 22.20 0.858 0.866 0.874 e1 19.80 20.00 20.20 0.779 0.787 0.795 e2 2.00 0.079 e3 17.50 0.689 e0.50 0.020 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.0393 k 0? (min.), 3.5? (typ.), 7?(max.) ccc 0.08 0.03 tqfp144 (20x20x1.0mm exposed pad down) 7386636 b note 1: exact shape of each corner is optional. tda7590 appendix 1 23/42 9 appendix 1 9.1 benchmarking program ;********************************* file header ********************************* ; ;title: salieri codec/sai functionality test ; ;file name: full_func.asm ; ;author: -- ; ;language: dsp2420 core assembler ; ;project: salieri ; ;description: codec + timer + hi gpios + essi + sci ; ; ; ; ; ; ; ;; ;******************************************************************************* ;*********************************** equates *********************************** ;******************************************************************************* npts equ 20 ntaps equ 4 ;------------------------------------------------------------------------ ; equates for i/o port programming ;------------------------------------------------------------------------ ; register addresses m_hdr equ $ffffc9 ; ps- host port gpio data register m_hddr equ $ffffc8 ; ps- host port gpio direction register m_pcrc equ $ffffbf ; port c control register m_prrc equ $ffffbe ; port c direction register m_pdrc equ $ffffbd ; port c gpio data register m_pcrd equ $ffffaf ; port d control register m_prrd equ $ffffae ; port d direction data register m_pdrd equ $ffffad ; port d gpio data register m_pcre equ $ffff9f ; port e control register m_prre equ $ffff9e ; port e direction register m_pdre equ $ffff9d ; port e data register m_ogdb equ $fffffc ; once gdb register ;------------------------------------------------------------------------ ; equates for exception processing ;------------------------------------------------------------------------ ; register addresses ipr_c equ $ffffff ; interrupt priority register core appendix 1 tda7590 24/42 ipr_p equ $fffffe ; interrupt priority register peripheral ; sai interrupt vectors sai_rof equ $070 ; receiver overflow sai_tuf equ $072 ; transmitter underflow sai_rdr equ $074 ; receiver data ready sai_tde equ $076 ; transmitter data empty ; timer interrupt vector timer0_tcf equ $24 ; timer0 compare timer0_tof equ $26 ; timer0 overflow timer1_tcf equ $28 ; timer1 compare timer1_tof equ $2a ; timer1 overflow timer2_tcf equ $2c ; timer2 compare timer2_tof equ $2e ; timer2 overflow ; sci interrupt vectors sci_rec equ $000050 ; sci receive data sci_rec_e equ $000052 ; sci receive data with exception status sci_trans equ $000054 ; sci transmit data sci_idle equ $000056 ; sci idle line sci_timer equ $000058 ; sci timer ;;; bit definition for sci_ssr framing equ 6 reset equ $000000 ; reset address location ;------------------------------------------------------------------------ ; equates for sai (y memory) ;------------------------------------------------------------------------ sai_rcs equ $ffffff ; sai receive control/status register sai_rx2 equ $fffffe ; sai channel 2 receiver data sai_rx1 equ $fffffd ; sai channel 1 receiver data sai_rx0 equ $fffffc ; sai channel 0 receiver data sai_tcs equ $fffffb ; sai transmit control/status register sai_tx2 equ $fffffa ; sai channel 2 transmitter data sai_tx1 equ $fffff9 ; sai channel 1 transmitter data sai_tx0 equ $fffff8 ; sai channel 0 transmitter data ;;; bit definitions for m_rcs rofcl equ 16 ; receiver data overflow clear rdr equ 15 ; receiver data ready rofl equ 14 ; receiver data overflow ;reserved rxie equ 12 ; receiver interrupt enable rdwj equ 11 ; receiver data word justification rrel equ 10 ; receiver relative timing rckp equ 9 ; receiver clock polarity rlrs equ 8 ; receiver left right selection rdir equ 7 ; receiver data shift direction rwl1 equ 6 ; receiver word length control 1 rwl0 equ 5 ; receiver word length control 0 ;reserved rmme equ 3 ; receiver master mode enable r2en equ 2 ; receiver 2 enable r1en equ 1 ; receiver 1 enable r0en equ 0 ; receiver 0 enable tda7590 appendix 1 25/42 ;;; bit definitions for m_tcs tufcl equ 16 ; transmitter data overflow clear tde equ 15 ; transmitter data ready tufl equ 14 ; transmitter data overflow ;reserved txie equ 12 ; transmitter interrupt enable tdwe equ 11 ; transmitter data word justification trel equ 10 ; transmitter relative timing tckp equ 9 ; transmitter clock polarity tlrs equ 8 ; transmitter left right selection tdir equ 7 ; transmitter data shift direction twl1 equ 6 ; transmitter word length control 1 twl0 equ 5 ; transmitter word length control 0 ;reserved tmme equ 3 ; transmitter master mode enable t2en equ 2 ; transmitter 2 enable t1en equ 1 ; transmitter 1 enable t0en equ 0 ; transmitter 0 enable ;------------------------------------------------------------------------ ; equates for codec ;------------------------------------------------------------------------ codec_csr equ $ffffcb ; codec control register address ;;; bit definitions for codec gadcl_0 equ 0 ; adc left gain bit 0 gadcl_1 equ 1 ; adc left gain bit 1 gadcl_2 equ 2 ; adc left gain bit 2 gadcr_0 equ 3 ; adc right gain bit 0 gadcr_1 equ 4 ; adc right gain bit 1 gadcr_2 equ 5 ; adc right gain bit 2 gdacl_0 equ 6 ; dac left gain bit 0 gdacl_1 equ 7 ; dac left gain bit 1 gdacl_2 equ 8 ; dac left gain bit 2 gdacr_0 equ 9 ; dac right gain bit 0 gdacr_1 equ 10 ; dac right gain bit 1 gdacr_2 equ 11 ; dac right gain bit 2 mutedac equ 12 ; mute dac - active hi, reset val = 1 pdndac equ 13 ; power down dac - active hi, reset val = 0 pdnadc equ 14 ; power down adc - active hi, reset val = 0 n_rst equ 15 ; asynchronoue reset - active lo, reset val = 1 ;------------------------------------------------------------------------ ; equates for pll ;------------------------------------------------------------------------ pll_csr equ $ffffd7 ; pll control/status register pll_fcr equ $ffffd6 ; pll fractional register pll_clkctl equ $ffffd5 ; pll clock control register ;;; bit definitions for pll_csr idf0 equ 0 ; input divide factor 0 idf1 equ 1 ; input divide factor 1 idf2 equ 2 ; input divide factor 2 idf3 equ 3 ; input divide factor 3 idf4 equ 4 ; input divide factor 4 ; reserved appendix 1 tda7590 26/42 lock equ 6 ; pll lock indication bit outlock equ 7 ; pll lost lock bit mf0 equ 8 ; multiplication bit 0 mf1 equ 9 ; multiplication bit 1 mf2 equ 10 ; multiplication bit 2 mf3 equ 11 ; multiplication bit 3 mf4 equ 12 ; multiplication bit 4 mf5 equ 13 ; multiplication bit 5 mf6 equ 14 ; multiplication bit 6 pllie equ 15 ; pll interrupt enable pwrdn equ 16 ; pll power down diten equ 17 ; dither enable fracen equ 18 ; pll fractional-n function enable pen equ 19 ; pll enable ;;; bit definitions for pll_clkcntl dspdf0 equ 0 ; dsp clock divider factor 0 dspdf1 equ 1 ; dsp clock divider factor 1 dspdf2 equ 2 ; dsp clock divider factor 2 dspdf3 equ 3 ; dsp clock divider factor 3 ; reserved dcksrc equ 6 ; dsp clock source 0->xti/(dspdf3:0 + 1) ; 1->vco/(dspdf3:0 + 1) daclken equ 7 ; enable bit for oversampling clock mfsdf0 equ 8 ; oversampling multiple bit 0 mfsdf1 equ 9 ; oversampling multiple bit 1 mfsdf2 equ 10 ; oversampling multiple bit 2 mfsdf3 equ 11 ; oversampling multiple bit 3 mfsdf4 equ 12 ; oversampling multiple bit 4 mfsdf5 equ 13 ; oversampling multiple bit 5 mfsdf6 equ 14 ; oversampling multiple bit 6 sel0 equ 15 ; sampling multiple select bit 0 sel1 equ 16 ; sampling multiple select bit 1 sel2 equ 17 ; sampling multiple select bit 2 dsp_xti equ 18 ; dsp_xti =0 -> use vco/dspdf for dclk ; dsp_xti =1 -> use xti for dclk dac_sel equ 19 ; selects between vco and ext_dac_clk xtld equ 20 ; disables the external crystal when set ;------------------------------------------------------------------------ ; equates for i/o port programming ;------------------------------------------------------------------------ ; register addresses hdr equ $ffffc9 ; ps- host port gpio data register hddr equ $ffffc8 ; ps- host port gpio direction register pcrc equ $ffffbf ; port c control register prrc equ $ffffbe ; port c direction register pdrc equ $ffffbd ; port c gpio data register pcrd equ $ffffaf ; port d control register prrd equ $ffffae ; port d direction data register pdrd equ $ffffad ; port d gpio data register pcre equ $ffff9f ; port e control register prre equ $ffff9e ; port e direction register pdre equ $ffff9d ; port e data register ogdb equ $fffffc ; once gdb register tda7590 appendix 1 27/42 ;------------------------------------------------------------------------ ; equates for gpios ;------------------------------------------------------------------------ ;;; register addresses gpioctrl equ $ffffc4 ; host port control register gpiodir equ $ffffc8 ; gpiodir register.(hi - hddr) gpiodat equ $ffffc9 ; gpiodat register.(hi - hdr) ;;; bit definitions for gpio direction register gpio0_dir equ $0 gpio1_dir equ $1 gpio2_dir equ $2 gpio3_dir equ $3 gpio4_dir equ $4 gpio5_dir equ $5 gpio6_dir equ $6 gpio7_dir equ $7 gpio8_dir equ $8 ;;; bit definitions for gpio data register gpio0_dat equ $0 gpio1_dat equ $1 gpio2_dat equ $2 gpio3_dat equ $3 gpio4_dat equ $4 gpio5_dat equ $5 gpio6_dat equ $6 gpio7_dat equ $7 gpio8_dat equ $8 ;------------------------------------------------------------------------ ; equates for timer ;------------------------------------------------------------------------ m_tcsr0 equ $ffff8f ;timer 0 control/status register (tcsr0) m_tlr0 equ $ffff8e ;timer 0 load register (tlr0) m_tcpr0 equ $ffff8d ;timer 0 compare register (tcpr0) m_tcr0 equ $ffff8c ;timer 0 count register (tcr0) m_tcsr1 equ $ffff8b ;timer 1 control/status register (tcsr1) m_tlr1 equ $ffff8a ;timer 1 load register (tlr1) m_tcpr1 equ $ffff89 ;timer 1 compare register (tcpr1) m_tcr1 equ $ffff88 ;timer 1 count register (tcr1) m_tcsr2 equ $ffff87 ;timer 2 control/status register (tcsr2) m_tlr2 equ $ffff86 ;timer 2 load register (tlr2) m_tcpr2 equ $ffff85 ;timer 2 compare register (tcpr2) m_tcr2 equ $ffff84 ;timer 2 count register (tcr2) m_tplr equ $ffff83 ;timer prescaler load register (tplr) m_tpcr equ $ffff82 ;timer prescaler count register (tpcr) ;------------------------------------------------------------------------ ; ; equates for enhanced synchronous serial interface (essi) ; ;------------------------------------------------------------------------ ;essi 0 interrupt equates essi0_rdf equ $30 essi0_roe equ $32 essi0_rls equ $34 appendix 1 tda7590 28/42 essi0_tde equ $36 essi0_tue equ $38 essi0_tls equ $3a ;essi 1 interrupt equates essi1_rdf equ $40 essi1_roe equ $42 essi1_rls equ $44 essi1_tde equ $46 essi1_tue equ $48 essi1_tls equ $4a ;register addresses of essi0 m_tx00 equ $ffffbc ; ssi0 transmit data register 0 m_tx01 equ $ffffbb ; ssi0 transmit data register 1 m_tx02 equ $ffffba ; ssi0 transmit data register 2 m_tsr0 equ $ffffb9 ; ssi0 time slot register m_rx0 equ $ffffb8 ; ssi0 receive data register m_ssisr0 equ $ffffb7 ; ssi0 status register m_crb0 equ $ffffb6 ; ssi0 control register b m_cra0 equ $ffffb5 ; ssi0 control register a m_tsma0 equ $ffffb4 ; ssi0 transmit slot mask register a m_tsmb0 equ $ffffb3 ; ssi0 transmit slot mask register b m_rsma0 equ $ffffb2 ; ssi0 receive slot mask register a m_rsmb0 equ $ffffb1 ; ssi0 receive slot mask register b ;register addresses of essi1 m_tx10 equ $ffffac ; ssi1 transmit data register 0 m_tx11 equ $ffffab ; ssi1 transmit data register 1 m_tx12 equ $ffffaa ; ssi1 transmit data register 2 m_tsr1 equ $ffffa9 ; ssi1 time slot register m_rx1 equ $ffffa8 ; ssi1 receive data register m_ssisr1 equ $ffffa7 ; ssi1 status register m_crb1 equ $ffffa6 ; ssi1 control register b m_cra1 equ $ffffa5 ; ssi1 control register a m_tsma1 equ $ffffa4 ; ssi1 transmit slot mask register a m_tsmb1 equ $ffffa3 ; ssi1 transmit slot mask register b m_rsma1 equ $ffffa2 ; ssi1 receive slot mask register a m_rsmb1 equ $ffffa1 ; ssi1 receive slot mask register b ;------------------------------------------------------------------------ ; equates for sci ;------------------------------------------------------------------------ pcre_adr equ $ffff9f ; serial port control register prre_adr equ $ffff9e ; serial port direction register pdre_adr equ $ffff9d ; serial port direction register scr_adr equ $ffff9c ; sci control register sccr_adr equ $ffff9b ; sci clock control register srxh_adr equ $ffff9a ; serial recieve register high srxm_adr equ $ffff99 ; serial recieve register mid srxl_adr equ $ffff98 ; serial recieve register low stxh_adr equ $ffff97 ; serial transmit register high stxm_adr equ $ffff96 ; serial transmit register mid stxl_adr equ $ffff95 ; serial transmit register low stxa_adr equ $ffff94 ; serial transmit adress register ssr_adr equ $ffff93 ; serial status register tda7590 appendix 1 29/42 ;------------------------------------------------------------------------ ; equates for expansion port ;------------------------------------------------------------------------ exp_bcr equ $fffffb ; bus control register address exp_aar0 equ $fffff9 ; address attribte register (aar0) address exp_aar1 equ $fffff8 ; address attribte register (aar1) address exp_aar2 equ $fffff7 ; address attribte register (aar2) address exp_aar3 equ $fffff6 ; address attribte register (aar3) address ext_ram_startequ $c00000 ;------------------------------------------------------------------------ ; equates for extended memory ;------------------------------------------------------------------------ eoc_adr equ $ffffca ;******************************************************************************* ;***************************** initialisation values ************************** ;******************************************************************************* ;------------------------------------------------------------------------------- ; codec intitialisation values ;------------------------------------------------------------------------------- ; --- init_ccr ----------------------------------------------------------------- ; settings fro the codec control register ; 321098765432109876543210 init_codec_csr equ %000000001110011011011011 ; $00e6db dacgain = 0db - adcgain = +0dbdb ; 011 --- gadcl[0:2] ; 011 ------ gadcr[0:2] ; 011 --------- gdacl[0:2] ; 011 ------------ gdacr[0:2] ; 0 --------------- mutedac (1=mute) ; 1 ---------------- pdndac (1=pwrdwn) ; 1 ----------------- pdnadc (1=pwrdwn) ; 1 ------------------ nrst (0=reset) ;------------------------------------------------------------------------------- ; sai intitialisation values ;------------------------------------------------------------------------------- ;--- init_rcs ------------------------------------------------------------------ ; settings for the receiver control/status register ; 321098765432109876543210 init_sai_rcs equ %000000000001000101001001 ; $000149 ; 1 --- r0en (0:disbaled; 1:enabled) ; 0 ---- r1en (0:disbaled; 1:enabled) ; 0 ----- r2en (0:disbaled; 1:enabled) ; 1 ------ rmme (1:master mode; 0:slave mode) ; 0 ------- reserved ; 10 -------- rwl[0:1] (00:16; 01:24; 10:32) ; 0 ---------- rdir (0:msb 1st; 1:lsb 1st) ; 1 ----------- rlrs (0:lrckr=0-lw; 1:lrckr=0-rw) ; 0 ------------ rckp (0:-ve ; 1:+ve) ; 0 ------------- rrel (0:trans-1st; 1:i2s) ; 0 -------------- rdwj ; 1 --------------- rxie (0:disabled; 1:enabled) ; 0 ---------------- reserved ; 0 ----------------- rofl appendix 1 tda7590 30/42 ; 0 ------------------ rdr ; 0 ------------------- rofcl ;--- init_tcs ------------------------------------------------------------------ ; settings for the transmitter control/status register ; 321098765432109876543210 init_sai_tcs equ %000000000001010101001001 ; $000549 - non incrociato ; 1 --- t0en (0:disbaled; 1:enabled) ; 0 ---- t1en (0:disbaled; 1:enabled) ; 0 ----- t2en (0:disbaled; 1:enabled) ; 1 ------ tmme (1:master mode; 0:slave mode) ; 0 ------- reserved ; 10 -------- twl[0:1] (00:16; 01:24; 10:32) ; 0 ---------- tdir (0:msb 1st; 1:lsb 1st) ; 1 ----------- tlrs (0:lrckr=0-lw; 1:lrckr=0-rw) ; 0 ------------ tckp (0:-ve ; 1:+ve) ; 1 ------------- trel (0:trans-1st; 1:i2s) ; 0 -------------- tdwe ; 1 --------------- txie (0:disabled; 1:enabled) ; 0 ---------------- reserved ; 0 ----------------- tufl ; 0 ------------------ tde ; 0 ------------------- tufcl ;------------------------------------------------------------------------------- ; pll intitialisation values ;------------------------------------------------------------------------------- if 1 ; settings per sci 115200 ;--- pll_csr ------------------------------------------------------------------- ; settings for the pll control register ; 321098765432109876543210 ; settings for the pll control register ; 321098765432109876543210 ;init_pll_csr equ $0e0c00 init_pll_csr equ %000011100000110000000000 ; $0e0c00 ; 00000 --- idf =0 (actual = idf+1=1) ; 0 -------- reserved ; 0 --------- lock (read only; 0:out of lock) ; 0 ---------- outlock (read only; 0:in lock) ; 0001100 ----------- mf =12 (actual = mf + 1 = 13) ; 0 ------------------ pllie (0:intr disable) ; 0 ------------------- pwrdn (1:power down mode) ; 1 -------------------- diten (0:disable) ; 1 --------------------- fractn (0:disable) ; 1 ---------------------- pen (1:pll enable) ;--- fract --------------------------------------------------------------------- ; settings for the fractional n part of the pll ; 321098765432109876543210 ;init_pll_fcr equ $0034bd init_pll_fcr equ %000000000011010010111101 ; $0034bd ; 01110000101001 --- fract = 13501 ;--- clkctl -------------------------------------------------------------------- tda7590 appendix 1 31/42 ; settings for the clock control register ; 321098765432109876543210 ;init_pll_clkctl equ $018cc1 init_pll_clkctl equ %000000011000001011000001 ; $018cc1 ; 0001 --- dspdf =1 (actual = dspdf+1=3) ; 00 ------- testsel ; 1 --------- dcksrc (0:xti; 1:fvco) ; 1 ---------- daclken (1: enable codec clocks) ; 0000010 ----------- mfsdf =2 (actual =mfsdf+1 = 3 ) ; 011 ------------------ sel (000:128,001:256, 010:384, etc) ; 0 --------------------- dsp_xti (0:vco/dspdf; 1:xti) ; 0 ---------------------- dac_sel (0:vco/mfsdf; 1:ext_dac_clk) ; 0 ----------------------- xtld (0:enabled; 1:disabled) endif ; settings per sci 115200 ;------------------------------------------------------------------------ ; timer intitialisation values ;------------------------------------------------------------------------ ;--- tcsr0 -------------------------------------------------------------------- ; settings for the timer control/status register ; 321098765432109876543210 init_tcsr0 equ %000000001000101000000100 ; $8a04 mode0 / trm=1 / tce=1 / pce=1/ dir=out init_tcsr1 equ %000000001000101000000100 ; $8a04 mode0 / trm=1 / tce=1 / pce=1/ dir=out init_tcsr2 equ %000000001000101000000100 ; $8a04 mode0 / trm=1 / tce=1 / pce=1/ dir=out ; xx ----------------------->[23-22]; unused ; 0 ---------------------->[21] tcf ; timer compare flag ; 0 --------------------->[20] tof ; timer overflow flag ; xxxx ----------------->[19-16] ; unused ; 0 ---------------->[15] pce ; prescaler clock enable ; x --------------->[14] ; unused ; 0 -------------->[13] do ; data output ; 0 ------------->[12] di ; data input ; 1 ------------>[11] dir ; direction ; x ----------->[10] ; unused ; 1 ---------->[ 9] trm ; timer reload mode ; 0 --------->[ 8] inv ; inverter ; 0000 ----->[7-4] tc[3-0] ; timer control = mode0 ; x ---->[ 3] ; unused ; 1 --->[ 2] tcie ; timer compare interrupt enable ; 0 -->[ 1] toie ; timer overflow enable ; 0 ->[ 0] te ; timer enable ;--- tlr0 -------------------------------------------------------------------- ; settings for the timer load register init_tlr0 equ $000000 init_tlr1 equ $000000 init_tlr2 equ $000000 ;--- tcpr0 -------------------------------------------------------------------- ; settings for the timer compare register ;init_tcpr0 equ $000002 ;init_tcpr1 equ $000004 ;init_tcpr2 equ $000008 init_tcpr0 equ $000000 init_tcpr1 equ $000000 appendix 1 tda7590 32/42 init_tcpr2 equ $000000 ;--- tplr -------------------------------------------------------------------- ; settings for the clock control register ; 321098765432109876543210 ;init_tplr equ %001000000000001111100111 ; $2003e7 source tio0 / divider = 999+1 init_tplr equ %000000000000001111100111 ; $0003e7 source internal / prescaler 999 ; x------------------------> ; reserved. write to zero for future compatibility. ; 01----------------------> ps[1-0] ; prescaler source [00 internal / 01 external tio0 / ; ; 10 external tio0 / 11 external tio0] ; 000000000010000000000-> pl[20-0] ; prescaler preload value200400 ;------------------------------------------------------------------------------- ; interrupt initialisation values ;------------------------------------------------------------------------------- ; settings for the interrupt priority register - core ; 321098765432109876543210 init_ipr_c equ %000000000000000000000000 ; $000000 ; settings for the interrupt priority register - peripherals ; 321098765432109876543210 init_ipr_p equ %000000000011111001000100 ; $29c4 glitch sull'uscita del dac ; 00---- hi ; 11------ essi0 ; 00-------- essi1 ; 11---------- sci ; 11------------ timer ; 11 ------------- sai ; 11 --------------- codec ; 00 ----------------- pll ; 00 ------------------- unknow ; 00 --------------------- i2c ; 00 ----------------------- spi ; 00 ------------------------- emi ;------------------------------------------------------------------------------- ; expansion port intitialisation values ;------------------------------------------------------------------------------- ;--- init_aar0 ----------------------------------------------------------------------- ; settings for the address attribute register1 ; 321098765432109876543210 init_aar0 equ %110000000000010000010000 ; c00410 ; 00 --- bat (00: synchronous sram; 01: sram; 10: dram; 11: reserved) ; 0 ----- baap (0:aa1 active low; 1: aa1 active high) ; 0 ------ bpen (0: p space disabled; 1: p space enabled) ; 1 ------- bxen (0: x data space disabled; 1: x data space enabled) ; 0 -------- byen (0: y data space disabled; 1: y data space enabled) ; 0 --------- bam (0: 8 lsb of address will appear on a0-a7; ; 1: 8 lsb of address will appear on a16-a23) ; 0 ---------- bpac (0: packing disabled; 1: packing enabled) ; 0100 ----------- bnc (number of bits to compare; 1111, 1110, 1101 reserved) ; 110000000000 --------------- bac (address to compare; bnc most significant) ;--- init_bcr ----------------------------------------------------------------------- tda7590 appendix 1 33/42 ; settings for the bus control register ; 321098765432109876543210 init_bcr equ %001100000010010000100001 ; 306e10 ;init_bcr equ %000001111111110011100111 ; 30fe07 ; 00111 --- ba0w (area 0 wait states) ; 00000 -------- ba1w (area 1 wait states) ; 111 ------------- ba2w (area 2 wait states) ; 111 ---------------- ba3w (area 3 wait states) ; 00000 ------------------- bdfw (default area wait states) ; 0 ------------------------ bbs (0: ; 1: dsp is bus master read only) ; 0 ------------------------- blh (0: ; 1: bln always asserted) ; 0 -------------------------- brh (0: ; 1: brn always asserted) ;******************************************************************************* ; definitions addded by paul cassidy for salieri testbench trigger_tube equ $12002 m_bcr equ $fffffb ; bus control register m_aar0 equ $fffff9 ; address attribute 0 m_aar1 equ $fffff8 ; address attribute 1 m_aar2 equ $fffff7 ; address attribute 2 m_aar3 equ $fffff6 ; address attribute 3 ;******************************************************************************* ;************************** main prog starts here ****************************** ;******************************************************************************* startp org p:$0 jmp start sci_int org p:sci_rec ; interrupt sci receive jsr int_scir org p:sci_trans ; interrupt sci transmit jsr int_scit org p:sci_rec_e ; interrupt sci framing error jsr int_scie sai_int org p:sai_rdr jsr int_rdr org p:sai_tde jsr int_tde org p:sai_rof jsr int_rof org p:sai_tuf jsr int_tuf essi_int org p:essi0_rdf jsr comp_0 nop org p:essi0_roe appendix 1 tda7590 34/42 movep x:m_ssisr0,a0 movep x:m_rx0,y:(r0)+ org p:essi0_rls nop nop org p:essi0_tde jsr clr_tde0 nop org p:essi0_tue jsr clr_tue0 nop org p:essi0_tls nop nop timer_int org p:timer0_tcf jsr int_tmr0_tcf org p:timer0_tof jsr int_tmr0_tof org p:timer1_tcf jsr int_tmr1_tcf org p:timer1_tof jsr int_tmr1_tof org p:timer2_tcf jsr int_tmr2_tcf org p:timer2_tof jsr int_tmr2_tof org x:0 states dsm ntaps org y:0 coef dc .1,.3,-.1,.2 org p:$100 start ; setup external memory for sync with testbench ;------------------------------------------------------------------------ ; initialise core ;------------------------------------------------------------------------ clr a clr b move #$0,r0 move #$fff,m0 ori #$3,mr ; mask interrupts movep #init_ipr_c,x:ipr_c ; set core interrupt priorities movep #init_ipr_p,x:ipr_p ; set peripheral interrupt priorities ;------------------------------------------------------------------------ ; initialise pll ;------------------------------------------------------------------------ init_pll movep #init_pll_csr,x:pll_csr ; enable the pll. jclr #lock,x:< appendix 1 tda7590 36/42 movep b1,x:m_crb0 endif if 1 ;------------------------------------------------------------------------ ; enable gpios for timer ;------------------------------------------------------------------------ init_gpio ; movep #$000000,x:< appendix 1 tda7590 38/42 bset #12,x:scr_adr ; start sci transmit mac x0,y0,a x:(r3)+,x0 y:(r4)+,y0 ; generates variations on mean value of dac move #$aaaaaa,x0 move x0,x:$caaaaa ; send data to expansion port move x0,x:gpiodat ; move portb pins bset #12,x:scr_adr ; start sci transmit mac x0,y0,a x:(r3)+,x0 y:(r4)+,y0 ; generates variations on mean value of dac move #$555555,x0 move x0,x:$c55555 ; send data to expansion port move x0,x:gpiodat ; move portb pins jmp loop endif ;------------------------------------------------------------------------ ; interrupt service routines ;------------------------------------------------------------------------ ;sai ;------------------------------------------------------------------------ int_tde ; the transmitter data empty flag is cleared as soon ; as the last move is performed movep a,y:< appendix 1 tda7590 40/42 clr_gpio bclr #0,x:m_pdre rti comp_1 rti ;sci ;------------------------------------------------------------------------ int_scir move x:srxl_adr,x0 movep #$3f02,x:scr_adr ; move x0,x:(r1)+ ; move x0,x:$c00000 rti int_scit ; movep x0,x:stxa_adr movep #$000041,x:stxa_adr ; movep #$000061,x:stxa_adr l3 jclr #0,x:< tda7590 42/42 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; 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