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rev. 0.1 7/15 copyright ? 2015 by silicon laboratories AN901 AN901 d esign g uide for i solated dc/dc using the s i 884 xx /886 xx 1. introduction the si884xx/si886xx product families integrate digital isolator channels with an isolated dc-dc controller. this application note provides guidance for selecting external components necessary for the operation of the dc-dc controller. digital isolation applications with primary side supply voltage v in > 5.5 v or load power requirements of >2 w can use si884xx/si886xx products. these product?s dc-dc controller uses the isolated flyback circuit topology. the advantage of this topology when compared with the si882xx/si883xx is that it can be tailored to work in higher voltage and higher power applications. figure 1 shows the minimum external components required for the isolated flyback, including optional support circuitry. the components shown in figure 1 are input capacitor c2, transformer t1, power switching fet q1, current sense resistor r12, primary snubber r16 and c19, secondary diode d1, output capacitor c10, secondary snubber r8 and c8, voltage sense resistors r5 and r6, and compensation network components r7 and c11. q2, r14, and c14 create a regulator circuit to power vdda from v in . c6 and r13 set the switching frequency and soft start characteristics for product variants that use external frequency and soft start control. figure 1. required external components
AN901 2 rev. 0.1 2. simplified dc steady state analysis analyzing the flyback behavior in dc steady state provides formulas to assist with selecting values for the components used in figure 1. for this analysis, it is assumed that components are ideal, at 100% efficiency (p in = p out ), and the circuit has reached equilibrium. figure 2 shows the critical components of the flyback converter. the transformer model includes magnetizing inductance l m and inductance leakage l lkg . r load does not necessarily represent a physical resistor, rather it is an expression of v out /i out . figure 2. flyback converter for dc steady state analysis, the two modes where the system operates the majority of the cycle are only required when s1 is closed and when s1 is open. figure 3 depicts the simplified magnetizing and secondary current waveforms.
AN901 rev. 0.1 3 figure 3. inductor currents
AN901 4 rev. 0.1 2.1. s1 closed v in is applied to the primary inductance l m . as a result, current flows through inductance l m and energy is stored in the magnetic field of the transformer t1: equation 1. i m,ripple is the magnetizing current ramp during t s1 , and t s1 is the time that s1 is closed. in discontinuous conduction mode (dcm), i m,ripple is equal to i m,pk as primary and secondary currents returning to zero before the next cycle. in continuous conduction mode (ccm), the currents do not reach zero before the next switching cycle. 2.2. s1 open the instant s1 opens, current can no longer flow through the primary and the magnetic field collapses, transferring energy to the secondary, causing current to flow out of the dot of the ideal transformer. the energy stored in the leakage inductance is not transferred and it must be dissipated in the primary through the snubber network. the voltage at the secondary will be impressed on the primary. the governing current equation is: equation 2. where n and t s2 are primary to secondary turns ratio and time that s1 is open, respectively. v in l m ?? i mripple ? t s1 -------------------------- = i m ripple ? nv out ? t s2 ? l m -------------------------------------- ? =
AN901 rev. 0.1 5 2.3. voltage transfer let duty cycle d be defined as the ratio of time s1 is closed over the complete switching period t sw : equation 3. now t s1 and t s2 can be expressed in terms of d and switching period as: equation 4. equation 5. and assume diode d1 has no voltage drop when conducting the volt-second balance equation for l m , which in ccm operation can be written as: equation 6. equation 6 simplifies to: equation 7. for dcm, current does not flow out of the secondary over the entire (1-d) portion, which changes the voltage transfer function shown in equation 7. unlike ccm, the voltage transfer characteristics in dcm are dependent on factors such as r load and switching period. the governing equation is: equation 8. d t s1 t s1 t s2 + --------------------- - = t s1 dt sw = t s2 1d ? ?? t sw = v in dt sw nv out ?? 1d ? ?? t sw ? 0 = v out v in d n1 d ? ?? --------------------- - ? v out v in d r load t sw 2l m ---------------------------- ?
AN901 6 rev. 0.1 2.4. magnetizing current substituting equation 4 into equation 1, the ripple magnetizing current is: equation 9. the average magnetizing current is related to the output current as: equation 10. when a flyback converter is operating in ccm, the peak magnetizing current is given by the average current plus one half of the ripple current: equation 11. when a flyback converter is operating in dcm, the peak magnetizing current is equal to the ripple current: equation 12. si884xx/si886xx controller limits the peak magnetizing current by comparing the voltage across the current sense resistor r12 to an internal reference voltage of approximately 100 mv. if more than 100 mv is developed across r12 during s1 closed, the controller immediately switches s1 open. the controller maintains the same switching period, but reduces the duty cycle d to limit peak current. the cycle by cycle current limit is given by: equation 13. i mripple ? v in t s1 l m ----------------- v in dt sw l m ----------------------- - == i m ave ? i load n1 d ? ?? --------------------- - = i mpkccm ?? i m ave ? v in dt sw 2l m ----------------------- - + = i mpkdcm ?? i mripple ? = i m limit ? 100mv r12 ------------------- =
AN901 rev. 0.1 7 2.5. optional primary snubber snubbers are used for two purposes in a flyback converter: to limit the peak voltage on the drain of the q1, and to attenuate high frequency ringing that leads to emissions. there are several methods to create a primary side flyback snubber. the rc snubber is presented here. the energy stored in the leakage inductance l lkg does not transfer to the secondary and must be dissipated in the primary. the power dissipated in the leakage inductance is given by: equation 14. when s1 opens, the current flowing in the primary will charge the drain-source capacitance of q1 causing the voltage at the drain to increase rapidly. when this voltage exceeds v in + nv out , a ringing occurs with frequency dependent on the inductance leakage l lkg and c ds . the rc snubber presents a load for which to dissipate the power stored in the inductance leakage. this load limits the switching speed of q1, which limits the peak voltage across the drain-source. a first order approximation for determining r16 and c19 is to set them to the characteristic impedance of the ringing caused by l lkg of t1 and c ds of q1. equation 15. r16 can be determined by measuring l lkg and ringing frequency: equation 16. c19 can be set to the same impedance using: equation 17. 2.6. input capacitor the purpose of c2 input capacitor is to provide filtering for v in during the switching cycle and reduce voltage ripple at the converter input. operating in ccm, during t s1 portion of the cycle c2 current is given by: equation 18. the voltage ripple on c2 can be written as: equation 19. p lkg l lkg i mpk 2 ? 2t sw --------------------------- - = r16 z c19 l lkg c ds --------- - ?? r16 2 ? f ring l lkg ? c19 1 2 ? f ring r16 ----------------------------- - ? i c2 i in i mave ? ? d1 ? ?? i load n1 d ? ?? --------------------- - i load n --------------- ? = == v in ripple ? i c2 dt sw c2 ---------------------- - i load dt sw nc2 ? ------------------------------ ==
AN901 8 rev. 0.1 2.7. optional regulator for vdda supply vdda valid operating range is between 3.0 v and 5.5 v. in applications where the only source available on the primary side is above 5.5 v, si884xx/si886xx provides a voltage reference for an external regulator circuit. the regulator circuit consists of transistor q2, r14, and c14, as shown in figure 4. the circuit behind the vrega pin can be modeled as a zener diode connected from vrega to gnda, and requires input current between 350 a to 950 a to establish a nominal 4.85 v reference at the vrega pin. this reference is tied to the base of q2 and the emitter outputs approximately a 4.3 v supply suitable to power vdda. figure 4. external regulator circuit the governing equations for the circuit are: equation 20. equation 21. equation 22. it is recommended to set i r to no more than 950 a no matter i dda load. as i dda increases, more of i r will flow into the base of q2. v rega reference voltage will be maintained as long as the i reg > 350 a. choose q2 with adequate gain to source the maximum expected i dda . the recommended value for c14 filter capacitor for the vrega reference is 100 nf. i r i b i reg + v in v rega ? r14 --------------------------------- == i dda i b ? 1 + ?? = v dda v rega v be ? =
AN901 rev. 0.1 9 2.8. diode and output capacitor in ccm, current flows through d1 only during the (1-d)t sw portion of the steady state cycle. during the dt sw portion of the cycle, i load is sourced solely by the output capacitor c10. output voltage ripple on c10 can be calculated by: equation 23. applying the charge balance of c10, equation 24. equation 25. when d1 is reversed biased, it must withstand: equation 26. 2.9. optional secondary snubber at the instant s1 closes, this reverse voltage applied to d1 can overshoot and ring before settling to v d1,rev(d) as given by equation 26. a rc snubber can be used to limit the voltage stress across d1. like the design of the optional primary snubber, a first order approximation for determining r8 and c8 is to set them to the characteristic impedance of the ringing caused by secondary side l lkg of t1 and parasitic capacitance of d1. equation 27. r8 can be determined by measuring l lkg and ringing frequency: equation 28. c8 can be set to the same impedance using: equation 29. v out ripple ? i load dt sw c10 ------------------------------ = i ? load dt sw i d1 ave 1 d ? ?? ? 1d ? ?? t sw i load 1d ? ?? t sw ? + 0 = i d1 ave 1 d ? ?? ? i load 1d ? --------------- = v d1 rev d ?? ? v in n -------- - v out + = r8 z c8 l lkg sec ? c d1 ---------------------- - ?? r8 2 ? f ring l lkg sec ? ? c8 1 2 ? f ring r8 -------------------------- ?
AN901 10 rev. 0.1 2.10. vsns voltage divider for the purpose of selecting sense resistors r5 and r6, the entire dc-dc converter can be modeled as a non- inverting amplifier as shown in figure 5. notice that the non-inverting input, supply voltage (v+), and output voltage of the amplifier correspond to the internal 1.05 v reference, v in , and v out of the dc-dc converter. figure 5. simplified v out gain model assuming infinite dc gain and applying kcl at the inverting input of the amplifier, v out can be expressed by: equation 30. where i vsns represents the input offset current at vsns pin. from equation 30, it can be observed that a very large r5 could reduce the output voltage accuracy. v out 1.05 r5 r6 ------- - 1 + ?? ?? r5 i vsns ? + =
AN901 rev. 0.1 11 3. dynamic response the si886xx start-up response consists of four regions of operation: calibration, soft-start (ss), proportional- mode (p-mode), and proportional integral mode (pi-mode). the si884xx has fixed switching frequency and soft- start behavior hence its dc-dc operation skips calibration and begins with soft-start. figure 6 shows a typical v out response during start up for the si886xx operating at 500 khz: figure 6. v out during start up
AN901 12 rev. 0.1 3.1. external soft-start and switching frequency calibration the si886xx has two additional external pins compared to si884xx for setting switching frequency and adjusting soft start time, sh_fc and ss. the capacitor c6 is connected between pin ss and gnda and sets the soft start time. the resistor r13 is connected between pin sh_fc and gnda when the dc-dc is operating. si886xx supports switching frequencies from 200 khz to 900 khz, and is set by: equation 31. a practical c6 value for soft start is: equation 32. with c6 = 470 nf, r13 range to set acceptable t sw is 2.42 k to 10.9 k . for any given t sw , soft start time may be increased or decreased by increasing or decreasing c6 while adjusting r13 to maintain the same r13 x c6 time constant. the time spent in calibration mode is approximately the time constant created by r13 and c6. 3.2. soft start in soft start mode, the dc-dc peak current limit is gradually increased to limit the sudden demand of current needed from the primary supply. this mode of operation guarantees that v out monotonically increases and minimizes the probability of a voltage overshoot. once 90% of the final v out is reached, soft start mode ends, and proportional (p) mode starts. the total duration of soft start is load dependent as it affects how many switching cycles are required for v out to reach 90% of final value. in this mode of operation, the voltage feedback loop is inactive, and hence, loop stability is not a concern. t sw r13 c6 ? 1025.5 ------------------------- ? c6 470nf =
AN901 rev. 0.1 13 3.3. proportional mode once the secondary side senses 90% of v out , the control loop begins its p-mode operation. during this mode of operation, the dc-dc converter closes the loop (dc-dc converter secondary side communicates with the primary side), and therefore, analyzing the loop stability is required. figure 7 shows a simplified block diagram of the dc-dc control feedback loop. gm p represents the equivalent modulator and power stage transconductance of the dc-dc converter, and resistors r5 and r6 are the feedback resistors used to sense v out . c10 is the output capacitor, and r load represents output load. parameter gm fb and r o,gmfb are the effective error amplifier transconductance and the error amplifier output resistance, respectively. during the p-mode, an integrated resistor r int is connected to the comp pin. figure 7. simplified feedback loop for stability analysis, the loop at the input of the error amplifier is broken to obtain the small-signal transfer function from v fb,in to v fb,out : equation 33. equation 34. equation 35. h p s ?? v fb out ? v fb in ? ----------------- - a dc p ? 1 1 s ? p ------ + ?? ?? --------------------- - == ? p 1 r load c 10 ------------------------ ? a dc p ? r6 r5 r6 + --------------------- - gm fb r int r ogmfb ? ?? ?? gm p r load r5 r6 + ?? ?? ?? ? ? =
AN901 14 rev. 0.1 equation 36. gm ea is the error amplifier transconductance. for the si884xx/si886xx, gm ea ? 1x10 -3 , r int ? 100 k , and r o,gmfb ? r int . if r5 and r6 are chosen such that their parallel resistance is sufficiently larger than 1 gm e a , equation 36 simplifies to: equation 37. gm p is given by: equation 38. typically, r load ? (r5 + r6) and the dc gain in p-mode simplifies to: equation 39. notice that the dc gain of p mode is proportional to r load and inversely proportional to r5. at heavy loads (small r load ), a very large r5 could significantly increase the output voltage error as the dc gain reduces. conversely, a very small r5 increases power consumption and gm fb variability due to higher dependency on gm ea , which can significantly vary more than 1/(r5||r6) over temperature or from part to part. the total duration of this mode is approximately 7 ms. gm fb gm ea gm ea r5 r6 ?? ?? 1 + -------------------------------------------------- = gm fb 1 r5 r6 ?? ?? ------------------------- - ? gm p n 10 r12 ? ----------------------- - ? a dc p ? 10 3 ? 10 n ? r load ? r5 r12 ? ---------------------------------------------------- - ? ?
AN901 rev. 0.1 15 3.4. proportional integral mode after p-mode, the controller switches to pi-mode, the steady state and final operation mode. during this mode of operation, the error amplifier drives an impedance that consists of the series combination of resistor r7 and capacitor c11. to achieve a smooth transition between p and pi modes, it is recommended to set r7 to match r int . equation 40. in pi-mode, the loop transfer is given by: equation 41. where: equation 42. equation 43. equation 44. equation 45. notice that the loop transfer function in pi-mode has an additional pole-zero pair when compared with p-mode. in addition, the loop dc-gain is much higher in pi-mode than in p-mode due to r o,gmfb ? r int . r7 r int 100 3 ? 10 ? = h pi s ?? a dc pi ? 1 s ? z1 --------- + ?? ?? 1 s ? p1 --------- + ?? ?? 1 s ? p2 --------- + ?? ?? ? -------------------------------------------------------- = ? p1 1 r ogmfb ? c11 --------------------------------- ? ? z1 1 r7 c11 ? ------------------------- = ? p2 1 r load c10 ----------------------------- - ? a dc pi ? r ogmfb ? gm p r load r5 ---------------------------------------------------- ? ?
AN901 16 rev. 0.1 figure 8 shows the magnitude bode plot of the loop in pi mode. figure 8. simplified bode magnitude plot of the loop in pi mode
AN901 rev. 0.1 17 4. design example consider the desired requirements listed in table 1. table 1. design requirements parameter value input voltage 24.0 v output voltage 5.0 v input voltage ripple 50 mv output voltage ripple 50 mv maximum output current 1a
AN901 18 rev. 0.1 4.1. transformer design for this example, operating in ccm was chosen. equation 7 establishes the relationship between turns ratio n and duty cycle d. accounting for forward voltage drop across d1 of 0.5 v and targeting a duty cycle of 40%, equation 7 can be solved for transformer turns ratio n: equation 46. a 3:1 turns ratio was chosen. the next parameters to choose are the switching period and primary inductance. the si886xx has externally set switching frequency range of 200 khz to 900 khz. 500 khz was chosen for this example. c6 is set to 470 nf and r13 is calculated by rearranging equation 31: equation 47. r13 was set to 4.32 k as that is the closest 1% resistor value. to determine l m , consider at what minimum load should the converter operate in ccm. for this design, it was targeted to operate in ccm between 70% and full load. at the cross-over point between dcm and ccm: equation 48. substituting, equation 49. and solving for l m : equation 50. a transformer with turns ratio of 3:1 and primary inductance of 25 h was chosen. n v in d v out vf d1 + ?? 1d ? ?? --------------------------------------------------------- 24 0.4 ? 5.5 0.6 ? ---------------------- 2.91 ??? r13 1025.5 t sw ? c6 ---------------------------------- 1025.5 2 6 ? ? 10 ? 470 9 ? ? 10 ------------------------------------------ 4.36k ? == = im ave im ripple 2 ------------------------- = 0.7 i load ? n1 d ? ?? ----------------------------- - v in dt sw 2l m ----------------------- - = l m nv in d1 d ? ?? t sw 1.4 i load ? ---------------------------------------------- 324 ? 0.4 ? 0.6 ? 2 6 ? ? 10 ? 1.4 --------------------------------------------------------------------- - 24.7 ? h == =
AN901 rev. 0.1 19 4.2. r12 sense resistor selection r12 is chosen to provide a cycle by cycle current limit. equation 10 gives the average magnetizing current at specified load. equation 51. the peak current in ccm is: equation 52. allowing for some variation in performance from design calculations, 1 a current limit is chosen. applying equation 13 and calculating for r12: equation 53. figure 9 shows the expected magnetizing current waveform at specified load. figure 9. magnetizing current im ave i load n1 d ? ?? --------------------- - 1 3 0.6 ? ----------------- 556ma === i mpkccm ?? i m ave ? v in dt sw 2l m ----------------------- - + 0.556 = 24 0.4 ? 2 6 ? ? 10 ? 225 6 ? ? 10 ? --------------------------------------------- 0.94a = + = r12 100mv i mlimit ? --------------------- 0.1 1 ------- - 100m ? ===
AN901 20 rev. 0.1 4.3. q1 selection the instant s1 opens, q1?s drain voltage increases rapidly from nearly 0 v and settles to: equation 54. however, energy stored in l lkg must be dissipated in the secondary which causes v ds,(d) to spike a higher voltage. q1 must be able to tolerate this voltage spike between drain and source. a n-channel mosfet with 100 v rating was chosen to accommodate the expected voltage stress caused by l lkg 4.4. d1 selection equation 25 and 26 define the requirements for d1. substituting into equation 25, equation 55. diode current capacities are specified in rms. assuming a linear current through d1, consider the translation of average to rms: equation 56. substituting into equation 26: equation 57. equation 26 and 57 do not include the voltage spike due to the interaction of the diode capacitance and secondary side leakage inductance, and as a result, a diode with a larger withstanding voltage is required in practice. when selecting d1, diodes with low v f are the preferred choice as it minimizes the associated power loss. equation 58. several diodes were tested in the circuit. a 5 a, 50 v diode was chosen for its tolerance to high operating temperatures at which diode leakage and package heat transfer characteristics affect overall performance and efficiency. 4.5. external regulator circuit for this design, an external regulator circuit was designed to work with the vrega voltage reference to create a regulated supply for vdda. r14 was selected for a 950 a sink current. equation 59. r14 was set to 19.6 k and c14 to the recommended 0.1 f. mmbt2222 was selected for q1. v ds 1 d ? ?? ? v in nv out v fd1 + ?? + 24 16.5 + 40.5v === i d1 ave 1 d ? ?? ? i load 1d ? --------------- 1 0.6 ------- - 1.6a === i d1 rms 1 d ? ?? ? i d1 ave 1 d ? ?? ? 2 3 ------- ?? ?? 1.84a == v d1 rev d ?? ? v in n -------- - v out + 24 3 ------ 5 + 13v === p d1 1 d ? ?? v fd1 i d1 ave 1 d ? ?? ? ? = r14 v in v rega ? i r --------------------------------- 24 4.85 ? 0.00095 ----------------------- - 20.15k ? ===
AN901 rev. 0.1 21 4.6. c10 selection c10 is inversely proportional to output voltage ripple and sets the crossover frequency of control loop gain. solving equation 23, equation 60. a 22 f x7r capacitor in 1210 package was chosen. 4.7. c2 selection in most applications, v in also supplies the vdda pin that powers the dc-dc controller and left side digital isolator circuitry. it is recommended to minimize voltage ripple at vdda. solving equation 19: equation 61. a 10 f x7r capacitor in 1210 package was chosen. 4.8. r5 and r6 selection the ratios of r5 and r6 are determined by the 5 v output voltage requirement. to reduce the dependence of feedback gain on the internal error amplifier transconductance, it is recommended to have the parallel combination resistance to be 10 k . higher values of r5 and r6 reduce power loss through the divider, but at the expense of increasing output voltage error due to i vsns , which varies part to part. so r5 and r6 are chosen to target 10 k parallel resistance. equation 62. equation 63. substituting equation 52 into equation 53 and solving for r6, equation 64. the nearest 1% resistor to 12.66 k is 12.7 k . however, setting r5 to either 47.5 k or 48.7 k does not target exactly 5 v as well as other 1% resistor pairs. a better match was found with r6 = 13.3 k and r5 = 49.9 k . c10 i load dt sw v out ripple ? ----------------------------------- 1 0.4 ? 2 6 ? ? 10 ? 0.05 ----------------------------------------- - 16 ? f ?? = c2 i load dt sw v in ripple ? n ? --------------------------------------- 1 0.4 ? 2 6 ? ? 10 ? 0.05 3 ? ----------------------------------------- - 5.33 ? f ?? ? 10 3 ? 10 r5 r6 ? r5 r6 + --------------------- - = 5 1.05 r5 r6 ------- - 1 + ?? ?? = 10 3 ? 10 3.76r6 4.76 ------------------- - r6 12.66 3 ? 10 r5 ? 48.1 3 ? 10 == ? =
AN901 22 rev. 0.1 4.9. compensation network the compensation network is comprised of r7 and c11. r7 is selected to match r int and 100 k is the nearest 1% resistor value. the c11 places the compensation zero in relationship to the crossover frequency. the equation for crossover frequency can be obtained by multiplying the p-mode gain (equation 33), by the frequency of the pole created by r load and c10 (equation 39): equation 65. to achieve good phase margin, it suggested to place the compensation zero near the pole created by r load and c10. equation 66. a 1.5 nf capacitor was chosen. 4.10. primary snubber without r19 and c16 installed, v ds of q1 was measured to spike at 108 v and ring briefly at 30 mhz until the energy stored in l lkg dissipated. see figure 10: figure 10. undamped vds ringing t1 was removed from the board and its primary inductance leakage was measured to be 456 nh. applying equation 16 and equation 17, r16 and c19 were calculated: equation 67. f c 10 3 ? 10 nr load ? ? r5 r12 ? ---------------------------------------------------- - 1 2 ? r load c10 ------------------------------------ - ? 43khz ?? c11 1 2 ? f p2 r7 ? ---------------------------- - r load c10 r7 ----------------------------- - 522 6 ? ? 10 ? 100 3 ? 10 ------------------------------ - 1.1nf == = = r16 2 ? f ring l lkg 2 ? 30 6 ? 10 ? 456 9 ? ? 10 ? 86 ? == =
AN901 rev. 0.1 23 equation 68. closest standard component values of r16 = 82 and c19 = 68 pf were selected and installed. q1 vds was measured again to gage effectiveness of the rc snubber. voltage spike was reduced to 74 v as shown in figure 11. figure 11. damped vds ringing r8 and c8 on the secondary side can be selected using the same methodology. without a secondary side snubber, the voltage spike across d1 at the instant that s1 closes was measured to be 35 v with a ringing frequency of 59 mhz. t1 was removed from the board and its primary inductance leakage was measured to be 74 nh. equation 69. equation 70. r8 is a 1% resistor value and c8 of 100 pf was chosen. the voltage spike was reduced to 23 v and the ringing damped. c19 1 2 ? f ring r16 ----------------------------- - 1 2 ? 30 6 ? 10 ? 86 ? -------------------------------------------- - 62pf == = r8 2 ? f ring l lkg 2 ? 59 6 ? 10 ? 74 9 ? ? 10 ? 27.4 ? == = c8 1 2 ? f ring r8 -------------------------- 1 2 ? 59 6 ? 10 ? 27.4 ? ------------------------------------------------- - 98.4pf == =
AN901 24 rev. 0.1 4.11. design summary table 2 shows the component selection that meets design requirements. table 2. ordering guide part reference description manufacturer manufacturer part number c2 cap, 10 f, 50 v, 20%, x7r, 1210 venkel c1210x7r500-106m c6 cap, 0.4 f, 16 v, 10%, x7r, 0805 venkel c0805x7r160-474k c8 cap, 100 pf, 50 v, 10%, x7r, 0603 venkel c0603x7r500-101k c10 cap, 22 f, 25 v, 10%, x7r, 1210 venkel c1210x7r250-226m c11 cap, 1.5 nf, 25 v, 10%, x5r, 0603 venkel c0603x5r250-152k c14 cap, 0.1 f, 10 v, 10%, x7r, 0603 venkel c0603x7r100-104k c19 cap, 68 pf, 100 v, 10%, c0g, 0603 venkel c0603c0g101-680k d1 dio, super barrier, 50 v, 5.0 a, sma diodes inc. sbrt5a50sa q1 transistor, mosfet, n-chnl, 100 v, 3.7 a, 3 w, switching, sot223 fairchild fdt3612 q2 transistor, npn, 30v, 600ma, sot23 on semi mmbt2222lt1 r5 res, 49.9 k, 1/16 w, 1%, thickfilm, 0603 venkel cr0603-16w-4992f r6 res, 13.3 k, 1/16 w, 1%, thickfilm, 0603 venkel cr0603-16w-1332f r7 res, 100 k, 1/10 w, 1%, thickfilm, 0603 venkel cr0603-10w-1003f r8 res, 27.4 , 1/10 w, 1%, thickfilm, 0603 venkel cr0603-10w-27r4f r12 res, 0.1 , 1/2 w, 1%, thickfilm, 1206 venkel lcr1206-r100f r13 res, 4.32 k, 1/10 w, 1%, thickfilm, 0603 venkel cr0603-10w-4321f r14 res, 19.6 k, 1/16 w, 1%, thickfilm, 0603 venkel cr0603-16w-1962f r16 res, 82.0 , 1/10 w, 1%, thickfilm, 0603 venkel cr0603-10w-82r0f t1 transformer, flyback, 25 h primary, 500 nh leakage, 3:1, smt umec utb02205s u1 ic, isolator, dc dc external switch, freq control, 2 digital ch, so20 wb silicon labs si88621ed-is
AN901 rev. 0.1 25 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. patent notice silicon labs invests in research and development to help our customers differentiate in the market with innovative low-power, s mall size, analog- intensive mixed-signal solutions. silicon labs' extensive patent portfolio is a testament to our unique approach and world-clas s engineering team. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resu lting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no warran- ty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laborato ries assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, in cluding without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applica tions intend- ed to support or sustain life, or for any other application in which the failure of the silicon laboratories product could crea te a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such unintended or unaut horized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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