 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| psd913f2 / 80c32 design guide application note 067 by mark rootz and tim wilkerson april, 2000 rev 1.2 waferscale integration inc. 47280 kato road, fremont, ca 94538 telephone: (510)-656-5400
wsi inc. - fremont ca - 800-832-6974 - waferscale.com i contents 1 introduction ............................................................................................................................... ................................ 1 2 physical connections ............................................................................................................................... ................. 4 3 first design example C iap with no memory paging ......................................................................................... 5 3.1 memory map ............................................................................................................................... ...................... 6 3.2 psdsoft express design entry ......................................................................................................................... 7 3.2.1 invoke psdsoft express and set up your project. ....................................................................................... 7 3.2.2 psd pin definition ............................................................................................................................... ........ 9 3.2.3 system memory map: psd page register and chip select definitions. ................................................ 12 3.2.4 additional psd configuration .................................................................................................................. 15 3.2.5 c code generation ............................................................................................................................... ...... 16 3.2.6 merging mcu firmware ........................................................................................................................... 16 3.2.7 programming the psd ............................................................................................................................... 18 4 second design example C iap with memory paging ........................................................................................ 20 4.1 memory map ............................................................................................................................... .................... 21 4.2 psdsoft express design entry ....................................................................................................................... 23 5 third design example C advanced iap with paging & swapping ................................................................. 25 5.1 memory map ............................................................................................................................... .................... 25 5.2 psdsoft express design entry ....................................................................................................................... 28 6 conclusion ............................................................................................................................... ................................. 31 7 references ............................................................................................................................... ................................. 31 wsi inc. - fremont ca - 800-832-6974 - waferscale.com 1 1 introduction easy flash tm psd9xxf devices are members of a family of flash-based peripherals for use with embedded microcontrollers (mcus). these programmable system devices (psds) consist of memory, logic, and i/o. when coupled with a low-cost, rom-less 80c32 mcu, the psd forms a complete embedded flash system that is 100% in-system-programmable (isp). there are many features in the psd silicon and in the psdsoft express development software that make isp easy for you, regardless of how much experience you have in embedded flash design. this document offers three flash 80c32 designs using a psd913f2 device. the first is a simple system to get up and running quickly for basic applications, or to check out your prototype 80c32 hardware. the second design illustrates the use memory paging. the third design covers enhanced features of psd in-system-programming, including memory paging and segment swapping (same design as dk-900 kit available at www.waferscale.com for $99 usd). you can start with the first design, and migrate to the second and third as your functional requirements grow. there are other members of the psd9xxf family, including the psd913f1 and the psd934f2. the psd913f1 contains some eeprom, and the psd934f2 has a larger flash memory and a larger sram than the psd913f2. see the psd9xxf data sheet for details. this application note is applicable to these other psd9xxf family members, with only slight variations. in-system programming and in-application re-programming our industry uses the term in-system programming, or isp, in a general sense. isp is applicable to programmable logic, as well as programmable non-volatile memory (nvm). however, an additional term will be used in this document: in-application re-programming (iap). there are subtle yet significant differences between isp and iap when microcontrollers are involved. isp of memory means that the mcu is off line and not involved while memory is being programmed. iap of memory means that the mcu participates in programming memory, which is important for systems that must be online while updating firmware. often, isp is well suited for manufacturing, while iap is appropriate for field updates. psd9xxf devices provide both isp and iap for your system. keep in mind that iap can only program the memory sections of the psd, not the configuration and programmable logic portions of the psd. isp can program all areas of the psd. problems with iap typically, a host computer downloads firmware into an embedded flash system through a communication channel that is serviced by the mcu. this channel is usually a uart, but any communication channel that the 80c32 supports will do (modem, spi, can, j1850, etc.). the 80c32 must execute the code that controls the iap process from an independent memory array that is not being erased or programmed. otherwise, boot code and flash programming algorithms (iap loader code) will be unavailable to the 80c32. it is absolutely necessary to use an alternate memory array (an independent memory that is not being programmed) to store the iap loader code. a system designer must choose the type of alternate memory to store iap loader code (rom, sram, flash, or eeprom); each type has advantages and disadvantages. this alternate wsi inc. - fremont ca - 800-832-6974 - waferscale.com 2 memory may reside external to the mcu or reside on-board the mcu. a top-level view of an embedded isp/iap flash system with external memory is shown in figure 1. figure 1 C embedded flash system capable of iap (5 devices) another problem, which is specific to the 8051 architecture, is related to the separate program and data address spaces. the 80c32 cannot write to program space, but that is where the flash memory resides that holds 80c32 firmware. how can one program flash memory in- system if the 80c32 cannot write to program space? a common solution without a psd device, implementing iap with the 80c32 can be difficult and time consuming. philips application note an440 contains a ram loader program (bootstrap loader). it shows how to load code into an external ram over a serial link after power-up and how to switch execution to that ram to complete the boot sequence. this method can be a cumbersome and error-prone exercise, which is difficult to debug and vulnerable to power outages. to overcome the issue of program versus data space, a common practice is to combine the two address spaces, which reduces the total address space of the 80c32 by 50%. a better, integrated solution figure 2 shows a two-chip solution using an easy flash psd913f2. this system has ample main flash memory, a second smaller flash memory to hold the iap loader code and general data, and more sram. all three of these memories can operate independently and concurrently; meaning the mcu can operate from one memory while erasing/writing the other. the psd takes care of reclassifying memory as program or data space dynamically with a built-in register that the 80c32 can access at runtime. this easy method allows iap without having to combine program and data spaces, as is commonly done. this system also has programmable logic, expanded i/o, and design security. the two-chip solution is 100% programmable in the factory or in the field. communication channel alternate memory for iap loader code main flash memory 128k bytes em bedded sy stem host computer system sram 2k bytes system i/o 80c32 cpld wsi inc. - fremont ca - 800-832-6974 - waferscale.com 3 figure 2 C embedded flash system capable of iap and isp (2 devices) by design, the iap method just described requires mcu participation to exercise a communication channel to implement a download to the main flash memory. the psd9xxf also offers an alternative method (isp) to program the psd using a built-in ieee-1149.1 jtag interface requiring no mcu participation. this means that a completely blank psd can be soldered into place and the entire chip can be programmed in-system using waferscales flashlink tm jtag cable and psdsoft express development software. no 80c32 firmware needs to be written, just plug in the flashlink tm cable to your pc parallel port and begin programming memory, logic, and configuration. this is a powerful feature of the psd9xxf that allows immediate development of application code in your lab, smart manufacturing techniques, and easy field updates. the flashlink tm cable and psdsoft express are available from our website, www.waferscale.com. the flashlink tm is $59 usd (credit cards are accepted) and psdsoft express is free. lets take a quick look inside the easyflash tm psd913f2, as shown in figure 3. there are three independent memory arrays that are selected on a segment basis when the proper mcu address is decoded in the decode pld. the page register participates in memory decoding, which greatly simplifies memory paging. the mcu address, data, and control signals have access to most areas of the chip. the gpld has 19 combinatorial logic outputs for external device chip-selects or general logic. there are 27 i/o pins. a power management scheme can selectively shut down parts of the chip and tailor special power saving mechanisms on-the-fly. the security feature can block access to all areas of the chip from a device programmer/reader. finally, the self-contained jtag-isp controller allows programming of all areas of the chip. communication channel embedded system host computer system i/o psd913f2 * 1 28k byte s fla sh * 32k bytes flash * 2 k byte s sram * programmable logic * i/o jtag isp 80c32 wsi inc. - fremont ca - 800-832-6974 - waferscale.com 4 figure 3 C top level block diagram of psd913f2 2 physical connections connect your 80c32 to the psd, as shown in figure 4. a 52-pin plcc package is used in this example. these same connections can be used for all three design examples in this document. all members of the psd9xx family share the same pinout. this example design uses an lcd module, an external lcd chip-select, six mcu controlled i/o signals (two of which control the lcd), and a six-pin jtag-isp interface. there are 13 unused psd i/o pins shown (should use pullups to vcc with 100k resistor or tie to gnd if not used in your design). mcu addr/data mcu control page reg decode pld gpld 19 combinatorial logicoutputs 128k byte main flash 8 segments 32k byte secondary flash 4 segments 2k byte sram i/o port a i/o port b i/o port c i/o port d power mng t device security jtag-isp co ntro l ler mcu addr/data/cntl bus pld bus i/o bus psd913f2 wsi inc. - fremont ca - 800-832-6974 - waferscale.com 5 figure 4 C physical connections, 80c32 and psd913f2 3 first design example C iap with no memory paging the first design example will outline the steps to get a flash 80c32 system up and running quickly. no memory paging is used. program space and data space for main flash memory is combined because of the small amount of memory used in this simple design. you will see a memory map and the necessary design entry in the psdsoft express software development environment. a psd913f2 is used in this example, but the other members of the easy flash tm family may be used instead, with minor changes. see the psd9xxf data sheet for a comparison of family members. t do t st at ad1 tm s ad2 ad6 t err\ ad3 ad0 ad7 ad4 t di ad5 t ck rwlcd m cuio2 m cuio3 reset\ cslcd m cuio1 m cuio0 rsl cd a14 a12 a15 a9 a13 wr\ as a8 a10 a11 psen\ rd\ u2 psd913f2-15j (52 pin plcc) 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 46 20 19 18 17 14 13 12 11 47 50 49 10 9 8 48 adio0 adio1 adio2 adio3 adio4 adio5 adio6 adio7 adio8 adio9 adio10 adio11 adio12 adio13 adio14 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 adio15 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 cntl0 cntl1 cntl2 pd0 pd1 pd2 reset u1 ea xt al1 xt al2 rs t int0 int1 t0 t1 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 rd ps en ale tx d rx d wr rese t int0\ int1\ rese t\ da ta bus 2 x 16 lc d module jtag-isp c o nnect o r rs r/w e mcu i/ o signal s xx mh z uar t por t spare i/o 80c32 re set csl cd ps d ad 7 - a d 0 wsi inc. - fremont ca - 800-832-6974 - waferscale.com 6 3.1 memory map we are using a psd913f2, which provides 128 kbytes of main flash memory, 32 kbytes of secondary flash memory, and 2 kbytes sram. however, for this first simple example we will only use 32 kbytes of main flash memory, 32 kbytes of secondary flash memory, and 2 kbytes of sram. see the 80c32 system memory map in figure 5. figure 5 C memory map for first design C iap with no memory paging the nomenclature fs0, fs1, csboot0-csboot3, rs0, and csiop in figure 5 refer to the individual internal memory segments of the psd. the main psd flash memory has a total of eight 16 kbyte segments (fs0-fs7). the secondary psd flash memory has a total of four 8 kbyte segments (csboot0-csboot3). the 2 kbyte psd sram has a single segment (rs0). the internal psd control registers lie in a 256-byte address space named csiop. there is also an external memory chip-select in this example, cslcd, that is used for the lcd module. these psd memory elements are placed at the desired locations within the system memory map by pointing and clicking choices within psdsoft express software. ffff 0000 4000 8000 c000 2000 80c32 regs/sram program space data space fs0 fs1 6000 fs0 fs1 1fff 3fff 5fff 7fff bfff 0000 - 00ff 0200 - 02ff csiop, psd cntl regs 0300 - 03ff 0400 - 1fff cslcd, ext lc d chip sel 2000 - 27ff nothing mapped rs0 , 2k bytes psd sram nothing mapped 2800 8000 7fff c000 bfff ffff 16k bytes psd main fl ash 16k bytes psd main fl ash 16k bytes psd main flash 16k bytes psd main flash csb oot3 8k bytes psd secondary flash csb oot2 8k bytes psd secondary flash csb oot1 8k bytes psd secondary flash csb oot0 8k bytes psd secondary flash iap loader code gets programmed here by jtag-isp or conventional programmer tool. wsi inc. - fremont ca - 800-832-6974 - waferscale.com 7 with the memory arrangement of figure 5, the 80c32 may perform iap by executing from the secondary flash segments (csboot0 C csboot3) while erasing and programming the main flash segments (fs0 and fs1). the secondary flash memory is initially programmed though jtag-isp or other programming devices with firmware containing the following: ? 80c32 reset vector and initialization routines ? 80c32 interrupt vectors and service routines ? i/o management routines ? iap loader code. at power-on or after reset, the 80c32 boots from secondary flash memory, runs a checksum of the main flash memory, programs and verifies main flash via the uart if necessary, then execution jumps to main flash memory. notice that the portion of the memory map assigned to the secondary psd flash memory (csboot0 C csboot3) is quite large, 32 kbytes. usually, iap loader code will fit within less than 8 kbytes of memory. you may want to designate less secondary flash memory and more main flash memory in your initial design. however, youll see how all of the large secondary memory in this design is used very efficiently as you proceed on to the second and third designs in this document. the segments of main psd flash memory (fs0 and fs1) reside in both program space and data space simultaneously while the secondary psd flash memory segments (csboot0 C csboot3) reside in program space only, as seen in the memory map of figure 5. this is done to allow the 80c32 to write to program storage during iap. otherwise, the 80c32 cannot write code to flash memory if it resided in program space only. psd silicon architecture and psdsoft express allow this kind of flexibility. you will see how to designate the initial configuration of program space and data space and you will learn in the second and third designs how to make the 80c32 change the definition of program space and data space on the fly for advanced iap techniques. 3.2 psdsoft express design entry highlights of the design entry will be given here. the steps are simple and navigation through psdsoft express is easy. invoke psdsoft express and follow along if you wish. 3.2.1 invoke psdsoft express and set up your project. ? start psdsoft express. ? create a new project. ? select your project folder and name the project (in this example, name the project simple32 in the folder psdexpress\my_project). ? select an mcu. in this example, were using a philips 80c32. ? select a psd913f2 and a 52-pin plcc package. ? select the main psd flash memory to reside in both program and data space. ? select the secondary psd flash memory to reside in program space only. based on these selections, at power-up and after reset, the main psd flash memory will reside in both program and data space simultaneously, while the secondary psd flash memory will reside in program space only. this simple combination allows iap. wsi inc. - fremont ca - 800-832-6974 - waferscale.com 8 this is what the screen should look like after youve made the selections: click ok. now you will be asked if you want to use the design assistant or a pre-defined template. choose design assistant. this exercise in the design assistant will help you become familiar with the design flow. in the future, you may choose to use a template which will make many of the choices for you, based on your selection of mcu and psd. always reference the main flow diagram shown below to help you navigate through the design process. clicking on individual boxes within the flow diagram will invoke a process. a box shadowed in red identifies the next process that needs to be completed. psdsoft express will automatically invoke the next required process only the first time though a design. when you reenter an existing design, you must choose the next process that you wish to enter from the design flow diagram. if you invoke a process that invalidates other processes downstream, the gray boxes indicate which processes must be invoked again, and the red shadow indicates which process to invoke first. wsi inc. - fremont ca - 800-832-6974 - waferscale.com 9 3.2.2 psd pin definition next you will see the pin definition screen which allows you to define each psd pin function on a point and click basis. notice that all of the psd pins that connect to the 80c32 are already defined for you. you need only define the remaining pins. for this example, well configure the psd to use: ? two pins on port a to drive control signals to the lcd module. ? four pins on port b as general purpose mcu i/o. ? one pin on port b as a chip-select output for the lcd module. ? six pins on port c as jtag interface signals for isp. click on pin pa0, type in signal name of rwlcd, click on mcu i/o in the other category, then add or update. this will produce an output controlled by mcu firmware at run-time, which controls the lcd module read/write input. the 80c32 will control this output signal by writing psd control registers at run-time. these psd control registers reside at various address offsets from the base address designated as csiop. in a later section of this document you will see how to place csiop in your system memory map. the signal rwlcd should be routed to the lcd module on the circuit board as shown in the schematic of figure 4. this is what the screen should now look like: wsi inc. - fremont ca - 800-832-6974 - waferscale.com 10 now click pa1, name the signal rslcd, click mcu i/o mode in the other category, and click add or update. this will produce another output controlled by mcu firmware at run-time, which controls the lcd module register select input. this scheme to control the lcd module allows a fast mcu to run with a slow lcd module. the screen should now look like this: now click pb0, name the signal mcuio0, click mcu i/o mode in the other category, and click add or update. repeat for pins pb1, pb2, and pb3, giving names mcuio1, mcuio2, and mcuio3 respectively. this creates four i/o pins on port b that can be set, cleared, and read by the 80c32 accessing psd control registers at runtime (register base address at csiop). the screen should have the following look: wsi inc. - fremont ca - 800-832-6974 - waferscale.com 11 next click pin pb7, name it cslcd, choose external chip-select C active-hi. click add or update. this designates pin pb7 as a chip-select output for the lcd module. see below: finally, set up six pins on port c for jtag-isp. four standard jtag pins are defined by default (tms, tck, tdi, tdo). for this example, add two more jtag signals, tstat and terr, to speed the isp process (see app note 54 to learn why it is faster with six pins). click on pin pc3, choose dedicated jtag C tstat then click add or update. the signal name is automatically filled in. also, the signal terr on pin pc4 is automatically added since tstat and terr must be used as a pair. the screen should now look like this: thats all there is to it. click view to see a summary, click next>> to exit the pin definition. wsi inc. - fremont ca - 800-832-6974 - waferscale.com 12 3.2.3 system memory map: psd page register and chip select definitions. now that the psd pins are defined, you will need to define the system memory map. this is accomplished by defining all the chip-selects in the system (both internal to the psd and external chip-selects), and also defining the function of the psd page register. the three memories inside the psd are individually selected segment-by-segment when mcu addresses are presented to the decode pld (dpld). each internal psd memory segment has its own individual chip-select signal name. for example, the main psd flash memory has eight individual chip-selects (one for each sector) named fs0 C fs7. see the psd9xxf data sheet for details. each psd memory segment must be defined in psdsoft express if it is to be accessed by the mcu. for this example, we must define the internal psd memory segment chip-selects: fs0, fs1, csboot0 - csboot3, rs0, and csiop to match the memory map of figure 5. the external chip-select for the lcd module, cslcd, must also be defined, as shown in figure 5. in many 80c32 system designs, memory paging is used to address more than 64 kbytes of address space. however, for this simple design, no paging is used so no psd page register bits need to be defined. the following page register definition screen should be present on your monitor, just click next >> since we are not using memory paging in this first design example. now define the internal and external chip-selects. start with the internal chip-select for psd sram, which is rs0. then enter start and stop mcu addresses to match the memory map of figure 5. additional signal qualifiers (80c32 control signals psen, rd, wr, ale) are not needed wsi inc. - fremont ca - 800-832-6974 - waferscale.com 13 for internal psd memory chip-selects as this is taken care of in silicon. the screen should look like the following: next, define the chip-select for the base address of the internal psd control registers by clicking on csiop in the left side of the screen. enter the address range as shown: continue to define internal psd memory chip-selects for the main flash memory segments fs0 and fs1, and then the secondary flash memory segments csboot0 C csboot3. use figure 5 as a guide for address ranges. again, no signal qualifiers are needed for internal psd memory chip- selects. this is what the screen should look like for each chip-select: fs0: fs1: csiop: rs0: wsi inc. - fremont ca - 800-832-6974 - waferscale.com 14 csboot0: csboot2: csboot1: csboot3: wsi inc. - fremont ca - 800-832-6974 - waferscale.com 15 finally, define the external chip-select for the lcd module, cslcd. this chip-select is different for two reasons. first, it is an external chip-select that does not activate any memory element inside the psd because the signal cslcd is output on a psd i/o pin. and second, this chip- select requires qualifiers, meaning that this logic signal is true only for a given mcu address range and only when one of two other another signals are active. in this design, cslcd is true only when the mcu presents an address in the range of 0300 to 03ff hex and when either the 80c32 control signal _rd is true, or when 80c32 signal _wr is true. to create this logic, enter information as shown in the screen below. since both signals, _rd and _wr, are active low as they leave the 80c32, the logical not operator (!) is used when they are specified as qualifiers. signal qualifiers may be added by setting the cursor where you want the signal name to go then just double click on the signal name in the list of qualifiers. click done. 3.2.4 additional psd configuration now you should see the main flow diagram again. click on the box additional psd configuration. this is where you may choose to set the security bit to prevent a device programmer from examining or copying the contents of the psd. you can also click through the other sheets on this screen to set the jtag usercode value and set sector protection on psd non-volatile memory segments. cslcd: wsi inc. - fremont ca - 800-832-6974 - waferscale.com 16 3.2.5 c code generation you can take advantage of the low level c code drivers that are generated by psdsoft express for accessing memory elements within the psd by clicking on the c code generation box in the design flow window. ansi c code functions and headers are generated for you to paste into your 80c32 c compiler environment. just tailor the code to meet your system needs and compile. c code generation can be performed anytime after a project is opened. to generate ansi c functions and headers, simply specify the folder(s) in which you want the header files and the c source file to be written, and name the c source file. select the categories of functions that you would like to include, then click generate. three files will be written to your specified folder(s): ? wsi inc. - fremont ca - 800-832-6974 - waferscale.com 17 the psd. this address translation process is transparent. all you need to do is type (or browse) the file names that were generated from your 80c32 linker into the appropriate boxes and psdsoft express does the rest. you can specify a single file name for more than one psd chip- select, or a different file name for each psd chip-select. it depends on how your 80c32 linker has created your firmware file(s). for each psd chip-select in which you have specified a firmware file name, psdsoft express will extract firmware from that file only between the specified start and stop addresses, and ignore firmware outside of the start and stop addresses. click on merge mcu firmware in the main flow diagram. first you will notice that psdsoft express will fit your psd configuration to the silicon architecture of the psd. after the fitting process is complete, youll see this screen: in the left column are individual psd memory segment chip-selects (fs0, fs1, etc). the next column shows the logic equations for selection of each internal psd memory segment. these equations reflect the choices that you made while defining psd internal chip-select equations in an earlier step. in the middle of the screen are hexadecimal start and stop addresses that psdsoft express has filled in for you based on your chip-select equations. on the right are fields to enter (browse) the mcu firmware files. wsi inc. - fremont ca - 800-832-6974 - waferscale.com 18 select intel hex record for record type as shown. now scroll down to the bottom until you see csboot0. use the browse button and select the firmware file, psdexpress\examples\isp_8032.hex. now do the same for csboot1. the screen should look like this: this specification places firmware in secondary psd flash memory segments csboot0 and csboot1. psdsoft express will extract any firmware that lies inside the file isp_8032.hex between mcu addresses 0000 and 1fff and place it in psd memory segment csboot0. it will also extract any firmware that lies inside the file isp_8032.hex between mcu addresses 2000 and 3fff and place it in psd memory segment csboot1. click ok to generate the composite object file, simple32.obj. note: the file isp_hc32.hex will run on the dk900 development board from waferscale, and display some messages on the lcd screen to indicate a successful isp session. for your own prototype project, create a simple firmware file that configures your system hardware and performs rudimentary tasks to check out your new hardware. in this design example, there are 32 kbytes available in secondary flash memory segments csboot0 C csboot3, which is more than enough for this simple boot and test code. after your new hardware is proven, you can add more code to the boot area to for advanced tasks, including iap of main psd flash memory. 3.2.7 programming the psd the simple32.obj file can be programmed into the psd by one of three ways: ? the waferscale flashlink tm jtag cable, which connects to the pc parallel port. ? the waferscale psdpro device programmer, which also uses the pc parallel port. ? third-party programmers, from stag, needhams, and others. see our web site at www.waferscale.com for compatible third-party programmers. wsi inc. - fremont ca - 800-832-6974 - waferscale.com 19 3.2.7.1 programming with flashlink tm connect the flashlink tm jtag-isp cable to your pc parallel port. click the jtag-isp box in the design flow window. you should see the following screen: this window enables you to perform jtag-isp operations and also offers a loop back test for your flashlink tm cable. if this is your first use, test your flashlink tm cable and pc parallel port by clicking the hw setup button, then click looptest button and follow the directions. now lets define our jtag-isp environment. for this example project, psdsoft express should have filled in the folder and filename of the object file to program, the psd device, and the jtag-isp operation, as shown in the screen above. for this design example, we have chosen to use all six jtag-isp pins (instead of four). be sure to indicate 6 pins as shown above to achieve minimum jtag-isp programming times (refer to application note 54 for details on six pins vs. four) to begin programming, connect the jtag cable to the target system, power-up the target system, and click execute on the jtag screen. the log window at the bottom of the jtag screen shows the progress. programming should just take a few seconds. there are optional choices available when the properties.. button is clicked. one choice includes setting the state of all non-jtag psd i/o pins during jtag-isp operations (make them inputs or outputs). the default state of all non-jtag psd i/o pins is input, which is fine for this design example. the other choice allows you to specify a usercode value to compare before any jtag-isp operation starts. this is typically used in a manufacturing environment (see on-screen description for details). after jtag-isp operations are completed, you can save the jtag setup for this programming session to a file for later use. to do so, click on the save button. to restore the setup of a different previous session, click the browse.. button. wsi inc. - fremont ca - 800-832-6974 - waferscale.com 20 3.2.7.2 programming with psdpro connect the psdpro device programmer to your pc parallel port per the installation instructions. click on the conventional programmer box in the design flow window. you will see this: if this is the first use of the psdpro, youll need to designate the psdpro as the device connected to your parallel port. to do this, click the set h icon button at the top of the conventional programming screen and choose the psdpro. then click on the h test icon to perform a test of the psdpro and the pc parallel port. after testing, place a psd913f2 into the socket of the psdpro and click on the program icon (the simple32.obj file is automatically loaded when this process is invoked). the messaging of psdsoft will inform you when programming is complete. note: this window is also helpful even if you do not have a psdpro device programmer. use this window to see where the merge mcu firmware utility has placed 80c32 firmware within physical memory of the psd. for this design example, click on the secondary psd flash memory icon fb in the tool bar to see the 80c32 reset vector at absolute mcu addresses 0001h and 0002h, which translates to direct physical psd addresses 20001h and 20002h respectively. to see how all of your 80c32 absolute addresses translated into direct physical psd memory addresses, veiw the report that psdsoft generates under reports from the main toolbar, then select address translation report. within the report, the start and stop addresses are the absolute mcu system addresses that you have specified. the addresses shown in square brackets are the direct physical addresses used by a device programmer to access the memory elements of the psd in a linear fashion (a special device programming mode that the mcu cannot access). 4 second design example C iap with memory paging this second design example builds upon the first by adding memory paging which allows the 80c32 to access all of the memory resident on the psd913f2. the physical connections between the 80c32 and psd913f2 do not change, but the memory map, psd page register definition, and some psd chip-select equations do change. a psd913f2 is still used in this example, but the wsi inc. - fremont ca - 800-832-6974 - waferscale.com 21 other members of the easy flash tm family may be used instead with minor changes. see the psd9xxf data sheet for a comparison of family members. 4.1 memory map the psd913f2 provides 128 kbytes of main flash memory, 32 kbytes of secondary flash memory, and 2 kbytes sram. in this second design, well use all of this memory. since the 80c32 cannot address more than 64 kbytes of address space directly, we will use paging (or banking) to access all 162 kbytes of memory. the psd has a built-in page register for this purpose. many mcu cross-compilers support paging today. figures 6 and 7 represent the system memory maps for this design. these maps have paged memory in the upper address range of 8000 to ffff hex, and common memory in the lower range of 0000 to 7fff hex. in data space, the 80c32 has access to system sram and i/o regardless of what memory page is active. in program space, the firmware in the secondary psd flash memory (csboot0 C csboot3) is available to the 80c32 regardless of what memory page is active. this common program area holds the following: ? 80c32 reset vector and initialization routines ? 80c32 interrupt vectors and service routines ? i/o and memory page management routines ? sram variables and sram stack ? iap loader code ? anything else that must be accessible no matter what memory page is selected. figure 6 represents the system memory map at power-up and after reset. this map is also valid during iap. notice that all of the main psd flash memory is initially in data space so that the 80c32 can write to it during iap. also notice that all of the secondary psd flash memory is initially in program space so the 80c32 can execute code from it during iap. the choice for this initial placement of memory in program or data space is made within psdsoft express (define mcu and psd in flow diagram). figure 7 represents the system memory map after iap is complete. all of main psd flash memory has moved to program space. the psd has a control register (named the vm register) that allows the 80c32 to change the definition of program space and data space at run-time for iap purposes. this vm register is accessed at an address offset from the base address, csiop. sequence of events for iap: ? fig 6 - at power on or after reset, the 80c32 boots from secondary psd flash memory ? fig 6 - 80c32 runs a checksum of the main psd flash memory in data space ? fig 6 - if needed, 80c32 programs and verifies main psd flash in data space via the uart ? fig 6 - 80c32 writes 06 hex to the vm register to place main psd flash into program space ? fig 7 C main flash has moved to program space as a result of writing 06 hex to vm register ? fig 7 - 80c32 can now execute application code from either main or secondary psd flash wsi inc. - fremont ca - 800-832-6974 - waferscale.com 22 figure 6 C memory map at boot-up or reset and during iap. psd vm register initially 12 hex, main psd flash in data space figure 7 C memory map just after 80c32 wites 06 hex to psd vm register . iap complete, main psd flash moves to program space ffff 0000 4000 8000 2000 80c32 regs/sram program space dat a space fs0 fs1 6000 1fff 3fff 5fff 7fff csio p, p sd cntl r egs cslcd, ext lcd chip sel nothing m apped rs 0 , 2k bytes psd sram nothing m apped 16k bytes psd main flash 16k bytes psd main flash csboot3 8k bytes psd secondar y f lash csboot2 8k bytes psd secondar y f lash csboot1 8k bytes psd secondar y f lash csboot0 8k bytes psd secondar y f lash iap lo ader co de gets progra mmed here by jta g-i sp or co nve ntio nal p ro g ra mmer tool. 80c32 regs/sram fs6 fs7 0000 - 00ff 0200 - 02ff csio p, p sd cntl r egs 0300 - 03ff 0400 - 1fff cslcd, ext lcd chip sel 2000 - 27ff nothing m ap ped rs 0 , 2k bytes psd sram nothing m ap ped 2800 8000 7 fff c000 b fff ffff 16k bytes psd main flash 16k bytes psd main flash 80c32 regs/sram fs2 fs3 csio p, p sd cntl r egs cslcd, ext lcd chip sel nothing m apped rs 0 , 2k bytes psd sram nothing m apped 16k bytes psd main flash 16k bytes psd main flash 80c32 regs/sram fs4 fs5 csio p, p sd cntl r egs cslcd, ext lcd chip sel nothing m apped rs 0 , 2k bytes psd sram nothing m apped 16k bytes psd main flash 16k bytes psd main flash nothing m apped co m mo n memory across all dat a pages p ag e x p ag e 0 p ag e 1 p ag e 2 p ag e 3 ffff 0000 4000 8000 2000 program space dat a space 6000 1f f f 3f f f 5f f f 7f f f csb o o t3 8k byte s psd secondary fla s h csb o o t2 8k byte s psd secondary fla s h csb o o t1 8k byte s psd secondary fla s h csb o o t0 8k byte s psd secondary fla s h 80c32 regs/sram 0000 - 00ff 0200 - 02ff csiop, psd cntl re g s 0300 - 03ff 0400 - 1fff cslc d, ext l cd chip sel 2000 - 27ff noth in g ma pped rs0 , 2 k byte s psd sram noth in g ma pped 2800 c000 bf f f ffff common memory a cross a ll program pag es page 0 page 1 page 2 page 3 page x csb o o t3 8k b yte s psd se c ondary flas h csb o o t2 8k b yte s psd se c ondary flas h csb o o t1 8k b yte s psd se c ondary flas h csb o o t0 8k b yte s psd se c ondary flas h csb o o t3 8k b yte s psd se c ondary flash csb o o t2 8k b yte s psd se c ondary flash csb o o t1 8k b yte s psd se c ondary flash csb o o t0 8k b yte s psd se c ondary flash csb o o t3 8k b ytes psd se c o ndary fla sh csb o o t2 8k b ytes psd se c o ndary fla sh csb o o t1 8k b ytes psd se c o ndary fla sh csb o o t0 8k b ytes psd se c o ndary fla sh fs6 fs7 16k b yte s psd ma in f la s h 16k b yte s psd ma in f la s h fs0 fs1 fs2 fs3 fs4 fs5 16k b yte s psd ma in f la s h 16k b yte s psd ma in f la s h 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h wsi inc. - fremont ca - 800-832-6974 - waferscale.com 23 your system design may require that you operate application code completely from main psd flash memory after iap is complete. this means swapping the secondary psd flash memory (containing iap loader code) out of program space, and replacing it with main psd flash memory (containing application code). this is explained in the third design example. 4.2 psdsoft express design entry to implement the memory map with paging techniques shown in figures 6 and 7, invoke psdsoft express, open the project simple32 from the first design example. now pull down the menu project from the top of the screen, and select save as. for this second design example, save the first project under the new name page32. click on the define psd and mcu box in the design flow diagram. change the settings for initial placement of program and data space in step 3 as shown here, then click ok: now click on the pin definition box in the design flow diagram. click ok to get to the page register definition screen since no pin assignment needs to be changed for this second design. there are a total of four memory pages used in figures 6 and 7, so you will need to define two psd page register bits for paging (2 2 = 4). to do so, click on pgr0 and pgr1 as shown below, then click next>>. wsi inc. - fremont ca - 800-832-6974 - waferscale.com 24 the chip-select equations for psd sram (rs0), psd control registers (csiop), and the external lcd module (cslcd) do not change from the first design example. only chip-selects for main psd flash memory will change because they are now paged in this design. define the internal psd main flash memory chip-select signals to implement the memory map of figures 6 and 7. the following illustrates how the chip-selects will look when you enter their definitions: continue defining fs4 and fs5 on memory page 2, and fs6 and fs7 on memory page 3. the chip- selects for csboot0 through csboot3 did not change from the first design example because no page number was specified in their definition. this means they will appear to the 80c32 on any memory page as indicated in figures 6 and 7. click done to get the main flow diagram. click the merge mcu firmware box in the design flow diagram. you will see an informational dialog box pop up that indicates memory paging is used and that the firmware file(s) you specify should be set up to handle paging. click ok, since for this design example the firmware that would run the iap process is not paged. it resides in csboot0 and csboot1 of the psd and is active on all pages (independent of what memory page is selected). click the more info button in step 1 of the merge firmware screen if your future 80c32 system design will execute code from different pages, and that code will be programmed into the psd with a device programmer (for example, you specify filename(s) in this screen that go to psd memory segments that are paged). fs0: fs1: fs2: fs3: wsi inc. - fremont ca - 800-832-6974 - waferscale.com 25 now specify the name of the 80c32 firmware file to place into the secondary flash memory segments csboot0 and csboot1. this can be any file that you create to implement iap with paging. no firmware filename needs to be designated for the main psd flash segments (fs0 C fs7) since they will be programmed by the 80c32 during iap. click ok in the merging screen to create a composite object file for programming. program the psd913f2 as in section 3.2.7. 5 third design example C advanced iap with paging & swapping the third design example adds enhanced iap features. the physical connections between the 80c32 and psd913f2 do not change, but the memory map, psd page register definition, and some psd chip-select definitions do change. this enhanced design gets the most out of the 64 kbyte address space that the 80c32 can access directly. this means swapping the iap loader code out of program space after iap is complete, and replacing it with application code, leaving the maximum amount of address space available for the application. swapping out the iap loader code not only frees up address space for application code, it also allows the software designer the option of having two sets of interrupt vectors and associated service routines; one set during iap, and a different set after iap during the normal application. in addition, this swapping technique allows the iap loader code itself to be programmed in the field while the 80c32 operates out of main psd flash memory. additionally, this design allows half of the secondary psd flash memory to be used for iap loader code, and the other half for general data. to actually use this third design, purchase the dk-900 kit from www.waferscale.com for $99 usd. it includes all hardware and firmware, and also a pc windows program to implement iap with a uart. 5.1 memory map the memory map is a sequence of four steps shown in figures 8 through 11. figure 8 is the memory map at system power-on or system reset. the swap bit is defined as one of the eight internal psd page register bits. the swap bit is an example of how page register bits can be implemented for uses other than memory paging. heres the sequence after power-up or reset: ? fig 8: 80c32 boots from secondary flash memory (csboot0/csboot1) at address 0000 ? fig 8: 80c32 performs a checksum of main flash memory while it resides in data space ? fig 8: 80c32 downloads to main flash from host computer if needed and validate contents ? fig 8: 80c32 writes 06 hex to psd vm register ? fig 9: main flash memory has moved to program space because of 06 hex in vm register ? fig 9: 80c32 sets swap bit to logic one (writes to psd page register) ? fig 10: secondary flash memory has moved out of mcu address range 0000 to 7fff and main flash memory has moved into its place because of the swap bit. this swapping action is implemented by qualifying the chip-selects with the swap signal. ? fig 10: 80c32 writes 0c hex to psd vm register ? fig 11: secondary flash memory has moved to data space because of 0c hex in vm register. figure 11 shows the final memory map. at this point, the 80c32 can download new iap loader code to csboot0/csboot1 if needed. another one of the eight psd page register bits is used for logic in this design, named unlock. the 80c32 must first set the unlock bit to logic one before updating iap loader code. all page register bits are cleared to zero at power-up or at reset. wsi inc. - fremont ca - 800-832-6974 - waferscale.com 26 figure 8 C memory map at boot-up or reset and during iap. psd vm register = 12 hex, swap = 0, unlock = 0 figure 9 Cmemory map just after 80c32 writes 06 hex to psd vm register. main psd flash moves to program space, swap = 0, unlock = 0 ffff 0000 4000 2000 80c32 regs/sram program space dat a space fs0 fs1 1fff 3fff csio p, p sd cntl r egs cslcd, ext lcd chip sel nothing m apped rs 0 , 2k bytes psd sram nothing m apped 16k bytes psd main flash 16k bytes psd main flash csboot1 8k bytes psd secondar y f lash csboot0 8k bytes psd secondar y f lash iap lo ader co de gets progra mmed here by jta g-i sp or co nve ntio nal p ro g ra mmer tool. 80c32 regs/sram fs6 fs7 0000 - 00ff 0200 - 02ff csio p, p sd cntl r egs 0300 - 03ff 0400 - 1fff cslcd, ext lcd chip sel 2000 - 27ff nothing m ap ped rs 0 , 2k bytes psd sram nothing m ap ped 2800 8000 7 fff c000 b fff ffff 16k bytes psd main flash 16k bytes psd main flash 80c32 regs/sram fs2 fs3 csio p, p sd cntl r egs cslcd, ext lcd chip sel nothing m apped rs 0 , 2k bytes psd sram nothing m apped 16k bytes psd main flash 16k bytes psd main flash 80c32 regs/sram fs4 fs5 csio p, p sd cntl r egs cslcd, ext lcd chip sel nothing m apped rs 0 , 2k bytes psd sram nothing m apped 16k bytes psd main flash 16k bytes psd main flash nothing m apped co m mo n memory across all dat a pages p ag e x p ag e 0 p ag e 1 p ag e 2 p ag e 3 ffff 0000 4000 8000 2000 program space dat a space 1f f f 3f f f 7f f f csb o o t1 8k byte s psd secondary fla s h csb o o t0 8k byte s psd secondary fla s h 80c32 regs/sram 0000 - 00ff 0200 - 02ff csiop, psd cntl re g s 0300 - 03ff 0400 - 1fff cslc d, ext l cd chip sel 2000 - 27ff noth in g ma pped rs0 , 2 k byte s psd sram noth in g ma pped 2800 c000 bf f f ffff common memory a cross a ll program pag es page 0 page 1 page 2 page 3 page x csb o o t1 8k b yte s psd se c ondary flas h csb o o t0 8k b yte s psd se c ondary flas h csb o o t1 8k b yte s psd se c ondary flash csb o o t0 8k b yte s psd se c ondary flash csb o o t1 8k b ytes psd se c o ndary fla sh csb o o t0 8k b ytes psd se c o ndary fla sh fs6 fs7 16k b yte s psd ma in f la s h 16k b yte s psd ma in f la s h fs0 fs1 fs2 fs3 fs4 fs5 16k b yte s psd ma in f la s h 16k b yte s psd ma in f la s h 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h noth in g mapped noth in g ma pped noth in g ma pped noth in g ma pped wsi inc. - fremont ca - 800-832-6974 - waferscale.com 27 figure 10 C memory map just after 80c32 sets swap = 1. iap loader code is swapped away, main psd flash takes its place.vm reg = 12, unlock = 0 figure 11 C memory map just after 80c32 writes 0c hex to psd vm register. secondary psd flash memory moves to data space. swap = 1, unlock = 0 ffff 0000 4000 8000 program sp ace dat a space 3f f f 7f f f 80c32 regs/sram 0000 - 00ff 0200 - 02ff csiop, psd c n tl r e gs 0300 - 03ff 0400 - 1fff cslc d, ext lcd chip sel 2000 - 27ff noth in g m apped rs0 , 2 k b yte s psd sram noth in g m apped 2800 c0 00 bf f f ffff common memory a cross a ll program pag es page 0 page 1 page 2 page 3 page x fs0 fs1 16k b yte s psd ma in f la s h 16k b yte s psd ma in f la s h fs0 fs1 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h fs0 fs1 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h fs0 fs1 16k b yte s psd ma in f la s h 16k b yte s psd ma in f la s h csb o o t3 8k b yte s psd secondary flash csb o o t2 8k b yte s psd secondary flash csb o o t1 appears if u nlock = 1 csb o o t0 appears if u nlock = 1 noth in g mapped fs2 fs3 fs4 fs5 fs6 fs7 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h 16k b yte s psd ma in f la s h 16k b yte s psd ma in f la s h df f f e000 bf f f c000 9f f f a000 df f f 8000 ffff 0000 4000 8000 program space dat a space 3f f f 7f f f 80c32 regs/sram 0000 - 00ff 0200 - 02ff csiop, psd cntl re g s 0300 - 03ff 0400 - 1fff cslc d, ext l cd chip sel 2000 - 27ff noth in g ma pped rs0 , 2 k byte s psd sram noth in g ma pped 2800 c000 bf f f ffff common memory a cross a ll program pag es page 0 page 1 page 2 page 3 page x csb o o t3 8k byte s psd secondary fla s h csb o o t2 8k byte s psd secondary fla s h fs0 fs1 16k b yte s psd ma in f la s h 16k b yte s psd ma in f la s h fs0 fs1 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h fs0 fs1 16k b ytes psd ma in f la s h 16k b ytes psd ma in f la s h fs0 fs1 16k b yte s psd ma in f la s h 16k b yte s psd ma in f la s h csb o o t3 8k b yte s psd se c ondary flas h csb o o t2 8k b yte s psd se c ondary flas h csb o o t3 8k b yte s psd se c ondary flash csb o o t2 8k b yte s psd se c ondary flash csb o o t3 8k b ytes psd se c o ndary fla sh csb o o t2 8k b ytes psd se c o ndary fla sh e000 df f f csb o o t1 8k byte s psd secondary fla s h csb o o t0 8k byte s psd secondary fla s h csb o o t1 8k b yte s psd se c ondary flas h csb o o t0 8k b yte s psd se c ondary flas h csb o o t1 8k b yte s psd se c ondary flash csb o o t0 8k b yte s psd se c ondary flash csb o o t1 8k b ytes psd se c o ndary fla sh csb o o t0 8k b ytes psd se c o ndary fla sh a000 9f f f wsi inc. - fremont ca - 800-832-6974 - waferscale.com 28 in this final configuration, the 80c32 has available: ? 32 kbytes of main flash memory in the common area (0000h-7fffh) ? 96 kbytes of main flash across three pages of upper memory (8000h-ffffh) ? 2 kbytes of sram in addition to the sram that resides on the 80c32 ? 16 kbytes of secondary flash for general data storage ? 16 kbytes of secondary flash for iap loader code. each time this 80c32 system gets reset or goes through a power-on cycle, the psd presents the memory map of figure 8 to the mcu, and the boot sequence is repeated. note: when the 80c32 is executing code from the secondary psd flash memory (csboot0 and csboot1), and then it sets the swap bit, it is very important that the 80c32 firmware linker has set up synchronized code in the segment of main psd flash memory that replaces the secondary psd flash memory. this is necessary to create seamless mcu operation during the actual swap of memory since the 80c32 is completely unaware that there is a swap going on. it just continues to fetch opcodes and operands during the memory swap. this requires that the operands and opcodes in main psd flash that follow the mcu instructions that actually set the swap bit in the secondary psd flash, are continuos. this means that the remainder of the instructions to complete setting the swap bit is present in main psd flash memory so there is continuos operation throughout the memory swapping process. to see example 80c32 code for this, go to the main flow diagram, then generate c code, then coded examples, then dk-900. 5.2 psdsoft express design entry to implement the advanced memory maps of figures 8 - 11, invoke psdsoft express, open the project page32 from the second design example. now pull down the menu project from the top of the screen, and select save as. for this third design example, save the second project under the new name advanc32. now click on the pin definition box in the design flow diagram. click ok to get to the page register definition screen since no pin assignment needs to be changed for this third design. you will need to define two additional psd page register bits to be used for logic. the two page register bits that were used for memory paging in the second design example stay just as they are. define page register bits for logic as shown below, labeling one bit swap and the other bit unlock: wsi inc. - fremont ca - 800-832-6974 - waferscale.com 29 click next >>. the chip-select equations for psd sram (rs0), psd control registers (csiop), and the external lcd module (cslcd), and most of the internal psd memory segments do not change from the second design example. only chip-selects for main psd flash memory segments fs0 and fs1, and the secondary psd flash memory segments csboot0 C csboot3 need to change for this third design because they are affected by memory swapping. these internal memory chip-selects must be qualified with the page register bit swap as shown below. the secondary psd memory segments, csboot0 and csboot1, must be additionally qualified by unlock to prevent the mcu from inadvertently writing to iap boot and loader code. the following illustrates how the chip-selects will look when you enter their definition: fs0: fs1: wsi inc. - fremont ca - 800-832-6974 - waferscale.com 30 csboot0: csboot1: csboot2: csboot3: wsi inc. - fremont ca - 800-832-6974 - waferscale.com 31 notice that these psd physical memory segments can appear in more that one mcu address space depending on the memory page and the swap and unlock qualifiers. now the memory maps of figures 8 - 11 have been implemented. click done and you should see the main flow diagram. click the merge mcu firmware box in the design flow diagram. you will see an informational dialog box pop up that indicates memory paging is used and that the firmware file(s) you specify should be set up to handle paging. click ok, since for this design example the firmware that would run the iap process example is not paged. when the mcu is executing iap code, it resides in csboot0 and csboot1 of the psd and is active on all pages (independent of what memory page is selected). click the more info button in step 1 of the merge firmware screen if your future 80c32 system design will execute code from different pages, and that code will be programmed into the psd with a device programmer (for example, you specify filename(s) in this screen that go to psd memory segments that are paged). now specify the name of the 80c32 firmware file to place into the secondary flash memory segments csboot0 and csboot1. this can be any firmware file that you create to implement iap with paging and swapping. if you have purchased the dk-900 kit you can use its firmware for iap. the dk-900 kit also includes a pc windows program (win95, win8, win nt) called psdload that will download (iap) the psd913f over a serial (rs-232) cable. it works directly with the memory map of this third design example. the dk-900 is $99 usd and can be purchased from www.waferscale.com with a credit card. no firmware filename needs to be designated for the main psd flash segments (fs0 C fs7) since they will be programmed by the 80c32 during iap. click ok in the merging screen to create a composite object file for programming. you are now ready to program your psd913f2. see section 3.2.7. 6 conclusion these examples are just three of an endless number of ways to configure the easy flash tm psd for your system. concurrent memories with a built-in programmable decoder at the segment level offer excellent flexibility. also, as you have seen with the swap and unlock bits, the page register bits do not have to be used just for paging through memory. the ability to enhance your system does not require any physical connection changes, as everything is configured internal to the psd. and finally, the jtag channel can be used for isp anytime, and anywhere, with no participation from the mcu. all of these features are cross-checked under the psdsoft express development environment to minimize your effort to design a flash 80c32 system capable of isp and iap. 7 references 1) psd9xxf family data sheet 2) application note an054 for detailed use of the jtag channel |
Price & Availability of AN1425
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |