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this is information on a product in full production. november 2012 doc id 16362 rev 1 1/12 12 DALC208SC6Y automotive low capacitance diode array for esd protection datasheet ? production data features protection of 4 lines peak reverse voltage: v rrm = 9 v per diode very low capacitance per diode: c < 5 pf very low leakage current: i r < 1 a benefits cost effective solution compared with discrete solution high efficiency in esd suppression no significant signal distortion thanks to very low capacitance high reliability offered by monolithic integration lower pcb area consumption versus discrete solution aec-q101 qualified complies with the following standards iso10605 - c = 150 pf, r = 330 ?? ? 15 kv (air discharge) ? 8 kv (contact discharge) iso10605 - c = 330 pf, r = 330 ? ? 8 kv (air discharge) ? 8 kv (contact discharge) iso7637-3: ? pulse 3a: v s = -150v ? pulse 3b: v s = +100v applications where esd and eos transient overvoltage protection in susceptible equipment is required, such as: information and entertainment signal communications connectivity comfort and convenience figure 1. functional diagram (top view) description the DALC208SC6Y diode array is designed to protect components which are connected to data and transmission lines from overvoltages caused by electrostatic discharge (esd) or other transients. it is a rail-to-rail protection device also suited for overshoot and undershoot suppression on sensitive logic inputs. the low capacitance of the DALC208SC6Y prevents significant signal distortion. 1 sot23-6l i/o 1 i/o 2 i/o 3 i/o 4 ref 2 ref 1 www.st.com
characteristics DALC208SC6Y 2/12 doc id 16362 rev 1 1 characteristics figure 2. electrical characteristics - definitions table 1. absolute maximum ratings (t amb = 25 c) symbol parameter value unit v pp (1) peak pulse voltage iso 10605 (c = 150 pf, r = 330 ? ) air discharge contact discharge iso 10605 (c = 330 pf, r = 330 ? ) air discharge contact discharge 15 8 8 8 kv v rrm peak reverse voltage per diode 9 v ? v ref reference voltage gap between v ref2 and v ref1 9v v in max. maximum operating signal input voltage v ref2 v v in min. minimum operating signal input voltage v ref1 v t j operating junction temperature range -40 to +150 c t stg storage temperature range -65 to +150 t l maximum junction temperature for soldering during 10 s 260 1. for a surge greater than the maximum val ues the diode will fail in short-circuit. table 2. thermal resistance symbol parameter value unit r th(j-a) junction to ambient (1) 500 c/w 1. device mounted on fr4 pcb with recommended footprint dimensions. i v i f i rm i r i pp v rm v f v br v cl symbol parameter i = leakage current @ v i = forward current v = forward voltage drop rm rm f f slope = 1/r d c line = line capacitance
DALC208SC6Y characteristics doc id 16362 rev 1 3/12 figure 3. input capacitance measurement figure 6. input capacitance versus reverse applied voltage (typical values) table 3. electrical characteristics - values (t amb = 25 c) symbol parameter conditions typ. max. unit v f forward voltage i f = 50 ma 1.2 v i r reverse leakage current per diode v r = 5 v 1 a c input capacitance between line and gnd see figure 3 . 7 10 pf g ref1 i/o +v cc ref1 connected to gnd ref2 connected to +vcc input applied : vcc = 5 v, vsign = 30 mv, f = 1 mhz ref2 v r figure 4. reverse clamping voltage versus peak pulse current (t j initial = 25 c), typical values figure 5. variation of leakage current versus junction temperature (typical values) 5 1015202530 0.1 1.0 2.0 v (v) cl i (a) pp tp=2.5s rectangular waveform i/o vs ref1 or ref2 25 50 75 100 125 150 0.01 0.1 1 10 100 t (c) j i r (a) 012345 5.0 5.5 6.0 6.5 7.0 7.5 8.0 v (v) r c(pf) f=1mhz vsign=30mv vref1/ref2=5v
technical information DALC208SC6Y 4/12 doc id 16362 rev 1 2 technical information 2.1 surge protection the DALC208SC6Y is particularly optimized to perform surge protection based on the rail to rail topology. the clamping voltage v cl can be calculated as follow: v cl + = v ref2 + v f for positive surges v cl - = v ref1 - v f for negative surges with v f = v t + r d .i p (v f forward drop voltage) / (v t forward drop threshold voltage) we assume that the value of the dynamic resistance of the clamping diode is typically r d = 0.7 ? and v t = 1.2 v. for an iec 61000-4-2 surge level 4 (contact discharge: v g =8 kv, r g = 330 ? ), v ref2 = +5 v, v ref1 = 0 v, and if in first approximation, we assume that: i p = v g / r g ? 24 a. so, we find: ?v cl + ?? +23 v ?v cl - ? -18 v note: the calculations do not take into account phenomena due to parasitic inductances. 2.2 surge protection application example if we consider that the connections from the pin ref 2 to v cc and from ref 1 to gnd are done by two tracks of 10 mm long and 0.5 mm large; we assume that the parasitic inductances of these tracks are about 6 nh. so when an iec 61000-4-2 surge occurs, due to the rise time of this spike (t r = 1 ns), the voltage v cl has an extra value equal to lw.di/dt. the di/dt is calculated as: di/dt = i p /t r ? 24 a/ns the overvoltage due to the parasitic inductances is: lw.di/dt = 6 x 24 ? 144v by taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will be: ?v cl + = +23 + 144 ? 167 v ?v cl - = -18 - 144 ? -162 v we can reduce as much as possible these phenomena with simple layout optimization. it?s the reason why some recommendations have to be followed closely. see section 2.3: how to ensure good esd protection .
DALC208SC6Y technical information doc id 16362 rev 1 5/12 figure 7. esd behavior: parasitic phenomena due to unsuitable layout 2.3 how to ensure good esd protection while the DALC208SC6Y provides a high immunity to esd surge, an efficient protection depends on the layout of the board. in the same way, with the rail to rail topology, the track from the v ref2 pin to the power supply +v cc and from the v ref1 pin to gnd must be as short as possible to avoid over voltages due to parasitic phenomena. see figure 7 . it?s often harder to connect the power supply near to the DALC208SC6Y unlike the ground thanks to the ground plane that allows a short connection. to ensure the same efficiency for positive surges when the connections can?t be short enough, we recommend putting a capacitance of 100 nf close to the DALC208SC6Y, between v ref2 and ground, to prevent these kinds of overvoltage disturbances. see figure 8 . the addition of this ca pacitance will allow a better protection by providing a constant voltage during a surge. figure 9 , figure 10 , and figure 11 show the improvement of the esd protection according to the recommendations described above. lw vi/o esd surge ref1=gnd i/o ref2=+vcc vf lw di dt lw di dt vcl+ = vcc+vf+ lw di dt surge >0 -vf- lw di dt surge <0 vcl- = t tr=1ns vcc+vf lw di dt vcl+ positive surge 167v -lw di dt t tr=1ns -vf vcl- negative surge -162v
technical information DALC208SC6Y 6/12 doc id 16362 rev 1 important put the protection device as close as possib le to the disturbance source (generally the connector). note: the measurements have been done with the DALC208SC6Y in open circuit. figure 8. esd behavior: optimized layout and add of a capacitance of 100 nf figure 9. esd behavior: measurement conditions (with coupling capacitance) ref1=gnd vi/o esd surge i/o ref2=+vcc c=100nf lw vcl+ = vcc+vf -vf surge >0 surge <0 vcl- = t vcl+ positive surge t vcl- negative surge +5v test board dalc 208 esd surge figure 10. remaining voltage after the DALC208SC6Y during positive esd surge figure 11. remaining voltage after the DALC208SC6Y during negative esd surge iec 61000-4-2 air discharge (150 pf/330 ) vpp=15 kv iec 61000-4-2 air discharge (150 pf/330 ) vpp=15 kv
DALC208SC6Y package information doc id 16362 rev 1 7/12 3 package information epoxy meets ul94, v0 lead-free package in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 12. footprint (dimensions in mm) note: product marking may be rotated by 90 for assembly plant differentiation. in no case should this product marking be used to orient the component for its placement on a pcb. only pin 1 mark is to be used for this purpose. table 4. sot23-6l dimensions ref. dimensions millimeters inches min. typ. max. min. typ. max. a 0.90 1.45 0.035 0.057 a1 0 0.10 0 0.004 a2 0.90 1.30 0.035 0.051 b 0.35 0.50 0.014 0.020 c 0.09 0.20 0.004 0.008 d 2.80 3.05 0.11 0.118 e 1.50 1.75 0.059 0.069 e0.95 0.037 h 2.60 3.00 0.102 0.118 l 0.10 0.60 0.004 0.024 ? 0 10 0 10 a2 a l h c b e d e e a1 0.95 0.60 1.20 1.10 3.50 2.30
package information DALC208SC6Y 8/12 doc id 16362 rev 1 figure 13. tape and reel specification user direction of unreeling all dimensions are typical values in mm 4.0 4.0 2.0 8.0 1.75 3.5 ? 1.55 1.24 3.1 0.21 2.1 2.9
DALC208SC6Y recommendation on pcb assembly doc id 16362 rev 1 9/12 4 recommendation on pcb assembly 4.1 solder paste 1. use halide-free flux, qualification rol0 according to ansi/j-std-004. 2. ?no clean? solder paste recommended. 3. offers a high tack force to resist component displacement during pcb movement. 4. use solder paste with fine particles: powder particle size 20-45 m. 4.2 placement 1. manual positioning is not recommended. 2. it is recommended to use the lead recognition capabilities of the placemen t system, not the outline centering. 3. standard tolerance of 0.05 mm is recommended. 4. 3.5 n placement force is recommended. too much placement force can lead to squeezed out solder paste and cause solder joints to short. too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. to improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. for assembly, a perfect supporting of the pcb (all the more on flexible pcb) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. 4.3 pcb design preference 1. to control the solder paste amount, the closed via is recommended instead of open vias. 2. the position of tracks and open vias in the solder area should be well balanced. the symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away.
recommendation on pcb assembly DALC208SC6Y 10/12 doc id 16362 rev 1 4.4 reflow profile figure 14. st ecopack? recommended soldering reflow profile for pcb mounting note: minimize air convection currents in the reflow oven to avoid component movement. 250 0 50 100 150 200 240 210 180 150 120 90 60 30 300 270 - 6c/s 240-245 c 2 - 3 c/s temperature (c) -2 c/s -3 c/s time (s) 0.9 c/s 60 sec (90 max)
DALC208SC6Y ordering information doc id 16362 rev 1 11/12 5 ordering information for the latest information on available order codes see the product pages on www.st.com. 6 revision history table 5. ordering information order code marking package weight base qty packing mode DALC208SC6Y daly sot23-6l 16.7 mg 3000 tape and reel table 6. document revision history date revision changes 07-nov-2012 1 first issue.
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