View AD7606_8329430.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

8- /6 - /4 - channel das with 16 - bit, bipolar input, simultaneous sampling adc data sheet AD7606 / AD7606 - 6 / AD7606 - 4 rev. c information furnished by analog d evices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change withou t notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 C 2012 analog devices, inc. all rights reserved. features 8/6/4 simultaneously sampled inputs true bipolar analog input ranges: 10 v, 5 v single 5 v analog supply and 2.3 v to 5 v v drive fully integrated data acquisition s olution analog input clamp p rotection input buffer with 1 m? analog input i mpedan ce second - order antialiasing analog filter on - chip accurate reference and reference buffer 16- bit adc with 200 ksps on all channels oversampling capability with digital filter flexible p arallel /s erial interface spi/qspi? / microwire? /dsp compatible performan ce 7 kv esd rating on a nalog input channels 9 5.5 db snr , ? 107 db thd 0.5 lsb inl, 0.5 lsb dnl low p ower : 100 mw standby mode : 25 mw 64- lead lqfp package applications power - line monitoring and protection systems multiphase motor control instrumentation and control systems multi axis positioning systems data acq uisition systems (das) table 1 . high resolution, bipolar input, simultaneous sampling das s olutions resolution single - ended inputs true differential inputs number of simultaneous sampling channels 18 bits ad7608 ad7609 8 16 bits AD7606 8 AD7606 -6 6 AD7606 -4 4 14 bits ad7607 8 functional block dia gram v1 v1gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v2 v2gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v3 v3gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v4 v4gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v5 v5gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v6 v6gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v7 v7gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v8 v8gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h 8:1 mux agnd busy frstdata convst a convst b reset range control inputs clk osc refin/refout ref select agnd os 2 os 1 os 0 d out a d out b rd/sclk cs par/ser/byte sel v drive 16-bit sar digital filter parallel/ serial interface 2.5v ref refcapb refcapa serial parallel regcap 2.5v ldo regcap 2.5v ldo av cc av cc db[15:0] AD7606 08479-001 figure 1.
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 2 of 36 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 timing specifications .................................................................. 7 absolute maximum ratings .......................................................... 11 thermal resistance .................................................................... 11 esd caution ................................................................................ 11 pin configurations and function descriptions ......................... 12 typical performance characteristics ........................................... 17 te rm inol ogy .................................................................................... 21 theory of operation ...................................................................... 22 converter details ........................................................................ 22 analog input ............................................................................... 22 adc transfer function ............................................................. 23 internal/external reference ...................................................... 24 typic al connection diagram ................................................... 25 power - down modes .................................................................. 25 conversion control ................................................................... 26 digital interface .............................................................................. 27 parallel interface ( pa r /ser/byte sel = 0) .......................... 27 parallel byte ( pa r /ser/ byte sel = 1, db15 = 1) ............... 27 serial interface ( pa r /ser/byte sel = 1) ............................. 27 reading during conversion ..................................................... 28 digital filter ................................................................................ 29 layout guidelines ....................................................................... 32 outline dimensions ....................................................................... 34 ordering guide .......................................................................... 34 revision history 1 /1 2 rev. b to rev. c changes to analog input ranges section ................................... 22 10/11 rev. a to rev. b changes to input high voltage (v inh ) and input lo w voltage (v inl ) parameters and endnote 6, table 2 ..................................... 4 changes to table 3 ............................................................................ 7 changes to table 4 .......................................................................... 11 changes to pin 32 description, table 6 ....................................... 13 changes to analog input clamp protection section ................. 22 changes to typical connection diagram section ..................... 25 8/10 rev. 0 to r ev. a changes to note 1, table 2 .............................................................. 6 5 /10 revision 0: initial versi on
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 3 of 36 general description the AD7606 1 /AD7606 - 6/AD7606 - 4 are 16 - bit, simultaneous sampling , analog - to - digital data acquisition systems (das) with eight, six, and four channels, respectively. e ach part contains analog input clamp protection, a second - order antialiasing filter, a track - and - hold amplifier, a 16 - bit charge redistribution successive approximation analog - to - digital converter ( adc ) , a flexible digital filter, a 2.5 v reference and ref erence buffer, and high speed serial and parallel interfaces. the ad76 06 /AD7606 - 6/AD7606 -4 operate from a single 5 v supply and can accommodate 10 v and 5 v true bipolar input signals while sampling at throughput rates up to 2 00 ksps for all channels . t he input clamp protection circuitry can tolerate voltages up to 16.5 v. the AD7606 has 1 m? analog input impedance regardless of sampling frequency. the single supply operation, on - chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. the ad76 06 /AD7606 - 6/AD7606 -4 antialiasing filter has a 3 db cutoff frequency of 22 khz and provides 40 db antialias rejection when sampling at 200 ksps. the flexible digital filter is pin driven, yields improvements in s nr, and reduces the 3 db bandwidth. 1 patent pending.
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 4 of 36 specifications v ref = 2.5 v external/internal, av cc = 4.75 v to 5.25 v, v drive = 2.3 v to 5.25 v, f sample = 200 ksps, t a = t min to t max , unless otherwise noted. 1 table 2. parameter test conditions/comments min typ max unit dynamic performance f in = 1 khz sine wave unless otherwise noted signal -to - noise ratio (snr) 2 , 3 overs ampling by 16; 10 v r ange ; f in = 130 hz 94 95.5 db overs ampling by 16; 5 v r ange ; f in = 130 hz 93 94.5 db no overs ampling; 10 v r ange 88.5 90 db no overs ampling; 5 v r ange 87.5 89 db signal -to - (noise + distortion) (sinad) 2 no oversampling; 10 v r ange 88 90 db no oversampling; 5 v r ange 87 89 db dynamic range no oversampling; 10 v r ange 90.5 db no oversampling; 5 v r ange 90 db total harmonic distortion (thd) 2 ?107 ? 95 db peak harmonic or spurious noise (sfdr) 2 ? 108 db intermodulation distortion (imd ) 2 fa = 1 khz, fb = 1.1 khz second - order terms ?11 0 db third - order terms ? 106 db channel - to - channel isolation 2 f in on unselected channels up to 160 khz ? 95 db analog input filter full power bandwidth ?3 db , 10 v range 23 k hz ?3 db, 5 v range 15 k hz ?0.1 db , 10 v range 10 k hz ?0.1 db , 5 v range 5 k hz t group delay 10 v range 11 s 5 v range 15 s dc accuracy resolution no missing c odes 16 bits differential nonlinearity 2 0.5 0.9 9 lsb 4 integral nonlinearity 2 0.5 2 lsb total unadjusted error (tue) 10 v r ange 6 lsb 5 v r ang e 12 lsb positive full - scale erro r 2 , 5 external reference 8 32 lsb internal reference 8 lsb positive full - scale error drift external reference 2 ppm/c internal reference 7 ppm/c positive full - scale e rror matching 2 10 v r ange 5 32 lsb 5 v r ange 16 40 lsb bipolar zero code error 2 , 6 10 v r ange 1 6 lsb 5 v r ange 3 12 lsb bipolar zero code error drift 10 v r ange 10 v/c 5 v r ange 5 v/c bipolar zero code error matching 2 10 v r ange 1 8 lsb 5 v r ange 6 22 lsb negative full - scale error 2 , 5 external reference 8 32 lsb internal reference 8 lsb negative full - scale error drift external reference 4 ppm/c internal reference 8 ppm/c negative full - scale error matching 2 10 v r ange 5 32 lsb 5 v r ange 16 40 lsb
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 5 of 36 parameter test conditions/comments min typ max unit analog input input voltage ranges range = 1 10 v range = 0 5 v analog input current 10 v ; s ee figure 31 5.4 a 5 v ; s ee figure 31 2.5 a input capacitance 7 5 pf input i mpedance see the analog input section 1 m reference input/output reference input voltage range see the adc transfer function section 2.475 2.5 2.525 v dc leakage current 1 a input capacit ance 7 ref select = 1 7.5 pf reference output voltage refin/refout 2.49/ 2.505 v reference temperature coefficient 10 ppm/c logic inputs input high voltage (v inh ) 0. 7 v drive v input low voltage (v inl ) 0. 3 v drive v input current (i in ) 2 a input capacitance (c in ) 7 5 pf logic outputs output high voltage (v oh ) i source = 1 00 a v drive ? 0.2 v output low voltage (v ol ) i sink = 1 00 a 0.2 v floating - state leakage current 1 20 a floating - state output capacitance 7 5 pf output coding twos complement conversion rate conversion time all eight channels included ; s ee table 3 4 s track - and - hold acquisition time 1 s throughput rate per channel, all eight channels included 200 ksps power requirements av cc 4.75 5.25 v v drive 2.3 5.25 v i to tal digital inputs = 0 v or v drive normal mode (static) AD7606 16 22 ma AD7606 -6 14 20 ma AD7606 - 4 12 17 ma normal mode (operational) 8 f sample = 200 ksps AD7606 20 27 ma AD7606 -6 18 24 ma AD7606 -4 15 21 ma standby mode 5 8 ma shutdown mode 2 6 a
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 6 of 36 parameter test conditions/comments min typ max unit power dissipation normal mode (static) AD7606 80 115.5 mw normal mode (operational) 8 f sample = 200 ksps AD7606 100 142 mw AD7606 - 6 90 126 mw AD7606 -4 75 111 mw standby mod e 25 42 mw shutdown mode 10 31.5 w 1 temperature range for the b version is ?40c to +85c. the AD7606 is operational up to 125c with throughput rates 160 ksps, and the snr typically reduces by 0.7 db at 125c. 2 see the terminology section. 3 this specification applies when reading during a conversion or after a conversion. if reading during a conversion in parallel mode with v drive = 5 v, snr typically reduces by 1.5 db and thd by 3 db . 4 lsb means least significant bit. with 5 v input range, 1 lsb = 152.58 v. with 10 v input range, 1 lsb = 305.175 v. 5 these specifications include the full temperature range variation and contribution from the internal reference buffer but do not include the error contribution from the external reference. 6 bipolar zero code error is calculated with respect to the analog input voltage. see the analog input clamp protection section. 7 sample tested during initial release to ensure compliance. 8 operational power/current figure includes contribution whe n running in oversampling mode.
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 7 of 36 timing specification s av cc = 4.75 v to 5.25 v, v drive = 2.3 v to 5.25 v, v ref = 2.5 v external reference/internal reference, t a = t min to t max , unless otherwise noted. 1 table 3. limit at t min , t max ( 0.1 v drive and 0.9 v drive logic input levels ) limit at t min , t max ( 0.3 v drive and 0.7 v drive logic input levels ) parameter min typ max min typ max unit description parallel/serial/byte mode t cycle 1/throughpu t rate 5 5 s parallel mode, reading during or after conversion; or serial mode: v drive = 3.3 v to 5.25 v, reading during a conversion using d out a and d out b lines 9.4 s serial mode reading after a conversion; v drive = 2.7 v 9.7 10. 7 s serial mode reading after a conversion; v drive = 2.3 v, d out a and d out b lines t conv 2 conversion time 3.45 4 4.15 3.45 4 4.15 s oversampling off; AD7606 3 3 s oversampling off; AD7606 -6 2 2 s oversampling off; AD7606 -4 7.87 9.1 7 .87 9.1 s oversampling by 2; AD7606 16.05 18.8 16.05 18.8 s oversampling by 4; AD7606 33 39 33 39 s oversampling by 8; AD7606 66 78 66 78 s oversampling by 16; AD7606 133 158 133 158 s oversampling by 32; AD7606 257 315 257 315 s oversampling by 64; AD7606 t wake - up standby 100 100 s stby rising edge to convst x rising edge; power - up time from standby mode t wake - up shutdown internal reference 30 30 ms stby rising edge to convs t x rising edge; power - up time from shutdown mode external reference 13 13 ms stby rising edge to convst x rising edge; power - up time from shutdown mode t reset 50 50 ns reset high pulse width t os_setup 20 20 ns busy to os x pin setup time t os_hold 20 20 ns busy to os x pin hold time t 1 40 45 ns convst x high to busy high t 2 25 25 ns minimum convst x low pulse t 3 25 25 ns minimum convst x high pulse t 4 0 0 ns busy falling edge to cs falling edge setup time t 5 3 0.5 0.5 ms maximum delay allowed between convst a, convst b rising edges t 6 25 25 ns maximum time between last cs rising edge and busy falling edge t 7 25 25 ns minimum delay between reset low t o convst x high parallel/byte read operation t 8 0 0 ns cs to rd setup time t 9 0 0 ns cs to rd hold time t 10 rd low pulse width 16 19 ns v drive above 4.75 v 21 24 ns v drive above 3.3 v 25 30 ns v drive above 2.7 v 32 37 ns v drive above 2.3 v t 11 15 15 ns rd high pulse width t 12 22 22 ns cs high pulse width (see figure 5 ); cs and rd linked
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 8 of 36 limit at t min , t max ( 0.1 v drive and 0.9 v drive logic input levels ) limit at t min , t max ( 0.3 v drive and 0.7 v drive logic input levels ) parameter min typ max min typ max unit description t 13 delay from cs until db[15:0] three - state disabled 16 19 ns v drive above 4.75 v 20 24 ns v drive above 3.3 v 25 3 0 ns v drive above 2.7 v 30 37 ns v drive above 2.3 v t 14 4 data access time after rd falling edge 16 19 ns v drive above 4.75 v 21 24 ns v drive above 3.3 v 25 30 ns v drive above 2.7 v 32 37 ns v drive above 2.3 v t 15 6 6 ns data hold time after rd falling edge t 16 6 6 ns cs to db[15:0] hold time t 17 22 22 ns delay from cs rising edge to db [15:0] three - state enabled serial read operation f sclk frequency of serial read clock 23.5 20 mhz v drive above 4.75 v 17 15 mhz v drive above 3.3 v 14.5 12.5 mhz v drive above 2.7 v 11.5 10 mhz v drive above 2.3 v t 18 delay from cs until d out a/d out b three - state disabled/delay from cs until msb valid 15 18 ns v drive above 4.75 v 20 23 ns v drive above 3.3 v 30 35 ns v drive = 2.3 v to 2.7 v t 19 4 data access time after sclk rising edge 17 20 ns v drive above 4.75 v 23 26 ns v drive above 3.3 v 27 32 ns v drive above 2.7 v 34 39 ns v drive above 2.3 v t 20 0.4 t sclk 0.4 t sclk ns sclk low pulse width t 21 0.4 t sclk 0.4 t sclk ns sclk high pulse width t 22 7 7 sclk rising edge to d out a/d out b valid hold time t 23 22 22 ns cs rising edge to d out a/d out b three - state enabled frstdata operation t 24 delay from cs falling edge until frstdata three - state disabled 15 18 ns v drive above 4.75 v 20 23 ns v drive above 3.3 v 25 30 ns v drive above 2.7 v 30 35 ns v drive above 2.3 v t 25 ns delay from cs falling edge until frstdata hig h, serial mode 15 18 ns v drive above 4.75 v 20 23 ns v drive above 3.3 v 25 30 ns v drive above 2.7 v 30 35 ns v drive above 2.3 v t 26 delay from rd falling edge to frstdata high 16 19 ns v drive above 4.75 v 20 23 ns v drive above 3.3 v 25 30 ns v drive above 2.7 v 30 35 ns v drive above 2.3 v
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 9 of 36 limit at t min , t max ( 0.1 v drive and 0.9 v drive logic input levels ) limit at t min , t max ( 0.3 v drive and 0.7 v drive logic input levels ) parameter min typ max min typ max unit description t 27 delay from rd falling edge to frstdata low 19 22 ns v drive = 3.3 v to 5.25v 24 29 ns v drive = 2.3 v to 2. 7v t 28 delay from 16 th sclk falling edge to frstdata low 17 20 ns v drive = 3.3 v to 5.25v 22 27 ns v drive = 2.3 v to 2.7v t 29 24 29 ns delay from cs rising edge until frstdata three - state enabled 1 sample tested during initial release to ensure compliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v drive ) and timed from a voltage level of 1.6 v. 2 in oversampling mode, typical t conv for the AD7606 - 6 and AD7606 - 4 can be calculated using ((n t conv ) + ((n ? 1) 1 s)). n is the oversampling ratio. for the AD7606 - 6, t conv = 3 s; and for the AD7606 - 4, t conv = 2 s. 3 the delay between the convst x signals was measured as the maximum time allowed while ensuring a <10 lsb performance matching between channel sets. 4 a buffer i s used on the data o utput pins for these measurements, which is equivalent to a load of 20 pf on the output pins. timing diagram s t cycle t 3 t 5 t 2 t 4 t 1 t 7 t reset t conv convst a, convst b convst a, convst b busy cs reset 08479-002 figure 2. convst t iming reading after a c onversion t cycle t 3 t 5 t 6 t 2 t 1 t conv convst a, convst b convst a, convst b busy cs t 7 t reset reset 08479-003 figure 3. convst timing reading during a c onversion
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 10 of 36 data: db[15:0] frstdata cs rd invalid v1 v2 v3 v7 v8 v4 t 10 t 8 t 13 t 24 t 26 t 27 t 14 t 11 t 15 t 9 t 16 t 17 t 29 08479-004 figure 4. parallel mode, separate cs and rd pulses data: db[15:0] frstdata cs and rd v1 v2 v3 v4 v5 v6 v7 v8 t 12 t 13 t 16 t 17 0 8479-005 figure 5. cs and rd , linked parallel mode sclk d out a, d out b frstdata cs db15 db14 db13 db1 db0 t 18 t 19 t 21 t 20 t 22 t 23 t 29 t 28 t 25 08479-006 figure 6. serial read operation (channel 1) data: db[7:0] frstdata cs rd invalid high byte v1 low byte v1 high byte v8 low byte v8 t 8 t 13 t 14 t 24 t 26 t 27 t 11 t 17 t 29 t 16 t 9 t 15 t 10 08479-007 figure 7. byte mode read operation
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 11 of 36 absolute maximum rat ings t a = 25c, unless otherwise noted . table 4 . parameter rating av cc to agnd ?0.3 v to + 7 v v drive to a gnd ?0.3 v to av cc + 0.3 v analog input voltage to agnd 1 16.5 v digital input voltage to a gnd ?0.3 v to v drive + 0.3 v digital output voltage to a gnd ?0.3 v to v drive + 0.3 v refin to agnd ?0.3 v to av cc + 0.3 v input curre nt to any pin except supplies 1 10 ma operating temperature range b version ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c pb/sn temperature, soldering reflow (10 sec to 30 sec) 240 (+0)c pb - free temperature, soldering reflow 260 (+0)c esd (all pins e xcept analog inputs) 2 kv esd (analog input pins o nly) 7 kv 1 transient currents of up to 100 ma do not cause scr latch - up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for exte nded periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. these specifications apply to a 4- layer board. table 5 . thermal resistance package type ja jc unit 64- lead lqfp 45 11 c /w esd caution
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 12 of 36 pin configuration s and function descrip tions AD7606 top view (not to scale) 64 63 62 61 60 59 58 57 v1gnd 56 55 54 53 52 51 50 49 v5 v4 v6 v3 v2 v1 pin 1 v7 v8 v2gnd v3gnd v4gnd v5gnd v6gnd v7gnd v8gnd db13 db12 db11 db14/hben v drive db1 17 18 19 20 21 22 23 24 25 agnd 26 27 28 29 30 31 32 db2 db3 db4 db5 db6 db7/d out a db9 db10 db8/d out b agnd av cc 1 3 4 frstdata 7 6 5 os 2 2 8 9 10 12 13 14 15 16 11 db0 busy convst b convst a range reset rd/sclk cs par/ser/byte sel os 1 os 0 stby decoupling cap pin data output power supply analog input ground pin digital output digital input reference input/output db15/byte sel refin/refout 48 46 45 42 43 44 47 41 40 39 37 36 35 34 33 38 agnd av cc refgnd refcapa agnd agnd agnd refcapb refgnd regcap regcap av cc av cc ref select 08479-008 figure 8. AD7606 pin configuration AD7606-6 top view (not to scale) 64 63 62 61 60 59 58 57 v1gnd 56 55 54 53 52 51 50 49 v4 agnd v5 v3 v2 v1 pin 1 v6 agnd v2gnd v3gnd agnd v4gnd v5gnd v6gnd agnd db13 db12 db11 db14/hben v drive db1 17 18 19 20 21 22 23 24 25 agnd 26 27 28 29 30 31 32 db2 db3 db4 db5 db6 db7/d out a db9 db10 db8/d out b agnd av cc 1 3 4 frstdata 7 6 5 os 2 2 8 9 10 12 13 14 15 16 11 db0 busy convst b convst a range reset rd/sclk cs par/ser/byte sel os 1 os 0 stby decoupling cap pin data output power supply analog input ground pin digital output digital input reference input/output db15/byte sel refin/refout 48 46 45 42 43 44 47 41 40 39 37 36 35 34 33 38 agnd av cc refgnd refcapa agnd agnd agnd refcapb refgnd regcap regcap av cc av cc ref select 08479-009 figure 9. AD7606 - 6 pin configuration
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 13 of 36 AD7606-4 top view (not to scale) 64 63 62 61 60 59 58 57 v1gnd 56 55 54 53 52 51 50 49 v3 agnd v4 agnd v2 v1 pin 1 agnd agnd v2gnd agnd agnd v3gnd v4gnd agnd agnd db13 db12 db11 db14/hben v drive db1 17 18 19 20 21 22 23 24 25 agnd 26 27 28 29 30 31 32 db2 db3 db4 db5 db6 db7/d out a db9 db10 db8/d out b agnd av cc 1 3 4 frstdata 7 6 5 os 2 2 8 9 10 12 13 14 15 16 11 db0 busy convst b convst a range reset rd/sclk cs par/ser/byte sel os 1 os 0 stby decoupling cap pin data output power supply analog input ground pin digital output digital input reference input/output db15/byte sel refin/refout 48 46 45 42 43 44 47 41 40 39 37 36 35 34 33 38 agnd av cc refgnd refcapa agnd agnd agnd refcapb refgnd regcap regcap av cc av cc ref select 08479-010 figure 10 . AD7606 - 4 pin configuration table 6 . pin function descriptions pin no. type 1 mnemonic description AD7606 AD7606 -6 AD7606 -4 1, 37, 38, 48 p av cc av cc av cc analog supply voltage, 4.75 v to 5.25 v. this supply voltage is applied to the internal front - end amplifiers and to the adc core. these supply pins should be decoupled to agnd . 2, 26, 35, 40, 41, 47 p agnd agnd agnd analog g round. these pin s are the g round reference point s for all analog circuitry on the AD7606 . all analog input signals and external reference signal s should be referred to th ese pin s. all six of the se agnd pins should connect to the agnd plane of a system. 5 , 4, 3 di os [2:0] os [2:0] os [2:0] o ver sam pling mode pins. logic inputs. these inp uts are used to select the over sampling ratio. o s 2 is the msb control bit, and os 0 is the lsb control bit. see the digital filter section for more details about the over sampling mo de of operation and table 9 for oversampling bit decoding. 6 di par /ser/ byte sel par /ser/ byte sel par /ser/ byte sel parallel/serial/byte interface selection i nput. logic i nput. if this pin is tied to a logic low, the parallel interface is selected . if this pin is tied to a logic high , the serial interface is selected. parallel b yte interface mode is selected when th is pin is logic high and db 15/byte sel is logic high (see table 8 ). in serial mode, t he rd /sclk pin function s as the serial clock input. the db7/d out a pin and t he db8/d out b pin function as serial data output s. when the serial interface is selected, the db[15:9] and db[6:0] pins should be tied to ground . in byte mode, db15 , in conjunction with par /ser/byte sel , is used to select the parallel byte mode of operation (see table 8 ). db14 is used as the hben pin. db[7:0] transfer th e 16 - bit conversion result s in two rd operations, with db0 as the lsb of the data transfers. 7 di stby stby stby standby mode input. this pin is used to place the AD7606 /AD7606 -6/ ad7 606 -4 into one of two power - down modes: standby mode or shutdown mode. the power - down mode entered depends on the state of the range pin, as shown in table 7 . when in standby mode, all circuitry , except the on - chip reference, re gulators, and regulator buffers , is powered down. when in shutdown mode, all circuitry is powered down .
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 14 of 36 pin no. type 1 mnemonic description AD7606 AD7606 -6 AD7606 -4 8 di range range range analog i nput range s elec tion . logic input. the polarity on this pin deter - mines the input range of the analog input channels. if this pin is tied to a logic high, the analog input range is 10 v for all channels. if this pin is tied to a logic low, the analog input range is 5 v for all channels. a logic change on this pin has an immediate effect on the analog input range. changing this pin during a conversion is not recommended for fast throughput rate applications . see the analog input section for more information. 9, 10 di convst a, convst b convst a, convst b convst a, convst b conversion start input a, conversion start input b. logic inputs. these logic inputs are used to initiate conversions on the analog input channels. for simultaneous sampling of all input channels, convst a and convst b can be shorted together , and a single convert start signal can be applied . alternatively, convst a can be used to initiate simultaneous sampling: v1, v2, v3, and v4 for the AD7606; v1, v2, and v3 for the AD7606 - 6; and v1 and v2 for the AD7606 -4. convst b can be used to initiate simultaneous sampling on the other a nalog inputs: v5, v6, v7, and v 8 for the AD7606; v4, v5, and v6 for the AD7606 - 6; and v3 and v4 for the AD7606 -4 . this is possible only when oversampling is not switched on. when the convst a or convst b pin transitions from low to high, the front - end trac k- and - hold circuitry for the respective analog inputs is set to hold. 11 di reset reset reset reset i nput. when set to logic high, the rising edge of reset resets the AD7606/AD7606 - 6/AD7606 - 4. the part shoul d receive a reset pulse after power - up. the res et high pulse should typically be 50 ns wide. if a reset pulse is applied during a conversion, the conversion is aborted. if a reset pulse is applied during a read, the contents of the output registers reset to all zeros. 12 di rd /sclk rd /sclk rd /sclk pa rallel data read c ontr ol input w hen the parallel i nterface is s elected ( rd )/ serial clock input w hen the serial interface is s elected (sclk) . when both cs and rd are logic low in parallel mode, the output bus is enabled. in serial mode, this pin acts as the serial clock input for data transfers. the cs falling edge takes the d out a and d out b data output l ines out of three - state and clo cks out the msb of the conversion result. the rising edge of sclk clocks all subsequent data bits onto the d out a and d out b serial data outputs. for more information, see the conversion control section. 13 di cs cs cs chip select. this active low logic input frames the data transfer. when both cs and rd are logic low in parallel mode, the db[15:0] output bus is enabled and the conversion resu lt is output on the parallel data bus lines. in serial mode, cs is used to frame the serial read transfer and clock out the msb of the serial output data. 14 do busy busy busy busy output. this pin transitions to a logic high after both convst a and convst b rising edges and indicates that the conversion process has started. the busy output remains high until the conversion process for all channels is complete. the falling edge of busy signals that the conversion data is being latched int o the output data registers and is available to read after a time t 4 . a ny data read while busy is high must be complete d before the falling edge of busy occurs. rising edges on convst a or convst b have no effect while the busy signal is high. 15 do frstd ata frstdata frstdata digital output. the frstdata output signal indicates when the first channel, v1, is being read back on the parallel, byte , or serial interface. when the cs input is high , the frstdata output pin is in three - state. th e falling edge of cs takes frstdata out of three - state. in parallel mode , the falling edge of rd corresp onding to the result of v1 then set s the frstdata pin high , indica ting that the result from v1 is available on the o utput data bus. t he frstdata output returns to a logic low following the next falling edge of rd . in serial mode, frstdata go es high on the falling edge of cs because this cloc ks out the msb of v1 on d out a. it returns lo w on the 16 th sclk falling edge after the cs falling edge. see the conversion control section for more details.
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 15 of 36 pin no. type 1 mnemonic description AD7606 AD7606 -6 AD7606 -4 22 to 16 do db[6:0 ] db[6:0] db[6:0] parallel output data b its , db6 to db 0 . when p ar /ser /byte sel = 0, these pins act as three - state parallel digital input/output pins. when cs and rd are low, t hese pins are used to output db6 to db0 of the conversion result. when par /ser /byte sel = 1 , these pins should be tied to a gnd . when operating in parallel byte interface mode, db[7:0] outputs the 16 - bit con - version result in two rd operations. db7 (pin 24) is the msb; db0 is the lsb. 23 p v drive v drive v drive logic power s upply input. the voltage ( 2.3 v to 5 .25 v) supplied at this pin determines the operating voltage of the interface. this pin is nominally at the same supply as the supply of the host interface (that is, dsp and fpga). 24 do db7/d out a db7/d out a db7/d out a pa rallel output data bit 7 (db7) /serial interface data output pin (d out a) . when par /ser /byte sel = 0, this pins acts as a three - state parallel digital input/output pin. when cs and rd are low, this p in is used to output db7 of the conversion result. when par /ser /byte sel = 1, this pin functions as d out a and outputs serial conversion data (see the conversion control section for more details). when operating in par all el byte mode, db7 is the msb of the byte. 25 do db8/d out b db8/d out b db8/d out b parallel o utput data bit 8 (db8) /serial interface data output pin (d out b) . when par /ser /byte sel = 0, this pin act s as a three - state parallel digital inpu t/output pin. when cs and rd are low, this p in is used to output db8 of the conversion result. when par /ser /byte sel = 1, this pin functions as d out b and outputs serial conversion data (see the conversion control section for more details). 31 to 27 do db [13:9] db [13:9 ] db [13:9] parallel output data bits, d b13 to db 9. when par /ser /byte sel = 0, these pins act as three - state parallel digital input/output pins. w hen cs and rd are low, these pins are used to output db13 to db9 of the conversion result. when par /ser /byte sel = 1 , these pins should be tied to a gnd . 32 do/di db14/ hben db14/ hben db14/ hben parall el output data bit 14 (db14) /high byte enable (hben) . when par / ser /byte sel = 0, this pin act s as a three - state parallel digital output pin. when cs and rd are low, this pin is used to output db14 of t he conversion result. when par /ser /byte sel = 1 and db15/byte sel = 1, the AD7606/ AD7606 - 6/AD7606- 4 operate in parallel byte interface mode. in parallel byte mode, t he hben pin is used to select whether the most significant byte (msb) or the least significant byte (lsb) of the conversion result is output first. when hben = 1 , the msb is output first, followe d by the lsb . when hben = 0 , the lsb is output first, followed by the msb . in serial mode , this pin should be tied to gnd. 33 do/d i db15/ byte sel db15/ byte sel db15/ byte sel parallel output data bit 15 (db15) /parallel byte mode select (byte sel) . when par /ser /byte sel = 0, this pin acts as a three - state parallel digital output pin. when cs and rd are low , this pin is used to output db15 of the conversion result. when par /ser /byte sel = 1, the byte sel pin is used to select between serial interface mode and parallel byte interface mode (see table 8 ). when par /ser /byte sel = 1 and db15/byte sel = 0 , the AD7606 operate s in s erial interface mode. when par /ser /byte sel = 1 and db15/byte sel = 1 , the AD7606 operate s in parallel byte interface mode. 34 di re f select ref select ref select internal/ external reference selection input. logic input. if this pin is set to logic high, the internal reference is selected and enabled. if this pin is set to logic low, the internal reference is disabled and an external r eference voltage must be applied to the refin/refout pin. 36, 39 p regcap regcap regcap decoupling capacitor pin for v oltage output from internal r egulator. these output pin s should be decoupled separately to agnd using a 1 f capacitor. the voltage on these pin s is in the range of 2.5 v to 2.7 v.
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 16 of 36 pin no. type 1 mnemonic description AD7606 AD7606 -6 AD7606 -4 42 ref refin/ refout refin/ refout refin/ refout reference input (refin) /reference output (refout). the on - chip referenc e of 2.5 v is available on this pin for external use if the ref select pin is set to logic high. alternatively, the internal reference can be disabled by setting the ref select pin to logic low , and an external reference of 2.5 v can be applied to this input (see the interna l/external reference section ) . decoupling is required on t his pin for both the internal and external reference options. a 10 f capacitor should be applied from this pin to ground close to the refgnd pins. 43, 46 ref refgnd refgnd refgnd reference ground pins. these pins should be connected to agnd. 44, 45 ref refcapa, refcapb refcapa, refcapb refcapa, refcapb reference buffer output force/sense p ins. these pins must be connected together and decoupled to agnd using a low esr , 10 f ceramic capacitor. the voltage on these pins is typically 4.5 v. 49 ai v1 v1 v1 analog input. this pin is a single - ended analog input . t he ana log input range o f this channel is determined by the range pin . 50, 52 ai gnd v1gnd, v2gnd v1gnd, v2gnd v1gnd, v2gnd analog input ground pins. these pins correspond to analog input pin v1 and analog input pin v2. all analog input agnd pins should connect to the agnd plane of a system. 51 ai v2 v2 v2 analog input. this pin is a single - ended analog input . t he analog input range o f this channel is determined by the range pin . 53 ai /gnd v3 v3 agnd anal og i nput 3. for the AD7606 -4, this is an agnd pin. 54 ai gnd/ gnd v3gnd v3gnd agnd analog input ground pin. for the AD7606 - 4, this is an agnd pin. 55 ai /gnd v4 agnd agnd analog i nput 4 . for the AD7606 - 6 and the AD7606 -4, this is an agnd pin. 56 ai gnd/ gnd v4gnd agnd agnd analog in put ground pin. for the AD7606 - 6 and AD7606 -4 , this is an agnd pin. 57 ai v5 v4 v3 analog input s . these pins are single - ended analog inputs. t he analog input range o f these channels is determined by the range pin . 58 ai gnd v5gnd v4gnd v3gnd analog input ground pin s. all a nalo g input agnd pins should connect to the agnd plane of a system. 59 ai v6 v5 v4 analog input s . these pins are single - ended analog inputs. 60 ai gnd v6gnd v5gnd v4gnd analog input g round pins . all analog input agnd pins should connect to the agnd plane of a system. 61 ai /gnd v7 v6 agnd analog input pin s . for the AD7606 - 4 , this is an agnd pin. 62 ai gnd/ gnd v7gnd v6gnd agnd analog input ground pin s . for the AD7606 - 4, this is an agnd pin. 63 ai /gnd v8 agnd agnd a nalog input p in. for the AD7606 - 4 and ad76 06 -6, this is an agnd pin. 64 ai gnd/ gnd v8gnd agnd agnd analog input g rou nd p in. for the AD7606 - 4 and AD7606 -6, this is an agnd pin. 1 p is power supply, di is digital input, do is d igital output, ref is reference input/output, ai is analog input, gnd is ground.
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 17 of 36 typical performance characteristics 0 0 100k90k80k70k60k50k 40k 30k20k10k ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 amplitude (db) input frequency (hz) av cc , v drive = 5v internal reference 10v range f sample = 200ksps f in = 1khz 16,384 point fft snr = 90.17db thd = ?106.25db 08479-011 figure 11. AD7606 fft, 10 v range 0 0 100k90k80k70k60k50k 40k 30k20k10k ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 amplitude (db) input frequency (hz) av cc , v drive = 5v internal reference 5v range f sample = 200ksps f in = 1khz 16,384 point fft snr = 89.48db thd = ?108.65db 08479-012 figure 12. AD7606 fft plot, 5 v range ?180 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 ?170 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 amplitude (db) frequency (khz) 08479-031 av cc , v drive = 5v internal reference 10v range f sample = 11.5ksps t a = 25c f in = 133hz 8192 point fft os by 16 snr = 96.01db thd = ?108.05db figure 13. fft plot oversa mpling by 16, 10 v range 2.0 060k 50k 40k 30k 20k 10k ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 inl (lsb) code av cc , v drive = 5v f sample = 200ksps t a = 25c internal reference 10v range 08479-013 figure 14. AD7606 typical inl, 10 v range 1.0 060k 50k 40k 30k 20k 10k ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.4 0.2 0.6 0.8 dnl (lsb) code 08479-014 av cc , v drive = 5v f sample = 200ksps t a = 25c internal reference 10v range figure 15. AD7606 typical dnl, 10 v range 2.0 0 65,536 57,344 49,152 40,960 32,768 24,576 16,384 8192 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 inl (lsb) code av cc , v drive = 5v internal reference 5v range f sample = 200ksps t a = 25c 08479-015 figure 16. AD7606 typical inl, 5 v range
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 18 of 36 1.00 0 65,536 57,344 49,152 40,960 32,768 24,576 16,384 8192 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 dnl (lsb) code av cc , v drive = 5v internal reference 5v range f sample = 200ksps t a = 25c 08479-016 figure 17. AD7606 typical dnl, 5 v range 20 15 10 5 0 ?5 ?10 ?15 ?40 ?25 ?10 5 20 35 50 65 80 ?20 nfs error (lsb) temperature (c) 08479-017 200ksps av cc , v drive = 5v external reference 5v range 10v range figure 18. nfs error vs. temperature 20 15 10 5 0 ?5 ?10 ?15 ?40 ?25 ?10 5 20 35 50 65 80 ?20 pfs error (lsb) temperature (c) 08479-118 200ksps av cc , v drive = 5v external reference 5v range 10v range figure 19. pfs error vs. temperature 10 ?40 ?25 ?10 5 20 35 50 65 80 ?10 ?9 ?6 ?4 ?2 0 2 4 6 8 nfs/pfs channel matching (lsb) temperature (c) 08479-018 10v range av cc , v drive = 5v external reference pfs error nfs error figure 20. nfs and pfs error matching 10 8 6 4 2 0 0 120k 100k 80k 60k 40k 20k ?2 pfs/nfs error (%fs) source resistance ( ? ) 08479-019 av cc , v drive = 5v f sample = 200 ksps t a = 25c external reference source resistance is matched on the vxgnd input 10v and 5v range figure 21. pfs and nfs error vs. source resistance 1.0 ?40 ?25 ?10 5 20 35 50 65 80 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 bipolar zero code error (lsb) temperature (c) 08479-023 200ksps av cc , v drive = 5v external reference 5v range 10v range figure 22. bipolar zero code error vs. temperature
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 19 of 36 4 3 2 1 0 ?1 ?2 ?3 ?40 ?25 ?10 5 20 35 50 65 80 ?4 bipolar zero code error matching (lsb) temperature (c) 08479-024 200ksps av cc , v drive = 5v external reference 5v range 10v range figure 23 . bipolar zero code error matching between channels ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 1k 100k 10k ?120 thd (db) input frequency (hz) 08479-021 10v range av cc , v drive = +5v f sample = 200ksps r source matched on vx and vxgnd inputs 105k? 48.7k? 23.7k? 10k? 5k? 1.2k? 100? 51? 0? figure 24 . thd vs . input frequency for various source i mpedan ces , 10 v r ange 1k 100k 10k thd (db) input frequency (hz) 08479-122 5v range av cc , v drive = +5v f sample = 200ksps r source matched on vx and vxgnd inputs 105k? 48.7k? 23.7k? 10k? 5k? 1.2k? 100? 51? 0? ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 figure 25 . thd vs. i nput frequency for various source impedances , 5 v range 98 96 94 92 90 88 86 84 82 10 100k 10k 1k 100 80 snr (db) input frequency (hz) 08479-020 no os os by 2 os by 4 os by 8 os by 16 os by 32 os by 64 av cc , v drive = 5v f sample changes with os rate t a = 25c internal reference 5v range figure 26 . snr vs. input frequency for different oversampling rates , 5 v range 100 98 96 94 92 90 88 86 84 82 10 100k 10k 1k 100 80 snr (db) input frequency (hz) 08479-121 no os os by 2 os by 4 os by 8 os by 16 os by 32 os by 64 av cc , v drive = 5v f sample changes with os rate t a = 25c internal reference 10v range figure 27 . snr vs. input frequency for different oversampling rates , 10 v range ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 0 160 140 120 100 80604020 ?140 channel-to-channel isolation (db) noise frequency (khz) 08479-025 10v range 5v range av cc , v drive = 5v internal reference AD7606 recommended decoupling used f sample = 150ksps t a = 25c interferer on all unselected channels figure 28 . channel -to- channel i solation
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 20 of 36 100 98 96 94 92 90 88 84 86 82 80 dynamic range (db) oversampling ratio 08479-026 10v range 5v range av cc , v drive = 5v t a = 25c internal reference f sample scales with os ratio off os2 os4 os8 os16 os32 os64 figure 29 . dynamic range vs. oversampling rate 2.5010 2.5005 2.5000 2.4995 2.4990 2.4985 ?40 ?25 ?10 5 20 35 50 65 80 2.4980 refout voltage (v) temperature (c) 08479-029 av cc = 4.75v av cc = 5v av cc = 5.25v figure 30 . reference output v oltage vs . temperature for dif ferent supply voltages 8 ?10 ?8 ?6 ?4 ?2 10 86420 ?10 ?8 ?6 ?4 ?2 0 2 4 6 input current (a) input voltage (v) 08479-028 ?40c +25c +85c av cc , v drive = 5v f sample = 200ksps figure 31 . analog input current vs . temperature for various supply v oltages 22 20 18 16 14 12 10 8 av cc supply current (ma) oversampling ratio 08479-027 av cc , v drive = 5v t a = 25c internal reference f sample varies with os rate no os os2 os4 os8 os16 os32 os64 figure 32 . supply current vs. oversampling r ate 140 0 11001000900800700600500400300200100 60 70 80 90 100 110 120 130 power supply rejection ratio (db) av cc noise frequency (khz) 08479-030 av cc , v drive = 5v internal reference AD7606 recommended decoupling used f sample = 200ksps t a = 25c 10v range 5v range figure 33 . psrr
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 21 of 36 terminology integral nonlinearity the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, at ? lsb below the first code transition; and full scale, at ? lsb above the last code transition. differential nonlinearity the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. bipolar zero code error the deviation of the midscale transition (all 1s to all 0s) from the ideal, which is 0 v ? ? lsb. bipolar zero code error match the absolute difference in bipolar zero code error between any two input channels. positive full-scale error the deviation of the actual last code transition from the ideal last code transition (10 v ? 1? lsb (9.99954) and 5 v ? 1? lsb (4.99977)) after bipolar zero code error is adjusted out. the positive full-scale error includes the contribution from the internal reference buffer. positive full-scale error match the absolute difference in positive full-scale error between any two input channels. negative full-scale error the deviation of the first code transition from the ideal first code transition (?10 v + ? lsb (?9.99984) and ?5 v + ? lsb (?4.99992)) after the bipolar zero code error is adjusted out. the negative full-scale error includes the contribution from the internal reference buffer. negative full-scale error match the absolute difference in negative full-scale error between any two input channels. signal-to-(noise + distortion) ratio the measured ratio of signal-to-(noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2, excluding dc). the ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by signal-to- ( noise + distortio n) = (6.02 n + 1.76) db thus, for a 16-bit converter, the signal-to-(noise + distortion) is 98 db. total harmonic distortion (thd) the ratio of the rms sum of the harmonics to the fundamental. for the AD7606/AD7606-6/AD7606-4, it is defined as thd (db) = 20log 1 6 54 32 v vvvvvvvv 2 9 2 8 2 7 22222 ??????? where: v 1 is the rms amplitude of the fundamental. v 2 to v 9 are the rms amplitudes of the second through ninth harmonics. peak harmonic or spurious noise the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is determined by a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. intermodulation distortion terms are those for which neither m nor n is equal to 0. for example, the second-order terms include (fa + fb) and (fa ? fb), and the third-order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the calculation of the intermodulation distortion is per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (db). power supply rejection ratio (psrr) variations in power supply affect the full-scale transition but not the converters linearity. psr is the maximum change in full- scale transition point due to a change in power supply voltage from the nominal value. the psr ratio (psrr) is defined as the ratio of the power in the adc output at full-scale frequency, f, to the power of a 100 mv p-p sine wave applied to the adcs v dd and v ss supplies of frequency f s . psrr (db) = 10 log ( pf / pf s ) where: pf is equal to the power at frequency f in the adc output. pf s is equal to the power at frequency f s coupled onto the av cc supply. channel-to-channel isolation channel-to-channel isolation is a measure of the level of crosstalk between all input channels. it is measured by applying a full-scale sine wave signal, up to 160 khz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 khz sine wave signal applied (see figure 28).
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 22 of 36 theory of operation converter details the AD7606 / AD7606 - 6/AD7606 -4 are data acquisition system s that employ a high speed, low power, charge redistribution , successive approximation analog - to - digital converter (adc) and allow the simultaneous sampling of eight/six/four analog input channels. the analog inputs on the AD7606/AD7606 - 6/AD7606 -4 can accept true bipolar input signals. the range pin is used to select either 10 v or 5 v as the input range. the AD7606 / AD7606 - 6/AD7606 -4 operate from a single 5 v supply. the AD7606 / AD7606 - 6/AD7606 -4 contain input clamp protection, in put signal scaling amplifiers, a second - order anti - aliasing filter, track - and - hold amplifiers, an on - chip reference, reference buffers, a high s peed adc , a digital filter , and high speed parallel and serial interfaces. sampling on the AD7606 / AD7606 - 6/AD7606 -4 is controlled using the convst sign als. analog input analog input ranges the AD7606/AD7606 - 6/AD7606- 4 can handle true bipolar , single-e nded input voltages. the logic level on the range pin determines the analog input range of all analog input channels. if this pin is tied to a logic high, t he analog input range is 10 v for all channels. if this pin is tied to a logic low, the analog input range is 5 v for all channels. a logic change on this pin has an imme diate effect on the analog input range; however , there is typically a settling time of approximately 80 s , in addition to the normal acquisition time requirement. the r ecommended p ractice is to hardwire the range pin according to the desired input range for the system signals. d uring normal operation, the applied analog input voltage sh ould remain within the analog input range selected via the range pin. a reset pulse must be applied after power up to ensure the analog input channels are configured for the range selected. when in a power - down mode, it is recommended to tie the analog in puts to gnd. p er the analog input clamp protection section , the overvoltage clamp protection is recommended for use in transient overvoltage conditions and should not remain active for extended periods. stressing the analog inputs outside of the conditions mentioned here may degrade the b ipolar z ero c ode error and thd performance of the AD7606/AD7606 - 6/ AD7606 - 4. analog input impedance the analog input impedance o f the AD7606/AD7606 - 6/ AD7606 -4 is 1 m?. this is a fixed input impedance that does not vary with the AD7606 sampling frequency. this high analog input impedance eliminates the need for a driver amplifier in front of the AD7606/AD7606 - 6/AD7606 -4, allowing for direct connection to the sou rce or sensor. w ith the need for a driver amplifier eliminated, bipolar supplies ( which are often a source of noise in a system ) can be removed from the signal chain . analog input clamp protection figure 34 shows the analog input structure of the AD7606 / AD7606 - 6/AD7606 - 4. each analog input of the AD7606/ AD7606 - 6/AD7606 -4 contains clamp protection circuitry. despite single 5 v supply operation , this analog input clamp protection allows for an input over voltage of up to 16.5 v. 1m? clamp vx 1m? clamp vxgnd second- order lpf r fb r fb 08479-032 figure 34 . analog input circuitry figure 35 shows the voltage vs . current characteristic of the clamp circuit. for input voltages of up to 16.5 v, no curre nt flows in the clamp circuit. for input voltages that are above 16.5 v, the AD7606 / AD7606 - 6/AD7606 - 4 clamp circuitry turn s on. 30 ?50 ?40 ?30 ?20 ?10 0 10 20 ?20 ?15 ?10 ?5 0 5 10 15 20 input clamp current (ma) source voltage (v) 08479-033 av cc , v drive = 5v t a = 25c figure 35 . input protection clamp p rofile a series resisto r should be placed on the analog input channels to limit the current to 10 ma for input voltages above 16.5 v. in an application where there is a series resistance on an analog input channel, vx, a corresponding resistance is required on the analog input gnd channel , vxgnd (see figure 36 ). if t here i s no corresponding resisto r on the vxgnd channel, a n offset error occurs on that channel. it is recommended that the input over voltage clamp protection circuitry be used to protect the AD7606/ad760 6- 6/AD7606 - 4 against transient o vervoltage events. it is no t recommended to leave the AD7606/AD7606 -6/ AD7606 - 4 in a condition where the clamp protection circuitry is active in normal or power - down conditions for extended periods because this may degrade the b ipolar zero c ode error performance of the AD7606/AD7606 - 6/AD7606 -4.
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 23 of 36 1m ? clamp vx 1m ? clamp vxgnd r fb r fb c r r a nalog input signal AD7606 0 8479-034 figure 36. input resistance matching on the analog input of the AD7606/AD7606-6/AD7606-4 analog input antialiasing filter an analog antialiasing filter (a second-order butterworth) is also provided on the AD7606/AD7606-6/AD7606-4. figure 37 and figure 38 show the frequency and phase response, respectively, of the analog antialiasing filter. in the 5 v range, the ?3 db frequency is typically 15 khz. in the 10 v range, the ?3 db frequency is typically 23 khz. 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 100 1k 10k 100k attenuation (db) input frequency (hz) 08479-035 10v range 5v range av cc , v drive = 5v f sample = 200ksps t a = 25c 10v range 0.1db 3db ?40 10,303 24,365hz +25 9619 23,389hz +85 9326 22,607hz 5v range 0.1db 3db ?40 5225 16,162hz +25 5225 15,478hz +85 4932 14,990hz figure 37. analog antialiasing filter frequency response 18 16 14 12 10 8 6 4 2 0 ?2 ?4 ?6 10 100k 10k 1k ?8 phase delay (s) input frequency (hz) 08479-036 av cc , v drive = 5v f sample = 200ksps t a = 25c 5v range 10v range figure 38. analog antialias filter phase response track-and-hold amplifiers the track-and-hold amplifiers on the AD7606/AD7606-6/ AD7606-4 allow the adc to accurately acquire an input sine wave of full-scale amplitude to 16-bit resolution. the track-and-hold amplifiers sample their respective inputs simultaneously on the rising edge of convst x. the aperture time for the track-and- hold (that is, the delay time between the external convst x signal and the track-and-hold actually going into hold) is well matched, by design, across all eight track-and-holds on one device and from device to device. this matching allows more than one AD7606/AD7606-6/AD7606-4 device to be sampled simultaneously in a system. the end of the conversion process across all eight channels is indicated by the falling edge of busy; and it is at this point that the track-and-holds return to track mode, and the acquisition time for the next set of conversions begins. the conversion clock for the part is internally generated, and the conversion time for all channels is 4 s on the AD7606, 3 s on the AD7606-6, and 2 s on the AD7606-4. on the AD7606, the busy signal returns low after all eight conversions to indicate the end of the conversion process. on the falling edge of busy, the track-and-hold amplifiers return to track mode. new data can be read from the output register via the parallel, parallel byte, or serial interface after busy goes low; or, alternatively, data from the previous conversi on can be read while busy is high. reading data from the AD7606/AD7606-6/AD7606-4 while a conversion is in progress has little effect on performance and allows a faster throughput to be achieved. in parallel mode at v drive > 3.3 v, the snr is reduced by ~1.5 db when reading during a conversion. adc transfer function the output coding of the AD7606/AD7606-6/AD7606-4 is twos complement. the designed code transitions occur midway between successive integer lsb values, that is, 1/2 lsb and 3/2 lsb. the lsb size is fsr/65,536 for the AD7606. the ideal transfer characteristic for the AD7606/AD7606-6/AD7606-4 is shown in figure 39. 011...111 011...110 000...001 000...000 111...111 100...010 100...001 100...000 ?fs + 1/2lsb 0v ? 1/2lsb +fs ? 3/2lsb adc code analog input +fs midscale ?fs lsb 10v range +10v 0v ?10v 305v 5v range +5v 0v ?5v 152v +fs ? (?fs) 2 16 lsb = vin 5v ref 2.5v 5v code = 32,768 v in 10v ref 2.5v 10v code = 32,768 08479-037 figure 39. AD7606/AD7606-6/AD7606-4 transfer characteristics the lsb size is dependent on the analog input range selected.
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 24 of 36 internal/e xternal reference the AD7606/AD7606 - 6/AD7606 -4 contain an on - chip 2.5 v band gap reference . the refin/refout pin allows access to the 2.5 v reference that generates the on - chip 4.5 v reference internally, or it allows an external reference of 2.5 v to be applied to the ad76 06/ AD7606 - 6/AD7606 -4 . an externally applied reference of 2.5 v is also g ained up to 4.5 v, usin g the internal buffer. this 4.5 v buffered reference is the reference used by the sar adc. the ref select pin is a logic input pin that allows the user to select between the in ternal referenc e and an external reference. if this pin is set to logic high , the intern al reference is selected and enabled. i f th is pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the refin/refout pin. the internal reference buffer is always ena bled. after a reset , the ad76 06/ AD7606 - 6/AD7606 -4 operate in the reference mode selected by the ref select pin . decoupling is required on the refin/ref out pin for both the internal and external reference options. a 10 f ceramic capacitor is required on th e refin/refout pin. the AD7606 / AD7606 - 6/AD7606 - 4 contain a reference buffer configured to gain the ref voltage up to ~4.5 v, as shown in figure 40 . the refcapa and refcapb pins must be shorted together externally , and a ceramic c apacitor of 10 f applied to refgnd , to ensure that th e reference buffer is in closed - loop operation. the reference voltage available at the refin/refout pin is 2.5 v. when the AD7606/AD7606 - 6/AD7606 - 4 are configured in external reference mode , the refin/ refout pin is a high input impedance pin. for applications using multiple AD7606 devices , the following configurations are recommended, depending on the application requirements. external reference m ode one adr421 external reference can be used to drive th e refin/re fout pins of all AD7606 devices ( see figure 41 ). in this configuration , each refin/refout pin of the AD7606/AD7606 - 6/AD7606 - 4 should be decoupled with a t least a 100 nf decoupling capacitor. internal r eference m ode one AD7606/AD7606 - 6/AD7606 - 4 device, configured to operate in the internal reference mode, can be used to drive the remaining AD7606/AD7606 - 6/AD7606 - 4 devices , which are configured to oper ate in external reference mode ( see figure 42 ). the refin/ refout pin of the AD7606/AD7606 - 6/AD7606- 4, configured in internal reference mode, should be decoupled using a 10 f ceramic decoupling capacitor. the other AD7606 / AD7606 - 6/ AD7606 - 4 devices, configured in external reference mode, should use a t least a 100 nf decoupling capacitor on their refin/refout pins. buf sar 2.5v ref refcapa refin/refout refcapb 10f 08479-038 figure 40 . reference circuitry AD7606 ref select refin/refout AD7606 ref select refin/refout 100nf 0.1f 100nf AD7606 ref select refin/refout 100nf adr421 08479-040 figure 41 . single external reference driving multiple AD7606/AD7606 - 6/ AD7606 -4 refin pins AD7606 ref select refin/refout + 10f AD7606 ref select refin/refout 100nf AD7606 ref select refin/refout 100nf v drive 08479-039 figure 42 . internal reference driving multiple AD7606/AD7606 - 6/AD7606 -4 refin p ins
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 25 of 36 typical connection d iagram figure 43 shows the typical connection diagram for the AD7606/ AD7606 - 6/AD7606 - 4. there are four av cc supply pins on the part , and each of the four pin s should be decoupled using a 100 nf cap acitor at each supply pin and a 10 f capacitor at the supply source. the AD7606/ AD7606 - 6/AD7606 -4 can operate with the internal reference or an externally applied re ference. in this configuration, the AD7606 is configured to operate with the in ternal reference. when using a single AD7606/AD7606 - 6/ AD7606 - 4 device on the board , the refin/refout pin should be decoupled with a 10 f capacitor . r efer to the internal/external reference section w hen using an application with multiple AD7606/ AD7606 - 6/AD7606 - 4 devices . t he refcap a and refcapb pins are shorted together and decoupled with a 10 f ceramic capacitor. the v drive supply is connected to the same supply as the processor. the v drive voltage controls the voltage va lue of the output logic signals. for layout, decoupling , and grounding hints , see the layout guidelines section. after supplies are applied to the AD7606/ad76 06- 6/AD7606 -4, a reset should be applied to the AD7606/AD7606 - 6/AD7606 -4 to ensure that it is configured for the correct mode of operation. power - down modes t wo power - down modes are available on the AD7606/ AD7606 - 6/ AD7606 - 4: standby mode and shutdown mod e. the stby pin controls whether the AD7606/AD7606 - 6/AD7606 - 4 are in normal mode or in one of the two power - down modes. the power - down mode is selected through the state of the range pin when the stby pin is low. table 7 s hows the configurations required to choo se the desired power - down mode. when the AD7606 / AD7606 - 6/AD7606 - 4 are placed in standby mode, the current consumption is 8 ma maximum and power - up t ime is approximately 100 s because the capacitor on the refcapa and r efcapb pins must charge up. in s tandby mode , the on - chip reference and regulators remain powered up , and the amplifiers and adc core are powered down. when the AD7606/ AD7606 - 6/AD7606 - 4 are placed in s hutdown mode , the curren t cons umption is 6 a max imum and power - up time is approximately 13 ms (external reference mode) . in s hut - down mode , all circuitry is powered down. when the AD7606/ AD7606 - 6/AD7606 - 4 are powered up from shutdown mode, a reset signal must be applied to the AD7606/AD7606 -6/ ad 7606- 4 after the required power - up time has elapsed. table 7. power -d own mode selection power - down m ode stby range standby 0 1 shutdown 0 0 av cc agnd v drive + refin/refout db0 to db15 convst a, convst b cs rd busy reset AD7606 1f 10f 100nf digital supply voltage +2.3v to +5.25v analog supply voltage 5v 1 eight analog inputs v1 to v8 parallel interface 1 decoupling shown on the av cc pin applies to each av cc pin (pin 1, pin 37, pin 38, pin 48). decoupling capacitor can be shared between av cc pin 37 and pin 38. 2 decoupling shown on the regcap pin applies to each regcap pin (pin 36, pin 39). regcap 2 + 10f refcapa refcapb os 2 os 1 os 0 oversampling 100nf v1 par/ser sel stby ref select range v2 v3 v4 v5 v6 v7 v8 refgnd v1gnd v2gnd v3gnd v4gnd v5gnd v6gnd v7gnd v8gnd v drive v drive 08479-041 microprocessor/ microconverter/ dsp figure 43 . AD7606 typic al connection diagram
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 26 of 36 conversion control simultaneous sampling on all analog input channels the ad76 06 /AD7606 - 6/AD7606 - 4 allow simultaneous sampling of all analog input channels. all channels are sampled simul - taneously when both convst pins (convst a, c onvst b) are tied together. a single convst signal is used to control both convst x inputs. the rising edge of this common convst signal initiates simultaneous sampling on all analog input channels (v1 to v8 for the AD7606, v1 to v6 for the AD7606 - 6, and v 1 to v4 for the AD7606 - 4). the AD7606 contains an on - chip oscillator that is used to perform the conversions. the conversion time for all adc channels is t conv . the busy signal indicates to the user when conversions are in progress, so when the rising edge of convst is applied, busy goes logic high and transitions low at the end of the entire conversion process. the falling edge of the busy signal is used to place all eight track - and - hold amplifiers back into track mode. the falling edge of busy also indica tes that the new data can now be read from the parallel bus (db[15:0]), the d out a and d out b serial data lines, or the parallel byte bus, db[7:0]. simultaneously sampling two sets of c hannels the ad760 6 /AD7606 - 6/AD7606 - 4 also allow the analog input channels to be sampled simultaneously in two sets. this can be used in power -l ine protection and measurement systems to compensate for phase difference s introduced by pt and ct transform ers. in a 50 hz system , this allows for up to 9 of phase compensation ; and in a 60 hz system , it allows for up to 10 of phase compensation. this is accomplished by pulsing the two convst pins independently and is possible only if oversampling is not in use. convst a is used to initiate simultaneous sampling of the first set of ch annels (v1 to v 4 for the AD7606, v1 to v3 for the AD7606 -6, and v1 and v2 for the AD7606 - 4) ; and convst b is used to initiate simultaneous sampling on the seco nd set of analog input channels (v 5 to v 8 for the AD7606, v4 to v6 for the AD7606 -6, and v3 and v 4 for the AD7606 - 4) , as illustrated in figure 44. on the rising edge of convst a , the track - and - hold amplifiers for the first set of channels are placed into hold mode . on the rising edge of convst b , the track - and - hold amplifiers for the second set of channels are placed into hold mode . the conversion process b egins once both rising edges of convst x have occurred; therefore busy go es high on the rising edge of the later convst x signal. in table 3 , time t 5 indicates the maximum allowable time be tween convst x sampling points. there is no change to the data read process when using two separate convst x signals. connect all unused analog input channel s to agnd. the results for any unused channels are still included in the data read because all channels are always converted. convst a convst b busy cs/rd data: db[15:0] frstdata v1 v2 v3 v7 v8 t 5 t conv v1 to v4 track-and-hold enter hold v5 to v8 track-and-hold enter hold AD7606 converts on all 8 channels 08479-042 figure 44 . AD7606 simultaneous sampling on channel sets while using i ndependent convst a and convst b signals parallel m ode
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 27 of 36 digital interface the ad76 06/ AD7606 - 6/AD7606 - 4 provide three interface options: a parallel interface , a high speed serial interface , and a parallel byte interface . the required interface mode is selected via the pa r /ser /byte sel and db15 /byte sel pin s. table 8 . interface mode s election par /ser /byte sel db15 interface mode 0 0 parallel interfac e mode 1 0 serial interface mode 1 1 parallel byte interface mode o peration of the interface modes is discussed in the following se ctions. parallel interface ( par /ser/byte sel = 0) data can be read from the ad76 06/ AD7606 - 6/AD7606 - 4 via the parallel data bus with standard cs and rd signals. to read the data over the parallel bus, th e pa r /ser/byte sel pin should be tied low. the cs and rd input signals are internally gated to enable the conversion result onto the data bus. the data lines , db15 to db0 , leave their high impedance state when both cs and rd are logic low. AD7606 14 busy 12 rd/sclk [33:24] [22:16] db[15:0] 13 cs digital host interrupt 08479-043 figure 45 . AD7606 interface diagram one AD7606 using the parallel bus, with cs and rd shorted together the rising edge of the cs input signal three - states the bus , and the falling edge of the cs input signal takes the bus out of the high impedance state. cs is the control sig nal that enables the data lines; it is the fu nction that allows multiple AD7606 / AD7606 - 6/ AD7606 - 4 devices to share the same parallel data bus. the cs signal can be permanently tied low, and the rd signal can be used to access the conversion results as shown in figure 4 . a read operation of new data can take place after the busy signal goes low ( see figure 2 ); or , alternatively , a read operation of data from the previous conversion process can take place while busy is high ( see figure 3 ). the rd pin is used to read data from the output conversion results register. applying a sequence of rd pulses to the rd pin of the AD7606 / AD7606 - 6/AD7606 - 4 clocks the conversion results out from each channel onto the parallel b us db[15:0] in ascending order. the first rd falling edge after busy goes low clocks out the conversion result from c hannel v1 . t he next rd falling edge updates the bus with the v2 conversion result , and so on. on the AD7606, the eighth falling edge of rd clocks out the conversion result for c hannel v8. when the rd signal is logic low, it enables the data c onversion result from each channel to be transferred to the digital host (dsp, fpga). when there is only one AD7606/ AD7606 - 6/AD7606 - 4 in a system/ board and it does not share the parallel bus, data can be read using just one control signal from the digital host. the cs and rd signals can be tied together , as shown in figure 5 . in this case , the data bus comes out of three - state on the falling edge of cs / rd . th e combined cs and rd signal allows the data to be clocked out of the AD7606 / AD7606 - 6/AD7606 - 4 and to be read by the digital host. in this case , cs is used to frame the data transfer of each data channel . parallel byte ( par /ser/byte sel = 1, db15 = 1) parallel byte interface mode operates much like the parallel interface mode, except that each channel conversion result is read out in two 8 - bit transfers. therefore, 16 rd pulses are required to read all eight conversion results from the AD7606. for the AD7606 - 6, 12 rd pulses are required; and on the AD7606 -4, eight rd pulses are required to read all the channel results. to configure the AD7606/ad76706 - 6/AD7606 - 4 to operate in parallel byte mode, the pa r /ser/byte sel and byte sel/ db15 pins should be tied to logic high (see table 8 ). in parallel byte mode, db[7:0] are used to transfer the data to the digital host. db0 is the lsb of the data transfer, and db7 is the msb of the data transfer. in parallel byte mode, db14 acts as an hben pin. when db14/hben is tied to logic high, the most significant byte (msb) of the conversion result is output fi rst, followed by the lsb of the conversion result. when db14 is tied to logic low, the lsb of the conversion result is output first, followed by the msb of the conversion result. the frstdata pin remains high until the entire 16 bits of the conversion resu lt from v1 are read from the AD7606 / AD7606 - 6/AD7606 -4. serial inte rface ( par /ser /byte sel = 1) to read data back from the ad76 06 over the serial interface, the pa r /ser/byte sel pin must be tied high. the cs and sclk signals are used to transfer data from the AD7606. the AD7606 / AD7606 - 6/AD7606 - 4 have two serial data output pins, d out a and d out b. data can be read back from the AD7606/ad76706 - 6/AD7606 - 4 using one or both of these d out lines. for the ad760 6, conversion results from channel v1 to channel v4 first appear on d out a, and conversion results from channel v5 to channel v8 first appear on d out b. for the AD7606 -6, conversion results from channel v1 to channel v3 first appear on d out a , and conversion results from channel v4 to channel v6 first appear on d out b. for the AD7606 - 4, conversion results from channel v1 and channel v2 first appear on d out a , and conversion results from channels v3 and channel v4 first appear on d out b.
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 28 of 36 the cs falling edge takes the data output lines, d out a and d out b, out of three-state and clocks out the msb of the conversion result. the rising edge of sclk clocks all subsequent data bits onto the serial data outputs, d out a and d out b. the cs input can be held low for the entire serial read operation, or it can be pulsed to frame each channel read of 16 sclk cycles. figure 46 shows a read of eight simultaneous conversion results using two d out lines on the AD7606. in this ca se, a 64 sclk transfer is used to access data from the AD7606, and cs is held low to frame the entire 64 sclk cycles. data can also be clocked out using just one d out line, in which case it is recommended that d out a be used to access all conversion data because the channel data is output in ascending order. for the AD7606 to access all eight conversion results on one d out line, a total of 128 sclk cycles is required. these 128 sclk cycles can be framed by one cs signal, or each group of 16 sclk cycles can be individually framed by the cs signal. the disadvantage of using just one d out line is that the throughput rate is reduced if reading occurs after conversion. the unused d out line should be left unconnected in serial mode. for the AD7606, if d out b is to be used as a single d out line, the channel results are output in the following order: v5, v6, v7, v8, v1, v2, v3, and v4; however, the frstdata indicator returns low after v5 is read on d out b. for the AD7606-6 and the AD7606-4, if d out b is to be used as a single d out line, the channel results are output in the following order: v4, v5, v6, v1, v2, and v3 for the AD7606-6; and v3, v4, v1, and v2 for the AD7606-4. figure 6 shows the timing diagram for reading one channel of data, framed by the cs signal, from the AD7606/AD7606-6/ AD7606-4 in serial mode. the sclk input signal provides the clock source for the serial read operation. the cs goes low to access the data from the AD7606/AD7606-6/AD7606-4. the falling edge of cs takes the bus out of three-state and clocks out the msb of the 16-bit conversion result. this msb is valid on the first falling edge of the sclk after the cs falling edge. the subsequent 15 data bits are clocked out of the AD7606/ AD7606-6/ad 7606-4 on the sclk rising edge. data is valid on the sclk falling edge. to access each conversion result, 16 clock cycles must be provided to the AD7606/ad 7606-6/AD7606-4. the frstdata output signal indicates when the first channel, v1, is being read back. when the cs input is high, the frstdata output pin is in three-state. in serial mode, the falling edge of cs takes frstdata out of three-state and sets the frstdata pin high, indicating that the result from v1 is available on the d out a output data line. the frstdata output returns to a logic low following the 16 th sclk falling edge. if all channels are read on d out b, the frstdata output does not go high when v1 is being output on this serial data output pin. it goes high only when v1 is available on d out a (and this is when v5 is available on d out b for the AD7606). reading during conversion data can be read from the AD7606/AD7606-6/AD7606-4 while busy is high and the conversions are in progress. this has little effect on the performance of the converter, and it allows a faster throughput rate to be achieved. a parallel, parallel byte, or serial read can be performed during conversions and when oversampling may or may not be in use. figure 3 shows the timing diagram for reading while busy is high in parallel or serial mode. reading during conversions allows the full throughput rate to be achieved when using the serial interface with v drive above 4.75 v. data can be read from the AD7606 at any time other than on the falling edge of busy because this is when the output data registers are updated with the new conversion data. time t 6 , as outlined in table 3, should be observed in this condition. v1 v4 v2 v3 v5 v8 v6 v7 sclk d out a d out b cs 64 08479-044 figure 46. AD7606 serial interface with two d out lines
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 29 of 36 digital f ilter the AD7606/ad760 6- 6/AD7606 - 4 contain an optional digital first - order sinc fi lter that should be used in applications where slower throughput rates are used or where higher signal - to - noise ratio or dynam ic range is desirable. the over sampling ratio of the digital filter is con trolled using the oversampling pins , os [2:0] ( see table 9 ). os 2 is the msb control bit , and os 0 is the lsb control bit. table 9 provides th e over sampling bit decodi ng to select the different over sample rates. the os pins are latched on the falling edge of busy. this set s the over sampli ng rate for the next conversion ( see figure 48) . in a ddition to the over sampling function, the output result is decimated to 16 - bit resolution. if the os pins are set to select an os ratio of eight , the next convst x rising edge takes the first sample for each channel , and the remaining seven samples for all channels are taken with an internally generated sampling signal. these samples are then averaged to yield an improvement in snr performance. table 9 shows typical snr performance for both the 10 v and the 5 v range. as table 9 shows, there is an improvement in snr as the os ratio increases. as the os ratio increases, the 3 db frequency is reduced , and the allowed sampling frequency is also reduced. in an application where the required sampling frequency is 10 ksps, an os ratio of up to 16 can be used. in this case, the application sees an improvement in snr , but the input 3 db bandwidth is limited to ~ 6 k hz. the convst a and convst b pins must be tied/driven together when oversampling i s turned on. when the over - sampling function is turned on, the busy high time for the conversion process extends. the actual busy high time depends on the ove r sampling rate that is selected: the higher the oversampling rate, the longer the busy high, or total conversion time (see table 3 ). 08479-046 cs rd data: db[15:0] busy convst a and convst b t cycle t conv 4s t 4 t 4 t 4 9s 19s os = 0 os = 2 os = 4 figure 47 . AD7606 no oversampling, oversampling 2 , and oversamplin g 4 while using read after c onversion figure 47 shows that the conversion time extends as the over - sampling rate is increased, and the busy signal lengthens for the different oversampling rates. for example, a sampling frequenc y of 10 ksps yields a cycle time of 100 s. figure 47 shows os 2 and os 4 ; for a 10 ksps example, there is adequate cycle time to further increase the oversampling rate and yield greater improve - ments in snr performance . in an application where the initial sampling or throughput rate is at 200 ksps, for example, and oversampling is turned on, the throughput rate must be reduced to accommodate the longer conversion time and to allow for the read. to achieve the fastest through put rate possible when over - sampling is turned on, the read can be performed during the busy high time. the falling edge of busy is used to update the output data registers with the new conversion data ; therefore, the reading of conversion data should not occur on this edge. convst a and convst b busy os x t os_setup t os_hold conversion n conversion n + 1 oversample rate latched for conversion n + 1 08479-045 figure 48 . os x pin t iming table 9. overs ample bit decoding os [2:0] os ratio snr 5 v r ange ( db ) snr 10 v r ange ( db ) 3 db bw 5 v r ange (k hz ) 3 db bw 10 v r ange (k hz ) max imum throughpu t convst f requency (khz) 000 no os 89 90 15 22 200 001 2 91.2 92 15 22 100 010 4 92.6 93.6 13.7 18.5 50 011 8 94.2 95 10.3 11.9 25 100 16 95.5 96 6 6 12.5 101 32 96.4 96.7 3 3 6.25 110 64 96.9 97 1.5 1.5 3.125 111 invalid
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 30 of 36 figure 49 to figure 55 illustrate the effect of oversampling on the code spread in a dc histogram plot. as the oversample rate is increased, the spread of the codes is reduced. 1000 0 100 200 300 400 500 600 700 800 900 number of occurences code (lsb) ?3 ?2 ?1 0 1 928 887 3 0 3 2 2 131 97 08479-047 no oversampling f sample = 200ksps av cc = 5v v drive = 2.5v figure 49 . hi stogram of codes no os (six codes) 1400 0 200 400 600 1000 1200 800 number of occurences code (lsb) ?3 ?2 ?1 0 1 3 0 0 0 2 16 08479-048 oversampling by 2 f sample = 100ksps av cc = 5v v drive = 2.5v 80 804 1148 figure 50 . histogram of codes os 2 ( four code s) 1400 0 200 400 600 1000 1200 800 number of occurences code (lsb) ?3 ?2 ?1 0 1 3 0 0 0 2 3 08479-049 oversampling by 4 f sample = 50ksps av cc = 5v v drive = 2.5v 19 764 1262 figure 51 . histogram of codes os 4 ( four c odes) 1400 0 200 400 600 1000 1200 800 number of occurences code (lsb) ?3 ?2 ?1 0 1 3 0 0 0 2 0 08479-050 oversampling by 8 f sample = 25ksps av cc = 5v v drive = 2.5v 2 783 1263 figure 52 . histogram of codes os 8 (t hree codes) 1400 0 200 400 600 1000 1200 800 number of occurences code (lsb) ?3 ?2 ?1 0 1 3 0 0 0 2 0 08479-151 oversampling by 16 f sample = 12.5ksps av cc = 5v v drive = 2.5v 0 595 1453 figure 53 . histogram of codes os 16 (t wo codes) 1600 1400 0 200 400 600 1000 1200 800 number of occurences code (lsb) ?3 ?2 ?1 0 1 3 0 0 0 2 0 08479-152 oversampling by 32 f sample = 6.125ksps av cc = 5v v drive = 2.5v 0 631 1417 figure 54 . histogram of codes os 32 (two codes) 1600 1400 0 200 400 600 1000 1200 800 number of occurences code (lsb) ?3 ?2 ?1 0 1 3 0 0 0 2 0 08479-153 oversampling by 64 f sample = 3ksps av cc = 5v v drive = 2.5v 0 1679 369 figure 55 . histogram of codes os 64 (two codes)
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 31 of 36 when the oversampling mode is selected for the AD7606/ AD7606 - 6/AD7606 - 4, it has the effect of adding a digital filter function after the adc. the different oversampling rates and the convst sampling frequency produce different digital filter frequency profiles. figure 56 to figure 61 show the digital filter frequency profiles for the different over sampling rates . the combination of the analog antialias ing filter and the oversampling digital filter can be used to eli minate and reduce the complexity of the design of any filter before the AD7606/AD7606 - 6/AD7606 - 4. the digital filtering combines steep roll - off and linear phase response. 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?90 attenuation (db) frequency (hz) 08479-051 av cc = 5v v drive = 5v t a = 25c 10v range os by 2 figure 56 . digital filter r esponse for os 2 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) 08479-052 av cc = 5v v drive = 5v t a = 25c 10v range os by 4 figure 57 . digital filter response for os 4 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) 08479-053 av cc = 5v v drive = 5v t a = 25c 10v range os by 8 figure 58 . digital filter response for os 8 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) 08479-154 av cc = 5v v drive = 5v t a = 25c 10v range os by 16 figure 59 . digital filter r esponse for os 16 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) 08479-155 av cc = 5v v drive = 5v t a = 25c 10v range os by 32 figure 60 . digital filter r e sponse for os 32 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 100 1k 10k 100k 10m 1m ?100 ?90 attenuation (db) frequency (hz) 08479-156 av cc = 5v v drive = 5v t a = 25c 10v range os by 64 figure 61 . digital filter response for os 64
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 32 of 36 layout g uidelines the printed circuit board that houses the ad76 06 /ad760 6- 6/ AD7606 - 4 should be designed so that the analog and digital sections are separated and conf ined t o different areas of the board. at least one ground plane should be used. it can be common or split between the digital and analog sections. in the case of the split plane, the digital and analog ground planes should be joined in only one place , pref erably as close as possible to the AD7606 /AD7606 - 6/AD7606 -4 . if the ad76 06/AD7606 - 6/AD7606 - 4 are in a system where multiple devices require analog - to - digital ground connections, the connection should still be made at only one p oint: a star ground point th at should be established as close as possible to the ad76 06 /AD7606- 6/AD7606 -4 . good connections should be made to the ground plane. avoid sharing one connecti on for multiple ground pins. use individual vias or multiple vias to the ground plane for each gro und pin. avoid running digital lines under the devices because doing so couples noise onto the die. the analog ground plane should be allowed to run under the AD7606 /AD7606 - 6/AD7606 -4 to avoid noise coupling. fast switching signals like convst a, convst b, or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. avoid c rossover of digital and analog signals. traces on layers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board. the power supply lines to the av cc and v drive pins o n the AD7606/AD7606 - 6/AD7606 - 4 should use as large a trace as possible to provide low impedance paths and re duce the effect of glitches on the power supply lines. where possible , use supply planes and make good connections betwee n the AD7606 supply pins an d the power tracks on the board . u se a single via or multiple vias for each supply pin. good decoupling is a lso important to lower the supply impedance presented t o the AD7606/AD7606 - 6/AD7606 - 4 and to reduce the magnitude of the supply spikes. the decoupling capaci tors should be placed close to ( ideally, righ t up against) these pins and their corresponding groun d pins. place t he decoupling capacitors for the refin/refout pin and the refcapa an d refcapb pins as close as possible to their respe ctive AD7606/ AD7606 - 6/AD7606 - 4 pins ; and , where possible , they should be placed o n the same side of the board as the ad760 6 device. figure 62 shows the recommended decoupling on the top layer of the AD7606 board. figure 63 shows bottom layer decoupling, which is used for the four av cc pins and the v drive pin decoupling . w here the ceramic 100 nf caps for the av cc pins are placed close to their respective device pins , a single 100 nf capa citor can be shared between pin 37 and pin 38. 08479-054 figure 62 . top layer decoupling refin/refout, refcapa, refcapb , and regcap p ins 08479-055 figure 63 . bottom layer d ecoupling
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 33 of 36 to ensure good device - to - device performance matching i n a system that contains multiple AD7606/ AD7606 - 6/AD7606 -4 devices, a symmetrical layout between the AD7606 / ad7 606- 6/ AD7606 - 4 devices is important. figure 64 shows a layout wi th two AD7606/AD7606 - 6/AD7606 -4 devices. the av cc supply plane runs to the right of both devices , and t he v drive supply track runs to the left of the two devices. t he reference chip is positioned between the two devices , and the referen ce voltage track runs north to pin 42 of u1 and south to pin 42 of u2. a solid ground plane is used. these symmetrical layout principles can also b e applied to a s ystem that contains more than two AD7606/ AD7606 - 6/ AD7606 - 4 devices. the AD7606/ AD7606 - 6/ AD7606 - 4 dev ices can be placed in a north -s outh direction , with the reference voltage located midway between the devices and the refer ence track running in the north - south direction , simil ar to figure 64 . avcc u2 u1 avcc u2 u1 08479-056 figure 64 . layout for multiple AD7606 devices top layer and supply plane layer
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 34 of 36 outline dimensions compliant t o jedec s t andards ms-026-bcd 051706- a top view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 1 1.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 0.15 0.05 7 3.5 0 figure 65 . 64 - lead low profile quad flat package [l qfp] (st - 64 - 2) dimensions shown in millimetres ordering guide model 1 , 2 , 3 temperature range package description package option AD7606bstz ?40c to +85c 64- lead low profile quad flat package [lqfp] st- 64 -2 AD7606bstz - rl ?40c to +85c 64- lead low profi le quad flat package [lqfp] st- 64 -2 AD7606bstz -6 ?40c to +85c 64- lead low profile quad flat package [lqfp] st- 64 -2 AD7606bstz - 6rl ?40c to +85c 64- lead low profile quad flat package [lqfp] st- 64 -2 AD7606bstz -4 ?40c to +85c 64- lead low profile quad flat package [lqfp] st- 64 -2 AD7606bstz - 4rl ?40c to +85c 64- lead low profile quad flat package [lqfp] st- 64 -2 eval - AD7606edz evaluation board for the AD7606 eval - AD7606- 6edz evaluation board for the AD7606 -6 eval - AD7606- 4edz evaluation board for the AD7606 -4 ced1z converter evaluation development 1 z = rohs compliant part. 2 the eval - AD7606edz, eval - AD7606 - 6edz, and eval - AD7606 - 4edz can be used as standalone evaluation boards or in conjunction with the ced1z for evaluation/demonstration purposes. 3 the ced1z allows the pc to control and communicate with all analog devices, inc., evaluation boards ending in the edz designator.
data sheet AD7606/AD7606-6/AD7606-4 rev. c | page 35 of 36 notes
AD7606/AD7606-6/AD7606-4 data sheet rev. c | page 36 of 36 notes ? 2010 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d08479 -0- 1/12(c)

▲Up To Search▲

Price & Availability of AD7606

	To Download AD7606 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .