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data sheet ics854s1208ayi revision a april 27, 2012 1 ?2012 integrated device technology, inc. differential-to-lvds fanout buffer w/divider and glitchless switch ICS854S1208I general description t he ICS854S1208I is a low skew, 8 output lvds fanout buffer with selectable divider. the ICS854S1208I has 2 selectable inputs that accept a variety of differential input types. the device provides the capability to suppress any glitch at the outputs of the device during an input clock switch to enhance clock redundancy in fault tolerant applications. the divide select inputs, div_sela and div_selb, control the output frequency of each bank. the output banks can be independently selected for 1 or 2 operation. the output enable pins assigned to each output, support enabling and disabling each output individually. the ICS854S1208I is characterize d at full 3.3v or 2.5v output operating supply modes. guaranteed output and part-to-part skew characteristics make the ICS854S1208I ideal for high performance applications. supply mode operation table features ? eight differential lvds output pairs each output has individual synchronous output enable ? two selectable differential clkx, nclkx input pairs ? clkx, nclkx pairs can accept the following differential input levels: lvpecl, lvds, hcsl ? maximum output frequency: 1.5ghz ? independent bank control for 1 or 2 operation ? glitchless output behavior during input switch ? output skew: 40ps (maximum) ? bank skew: 35ps (maximum) ? full 3.3v or 2.5v supply mode ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package pin assignment ICS854S1208I 48-pin tqfp, e-pad 7mm x 7mm x 1mm package body y package top view 3.3v operation 2.5v operation v dd = 3.3v v dd = 2.5v v ta p = float v ta p = 2.5v 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 v dd div_sela v tap clk0 nclk0 gnd clk_sel nclk1 clk1 gnd div_selb v dd v dd oeb0 oeb1 oeb2 oeb3 gnd v dd oea3 oea2 oea1 oea0 v dd gnd qa0 nqa0 qa1 nqa1 v dd v dd nqb1 qb1 nqb0 qb0 gnd qa2 nqa2 qa3 nqa3 v dd v dd nqb3 qb3 nqb2 qb2 gnd gnd 48 47 46 45 44 43 42 41 40 39 38 37
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 2 ?2012 integrated device technology, inc. block diagram 1 2 0 1 0 1 pulldown pulldown pulldown pullup/pulldown pullup/pulldown pulldown qa0 nqa0 div_sela clk0 nclk0 clk1 clk_sel pulldown div_selb nclk1 oea0 qa1 oea1 qa2 oea2 qa3 oea3 pullup pullup nqa1 nqa2 nqa3 pullup pullup 0 1 qb0 nqb0 oeb0 qb1 oeb1 qb2 oea2 qb3 oeb3 pullup pullup nqb1 nqb2 nqb3 pullup pullup v ta p
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 3 ?2012 integrated device technology, inc. function description the ICS854S1208I has a glitch free input mux that is controlled by the clk_sel pin. it is designed to switch between 2 input clocks whether running or not. in the case where both clocks are running, when clk_sel changes , the output clocks go low after one cycle of the output clock (nominally). the outputs then stay low for one cycle of the new input clock (nominally) and then begin to follow the new input clock. this is shown in figure 1a. figure 1a. clk_sel timing diagram another case is where one of the inputs was selected and running but has since stopped (either high or low). if a clk_sel event happens after a clock has stopped, the output change can take effect up to 1s after the input clock stopped. th e output will go low and then follow the second period of the new clock input. figure 1b shows an example of this. figure 1b. clk_sel with bad input timing diagram clk0 clk1 clk_sel output clk0 clk1 clk_sel output 1s
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 4 ?2012 integrated device technology, inc. table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1, 12, 18, 19, 25, 30, 36, 42, 43 v dd power power supply pins. 2 div_sela input pulldown controls frequency division fo r qa[0:3], nqa[0:3] outputs. lvcmos / lvttl interface levels. 3v ta p power power supply mode. see supply mode operation table on page 1. 4 clk0 input pulldown non-inverting differential clock input. 5nclk0input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 6, 10, 13, 24, 31, 37, 48 gnd power power supply ground. 7 clk_sel input pulldown clock select input. when high, selects clk1/nclk1 inputs. when low, selects clk0, nclk0 inputs. lvcmos / lvttl interface levels. 8nclk1input pullup/ pulldown inverting differential clock input. v dd /2 default when left floating. 9 clk1 input pulldown non-inverting differential clock input. 11 div_selb input pulldown controls frequency division for qb[0:3], nqb[0:3] outputs. lvcmos / lvttl interface levels. 14, 15 qa0, nqa0 output differential output pair. lvds interface levels. 16, 17 qa1, nqa1 output differential output pair. lvds interface levels. 20, 21 nqb1, qb1 output differential out put pair. lvds interface levels. 22, 23 nqb0, qb0 output differential out put pair. lvds interface levels. 26 oea0 input pullup output enable for qa0 output pair. lvcmos/lvttl interface levels. see table 3a. 27 oea1 input pullup output enable for qa1 output pair. lvcmos/lvttl interface levels. see table 3a. 28 oea2 input pullup output enable for qa2 output pair. lvcmos/lvttl interface levels. see table 3a. 29 oea3 input pullup output enable for qa3 output pair. lvcmos/lvttl interface levels. see table 3a. 32 oeb3 input pullup output enable for qb3 output pair. lvcmos/lvttl interface levels. see table 3b. 33 oeb2 input pullup output enable for qb2 output pair. lvcmos/lvttl interface levels. see table 3b. 34 oeb1 input pullup output enable for qb1 output pair. lvcmos/lvttl interface levels. see table 3b. 35 oeb0 input pullup output enable for qb0 output pair. lvcmos/lvttl interface levels. see table 3b. 38, 39 qb2, nqb2 output differential output pair. lvds interface levels. 40, 41 qb3, nqb3 output differential output pair. lvds interface levels. 44, 45 nqa3, qa3 output differential out put pair. lvds interface levels. 46, 47 nqa2, qa2 output differential out put pair. lvds interface levels.
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 5 ?2012 integrated device technology, inc. table 2. pin characteristics function tables table 3a. oeax function table table 3c. div_sela function table table 3e. clk_sel function table table 3b. oebx function table table 3d. div_selb function table symbol parameter test conditions minimum typical maximum units c in input capacitance 2pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? inputs outputs oea[0:3] qa[0:3] nqa[0:3] 0 low high 1 (default) active active input frequency division div_sela 0 (default) 1 12 input input selection clk_sel 0 (default) clk0, nclk0 1 clk1, nclk1 inputs outputs oeb[0:3] qb[0:3] nqb[0:3] 0lowhigh 1 (default) active active input frequency division div_selb 0 (default) 1 12
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 6 ?2012 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4b. power supply dc characteristics, v dd = v ta p = 2.5v 5%, t a = -40c to 85c table 4c. lvcmos/lvttl dc characteristics, v dd = 3.3v 5% or v dd = v ta p = 2.5v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 33.1 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v v ta p power supply mode float v i dd power supply current 305 ma symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v v ta p positive supply voltage 2.375 2.5 2.625 v i dd power supply current 290 ma i ta p power supply current 2.2 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v dd = 3.465v 2.2 v dd + 0.3 v v dd = 2.625v 1.7 v dd + 0.3 v v il input low voltage v dd = 3.465v -0.3 0.8 v v dd = 2.625v -0.3 0.7 v i ih input high current div_selx, clk_sel v dd = v in = 3.465v or 2.625v 150 a oea[3:0], oeb[3:0] v dd = v in = 3.465v or 2.625v 10 a i il input low current div_selx, clk_sel v dd = 3.465v or 2.625v, v in = 0v -10 a oea[3:0], oeb[3:0] v dd = 3.465v or 2.625v, v in = 0v -150 a
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 7 ?2012 integrated device technology, inc. table 4d. differential dc characteristics, v dd = 3.3v 5% or v dd = v ta p = 2.5v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . table 4e. lvds dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4f. lvds dc characteristics, v dd = v ta p = 2.5v 5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units i ih input high current clk0, clk1, nclk0, nclk1 v dd = v in = 3.465v or 2.625v 150 a i il input low current clk0, clk1 v dd = 3.465v or 2.625v, v in = 0v -10 a nclk0, nclk1 v dd = 3.465v or 2.625v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.2 1.47 v ? v os v os magnitude change 50 mv symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.15 1.45 v ? v os v os magnitude change 50 mv
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 8 ?2012 integrated device technology, inc. ac electrical characteristics table 5a. ac characteristics, v dd = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input cr ossing point to the differential cross points. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differential cross points. note 3: these parameters are guaranteed by characterization. not tested in production. note 4: defined as skew between outputs on different devices operating a the same supply volt age, same temperature and with equ al load conditions. using the same type of input on each device , the output is measured at the differential cross points. note 5: defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. note 6: these parameters are guaranteed by characterization. not tested in production. table 5b. ac characteristics, v dd = v ta p = 2.5v 5%, t a = -40c to 85c for notes, see table 5a above. symbol parameter test conditio ns minimum typical maximum units f out output frequency 1.5 ghz t pd propagation delay; note 1 0.7 1.75 ns t sk(o) output skew; note 2, 3 40 ps t sk(pp) part-to-part skew; note 3, 4 400 ps t sk(b) bank skew; note 3, 5 35 ps t r / t f output rise/fall time 20% to 80% 55 250 ps odc output duty cycle ? 750mhz 44 56 % t en output enable time; note 6 10 ns t dis output disable time; note 6 10 ns symbol parameter test conditio ns minimum typical maximum units f out output frequency 1.5 ghz t pd propagation delay; note 1 0.6 1.8 ns t sk(o) output skew; note 2, 3 40 ps t sk(pp) part-to-part skew; note 3, 4 400 ps t sk(b) bank skew; note 3, 5 35 ps t r / t f output rise/fall time 20% to 80% 50 275 ps odc output duty cycle ? 750mhz 44 56 % t en output enable time; note 6 10 ns t dis output disable time; note 6 10 ns
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 9 ?2012 integrated device technology, inc. parameter measureme nt information 3.3v lvds output load ac test circuit differential input level part-to-part skew 2.5v lvds output load ac test circuit output skew bank skew scope qx nqx lvds 3.3v5% power supply +? float gnd float v ta p v dd v dd nclk0, nclk1 clk0, clk1 gnd v cmr cross points v pp t sk(pp) part 1 part 2 qx nqx qy nqy scope qx nqx 2.5v5% power supply +? float gnd v dd v ta p t sk(o) qx nqx qy nqy t sk(b) nqxx qxx nqxx qxx where x = bank a or b
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 10 ?2012 integrated device technology, inc. parameter measurement in formation, continued propagation delay output duty cycle/pulse width/period offset voltage setup output rise/fall time differential output voltage setup t pd nqa[0:3], nqb[0:3] qa[0:3], qb[0:3] nclk0, nclk1 clk0, clk1 nqa[0:3], nqb[0:3] qa[0:3], qb[0:3] t pw t period t pw t period odc = x 100% out out lvds dc input ? ? ? v os / ? v os v dd 20% 80% 80% 20% t r t f v od nqa[0:3], nqb[0:3] qa[0:3], qb[0:3] ? ? ? 100 out out lvds dc input v od / ? v od v dd
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 11 ?2012 integrated device technology, inc. applications information wiring the differential input to accept single-ended levels figure 2 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration requires that th e sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, match ed termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 2. recommended schematic for wiring a diff erential input to accept single-ended levels recommendations for unused input and output pins inputs: clk/nclk inputs for applications requiring only one differential input, the unused clk and nclk input can be left float ing. though not required, but for additional protection, a 1k ? resistor can be tied from clk pin to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 12 ?2012 integrated device technology, inc. 3.3v differential clock input interface the clk /nclk accepts lvds, lvpec l, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 3a to 3d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. 3a. clk/nclk input driven by a 3.3v lvpecl driver figure 3c. clk/nclk input driven by a 3.3v hcsl driver figure 3b. clk/nclk input driven by a 3.3v lvpecl driver figure 3d. clk/nclk input driven by a 3.3v lvds driver r3 125 ? r4 125 ? r1 84 ? r2 84 ? 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl differential input hcsl *r3 33 ? *r4 33 ? clk nclk 3.3v 3.3v zo = 50 ? zo = 50 ? differential input r1 50 ? r2 50 ? *optional ? r3 and r4 can be 0 ? clk nclk differential input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 ? r2 50 ? r2 50 ? 3.3v r1 100 ? lvds clk nclk 3.3v receive r zo = 50 ? zo = 50 ?
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 13 ?2012 integrated device technology, inc. 2.5v differential clock input interface the clk /nclk accepts lvds, lvpec l, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 4a to 4d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 4a. clk/nclk input driven by a 2.5v lvpecl driver figure 4c. clk/nclk input driven by a 2.5v hcsl driver figure 4b. clk/nclk input driven by a 2.5v lvpecl driver figure 4d. clk/nclk input driven by a 2.5v lvds driver r3 250 ? r4 250 ? r1 6 2. 5 ? r2 6 2. 5 ? 2 . 5v zo = 50 ? zo = 50 ? c l k nc l k 2 . 5v 2 . 5v l vpe cl d i ffe r e nti a l i nput hcsl * r 3 33 ? *r4 33 ? c l k nc l k 2 . 5v 2 . 5v zo = 50 ? zo = 50 ? d i ffe r e nti a l i nput r1 50 ? r2 50 ? *o ptional ? r 3 a n d r4 ca n be 0 ? c l k nc l k d i ffe r e nti a l i nput l vpe cl 2 . 5v zo = 50 ? zo = 50 ? 2 . 5v r1 50 ? r2 50 ? r3 1 8 ? 2 . 5v r1 1 00 ? l vd s c l k nc l k 2 . 5v d i ffe r e nti a l i nput zo = 50 ? zo = 50 ?
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 14 ?2012 integrated device technology, inc. lvds driver termination a general lvds interface is shown in figure 5a. standard termination for lvds type outp ut structure r equires both a 100 ? parallel resistor at the receiver and a 100 ? differential transmission line environment. in order to avoid any transmission line reflection issues, the 100 ? resistor must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 5a can be used with either type of ou tput structure. if using a non-standard termination, it is recommended to contact idt and confirm if the output is a current source or a voltage source type structure. in addition, since these outputs are lvds compatible, the amplitude and common mode input range of the input receivers should be verified for compatibility with the output. lvds driver termination lv d s driver lv d s driver lv d s receiver lvds receiver z t c z o z t z o z t z t 2 z t 2 figure 5a. standard termination figure 5b. optional termination
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 15 ?2012 integrated device technology, inc. lvds power considerations this section provides information on power dissipati on and junction temperature for the ICS854S1208I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS854S1208I is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. max power dissipation occurs at -40c. max i dd at -40c = 305ma power max = v dd_max * i dd_max = 3.465v * 305ma = 1056.825mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 33.1c/w per table 6 below. max i dd at 85c = 287.8ma. max power at 85c = 3.465v * 287.8ma = 997.227mw. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.997w * 33.1c/w = 118c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 48 lead tqfp, e-pad, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 33.1c/w 27.2c/w 25.7c/w
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 16 ?2012 integrated device technology, inc. reliability information table 7. ja vs. air flow table for a 48 lead tqfp, e-pad transistor count the transistor count for ICS854S1208I is: 9878 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 33.1c/w 27.2c/w 25.7c/w
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 17 ?2012 integrated device technology, inc. package outline and package dimensions package outline - y suffix for 48 lead tqfp, e-pad table 8. package dimensions for 48 lead tqfp, e-pad reference document: jedec publication 95, ms-026 jedec variation: bbc - hd all dimensions in millimeters symbol minimum nominal maximum n 48 a 1.20 a1 0.05 0.10 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.50 ref. d3 & e3 3.5 e 0.5 basic l 0.45 0.60 0.75 ccc 0.08 0 7 -hd version exposed pad down -tab, exposed part of connection bar or tie bar 0.20 tab
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch ics854s1208ayi revision a april 27, 2012 18 ?2012 integrated device technology, inc. ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 854s1208ayilf ics4s1208ail ?lead-free? 48 lead tqfp, e-pad tray -40 c to 85 c 854s1208ayilft ics4s1208ail ?lead-free? 48 lead tqfp, e-pad 1000 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, whic h would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS854S1208I data sheet differential-to-lvds fa nout buffer w/divider and glitchless switch disclaimer integrated device technology, inc. (idt) and its subsid iaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the de scribed products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informati on contained herein is provided without re presentation or warranty of any kind, whether expr ess or implied, including, but not limited to, the suitability of idt?s products fo r any particular purpose, an implied warranty of merchantability, or non-infringement of the in tellectual property rights of others . this document is presented only as a guide and does not convey any license under intellectual property right s of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices wher e the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ris k, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2012. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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