integrated circuit systems, inc. general description features ics9147-09 block diagram pentium is a trademark of intel corporation frequency generator & integrated buffers for 686 series cpus 9147-09 rev a 10/2897p pin configuration the ics9147-09 generates all clocks required for high speed risc or cisc microprocessor systems such as intel pentiumpro, amd or cyrix processors. four bidirectional i/o pins (fs0, fs1, fs2, bsel) are latched at power-on to the functionality table. the six bus clocks can be selected as either synchronous at 1/2 cpu speed or asynchronous at 32mhz selected by bsel latched input.the inputs provide for tristate and test mode conditions to aid in system level testing.these multiplying factors can be customized for specific applications. glitch-free stop clock controls provided for cpu. high drive bus and sdram outputs typically provide greater than 1 v/ns slew rate into 30 pf loads. cpu outputs typically provide better than 1v/ns slew rate into 20pf loads while maintaining 505% duty cycle. the ref clock outputs typically provide better than 0.5v/ns slew rates. seperate buffer supply pin vddl allows for nominal 3.3v voltage or reduced voltage swing (from 2.9 to 2.5v) for cpul (1:2) and ioapic outputs. ? total of 15 cpu speed clocks: - two copies of cpu clock with vddl (2.5 to 3.3v) - twelve (12) sdram (3.3v) plus one cpuh/agp (3.3v) clocks ? six copies of bus clock (synchronous with cpu clock/2 or asynchronous 32 mhz) ? 250ps output skew window for cpu andsdram clocks and 500ps window bus clocks. cpu clocks to busclocks skew 1-4ns (cpu early) ? two copies of ref. clock @14.31818 mhz (one driven by vddl as ioapic) ? one 48 mhz (3.3 v ttl) for usb support and single 24 mhz. ? separate vddl for cpul (1:2) clock buffers and ioapic to allow 2.5v output (or s td. vdd) ? 3.0v ? 3.7v supply range w/2.5v compatible outputs ? 48-pin ssop package 48-pin ssop ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ics9147-09 pin descriptions * bidirectional input/output pins, input logic level determined at internal power-on-reset are latched. use 10kohm resistor to program logic hi to vdd or gnd for logic low. pin number pin name type description 2 ref out reference clock output* fs1 in logic input frequency select bit1*. input latched at poweron. 3, 9, 16, 22, 27, 33, 39, 45 gnd pwr ground. 4 x1 in crystal input. nominally 14.318 mhz. has internal load cap 5 x2 out crystal output. has internal load cap and feedack resistor to x1 41 vddl pwr 2.5 or 3.3v buffer power for cpul and ioapic output buffers. 8, 10, 11, 12, 14, bus (1:5) out bus clock outputs. see select table for frequency 15 bus6 out bus clock output. see select table for frequency.* fs0 in logic input frequency select bit0.*. input latched at poweron. 23 cpu_stop# in halts cpu clocks at logic "0" level when low. internal pull-up 24 pd# in powers down chip, active low. internal pull-up 47 24m out 24mhz fixed clock.* bsel in logic input* for selecting synchronous or asynchronous bus frequency- see table above. input latched at poweron.* 1, 6, 13, 19, 30, 36, 48 vdd3 pwr 3.3 volt core logic and buffer power 17, 18, 20, 21, 28, 29, 31, 32, 34, 35, 37, 38 sdram (1:12) out sdram clocks at cpu speed. see select table for frequency. 40 cpuh/agp out cpu clock operates at sdram vdd level (3.3v nom), for agp etc. 42, 43 cpul (1:2) out cpu clocks .see select table for frequency. operates at down to 2.5v controlled by vddl pin. 7, 25, 26 n/c pins not internally connected. 46 48m out 48 mhz fixed clock output*. fs2 in logic input frequency select bit 2*. input latched at poweron. 44 ioapic out reference clock (14.318mhz) powered by vddl, operating 2.5 to 3.3v.
3 ics9147-09 functionality with (14.31818 mhz input) clock enable configuration **test: is the frequency applied to the x1 input. can be crystal or tester generated clock overriding crystal at x1 pin. address select cpul (1:2) cpuh sdram (1:12) bus (1:6) (mhz) 24m (mhz) 48m (mhz) fs2 fs1 fs0 (mhz) bsel=1 bsel=0 (mhz) (mhz) 000 60 30 32 24 48 001 66.8 33.4 32 24 48 010 50 25 32 24 48 011 55 27.5 32 24 48 100 75 37.5 32 24 48 101 68.5 34.3 32 24 48 1 1 0 83.3 41.65 32 24 48 1 1 1 tristate tristate tristate tristate tristate pd# cpustop# cpul (1:2) cpuh sdram (1:12) bus (1:6) 24mhz 48mhz ref 1 1 running running running running running running 1 0 stop low running running running running running 0 x stop low stop low stop low stop low stop low stop low
4 ics9147-09 absolute maximum ratings electrical characteristics at 3.3v supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc characteristics parameter symbol test conditions min typ max units input low voltage v il latched inputs and fulltime inputs - - 0.2v dd v input high voltage v ih latched inputs and fulltime inputs 0.7v dd --v input low current i il v in = 0v (fulltime inputs) -28.0 -10.5 - a input high current i ih v in =v dd (fulltime inputs) -5.0 - 5.0 a output low current i ol1a v ol = 0.8v; cpu, sdram ioapic, ref, bus; v dd2 = 3.3v 19.0 30.0 - ma i ol1b v ol = 0.8v; cpul, ioapic; vdd2 = 2.5v 19.0 30.0 ma output high current i oh1a v oh = 2.0v; cpu, sdram ioapic, ref, bus; v dd2 = 3.3v - -26.0 -16.0 ma i oh1b v oh = 2.0v; cpul, ioapic; v dd2 = 2.5v -12.5 -9.5 ma output low current i ol2 v ol = 0.8v; for fixed 24, 48 16.0 25.0 - ma output high current i oh2 v oh = 2.0v; for fixed 24, 48 - -22.0 -14.0 ma output low voltage v ol1a i ol = 10ma; cpu, sdram ioapic ref, bus;v dd2 = 3.3v -0.30.4v v ol1b i ol = 10ma; cpul, ioapic; v dd2 =2.5v 0.3 0.4 v output high voltage v oh1a i oh = -10ma; cpu, sdram, ioapic, ref, bus; v dd = 3.3v 2.4 2.8 - v v oh1b i oh = -10ma; cpul, ioapic; vdd2=2.5v 1.95 2.1 v output low voltage v ol2 i ol = 8ma; for fixed 24, 48mhz clks - 0.3 0.4 v output high voltage v oh2 i oh = -8ma; for fixed 24, 48mhz clks 2.4 2.8 - v supply current i dd @66.6 mhz; all outputs unloaded - 120 180 ma power down current i pd pd#=0 - 5.0 20.0 a pull-up resistor r pu cpustop#; pd# 20 40 80 kohms
5 ics9147-09 electrical characteristics at 3.3v v dd = 3.0 ? 3.7 v, t a = 0 ? 70 c unless otherwise stated note 1: parameter is guaranteed by design and characterization. not 100% tested in production. ac characteristics parameter symbol test conditions min typ max units rise time 1 tr1 20pf load, 0.8 to 2.0v cpu, sdram, bus & ref -0.91.5ns fall time 1 tf1 20pf load, 2.0 to 0.8v cpu, sdram, bus & ref -0.81.4 ns rise time 1 tr3 20pf load, 0.8 to 2.0v fixed 20 & 48 clocks -0.91.5 ns fall time 1 tf3 20pf load, 2.0 to 0.8v fixed 20 & 48 clocks -1.11.5 ns rise time 1 tr4 20pf load, 0.4 to 2.0v , cpul with vddl = 2.5v -2.02.5 ns fall time 1 tf4 20pf load, 2.0 to 0.4v, cpul with vddl = 2.5v -1.62.5 ns duty cycle 1 dt 20pf load @ vout=1.4v all clocks except 48mhz and ref 47 52 57 % duty cycle 1 dt2 20pf load @ vout=1.4v 48mhz and ref outputs 40 50 60 % jitter, one sigma 1 tjis1 cpu & bus clocks; load=20pf, sdram; load = 30pf, vddl = 3.3 or 2.5v fout=25 mhz, bsel=1 -50150 ps jitter, absolute 1 tjab1 cpu & bus clocks; load=20pf, sdram; load = 30pf, vddl = 3.3 or 2.5v fout 3 25 mhz, bsel=1 -250 - 250 ps jitter, one sigma 1 tjis2 fixed clk; load=20pf - 1 3 % jitter, absolute 1 tjab2 fixed clk; load=20pf -5 2 5 % jitter, cycle to cycle 1 tcc1 cpu clocks, load=20pf bsel=1 - 250 ps jitter, cycle to cycle 1 tcc2 cpu clocks, load=20pf bsel=1 vddl=2.5v - 350 ps input frequency 1 fi 12.0 14.318 16.0 mhz ratio of nominal to output frequency fout1 with input driven at 14.31818mhz to 20.0, 48.0mhz -1 -0.1 +1 ppm logic input capacitance 1 cin logic input pins - 5 - pf crystal oscillator capacitance 1, 2 cinx x1, x2 pins 2 4 6 pf power-on time 1 ton from vdd=1.6v to 1st crossing of 66.6 mhz vdd supply ramp < 40ms -2.54.5 ms clock skew window 1 tsk1 cpu to cpu or sdram; load=20pf; @1.4v (same vdd) - 150 250 ps clock skew window 1 tsk2 bus to bus, sdram to sdram; load=20pf; @1.4v - 300 500 ps clock skew window 1 tsk3 cpu to bus; load=20pf; @1.4v (cpu is early) 1.6 2.1 4.6 ns clock skew window 1 tsk4 cpul to bus, vddl=2.5v vth=1.25, cpul (bus vth=1.4v) 0.50 1.50 3.0 ns clock skew window 1 tsk5 sdram, cpuh (@3.3v, vth=1.4v) to cpul (@2.5v vth=1.25v) load=20pf (2.5v cpul is late) 100 600 850 ps
6 ics9147-09 pins 2, 15, 46 and 47 on the ics9147-09 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm(10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figs. 1 and 2 show the recommended means of implementing this function. in fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device?s internal logic. figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. these figures illustrate the optimal pcb physical layout options. these configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. the layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s). shared pin operation - input/output pins the ics9147-09 includes a production test verification mode of operation. this requires that the fs2 and fs1 pins be programmed to a logic high and the fs0 pin be programmed to a logic low(see shared pin operation section). in this mode the device will output the following frequencies. note: ref is the frequency of either the crystal connected between the devices x1and x2, or, in the case of a device being driven by an external reference clock, the frequency of the reference (or test) clock on the device?s x1 pin. test mode operation fig. 1 pin frequency ref, ioapic ref 48mhz ref/2 24mhz ref/4 cpu, sdram ref2 bus bsel=1 ref/4 bus bsel=0 ref/3
7 ics9147-09 fig. 2a fig. 2b
8 ics9147-09 recommended pcb layout for ics9147-09 note: this pcb layout is based on a 4 layer board with an internal ground (common) and v dd plane. placement of components will depend on routing of signal trace. the 0.1uf capacitors should be placed as close as possible to the power pins. placement on the backside of the board is also possible. the ferrite beads can be replaced with 10-15ohm resistors. for best results, use a fixed voltage regulator between the main (board) v dd and the different v dd planes.
9 ics9147-09 ordering information ics9147f-09 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop device type (consists of 3 or 4 digit numbers) prefix ics = standard device example: ics xxxx f - ppp ssop package symbol common dimensions variations d n min. nom. max. min. nom. max. a .095 .101 .110 ac .620 .625 .630 48 a1 .008 .012 .016 ad .720 .725 .730 56 a2 .088 .090 .092 b .008 .010 .0135 c.005- .010 d see variations e .292 .296 .299 e0.025 bsc h .400 .406 .410 h .010 .013 .016 l .024 .032 .040 n see variations 0 5 8 x .085 .093 .100 advance information documents contain information on new products in the sampling or preproduction phase of devel- opment. characteristic data and other specifications are subject to change without notice.
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