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this is information on a product in full production. october 2014 docid022580 rev 7 1/48 m95160 m95160-w m95160-r m95160-df 16-kbit serial spi bus ee prom with high-speed clock datasheet - production data features ? compatible with the serial peripheral interface (spi) bus ? memory array ? 16 kb (2 kbytes) of eeprom ? page size: 32 bytes ? additional write lockable page (identification page) ? write ? byte write within 5 ms ? page write within 5 ms ? write protect: quarter, half or whole memory array ? high-speed clock: 20 mhz ? single supply voltage: ? 2.5 v to 5.5 v for m95160-w ? 1.8 v to 5.5 v for m95160-r ? 1.7 v to 5.5 v for m95160-df ? operating temperature range: from -40c up to +85c ? enhanced esd protection ? more than 4 million write cycles ? more than 200-year data retention ? packages ? rohs compliant and halogen-free (ecopack2 ? ) so8 (mn) 150 mil width tssop8 (dw) 169 mil width wlcsp (cs) ufdfpn8 (mc) 2 x 3 mm www.st.com
contents m95160 m95160-w m95160-r m95160-df 2/48 docid022580 rev 7 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 serial data output (q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 serial data input (d) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3 serial clock (c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 chip select (s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.5 hold (hold ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.6 write protect (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.7 v cc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.8 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 connecting to the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 spi modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.1 operating supply voltage (v cc ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.2 device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.3 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.4 power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 active power and standby power modes . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.4 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.5 data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 write enable (wren) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 write disable (wrdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 read status register (rdsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.1 wip bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
docid022580 rev 7 3/48 m95160 m95160-w m95160-r m95160-df contents 3 6.3.2 wel bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 bp1, bp0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.4 srwd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 write status register (wrsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 read from memory array (read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.6 write to memory array (write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.7 read identification page (available only in m95160-d devices) . . . . . . . 26 6.8 write identification page (available only in m95160-d devices) . . . . . . . 27 6.9 read lock status (available only in m95160-d devices) . . . . . . . . . . . . . 28 6.10 lock id (available only in m95160-d devices) . . . . . . . . . . . . . . . . . . . . . 29 7 power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.2 initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
list of tables m95160 m95160-w m95160-r m95160-df 4/48 docid022580 rev 7 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. significant bits within the two address bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. status register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. operating conditions (m95160-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 9. operating conditions (m95160-r, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. operating conditions (m95160-df, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11. ac measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. cycling performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. memory cell data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15. dc characteristics (m95160-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 16. dc characteristics (m95160-r or m95160-df, devi ce grade 6). . . . . . . . . . . . . . . . . . . . . 35 table 17. ac characteristics (m95160-w, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 18. ac characteristics (m95160-r or m95160-df, dev ice grade 6) . . . . . . . . . . . . . . . . . . . . 37 table 19. ac characteristics (m95160-f, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 20. ac characteristics (m95160-w, device grade 6) end of life products: these values apply only to m95160-wmn6tp/s and m95160-wdw6tp/s devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 21. so8n ? 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 41 table 22. tssop8 ? 8-lead thin shrink small outline, pa ckage mechanical data. . . . . . . . . . . . . . . . 42 table 23. ufdfpn8 (mlp8) ? 8-lead ultra th in fine pitch dual flat package no lead 2 x 3 mm, data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 24. m95160-rcs6tp/s wlcsp package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 25. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 26. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
docid022580 rev 7 5/48 m95160 m95160-w m95160-r m95160-df list of figures 5 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. wlcsp connections (top view, marking side, with bumps on the underside) . . . . . . . . . . . 7 figure 4. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. bus master and memory devices on the spi bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. spi modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8. write enable (wren) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 figure 9. write disable (wrdi) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. read status register (rdsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. write status register (wrsr) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. read from memory array (read) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. byte write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. page write (write) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. read identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. write identification page sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 17. read lock status sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 18. lock id sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 19. ac measurement i/o wa veform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20. serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 21. hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 22. serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 23. so8n ? 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 41 figure 24. tssop8 ? 8-lead thin shrink small outline, pa ckage outline . . . . . . . . . . . . . . . . . . . . . . . 42 figure 25. ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat no lead, package outline. . . . . . . 43 figure 26. m95160-rcs6tp/s wlcsp package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
description m95160 m95160-w m95160-r m95160-df 6/48 docid022580 rev 7 1 description the m95160 devices are electrically eras able programmable memories (eeproms) organized as 2048 x 8 bits, accessed through the spi bus. the m95160-w can operate with a supply voltage from 2.5 v to 5.5 v, the m95160-r can operate with a supply voltage from 1.8 v to 5.5 v, and the m95160-df can operate with a supply voltage from 1.7 v to 5.5 v, over an ambient temperature range of -40 c / +85 c. the m95160-d offers an additional page, named the identification page (32 bytes). the identification page can be used to store se nsitive application parameters which can be (later) permanently locked in read-only mode. figure 1. logic diagram the spi bus signals are c, d and q, as shown in figure 1 and table 1 . the device is selected when chip select ( s ) is driven low. communications with the device can be interrupted when the hold is driven low. table 1. signal names signal name function direction c serial clock input d serial data input input q serial data output output s chip select input w write protect input hold hold input v cc supply voltage - v ss ground - !)# 3 6 ## -xxx (/,$ 6 33 7 1 # $
docid022580 rev 7 7/48 m95160 m95160-w m95160-r m95160-df description 47 figure 2. 8-pin package connections (top view) 1. see section 10: package mechanical data for package dimensions, and how to identify pin-1. figure 3. wlcsp connections (top view, ma rking side, with bumps on the underside) $ 6 33 # (/,$ 1 36 ## 7 !)$ -xxx 069 0dunlqjvlghwrsylhz %xpsvlgherwwrpylhz y s ^^ t ^ ,k> s k?]v??]}v?(?v t s ^^ y ,k> s ^
memory organization m95160 m95160-w m95160-r m95160-df 8/48 docid022580 rev 7 2 memory organization the memory is organized as shown in the following figure. figure 4. block diagram 069 ,k> ^ t }v??}oo}p] ,]pz}o?p pv??}? /lk?z](??p]??? ????p]??? v}v?? ? ?p]??? ?p y}? z}? y ^]}(?z z}vo? wzkd ? ^??? ?p]??? /v?](]?]}v?p le l?
docid022580 rev 7 9/48 m95160 m95160-w m95160-r m95160-df signal description 47 3 signal description during all operations, v cc must be held stable and within the specified valid range: v cc (min) to v cc (max). all of the input and output signals must be held high or low (according to voltages of v ih , v oh , v il or v ol , as specified in section 9: dc and ac parameters ). these signals are described next. 3.1 serial data output (q) this output signal is used to transfer data seria lly out of the device. data is shifted out on the falling edge of serial clock (c). 3.2 serial data input (d) this input signal is used to transfer data seri ally into the device. it receives instructions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). 3.3 serial clock (c) this input signal provides the timing of the serial interface. instructions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) change from the falling edge of serial clock (c). 3.4 chip select (s ) when this input signal is high, the device is de selected and serial data output (q) is at high impedance. the device is in the standby power mode, unless an internal write cycle is in progress. driving chip select ( s ) low selects the device, plac ing it in the active power mode. after power-up, a falling e dge on chip select ( s ) is required prior to the start of any instruction. 3.5 hold (hold ) the hold ( hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be sele cted, with chip select ( s ) driven low.
signal description m95160 m95160-w m95160-r m95160-df 10/48 docid022580 rev 7 3.6 write protect (w ) the main purpose of this input signal is to fr eeze the size of the area of memory that is protected against write instructions (as specifi ed by the values in the bp1 and bp0 bits of the status register). this pin must be driven either high or low, and must be stable during all write instructions. 3.7 v cc supply voltage v cc is the supply voltage. 3.8 v ss ground v ss is the reference for all signals, including the v cc supply voltage.
docid022580 rev 7 11/48 m95160 m95160-w m95160-r m95160-df connecting to the spi bus 47 4 connecting to the spi bus all instructions, addresses and input data bytes ar e shifted in to the device, most significant bit first. the serial data input (d) is sampled on the first rising edge of the serial clock (c) after chip select ( s ) goes low. all output data bytes are shifted out of the devi ce, most significant bit first. the serial data output (q) is latched on the first falling edge of the serial clock (c ) after the instruction (such as the read from memory array and read status register instructions) have been clocked into the device. figure 5. bus master and memory devices on the spi bus 1. the write protect (w ) and hold (hold ) signals should be driven, high or low as appropriate. figure 5 shows an example of three memory devices connected to an spi bus master. only one memory device is selected at a time, so on ly one memory device drives the serial data output (q) line at a time. the other memory devices are high impedance. the pull-up resistor r (represented in figure 5 ) ensures that a device is not selected if the bus master leaves the s line in the high impedance state. in applications where the bus master may leav e all spi bus lines in high impedance at the same time (for example, if the bus master is re set during the transmission of an instruction), the clock line (c) must be connected to an ex ternal pull-down resistor so that, if all inputs/outputs become high impedance, the c line is pulled low (while the s line is pulled high): this ensures that s and c do not become high at the same time, and so, that the t shch requirement is met. the typical value of r is 100 k . $,e 63,%xv0dvwhu 6'2 6', 6&. &4' &4' 63,0hpru\ 'hylfh &4' &6 &6 &6 63,,qwhuidfhzlwk &32/&3+$ ru : : +2/' : 5 55 5 63,0hpru\ 'hylfh 63,0hpru\ 'hylfh 9 && 9 && 9 66 9 66 9 66 9 && 6 6 6 +2/' +2/' 9 && 9 66
connecting to the spi bus m95160 m95160-w m95160-r m95160-df 12/48 docid022580 rev 7 4.1 spi modes these devices can be driven by a microcontrolle r with its spi peripheral running in either of the following two modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output data is available from t he falling edge of serial clock (c). the difference between the two modes, as shown in figure 6 , is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1) figure 6. spi modes supported !)" # -3" #0(! $ #0/, 1 # -3"
docid022580 rev 7 13/48 m95160 m95160-w m95160-r m95160-df operating features 47 5 operating features 5.1 supply voltage (v cc ) 5.1.1 operating supply voltage (v cc ) prior to selecting the memory and issuing instructions to it, a valid and stable v cc voltage within the specified [v cc (min), v cc (max)] range must be applied (see operating conditions in section 9: dc and ac parameters ). this voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (t w ). in order to secure a stab le dc supply voltage, it is recommended to decouple the v cc line with a suitable capacitor (usually of the order of 10 nf to 100 nf) close to the v cc /v ss device pins. 5.1.2 device reset in order to prevent erroneous instruction dec oding and inadvertent write operations during power-up, a power-on-reset (por) circuit is included. at power-up, the device does not respond to any instruction until vcc reaches t he por threshold voltage. this threshold is lower than the minimum v cc operating voltage (see operating conditions in section 9: dc and ac parameters ). at power-up, when v cc passes over the por threshold, th e device is reset and is in the following state: ? in standby power mode, ? deselected, ? status register values: ? the write enable latch (wel) bit is reset to 0. ? the write in progress (wip) bit is reset to 0. ? the srwd, bp1 and bp0 bits remain unchanged (non-volatile bits). it is important to note that the device must not be accessed until v cc reaches a valid and stable level within the specified [v cc (min), v cc (max)] range, as defined under operating conditions in section 9: dc and ac parameters . 5.1.3 power-up conditions when the power supply is turned on, v cc rises continuously from v ss to v cc . during this time, the chip select ( s ) line is not allowed to float but should follow the v cc voltage. it is therefore recommended to connect the s line to v cc via a suitable pull-up resistor (see figure 5 ). in addition, the chip select ( s ) input offers a built-in safety feature, as the s input is edge- sensitive as well as level-sensitive: after power-up, the device does not become selected until a falling edge has first be en detected on chip select ( s ). this ensures that chip select ( s ) must have been high, prior to going low to start the first operation. the v cc voltage has to rise continuously from 0 v up to the minimum v cc operating voltage defined under operating conditions in section 9: dc and ac parameters , and the rise time must not vary faster than 1 v/s.
operating features m95160 m95160-w m95160-r m95160-df 14/48 docid022580 rev 7 5.1.4 power-down during power-down (continuous decrease of the v cc supply voltage below the minimum v cc operating voltage defined under operating conditions in section 9: dc and ac parameters ), the device must be: ? deselected (chip select s should be allowe d to follow the voltage applied on v cc ), ? in standby power mode (there should not be any internal write cycle in progress). 5.2 active power and standby power modes when chip select ( s ) is low, the device is selected, and in the active power mode. the device consumes i cc . when chip select ( s ) is high, the device is deselected. if a write cycle is not currently in progress, the device then goes into the st andby power mode, and the device consumption drops to i cc1 , as specified in dc characteristics (see section 9: dc and ac parameters ). 5.3 hold condition the hold ( hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. to enter the hold condition, the device must be selected, with chip select ( s ) low. during the hold condition, the serial data ou tput (q) is high impedance, and the serial data input (d) and the serial clock (c) are don?t care. normally, the device is kept selected for th e whole duration of the hold condition. deselecting the device while it is in the hold condition has the effect of resetting the state of the device, and this mechanism can be used if required to reset any processes that had been in progress. (a) (b) figure 7. hold condition activation a. this resets the internal logic, except the wel and wip bits of the status register. b. in the specific case where the device has shifted in a write command (inst + address + data bytes, each data byte being exactly 8 bits), deselec ting the device also triggers the write cycle of this decoded command. dl( f +2/' +rog frqglwlrq +rog frqglwlrq
docid022580 rev 7 15/48 m95160 m95160-w m95160-r m95160-df operating features 47 the hold condition starts when the hold (hold) signal is dr iven low when serial clock (c) is already low (as shown in figure 7 ). figure 7 also shows what happens if the rising an d falling edges are not timed to coincide with serial clock (c) being low. 5.4 status register the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. see section 6.3: read status register (rdsr) for a detailed description of t he status register bits. 5.5 data protection and protocol control the device features the following data protection mechanisms: ? before accepting the execution of the write and write status register instructions, the device checks whether the number of clock pulses comprised in the instructions is a multiple of eight. ? all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. ? the block protect (bp1, bp0) bits in the status register are used to configure part of the memory as read-only. ? the write protect (w ) signal is used to protect the block protect (bp1, bp0) bits in the status register. for any instruction to be accept ed, and executed, chip select ( s ) must be driven high after the rising edge of serial clock (c) for the last bi t of the instruction, and before the next rising edge of serial clock (c). two points should be noted in the previous sentence: ? the ?last bit of the instruction? can be the eigh th bit of the instruction code, or the eighth bit of a data byte, depending on the instru ction (except for read status register (rdsr) and read (read) instructions). ? the ?next rising edge of serial clock (c )? might (or might not) be the next bus transaction for some other device on the spi bus. table 2. write-protected block size status register bits protected block protected array addresses bp1 bp0 0 0 none none 0 1 upper quarter 0600h - 07ffh 1 0 upper half 0400h - 07ffh 1 1 whole memory 0000h - 07ffh
instructions m95160 m95160-w m95160-r m95160-df 16/48 docid022580 rev 7 6 instructions each command is composed of bytes (msbit tran smitted first), initiate d with the instruction byte, as summarized in table 3 . if an invalid instruction is sent (one not contained in table 3 ), the device automatically enters a wait state until deselected. for read and write commands to memory array and identification page, the address is defined by two bytes as explained in table 4 . table 3. instruction set instruction description instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read from memory array 0000 0011 write write to memory array 0000 0010 rdid (1) 1. instruction available only for the m95160-d device. read identification page 1000 0011 wrid (1) write identification page 1000 0010 rdls (1) reads the identification page lock status 1000 0011 lid (1) locks the identification page in read-only mode 1000 0010 table 4. significant bits wi thin the two address bytes (1)(2) instructions msb address byte lsb address byte b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 read or write xxxxxa10a9a8a7a6a5a4a3a2a1a0 rdid or wrid (3) 00000000000a4a3a2a1a0 rdls or lid (3) 0000010000000000 1. a: significant address bit. 2. x: bit is don?t care. 3. instruction available only for the m95160-d device.
docid022580 rev 7 17/48 m95160 m95160-w m95160-r m95160-df instructions 47 6.1 write enable (wren) the write enable latch (wel) bit must be set prior to each write a nd wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in figure 8 , to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits for the device to be deselected, by chip select ( s ) being driven high. figure 8. write enable (wren) sequence # $ !)e 3 1 (igh)mpedance )nstruction
instructions m95160 m95160-w m95160-r m95160-df 18/48 docid022580 rev 7 6.2 write disable (wrdi) one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in figure 9 , to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait st ate. it waits for a the device to be deselected, by chip select ( s ) being driven high. the write enable latch (wel) bit, in fact, becomes reset by any of the following events: ? power-up ? wrdi instruction execution ? wrsr instruction completion ? write instruction completion. figure 9. write disable (wrdi) sequence $,g & ' 6 4 +ljk,pshgdqfh ,qvwuxfwlrq
docid022580 rev 7 19/48 m95160 m95160-w m95160-r m95160-df instructions 47 6.3 read status register (rdsr) the read status register (rdsr) instruction is used to read the status register. the status register may be read at any time, even while a write or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 10 . figure 10. read status register (rdsr) sequence the status and control bits of th e status register are as follows: 6.3.1 wip bit the write in progress (wip) bit indicates whether the memory is busy with a write or write status register cycle. when set to 1, such a cy cle is in progress, when reset to 0, no such cycle is in progress. 6.3.2 wel bit the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1, the internal write enable latch is set. when set to 0, the internal write enable latch is reset, and no write or writ e status register instruction is accepted. the wel bit is returned to its reset state by the following events: ? power-up ? write disable (wrdi) instruction completion ? write status register (wrs r) instruction completion ? write (write) instruction completion 6.3.3 bp1, bp0 bits the block protect (bp1, bp0) bits are non volat ile. they define the size of the area to be software-protected against write instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits is set to 1, the relevant memory area (as defined in table 2 ) becomes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. # $ 3 )nstruction !)% 1 3tatus2egister/ut (igh)mpedance -3" 3tatus2egister/ut -3"
instructions m95160 m95160-w m95160-r m95160-df 20/48 docid022580 rev 7 6.3.4 srwd bit the status register write disable (srwd) bi t is operated in conjunction with the write protect ( w ) signal. the status register write disable (srwd) bit and write protect ( w ) signal enable the device to be put in the ha rdware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect ( w ) is driven low). in this mode, the non-volatile bits of the status re gister (srwd, bp1, bp0) become read-only bits and the write status register (wrsr) instru ction is no longer accepted for execution. table 5. status register format b7 b0 srwd 0 0 0 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit
docid022580 rev 7 21/48 m95160 m95160-w m95160-r m95160-df instructions 47 6.4 write status register (wrsr) the write status register (wrs r) instruction is used to wr ite new values to the status register. before it can be accepted, a writ e enable (wren) instruction must have been previously executed. the write status register (wrsr) instruct ion is entered by driving chip select ( s ) low, followed by the instruction code, the data byte on serial data input (d) and chip select ( s ) driven high. chip select ( s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and befo re the next rising edge of serial clock (c). otherwise, the write status register (wrsr) instruction is not executed. the instruction sequence is shown in figure 11 . figure 11. write status register (wrsr) sequence driving the chip select ( s ) signal high at a byte boundary of the input data triggers the self- timed write cycle that takes t w to complete (as specified in ac tables under section 9: dc and ac parameters ). while the write status register cycle is in pr ogress, the status register may still be read to check the value of the write in progress (wip) bit: the wip bit is 1 during the self-timed write cycle t w , and 0 when the write cycle is complete. the wel bit (write enable latch) is also reset at the end of the write cycle t w . the write status register (wrsr) instruction enables the user to change the values of the bp1, bp0 and srwd bits: ? the block protect (bp1, bp0) bits define the si ze of the area that is to be treated as read-only, as defined in table 2 . ? the srwd (status register write disable) bit, in accordance with the signal read on the write protect pin (w ), enables the user to set or reset the write protection mode of the status register itself, as defined in table 6 . when in write-protected mode, the write status register (wrsr) instruction is not executed. the contents of the srwd and bp1, bp0 bits are updated after the completion of the wrsr instruction, including the t w write cycle. the write status register (wrsr) instruction has no effect on the b6, b5, b4, b1, b0 bits in the status register. bits b6, b5, b4 are always read as 0. # $ !)d 3 1 (igh)mpedance )nstruction 3tatus 2egister)n -3"
instructions m95160 m95160-w m95160-r m95160-df 22/48 docid022580 rev 7 the protection features of the device are summarized in table 6 . when the status register write disable (srwd) bit in the status register is 0 (its initial delivery state), it is possible to write to the status register (provided that the wel bit has previously been set by a wren instruction), regardless of the logic level applied on the write protect ( w ) input pin. when the status register write disable (srwd) bi t in the status register is set to 1, two cases should be considered, depending on the state of the write protect ( w ) input pin: ? if write protect (w ) is driven high, it is possible to write to the status register (provided that the wel bit has previously be en set by a wren instruction). ? if write protect (w ) is driven low, it is not possible to write to the status register even if the wel bit has previously been set by a wren instruction. (attempts to write to the status register are rejected, and are not a ccepted for execution). as a consequence, all the data bytes in the memory area, which are software-protected (spm) by the block protect (bp1, bp0) bits in the status register, are also hardware-protected against data modification. regardless of the order of the two events, the hardware-protected mode (hpm) can be entered by: ? either setting the srwd bit after driving the write protect (w ) input pin low, ? or driving the write protect (w ) input pin low after setting the srwd bit. once the hardware-protected mode (hpm) has been entered, the only way of exiting it is to pull high the write protect ( w ) input pin. if the write protect ( w ) input pin is permanently tied high, the hardware-protected mode (hpm) can never be activated, and only th e software-protected mode (spm), using the block protect (bp1, bp0) bits in the status register, can be used. table 6. protection modes w signal srwd bit mode write protection of the status register memory content protected area (1) 1. as defined by the values in the block protec t (bp1, bp0) bits of the status register. see table 2 . unprotected area (1) 10 software- protected (spm) status register is writable (if the wren instruction has set the wel bit). the values in the bp1 and bp0 bits can be changed. write-protected ready to accept write instructions 00 11 01 hardware- protected (hpm) status register is hardware write- protected. the values in the bp1 and bp0 bits cannot be changed. write-protected ready to accept write instructions
docid022580 rev 7 23/48 m95160 m95160-w m95160-r m95160-df instructions 47 6.5 read from memory array (read) as shown in figure 12 , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte and address bytes are then shifted in, on serial data input (d). the address is loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). figure 12. read from memory array (read) sequence 1. depending on the memory size, as shown in table 4 , the most significant address bits are don?t care. if chip select ( s ) continues to be driven low, the internal address register is incremented automatically, and the byte of data at the new address is shifted out. when the highest address is reached, the addr ess counter rolls over to zero, a llowing the read cycle to be continued indefinitely. the whole memory can, ther efore, be read with a single read instruction. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time during the cycle. the instruction is not accepted, and is not execut ed, if a write cycle is currently in progress. & ' $,' 6 4 +ljk,pshgdqfh 'dwd2xw ,qvwuxfwlrq %lw$gguhvv 06% 06% 'dwd2xw
instructions m95160 m95160-w m95160-r m95160-df 24/48 docid022580 rev 7 6.6 write to memo ry array (write) as shown in figure 13 , to send this instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip select ( s ) high at a byte boundary of the input data. the self-timed write cycle, tr iggered by the chip select ( s ) rising edge, continues for a period t w (as specified in ac characteristics in section 9: dc and ac parameters ), at the end of which the write in progress (wip) bit is reset to 0. figure 13. byte write (write) sequence 1. depending on the memory size, as shown in table 4 , the most significant addr ess bits are don?t care. in the case of figure 13 , chip select ( s ) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. however, if chip select ( s ) continues to be driven low, as shown in figure 14 , the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. each time a new data byte is shifted in, the le ast significant bits of the internal address counter are incremented. if more bytes are sent than will fit up to the end of the page, a condition known as ?roll-over? occurs. in case of roll-over, the bytes exceeding the page size are overwritten from location 0 of the same page. the instruction is not accepted, and is not executed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before), ? if a write cycle is already in progress, ? if the device has not been deselected, by driving high chip select (s ), at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in), ? if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. # $ !)$ 3 1 (igh)mpedance )nstruction "it!ddress $ata"yte
docid022580 rev 7 25/48 m95160 m95160-w m95160-r m95160-df instructions 47 note: the self-timed write cycle t w is internally executed as a sequence of two consecutive events: [erase addressed byte(s)], followed by [program addressed byte(s)]. an erased bit is read as ?0? and a programmed bit is read as ?1?. figure 14. page write (write) sequence 1. depending on the memory size, as shown in table 4 , the most significant addr ess bits are don?t care. # $ !)$ 3 # $ 3 )nstruction "it!ddress $ata"yte $ata"yte $ata"yte $ata"yte.
instructions m95160 m95160-w m95160-r m95160-df 26/48 docid022580 rev 7 6.7 read identification page (available only in m95160-d devices) the read identification page ( rdid) instruction is used to read the identification page (additional page of 32 bytes which can be writ ten and later permanently locked in read-only mode). the chip select ( s ) signal is first driven low, the bits of the instruction byte and address bytes are then shifted in (msb first) on serial data input (d). address bit a10 must be 0, other upper address bits are don't care (it migh t be easier to define these bits as 0, as shown in table 4 ). the data byte pointed to by the lower address bits [a4:a0] is shifted out (msb first) on serial data output (q). the first byte addressed can be any byte within the identification page. if chip select ( s ) continues to be driven low, the internal address register is automatically incremented and the byte of data at the new address is shifted out. note that there is no roll over feature in the identification page. the address of bytes to read must not exceed the page boundary. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time when the data bits are shifted out. the instruction is not accepted, and is not execut ed, if a write cycle is currently in progress. figure 15. read identification page sequence & ' $l 6 4 +ljklpshgdqfh 'dwd2xw ,qvwuxfwlrq elwdgguhvv 06% 06% 'dwd2xw
docid022580 rev 7 27/48 m95160 m95160-w m95160-r m95160-df instructions 47 6.8 write identification page (available only in m95160-d devices) the write identification page (wrid) instructio n is used to write th e identification page (additional page of 32 bytes which can also be permanently locked in read-only mode). the chip select signal ( s ) is first driven low, and then the bits of the instruction byte, address bytes, and at least one data byte are shifted in (msb first) on serial data input (d). address bit a10 must be 0, other upper address bits are don't care (it might be easier to define these bits as 0, as shown in table 4 ). the lower address bits [a4:a0] define the byte address inside the identification page. the self-timed write cycle starts from the rising edge of chip select ( s ), and continues for a period t w (as specified in section 9: dc and ac parameters ). figure 16. write identification page sequence the instruction is discarded, and is no t executed, under the following conditions: ? if the write enable latch (w el) bit has not been set to 1 (by executing a write enable instruction just before). ? if a write cycle is already in progress. ? if the device has not been deselected, by driving high chip select (s), at exactly a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in). & ' $l 6 4 +ljklpshgdqfh ,qvwuxfwlrq elwdgguhvv 'dwde\wh
instructions m95160 m95160-w m95160-r m95160-df 28/48 docid022580 rev 7 6.9 read lock status (availa ble only in m95160-d devices) the read lock status (rdls) instruction is used to read the lock status. to send this instruction to the device, chip select ( s ) first has to be driven low. the bits of the instruction byte and address bytes are then shifted in (msb first) on serial data input (d). address bit a10 must be 1; all other address bits are don't care (it might be easier to define these bits as 0, as shown in table 4 ). the lock bit is the lsb (least significant bit) of the byte read on serial data output (q). it is at ?1? when the lock is active and at ?0? when the lock is not active. if chip select ( s ) continues to be driven low, the same data byte is shifted out. the read cycle is terminated by driving chip select ( s ) high. the instruction sequence is shown in figure 17 . the read lock status instruction is not accepted and not executed if a write cycle is currently in progress. figure 17. read lock status sequence & ' $l 6 4 +ljklpshgdqfh 'dwd2xw ,qvwuxfwlrq elwdgguhvv 06% 06% 'dwd2xw
docid022580 rev 7 29/48 m95160 m95160-w m95160-r m95160-df instructions 47 6.10 lock id (available on ly in m95160-d devices) the lock identification page (lid) command is used to permanently lock the identification page in read-only mode. the lid instruction is issued by driving ch ip select (s) low, sending (msb first) the instruction code, the address and a data byte on serial data input (d), and driving chip select (s) high. in the address sent, a10 must be equal to 1. all other address bits are don't care (it might be easier to define these bits as 0, as shown in table 4 ). the data byte sent must be equal to the binary value xxxx xx1x, where x = don't care. the lid instruction is terminated by driving chip select (s) high at a data byte boundary, otherwise, the instruction is not executed. driving chip select ( s ) high at a byte boundary of the input data triggers the self-timed write cycle which duration is t w (specified in section 9: dc and ac parameters ). the instruction sequence is shown in figure 18 . the instruction is discarded, and is no t executed, under the following conditions: ? if the write enable latch (w el) bit has not been set to 1 (by executing a write enable instruction just before). ? if a write cycle is already in progress. ? if the device has not been deselected, by driving high chip select (s), at exactly a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in). figure 18. lock id sequence & ' $l 6 4 +ljklpshgdqfh ,qvwuxfwlrq elwdgguhvv 'dwde\wh
power-up and delivery state m95160 m95160-w m95160-r m95160-df 30/48 docid022580 rev 7 7 power-up and delivery state 7.1 power-up state after power-up, the device is in the following state: ? standby power mode, ? deselected (after power-up, a falling ed ge is required on chip select (s ) before any instructions can be started), ? not in the hold condition, ? the write enable latch (wel) is reset to 0, ? write in progress (wip) is reset to 0. the srwd, bp1 and bp0 bits of the status register are unchanged from the previous power-down (they are non-volatile bits). 7.2 initial delivery state the device is delivered with: ? the memory array set to all 1s (each byte = ffh) ? status register: bit srwd =0, bp1 =0 and bp0 =0 ? identification page: byte values are don?t care.
docid022580 rev 7 31/48 m95160 m95160-w m95160-r m95160-df maximum rating 47 8 maximum rating stressing the device outside the ratings listed in table 7 may cause permanent damage to the device. these are stress ratings only, and o peration of the device at these, or any other conditions outside those indicated in the operat ing sections of this specification, is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 7. absolute maximum ratings symbol parameter min. max. unit ambient operating temperature ?40 130 c t stg storage temperature ?65 150 c t lead lead temperature during soldering see note (1) 1. compliant with jedec std j-std-020d (for small bod y, sn-pb or pb-free assembly), the st ecopack? 7191395 specification, and the european directive on rest rictions of hazardous substances (rohs) 2011/65/eu. c v o output voltage ?0.50 v cc +0.6 v v i input voltage ?0.50 6.5 v v cc supply voltage ?0.50 6.5 v i ol dc output current (q = 0) - 5 ma i oh dc output current (q = 1) - 5 ma v esd electrostatic discharge voltage (human body model) (2) 2. positive and negative pulses applied on different co mbinations of pin connec tions, according to aec- q100-002 (compliant with ansi/esda/jedec js-001-2012, c1=100 pf, r1=1500 , r2=500 ). - 4000 v
dc and ac parameters m95160 m95160-w m95160-r m95160-df 32/48 docid022580 rev 7 9 dc and ac parameters this section summarizes the operating condi tions and the dc/ac characteristics of the device. figure 19. ac measurement i/o waveform table 8. operating conditions (m95160-w, device grade 6) symbol parameter min. max. unit v cc supply voltage 2.5 5.5 v t a ambient operating temperature ?40 85 c table 9. operating conditions (m95160-r, device grade 6) symbol parameter min. max. unit v cc supply voltage 1.8 5.5 v t a ambient operating temperature ?40 85 c table 10. operating conditions (m95160-df, device grade 6) symbol parameter min. max. unit v cc supply voltage 1.7 5.5 v t a ambient operating temperature ?40 85 c table 11. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times - 50 ns input pulse voltages 0.2 v cc to 0.8 v cc v input and output timing reference voltages 0.3 v cc to 0.7 v cc v !)# 6 ## 6 ## 6 ## 6 ## )nputandoutput timingreferencelevels )nputvoltagelevels
docid022580 rev 7 33/48 m95160 m95160-w m95160-r m95160-df dc and ac parameters 47 table 12. cycling performance symbol parameter (1) 1. cycling performance for products iden tified by process letter k (previous products were specified with 1 million cycles at 25 c). test conditions min. max. unit ncycle write cycle endurance ta 25 c, v cc (min) < v cc < v cc (max) - 4,000,000 write cycle ta = 85 c, v cc (min) < v cc < v cc (max) - 1,200,000 table 13. memory ce ll data retention parameter test conditions min. unit data retention (1) (2) 1. the data retention behavior is checked in producti on, while the 200-year limit is defined from characterization and qualification results. 2. for products identified by process letter k (previou s products were specified with a data retention of 40 years at 55c). ta = 55 c 200 year table 14. capacitance symbol parameter test conditions (1) 1. sampled only, not 100% tested, at t a = 25 c and a frequency of 5 mhz. min. max. unit c out output capacitance (q) v out = 0 v - 8 pf c in input capacitance (d) v in = 0 v - 8 pf input capacitance (other pins) v in = 0 v - 6 pf
dc and ac parameters m95160 m95160-w m95160-r m95160-df 34/48 docid022580 rev 7 table 15. dc characteristics (m95160-w, device grade 6) symbol parameter test conditions in addition to those defined in table 8 and table 11 min. max. unit i li input leakage current v in = v ss or v cc - 2a i lo output leakage current s = v cc , v out = v ss or v cc - 2a i cc supply current (read) v cc = 2.5 v, f c = 5 mhz, c = 0.1 v cc /0.9 v cc, q = open -2 ma v cc = 2.5 v, f c = 10 mhz, c = 0.1 v cc /0.9 v cc, q = open -2 (1) 1. 5 ma for the devices identified with process letter g or s. v cc = 5.5 v, f c = 20 mhz, c = 0.1 v cc /0.9 v cc, q = open -5 (2) 2. only for the devices iden tified by process letter k. i cc0 (3) 3. characterized only, not tested in production. supply current (write) during t w , s = v cc , 2.5 v < v cc < 5.5 v - 5 ma i cc1 supply current (standby) s = v cc , v cc = 5.5 v, v in = v ss or v cc , -3 a s = v cc , v cc = 2.5 v, v in = v ss or v cc , -2 v il input low voltage - ?0.45 0.3 v cc v v ih input high voltage - 0.7 v cc v cc +1 v v ol output low voltage i ol = 1.5 ma, v cc = 2.5 v - 0.4 v v oh output high voltage v cc = 2.5 v and i oh = 0.4 ma or v cc = 5.5 v and i oh = 2 ma 0.8 v cc -v v res (3) internal reset threshold voltage -1.0 (4) 4. 0.5 v with the device identified by process letter k. 1.65 (5) 5. 1.5 v with the device identified by process letter k. v
docid022580 rev 7 35/48 m95160 m95160-w m95160-r m95160-df dc and ac parameters 47 table 16. dc characteristics (m95160-r or m95160-df, device grade 6) symbol parameter test conditions in addition to those defined in in table 9 or table 10 and table 11 (1) min. max. unit i li input leakage current v in = v ss or v cc - 2a i lo output leakage current s = v cc , voltage applied on q = v ss or v cc - 2a i cc supply current (read) v cc = 1.8 v or 1.7 v, f c = 5 mhz, c = 0.1 v cc /0.9 v cc , q = open -2 (2) ma i cc0 (3) supply current (write) v cc = 1.8 v or 1.7 v, during t w , s = v cc -5ma i cc1 supply current (standby) v cc = 1.8 v or 1.7 v, s = v cc , v in = v ss or v cc -1a v il input low voltage v cc < 2.5 v ?0.45 0.25 v cc v v ih input high voltage v cc < 2.5 v 0.75 v cc v cc +1 v v ol output low voltage i ol = 0.15 ma, v cc = 1.8 v or 1.7 v - 0.3 v v oh output high voltage i oh = ?0.1 ma, v cc = 1.8 v or 1.7 v 0.8 v cc -v v res (3) internal reset threshold voltage -1.0 (4) 1.65 (5) v 1. if the application uses the m95160-r or m95160-df devices with 2.5 v v cc 5.5 v and -40 c t a +85 c, please refer to table 15: dc characterist ics (m95160-w, device grade 6) , rather than to the above table. 2. 2 ma at 3.5 mhz for the devices i dentified with process letters g or s. 3. characterized only, not tested in production. 4. 0.5 v with the device identified by process letter k. 5. 1.5 v with the device identified by process letter k.
dc and ac parameters m95160 m95160-w m95160-r m95160-df 36/48 docid022580 rev 7 table 17. ac characteristics (m95160-w, device grade 6) test conditions specified in table 8 and table 11 symbol alt. parameter v cc = 2.5 to 5.5 v (1) v cc = 4.5 to 5.5 v unit min. max. min. max. f c f sck clock frequency d.c. 10 d.c. 20 mhz t slch t css1 s active setup time 30 - 15 - ns t shch t css2 s not active setup time 30 - 15 - ns t shsl t cs s deselect time 40 - 20 - ns t chsh t csh s active hold time 30 - 15 - ns t chsl s not active hold time 30 - 15 - ns t ch (2) t clh clock high time 40 - 20 - ns t cl (2) t cll clock low time 40 - 20 - ns t clch (3) t rc clock rise time - 2 - 2 s t chcl (3) t fc clock fall time - 2 - 2 s t dvch t dsu data in setup time 10 - 5 - ns t chdx t dh data in hold time 10 - 10 - ns t hhch clock low hold time after hold not active 30 - 15 - ns t hlch clock low hold time after hold active 30 - 15 - ns t clhl clock low set-up time before hold active 0 - 0 - ns t clhh clock low set-up time before hold not active 0 - 0 ns t shqz (3) t dis output disable time - 40 - 20 ns t clqv (4) t v clock low to output valid - 40 - 20 ns t clqx t ho output hold time 0 - 0 - ns t qlqh (3) t ro output rise time - 40 - 20 ns t qhql (3) t fo output fall time - 40 - 20 ns t hhqv t lz hold high to output valid - 40 - 20 ns t hlqz (3) t hz hold low to output high-z - 40 - 20 ns t w t wc write time - 5 - 5 ms 1. only for devices identi fied by process letter k. 2. t ch + t cl must never be lower than the s hortest possible clock period, 1/f c (max). 3. characterized only, not tested in production. 4. t clqv must be compatible with t cl (clock low time): if the spi bus master offers a read setup time t su = 0 ns, t cl can be equal to (or greater than) t clqv ; in all other cases, t cl must be equal to (or greater than) t clqv +t su .
docid022580 rev 7 37/48 m95160 m95160-w m95160-r m95160-df dc and ac parameters 47 table 18. ac characteristics (m95160-r or m95160-df, device grade 6) test conditions specified in table 9 or table 10 and table 11 (1) symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 60 - ns t shch t css2 s not active setup time 60 - ns t shsl t cs s deselect time 90 - ns t chsh t csh s active hold time 60 - ns t chsl s not active hold time 60 - ns t ch (2) t clh clock high time 80 - ns t cl (2) t cll clock low time 80 - ns t clch (3) t rc clock rise time - 2 s t chcl (3) t fc clock fall time - 2 s t dvch t dsu data in setup time 20 - ns t chdx t dh data in hold time 20 - ns t hhch clock low hold time after hold not active 60 - ns t hlch clock low hold time after hold active 60 - ns t clhl clock low set-up time before hold active 0 - ns t clhh clock low set-up time before hold not active 0 - ns t shqz (3) t dis output disable time - 80 ns t clqv t v clock low to output valid - 80 ns t clqx t ho output hold time 0 - ns t qlqh (3) t ro output rise time - 80 ns t qhql (3) t fo output fall time - 80 ns t hhqv t lz hold high to output valid - 80 ns t hlqz (3) t hz hold low to output high-z - 80 ns t w t wc write time - 5 ms 1. if the application uses the m95160- r or m95160-df devices at 2.5 v v cc 5.5 v and -40 c t a +85 c, please refer to table 17: ac characterist ics (m95160-w, device grade 6) , rather than to the above table. 2. t ch + t cl must never be lower than the s hortest possible clock period, 1/f c (max). 3. characterized only, not tested in production.
dc and ac parameters m95160 m95160-w m95160-r m95160-df 38/48 docid022580 rev 7 table 19. ac characteristics (m95160-f (1) , device grade 6) 1. not recommended for new designs, please refer to table 18: ac characteristics (m95160-r or m95160- df, device grade 6) . test conditions specified in table 10 and table 11 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 3.5 mhz t slch t css1 s active setup time 85 - ns t shch t css2 s not active setup time 85 - ns t shsl t cs s deselect time 120 - ns t chsh t csh s active hold time 85 - ns t chsl s not active hold time 85 - ns t ch (2) 2. t ch + t cl must never be lower than the s hortest possible clock period, 1/f c (max). t clh clock high time 110 - ns t cl (2) t cll clock low time 110 - ns t clch (3) 3. characterized only, not tested in production. t rc clock rise time - 2 s t chcl (3) t fc clock fall time - 2 s t dvch t dsu data in setup time 30 - ns t chdx t dh data in hold time 30 - ns t hhch clock low hold time after hold not active 85 - ns t hlch clock low hold time after hold active 85 - ns t clhl clock low set-up time before hold active 0 - 0 t clhh clock low set-up time before hold not active 0 - 0 t shqz (3) t dis output disable time - 120 ns t clqv t v clock low to output valid - 120 ns t clqx t ho output hold time 0 - ns t qlqh (3) t ro output rise time - 100 ns t qhql (3) t fo output fall time - 100 ns t hhqv t lz hold high to output valid - 110 ns t hlqz (3) t hz hold low to output high-z - 110 ns t w t wc write time - 5 ms
docid022580 rev 7 39/48 m95160 m95160-w m95160-r m95160-df dc and ac parameters 47 the values in the following table must not be considered for any new design. table 20. ac characteristics (m95160-w, device grade 6) end of life products: these values apply only to m95160-wmn6tp/s and m95160-wdw6tp/s devices) test conditions specified in table 8 and table 11 symbol alt. parameter min. max. unit f c f sck clock frequency d.c. 5 mhz t slch t css1 s active setup time 90 - ns t shch t css2 s not active setup time 90 - ns t shsl t cs s deselect time 100 - ns t chsh t csh s active hold time 90 - ns t chsl s not active hold time 90 - ns t ch (1) 1. t ch + t cl must never be lower than the sh ortest possible clock period, 1/f c (max). t clh clock high time 90 - ns t cl (1) t cll clock low time 90 - ns t clch (2) 2. characterized only, not tested in production. t rc clock rise time - 1 s t chcl (2) t fc clock fall time - 1 s t dvch t dsu data in setup time 20 - ns t chdx t dh data in hold time 30 - ns t hhch clock low hold time after hold not active 70 - ns t hlch clock low hold time after hold active 40 - ns t clhl clock low set-up time before hold active 0 - ns t clhh clock low set-up time before hold not active 0-ns t shqz (2) t dis output disable time - 100 ns t clqv t v clock low to output valid - 60 ns t clqx t ho output hold time 0 - ns t qlqh (2) t ro output rise time - 50 ns t qhql (2) t fo output fall time - 50 ns t hhqv t lz hold high to output valid - 50 ns t hlqz (2) t hz hold low to output high-z - 100 ns t w t wc write time - 5 ms
dc and ac parameters m95160 m95160-w m95160-r m95160-df 40/48 docid022580 rev 7 figure 20. serial input timing figure 21. hold timing figure 22. serial output timing # $ !)d 3 -3"). 1 t$6#( (ighimpedance ,3"). t3,#( t#($8 t#,#( t3(#( t3(3, t#(3( t#(3, t#( t#, t#(#, # 1 !)c 3 1 t#,(, t(,#( t((#( t#,(( t((16 t(,1: # 1 !)f 3 $ !$$2 ,3"). t3(1: t#( t#, t1,1( t1(1, t#(#, t#,18 t#,16 t3(3, t#,#(
docid022580 rev 7 41/48 m95160 m95160-w m95160-r m95160-df package mechanical data 47 10 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 23. so8n ? 8-lead plas tic small outline, 150 mils body width, package outline 1. drawing is not to scale. table 21. so8n ? 8-lead plastic small outli ne, 150 mils body width, mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a - - 1.750 - - 0.0689 a1 - 0.100 0.250 - 0.0039 0.0098 a2 - 1.250 - - 0.0492 - b - 0.280 0.480 - 0.0110 0.0189 c - 0.170 0.230 - 0.0067 0.0091 ccc - - 0.100 - - 0.0039 d 4.900 4.800 5.000 0.1929 0.1890 0.1969 e 6.000 5.800 6.200 0.2362 0.2283 0.2441 e1 3.900 3.800 4.000 0.1535 0.1496 0.1575 e 1.270 - - 0.0500 - - h - 0.250 0.500 - 0.0098 0.0197 k-08-08 l - 0.400 1.270 - 0.0157 0.0500 l1 1.040 - - 0.0409 - - 62$ ( fff e h $ ' f ( k[? $ n pp / / $ *$8*(3/$1(
package mechanical data m95160 m95160-w m95160-r m95160-df 42/48 docid022580 rev 7 figure 24. tssop8 ? 8-lead thin shrink small outline, package outline 1. drawing is not to scale. table 22. tssop8 ? 8-lead thin shrink small outline, package mechanical data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a - - 1.200 - - 0.0472 a1 - 0.050 0.150 - 0.0020 0.0059 a2 1.000 0.800 1.050 0. 0394 0.0315 0.0413 b - 0.190 0.300 - 0.0075 0.0118 c - 0.090 0.200 - 0.0035 0.0079 cp - - 0.100 - - 0.0039 d 3.000 2.900 3.100 0.1181 0.1142 0.1220 e 0.650 - - 0.0256 - - e 6.400 6.200 6.600 0. 2520 0.2441 0.2598 e1 4.400 4.300 4.500 0. 1732 0.1693 0.1772 l 0.600 0.450 0.750 0. 0236 0.0177 0.0295 l1 1.000 - - 0.0394 - - -08-08 n8 8 76623$0 &3 f / ( ( ' $ $ d h e $ /
docid022580 rev 7 43/48 m95160 m95160-w m95160-r m95160-df package mechanical data 47 figure 25. ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat no lead, package outline 1. drawing is not to scale. 2. the central pad (area e2 by d2 in the above illustration) must be either connected to v ss or left floating (not connected) in the end application. table 23. ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data symbol millimeters inches (1) 1. values in inches are converted fr om mm and rounded to four decimal digits. typ min max typ min max a 0.550 0.450 0.600 0.0217 0.0177 0.0236 a1 0.020 0.000 0.050 0.0008 0.0000 0.0020 b 0.250 0.200 0.300 0.0098 0.0079 0.0118 d 2.000 1.900 2.100 0.0787 0.0748 0.0827 d2 - 1.200 1.600 - 0.0472 0.0630 e 3.000 2.900 3.100 0.1181 0.1142 0.1220 e2 - 1.200 1.600 - 0.0472 0.0630 e 0.500 - - 0.0197 - - k - 0.300 - - 0.0118 - l - 0.300 0.500 - 0.0118 0.0197 l1 - - 0.150 - - 0.0059 l3 - 0.300 - - 0.0118 - eee (2) 2. applied for exposed die paddle and terminals. exclude embedding part of exposed die paddle from measuring. - 0.080 - - 0.0031 - $ % :7?-%e6 ! ! eee , e b $ , % , 0in +
package mechanical data m95160 m95160-w m95160-r m95160-df 44/48 docid022580 rev 7 figure 26. m95160-rcs6tp/s wlcsp package outline 1. primary datum z and seating plane are defined by the spherical crowns of the bump. 2. drawing is not to scale. 3. preliminary data. : : 8 ccc- 9 ? ? ddd- e ' ( h h * h ) h & % $ $ $ hhh= $ = ddd ? #?-%?6 bbb : 7aferbackside "umpside /rientation reference "ump 3ideview /rientation reference $etail! $etail! 2otated? 3eatingplane seenote 8 9
docid022580 rev 7 45/48 m95160 m95160-w m95160-r m95160-df package mechanical data 47 table 24. m95160-rcs6tp/s wlcsp package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to four decimal digits. typ min max typ min max a 0.545 0.490 0.600 0.0215 0.0193 0.0236 a1 0.190 - - 0.0075 - - a2 0.355 - - 0.0140 - - b 0.270 0.0106 0.0094 0.0118 d 1.350 - 1.475 0.0531 - 0.0581 e 1.365 - 1.490 0.0537 - 0.0587 e 0.400 - - 0.0157 - - e1 0.800 - - 0.0315 - - f 0.282 - - 0.0111 - - g 0.275 - - 0.0108 - - n (2) 2. n is the total number of terminals. 88 aaa 0.110 0.0043 bbb 0.110 0.0043 ccc 0.110 0.0043 ddd 0.060 0.0024 eee 0.060 0.0024
part numbering m95160 m95160-w m95160-r m95160-df 46/48 docid022580 rev 7 11 part numbering table 25. ordering information scheme example: m95160-d w mn 6 t p \s device type m95 = spi serial access eeprom device function 160 = 16 kbit (2048 x 8) 160-d = 16 kbit (2048 x 8) plus identification page operating voltage w = v cc = 2.5 to 5.5 v r = v cc = 1.8 to 5.5 v f = v cc = 1.7 to 5.5 v package (1) 1. all packages are ecopack2? (r ohs-compliant and free of bromi nated, chlorinated and antimony-oxide flame retardants). mn = so8 (150 mil width) dw = tssop8 (169 mil width) mc = ufdfpn8 (mlp8) cs = wlcsp device grade 6 = industrial temperature range, ?40 to 85 c device tested with standard test flow option t = tape and reel packing blank = tube packing plating technology g or p = rohs compliant and halogen-free (ecopack?) process (2) 2. the process letters apply to wlcsp devices only . the process letters appear on the device package (marking) and on the shipment box. please contact your nearest st sales office for further information. /g or /s = manufacturing technology code
docid022580 rev 7 47/48 m95160 m95160-w m95160-r m95160-df revision history 47 12 revision history table 26. document revision history date revision changes 22-mar-2012 1 initial release. 17-dec-2012 2 updated: ? all information about package ufdfpn8 ? introduction of description ? section 7.2: initial delivery state 08-jan-2013 3 updated plating technology in section : . 16-sep-2013 4 replaced ?m95160-f? by ?m95160-df? part number. updated: ? package figure on cover page ? features : high-speed clock frequency, write cycles and data retention ? section 1: description ? figure 4: block diagram ? section 6: instructions : updated introduction and added section 6.7 to section 6.10 ? section 7.2: initial delivery state ? note 1 in table 7: absolute maximum ratings ? table 15: dc characteristics (m95160-w, device grade 6) , table 16: dc characteristics (m95160-r or m95160-df, device grade 6) , table 17: ac characteristics (m95160-w, device grade 6) and table 18: ac characteristics (m95160-r or m95160-df, device grade 6) . ? table 25: ordering information scheme added table 12: cycling performance and table 13: memory cell data retention . 11-mar-2014 5 added in cover page ?wri te lockable page (identification page)" 21-may-2014 6 updated figure 3: wlcsp connections (top view, marking side, with bumps on the underside) . deleted caution in figure 3: wlcsp connections (top view, marking side, with bumps on the underside) . updated footnote 2. in figure 25: ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat no lead, package outline . updated table 23: ufdfpn8 (mlp8) ? 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, data . and table 24: m95160-rcs6tp/s wlcsp package mechanical data . updated figure 26: m95160-rcs6tp/s wlcsp package outline . 06-oct-2014 7 updated package information in features . updated footnotes: ? 2 in table 7: absolute maximum ratings ; ? 1 in table 15: dc characteristics (m95160-w, device grade 6) ; ? 1 in table 25: ordering information scheme . updated table 25: ordering information scheme .
m95160 m95160-w m95160-r m95160-df 48/48 docid022580 rev 7 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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