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| Datasheet File OCR Text: |
| this is information on a product in full production. may 2014 docid025869 rev 3 1/200 l9678 l9678-s user configurable airbag ic datasheet - production data features ? energy reserve voltage power supply ? high frequency boost regulator, 1.882 mhz ? output voltage user selectable, 23 v or 33 v 5% ? user configurable linear power supplies ? 5.0 v and 7.2 v 4% output voltages ? external pass transistor ? fully integrated 3.3 v 4% linear regulator ? battery voltage monitor and shutdown control with wake-up control ? system voltage diagnostics with integrated adc ? crossover switch ? crossover performance, max 3 ? , 600 ma max. ? squib deployment drivers ? 4 channel hsd/lsd ? 25 v maximum deployment voltage ? 1.2 a @ 2 ms and 1.75 a @ 0.5/0.7 ms deployment profiles ? integrated safing fet linear regulator, 20 v/25 v nominal ? current monitoring ? rmeasure, stb, stg and leakage diagnostics ? high and low side driver fet tests ?safing fet test ? user customizable safing logic ? two channel psi-5 remote sensor interface (asynchronous mode), [only for l9678-s version] ? four channel hall-effect, resistive or switch sensor interface ? iso9141 transceiver ? dual channel configurable high-side/low-side led driver ? watchdog timer ? two integrated osc illators: 7.5/16 mhz ? temperature sensor ? 32 bit spi communications ? minimum operating voltage = 6 v ? operating temperature, -40 c to 95 c ? packaging - 64 pin ' ! 0 ' 0 3 lqfp64 (10x10x1.4mm) table 1. device summary order code package packing remote sensor interface l9678 lqfp64 (10 x 10 x 1.4 mm) tray no l9678-s lqfp64 (10 x 10 x 1.4 mm) tray yes www.st.com
contents l9678, l9678-s 2/200 docid025869 rev 3 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 absolute and operative maximu m ratings . . . . . . . . . . . . . . . . . . . . . . 12 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 operative maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3 pin-out description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3 overview and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 start-up power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 power mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.1 power_off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.2 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.3 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.4 passive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2.5 power-up and power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.6 operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3 configurable system power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.1 erboost switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3.2 energy reserve capacitor charging circuit . . . . . . . . . . . . . . . . . . . . . . . 29 4.3.3 er switch and covract pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3.4 vdd5 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.3.5 vdd3v3 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.6 vsup linear regulator (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3.7 vsf linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 reset functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.1 global spi register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 read/write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1.1 fault status register (fltsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1.2 system configuration regist er (sys_cfg) . . . . . . . . . . . . . . . . . . . . . . 53 5.1.3 system control register (sys_ ctl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 docid025869 rev 3 3/200 l9678, l9678-s contents 6 5.1.4 spi sleep command register (spi_sleep) . . . . . . . . . . . . . . . . . . . . . 56 5.1.5 system status register (sys_state) . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.1.6 power state register (power_state) . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.1.7 deployment configuration registers (dcr_x) . . . . . . . . . . . . . . . . . . . . 61 5.1.8 deployment command (depcom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.1.9 deployment configuration re gisters (dsr_x) . . . . . . . . . . . . . . . . . . . . 64 5.1.10 deployment current monitor status r egisters (dcmtsxy) . . . . . . . . . . . 65 5.1.11 deploy enable register (spidepen) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.1.12 squib ground loss register (lp_gndloss) . . . . . . . . . . . . . . . . . . . . . 66 5.1.13 device version register (version_id) . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.1.14 watchdog retry configuration register (wd_retry_conf) . . . . . . . . 67 5.1.15 watchdog timer configuration register (wdtcr) . . . . . . . . . . . . . . . . . 68 5.1.16 wd1 timer control register (wd1t) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1.17 wd1 state register (wdstate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.1.18 clock configuration register (clk_conf) . . . . . . . . . . . . . . . . . . . . . . . 70 5.1.19 scrap state entry command register (scrap_state) . . . . . . . . . . . . . 71 5.1.20 safing state entry command register (safing_state) . . . . . . . . . . . . 71 5.1.21 wd1 test command register (wd1_test) . . . . . . . . . . . . . . . . . . . . . . 72 5.1.22 system diagn ostic register (sysdiagreq) . . . . . . . . . . . . . . . . . . . . . 72 5.1.23 diagnostic result regist er for deployment loops (lpdiagstat) . . . . . . 74 5.1.24 loops diagnostic configur ation command register for low level diagnostic (lpdiagreq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.1.25 loops diagnostic configur ation command register for high level diagnostic (lpdiagreq) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.1.26 dc sensor diagnostic configurat ion command register (swctrl) . . . . 81 5.1.27 adc request and data re gisters (diagctrl_x) . . . . . . . . . . . . . . . . . . 82 5.1.28 gpo configuration register (gpocr) . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.1.29 gpo configuration register (gpoctrlx) . . . . . . . . . . . . . . . . . . . . . . . 86 5.1.30 gpo fault status register (gpofltsr) . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.1.31 iso fault status register (isofltsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.1.32 remote sensor configuration register (rscrx) . . . . . . . . . . . . . . . . . . 89 5.1.33 remote sensor control register (rsctrl) . . . . . . . . . . . . . . . . . . . . . . 90 5.1.34 remote sensor data/fault registers w/o fault (rsdrx) . . . . . . . . . . . . . 91 5.1.35 safing algorithm configuration register (saf_algo_conf) . . . . . . . . 95 5.1.36 arming signals register (arm_state) . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.1.37 armx assignment registers (loop_matrix_armx) . . . . . . . . . . . . . 97 5.1.38 armx pulse stretch regi sters (aepsts_armx) . . . . . . . . . . . . . . . . . . 98 contents l9678, l9678-s 4/200 docid025869 rev 3 5.1.39 safing records enable register (saf_en able) . . . . . . . . . . . . . . . . . . 99 5.1.40 safing records request mask regi sters (saf_req_mask_x) . . . . . . 100 5.1.41 safing records request target re gisters (saf_req_target_x) . . . . 101 5.1.42 safing records resp onse mask registers (saf _resp_mask_x) . . . . 102 5.1.43 safing records re sponse target registers (saf_resp_target_x) . . 103 5.1.44 safing records data mask registers (saf_data_mask_x) . . . . . . . . 104 5.1.45 safing records threshold register s (saf_threshold_x) . . . . . . . . . 105 5.1.46 safing control registers (saf_control_x) . . . . . . . . . . . . . . . . . . . 106 5.1.47 safing record compare complete regist er (saf_cc) . . . . . . . . . . . . . 109 6 deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6.1 control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 6.1.1 deployment current selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1.2 deploy command expiration timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.1.3 deployment control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.1.4 deployment success . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2 energy reserve - deployment voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.3 deployment ground return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.4 deployment driver protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 6.4.1 delayed low-side deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.4.2 low-side voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.4.3 short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.4.4 short to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.4.5 intermittent open squib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.5 diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 6.5.1 low level diagnostic approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.5.2 high level diagnostic approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7 remote sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.1 psi-5 protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.1.1 functional description - remote sensor modes . . . . . . . . . . . . . . . . . . 126 7.1.2 rsu data fields and crc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7.1.3 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 7.2 remote sensor interface fault protection . . . . . . . . . . . . . . . . . . . . . . . . 130 7.2.1 short to ground, current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.2.2 short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 docid025869 rev 3 5/200 l9678, l9678-s contents 6 7.2.3 cross link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 7.2.4 leakage to battery, open condition . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.2.5 leakage to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 7.2.6 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 8 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.1 temporal watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 8.1.1 watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8.1.2 watchdog timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 8.2 watchdog reset assertion timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 8.3 watchdog timer disable input (wdt/tm) . . . . . . . . . . . . . . . . . . . . . . . . 135 9 dc sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10 safing logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.1 safing logic overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 10.2 spi sensor data decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 10.3 in-frame and out-of-frame responses . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.4 safing state machine operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 10.4.1 simple threshold comparison operation . . . . . . . . . . . . . . . . . . . . . . . 148 10.5 safing engine output logic (armxint) . . . . . . . . . . . . . . . . . . . . . . . . . . 149 10.6 arming pulse stretch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 10.7 additional communication line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11 general purpose output (gpo) dr ivers . . . . . . . . . . . . . . . . . . . . . . . . 154 12 iso9141 transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 13 system voltage diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 13.1 analog to digital algorithmic converter . . . . . . . . . . . . . . . . . . . . . . . . . . 162 14 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 15 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.1 configuration and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 15.2 internal analog reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 contents l9678, l9678-s 6/200 docid025869 rev 3 15.3 internal regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.4 oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 15.5 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 15.7 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 15.8 er boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 15.9 er charge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.10 er switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 15.11 covract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.12 vdd5 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 15.13 vdd3v3 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 15.14 vsup regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 15.15 vsf regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 15.16 deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 15.17 squib diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.17.1 squib resistance measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 15.17.2 squib leakage test (vrcm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 15.17.3 high/low side fet test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.17.4 deployment timer test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 15.18 remote sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 15.19 dc sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15.20 safing engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 15.21 general purpose output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 15.22 iso9141 interface (k-line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15.22.1 analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.23 voltage diagnostics (analog mux) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.24 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 16 quality information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 16.1 otp trim bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 17 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 docid025869 rev 3 7/200 l9678, l9678-s list of tables 8 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 3. operative maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. functions disabling by state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5. spi register r/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 6. global spi register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 7. global status word (gsw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 8. short between loops diagnostics decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 9. watchdog timer status description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 33 table 10. records results compare against two threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 11. diagnostics control register (d iagctrlx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 table 12. diagnostics divider ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 table 13. configuration and control dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 table 14. configuration and control ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 15. open ground detection dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 16. open ground detection ac specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 17. internal analog reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 table 18. internal regulators dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 19. internal regulators ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 20. oscillators ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 table 21. temporal watchdog timer ac specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 22. reset dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 23. reset ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 table 24. spi dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 table 25. spi ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 table 26. er boost converter dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 table 27. er boost converter ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 28. er boost converter external components (design in fo) . . . . . . . . . . . . . . . . . . . . . . . . . . 173 table 29. er current generator dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 30. er current generator ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 31. er switch dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 32. er switch ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 table 33. covract dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 75 table 34. covract ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 table 35. vdd5 regulator dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 75 table 36. vdd5 regulator ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 76 table 37. vdd5 regulator external components (design info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 table 38. vdd3v3 regulator dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 39. vdd3v3 regulator ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 40. vdd3v3 regulator external components (design info ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 table 41. vsup regulator dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 78 table 42. vsup ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 43. vsup regulator external components (design info) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 table 44. vsf regulator dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 45. vsf regulator ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 table 46. deployment drivers - dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 table 47. deployment drivers - ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 table 48. deployment drivers diagnostics (squib resistance) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 list of tables l9678, l9678-s 8/200 docid025869 rev 3 table 49. squib leakage test (vrcm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 table 50. high/low side fet test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 51. deployment timer test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 table 52. remote sensor i/f dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 table 53. psi-5 remote sensor transceiver - ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 table 54. dc sensor interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 table 55. arming interface - dc specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 table 56. arming interface - ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 table 57. gpo interface dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 table 58. gpo driver interface - ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 table 59. iso9141 interface dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 table 60. iso9141 interface transceiver ac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 table 61. analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 table 62. voltage diagnostics (analog mux) dc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 table 63. temperature sensor specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 96 table 64. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 docid025869 rev 3 9/200 l9678, l9678-s list of figures 10 list of figures figure 1. pin-out description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 2. functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3. power control state flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 4. wake-up input signal behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 5. normal power-up sequence - w akeup controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 6. normal power-up sequence - vin controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. normal power down sequenc e - wakeup and spi controlled . . . . . . . . . . . . . . . . . . . . . 25 figure 8. normal power down sequence - vin controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 9. system operating state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10. erboost block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 11. erboost control behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12. er cap charging circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 13. er switch control behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 14. vdd5 control behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 15. vdd3v3 control behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 16. vsup control behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 17. vsf control logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 18. internal voltage errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19. reset control diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 20. deployment driver control blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 21. deployment driver control logic - enable signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 22. deployment driver control logic - turn-on signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 23. deployment driver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 24. global spi deployment enable state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 25. deployment loop diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 26. srx pull-down enable logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 27. deployment timer diagnostic sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 28. high level loop diagnostic flow1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 29. high level loop diagnostic flow2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 figure 30. remote sensor interface logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 24 figure 31. remote sensor interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 figure 32. psi-5 remote sensor protocol (10-bit, 1-bit parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 33. manchester bit encodi ng. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 34. manchester decoder state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 figure 35. remote sensor current sensing auto adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 36. watchdog state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 figure 37. watchdog timer refresh diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 38. switch sensor interface block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 figure 39. top level safing engine flow ch art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 figure 40. safing engine - 16-bit message decoding flow char t . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 41. safing engine - 32-bit message decoding flow char t . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 42. safing engine - validate data flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 43. safing engine - combine function flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 44. safing engine threshold comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 figure 45. safing engine - compare complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 45 figure 46. in-frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 47. out of frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 figure 48. safing engine arming flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 50 list of figures l9678, l9678-s 10/200 docid025869 rev 3 figure 49. safing engine diagnostic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 50. arm output control logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 figure 51. pulse stretch timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 figure 52. scrap acl state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 53. disposal pwm signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 figure 54. gpo driver block diagram - ls configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 figure 55. gpo driver block diagram - hs configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 56. iso9141 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 57. adc conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 figure 58. spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 figure 59. deployment drivers diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 figure 60. lqfp64 (10 x 10) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . 198 docid025869 rev 3 11/200 l9678, l9678-s description 199 1 description the l9678 ic is a system chip solution targeted for emerging market applications. base system designs can be completed with the l9678, spc560px microcontroller and an on- board acceleration sensor or psi5 sensor. energy reserve voltage is derived through a co st effective high frequency boost regulator. high frequency operation allows the user to pick up low value and cheap inductance. the voltage is programmable to 23 v or 33 v nominal. battery voltage is sensed through the vba tmon pin providing start-up and shutdown control for the system. once battery voltage drops below the minimum operating voltage, the device enables the integrated crossover switch to permit orderly shutdown. l9678 offers two linear regulators (5 v with external pass transistor and fully integrated 3.3 v). user can use one of these regulators to supply c. input/output pins are compatible with both ranges by dedicated s upply pin vddq. external pass transistor gives the flexibility to easily address different current loads in case of different micro-controllers. one optional 7.2 v linear regulator with external pass transistor can be used to supply remote sensor interface. external acceleration data is received throug h the psi-5 remote sensor interface. both channels have independent decoders. sensor data and diagnostics are available via spi. the safing logic monitors inertial sensors (r emote sensors via psi-5 or on-board sensors via spi) to determine if a crash event is in prog ress, thereby enabling deployment to occur. parameters for sensor configuration and thresholds are user programmable. squib deployment uses four independent high and low side drivers, capable of deploying at 25 v max. diagnostic data control is provided through the spi interface. the hall-effect, resistive or switch sensor interface can be used to determine the state of external switch devices, such as buckle switches, seat track position sensors, weight sensors, deactivation switches. the integrated clock module provides a fixed cl ock signal for the microcontroller. the clock module provides the user the option of del eting the commonly used resonator or crystal. absolute and operative maximum ratings l9678, l9678-s 12/200 docid025869 rev 3 2 absolute and operative maximum ratings 2.1 absolute maximum ratings warning: this part may be irreparably damaged if taken outside the specified absolute maximum ratings. operation above the absolute maximum ratings may also cause a decrease in reliability. table 2. absolute maximum ratings pin # pin name pin function min. max. unit 1 reset reset output -0.3 vddq+0.3 ? 6.5 v 2 spi_miso spi interface data out / safing sensor data in -0.3 vddq+0.3 ? 6.5 v 3 spi_mosi spi interface data in -0.3 vddq+0.3 ? 6.5 v 4 spi_sck spi interface clock -0.3 vddq+0.3 ? 6.5 v 5 spi_cs spi interface chip select -0.3 vddq+0.3 ? 6.5 v 6 wdt/tm watchdog disable (not for application) -0.3 20 v 7 vdd3v3 3.3 v regulator output -0.3 4.6 v 8 nc not connected (1) --- 9 cvdd internal 3.3 v r egulator output -0.3 4.6 v 10 gndd digital ground -0.3 0.3 v 11 sr0 squib 0 low-side pin -0.3 40 v 12 sf0 squib 0 high-side pin -1.0 40 v 13 sg01 squib 0 & 1 deployment ground pin -0.3 0.3 v 14 ss01 squib 0 & 1 deployment supply pin -0.3 40 v 15 sf1 squib 1 high-side pin -1.0 40 v 16 sr1 squib 1 low-side pin -0.3 40 v 17 dcs3 sensor switch interface channel 3 -1.0 40 v 18 dcs2 sensor switch interface channel 2 -1.0 40 v 19 dcs1 sensor switch interface channel 1 -1.0 40 v 20 dcs0 sensor switch interface channel 0 -1.0 40 v 21 vresdiag reserve voltage diagnostic input -0.3 40 v 22 rsu0/nc psi-5 ch. 0 remote sensor output (only l9678-s), nc on l9678 -1.0 40 v 23 rsu1/nc psi-5 ch. 1 remote sensor output (only l9678-s), nc on l9678 -1.0 40 v 24 vsup/nc remote sensor power supply (only l9678-s), nc (1) on l9678 -0.3 40 v docid025869 rev 3 13/200 l9678, l9678-s absolute and operative maximum ratings 199 25 bvsup/nc vsup external transistor control (only l9678-s), nc (1) on l9678 -0.3 40 v 26 gpod0 gpo driver 1 drain output pin -1.0 40 v 27 gpos0 gpo driver 1 source output pin -1.0 40 v 28 gpos1 gpo driver 0 source output pin -1.0 40 v 29 gpod1 gpo driver 0 drain output pin -1.0 40 v 30 nc not connected (1) --- 31 isok iso9141 bus pin (k-line) -18.0 40 v 32 gndsub1 substrate ground -0.3 0.3 v 33 sr3 squib 3 low-side pin -0.3 40 v 34 sf3 squib 3 high-side pin -1.0 40 v 35 ss23 squib 2 & 3 deployment supply pin -0.3 40 v 36 sg23 squib 2 & 3 deployment ground pin -0.3 0.3 v 37 sf2 squib 2 high-side pin -1.0 40 v 38 sr2 squib 2 low-side pin -0.3 40 v 39 gnda analog ground -0.3 0.3 v 40 isorx iso9141 receiver pin -0.3 vddq+0.3 ? 6.5 v 41 isotx iso9141 transmit pin -0.3 vddq+0.3 ? 6.5 v 42 fenl ls driver fet control input -0.3 vddq+0.3 ? 6.5 v 43 fenh hs driver fet control input -0.3 vddq+0.3 ? 6.5 v 44 saf_cs0 spi interface safing se nsor chip select -0.3 vddq+0.3 ? 6.5 v 45 saf_cs1 spi interface safing se nsor chip select -0.3 vddq+0.3 ? 6.5 v 46 nc not connected (1) --- 47 wakeup wake-up control input -0.3 40 v 48 vbatmon battery line voltage monitor -18 40 v 49 vsf safing regulator supply output -0.3 erboost+0.3 ? 40 v 50 vin battery connection -0.3 40 v 51 ver reserve voltage -0.3 40 v 52 erboost energy reserve regulator output -0.3 40 v 53 erbstsw boost switching output -0.3 40 v 54 nc not connected (1) --- 55 bstgnd boost regulator ground -0.3 0.3 v 56 acl eol disposal control input -0.3 40 v 57 bvdd5 vdd5 external transistor control -0.3 40 v 58 nc not connected - - - 59 vdd5 5v regulator output -0.3 6.5 v 60 nc not connected (1) --- table 2. absolute maximum ratings (continued) pin # pin name pin function min. max. unit absolute and operative maximum ratings l9678, l9678-s 14/200 docid025869 rev 3 2.2 operative maximum ratings within the operative ratings the part operates as specified and without parameter deviations once taken beyond the operative ratings and re turned back within, the part will recover with no damage or degradation. additional supply-voltage and temperature conditions are given separately at the beginning of each specification table. 61 covract external crossover switch control -0.3 vddq+0.3 ? 6.5 v 62 vddq i/o supply -0.3 6.5 v 63 arm arming output -0.3 vddq+0.3 ? 6.5 v 64 gndsub2 substrate ground -0.3 0.3 v 1. not connected internally, should be connected to gnd externally. table 2. absolute maximum ratings (continued) pin # pin name pin function min. max. unit table 3. operative maximum ratings pin # pin name pin function min. max. unit 1 reset reset output -0.1 vddq+0.1 ? 5.5 v 2 spi_miso spi interface data out / safing sensor data in -0.1 vddq+0.1 ? 5.5 v 3 spi_mosi spi interface data in -0.1 vddq+0.1 ? 5.5 v 4 spi_sck spi interface clock -0.1 vddq+0.1 ? 5.5 v 5 spi_cs spi interface ch ip select -0.1 vddq+0.1 ? 5.5 v 6 wdt/tm watchdog disable -0.1 20 v 7 vdd3v3 3.3v regulator output -0.1 3.6 v 8 nc not connected (1) --- 9 cvdd internal 3.3v regulator output -0.1 3.6 v 10 gndd digital ground -0.1 0.1 v 11 sr0 squib 0 low-side pin -0.1 ver v 12 sf0 squib 0 high-side pin -1.0 ver v 13 sg01 squib 0 & 1 deployment ground pin -0.1 0.1 v 14 ss01 squib 0 & 1 deployment supply pin -0.1 40 v 15 sf1 squib 1 high-side pin -1.0 ver v 16 sr1 squib 1 low-side pin -0.1 ver v 17 dcs3 sensor switch interface channel 3 -1.0 v dcs_l v 18 dcs2 sensor switch interface channel 2 -1.0 v dcs_l v 19 dcs1 sensor switch interface channel 1 -1.0 v dcs_l v 20 dcs0 sensor switch interface channel 0 -1.0 v dcs_l v 21 vresdiag reserve voltage diagnostic input -0.1 35 v 22 rsu0/nc psi-5 ch. 0 remote sensor output (only l9678-s), nc on l9678 -1.0 vsup v docid025869 rev 3 15/200 l9678, l9678-s absolute and operative maximum ratings 199 23 rsu1/nc psi-5 ch. 1 remote sensor output (only l9678-s), nc on l9678 -1.0 vsup v 24 vsup/nc remote sensor power supply (only l9678-s, nc (1) on l9678) -0.1 vin v 25 bvsup/nc vsup external transistor control (only l9678-s, nc (1) on l9678) -0.1 vin v 26 gpod0 gpo driver 1 drain output pin -0.1 40 v 27 gpos0 gpo driver 1 source output pin -1.0 vin v 28 gpos1 gpo driver 0 source output pin -1.0 vin v 29 gpod1 gpo driver 0 drain output pin -0.1 40 v 30 nc not connected (1) --- 31 isok iso9141 bus pin -1.0 40 v 32 gndsub1 substrate ground -0.1 0.1 v 33 sr3 squib 3 low-side pin -0.1 ver v 34 sf3 squib 3 high-side pin -1.0 ver v 35 ss23 squib 2 & 3 deployment supply pin -0.1 40 v 36 sg23 squib 2 & 3 deployment ground pin -0.1 0.1 v 37 sf2 squib 2 high-side pin -1.0 ver v 38 sr2 squib 2 low-side pin -0.1 ver v 39 gnda analog ground -0.1 0.1 v 40 isorx iso9141 receiver pin -0.1 vddq+0.1 ? 5.5 v 41 isotx iso9141 transmit pin -0.1 vddq+0.1 ? 5.5 v 42 fenl ls driver fet control input -0.1 vddq+0.1 ? 5.5 v 43 fenh hs driver fet control input -0.1 vddq+0.1 ? 5.5 v 44 saf_cs0 spi interface safing se nsor chip select -0.1 vddq+0.1 ? 5.5 v 45 saf_cs1 spi interface safing se nsor chip select -0.1 vddq+0.1 ? 5.5 v 46 nc not connected (1) --- 47 wakeup wake-up control input -0.1 vin v 48 vbatmon battery line voltage monitor -0.1 18 v 49 vsf safing regulator supply output -0.1 27 v 50 vin battery connection -0.1 35 v 51 ver reserve voltage -0.1 35 v 52 erboost energy reserve regulator output -0.1 35 v 53 erbstsw boost switchin g output -0.1 erboost+1 v 54 nc not connected (1) --- 55 bstgnd boost regulator ground -0.1 0.1 v 56 acl eol disposal control input --0.1 40 v 57 bvdd5 vdd5 external transistor control -0.1 vin v table 3. operative maximum ratings (continued) pin # pin name pin function min. max. unit absolute and operative maximum ratings l9678, l9678-s 16/200 docid025869 rev 3 2.3 pin-out description the l9678-s/l9678 pin-out is shown below. the package is a lqfp 64-pin full plastic package. figure 1. pin-out description 58 nc not connected (1) --- 59 vdd5 5v regulator output -0.1 5.5 v 60 nc not connected (1) --- 61 covract external crossover switch control -0.1 vddq+0.1 ? 5.5 v 62 vddq i/o supply -0.1 5.5 v 63 arm arming output -0.1 vddq+0.1 ? 5.5 v 64 gndsub2 substrate ground -0.1 0.1 v 1. not connected internally, should be connected to gnd externally. table 3. operative maximum ratings (continued) pin # pin name pin function min. max. unit 6 5 6 * , 6 2 7 ; ) ( 1 / ) ( 1 + 6 $ ) b & 6 6 $ ) b & 6 1 & : $ . ( 8 3 9 % $ 7 0 2 1 , 6 2 5 ; * 1 ' $ 6 5 6 ) 6 6 6 ) ' & 6 ' & 6 ' & 6 ' & 6 * 1 ' 6 8 % $ 5 0 9 ' ' 4 & 2 9 5 $ & 7 9 ' ' ( 5 % 6 7 6 : ( 5 % 2 2 6 7 9 ( 5 1 & % 6 7 * 1 ' $ & / % 9 ' ' 1 & 1 & 9 , 1 9 6 ) 9 5 ( 6 ' , $ * 5 6 8 1 & 5 6 8 1 & 9 6 8 3 1 & % 9 6 8 3 1 & * 3 2 ' * 3 2 6 * 3 2 6 * 3 2 ' 1 & , 6 2 . * 1 ' 6 8 % 5 ( 6 ( 7 6 3 , b 0 , 6 2 6 3 , b 0 2 6 , 6 3 , b 6 & . , 6 3 , b & 6 : ' 7 7 0 9 ' ' 9 1 & & 9 ' ' * 1 ' ' 6 5 6 ) 6 * 6 6 6 ) 6 5 * $ 3 * 3 6 7 k r v h s l q v d u h 1 & l q w k h / y h u v l r q 1 r w f r q q h f w h g l q w h u q d o o \ v k r x o g e h f r q q h f w h g w r * 1 ' h [ w h u q d o o \ docid025869 rev 3 17/200 l9678, l9678-s overview and block diagram 199 3 overview and block diagram the l9678 is a unique solution specifically targeted for entry level airbag systems while permitting the system designer significant flexibility in co nfiguring the system power and management block. the configurable methodol ogy allows cost versus performance trade- off without changing devices or circuit board designs. the l9678 contains the base functionality required for entr y level systems and can comple te a system design with a microcontroller and acceleration sensor. th e high level block diagram is shown below figure 2 . basic features include a configurable power supply & management block, 4 channel squib drivers, 2 channel hs/ls gpo drivers, 4 channel sensor interface, safing logic, watchdog timer, iso9141 communications and temperat ure sensor. the l9678-s device is pin compatible to the l9678 and includes two psi-5 remote sensor interface channels and a dedicated regulator for remote sensor. overview and block diagram l9678, l9678-s 18/200 docid025869 rev 3 figure 2. functional block diagram 6 6 6 ) 6 * 6 t x l e g u l y h u v d q g ' l d j q r v w l f 2 s w l r q d o / 6 9 e d w 9 , 1 ( 5 % 6 7 6 : 9 ( 5 ( 5 % 2 2 6 7 9 % d w 0 r q 9 ' ' % 6 7 * 1 ' 6 d i l q j u h j x o d w r u p ) w r p ) % 9 ' ' 9 ' ' 9 9 6 8 3 % 9 6 8 3 9 ' ' 4 9 6 ) 9 5 ( 6 ' , $ * : $ . ( 8 3 9 , j q * 3 2 ' 6 6 * 1 ' ' * 1 ' $ ( q d e o h & r q w u r o 6 d w h o o l w h ' u l y h u ' h f r g h u ' h f r g h u 5 6 8 6 3 , b & 6 6 $ ) b & 6 6 $ ) b & 6 6 3 , b 0 , 6 2 6 3 , b 6 & . 6 3 , b 0 2 6 , 5 ( 6 ( 7 : ' 7 ' , 6 7 0 $ & / ) ( 1 / , 6 2 7 ; , 6 2 5 ; , 6 2 . * 1 ' , 6 2 * 1 ' 6 8 % [ * 1 ' 6 8 % 9 e d w ) ( 1 + $ 5 0 6 6 ? + $ q ) ) n n 5 6 8 ' & 6 ' & 6 ' & 6 ' & 6 & 9 ' ' q ) 6 * 6 ) 6 ) 6 ) 6 5 6 5 6 5 6 5 q ) q ) * 3 2 ' * 3 2 6 * 3 2 6 q ) q ) x & b ) / ( 1 q ) ? ) q ) ) ) % & 3 % & 3 q ) 9 ' ' o l q h d u u h j x o d w r u / 6 9 6 8 3 o l q h d u u h j x o d w r u ' l j l w d o e o r f n 9 , 1 7 9 u h j i r u d q d o r j e o r f n v ' l j l w d o 2 x w s x w v & 9 ' ' u h j i r u g l j l w d o e o r f n v 9 ' ' 9 o l q h d u u h j ( 5 % r r v w ( 5 6 z l w f k ( 5 & k d u j h * 3 2 g u l y h u v v x s s o \ + 9 d q d o r j 0 8 ; d q g $ w r ' f r q y h u w h u e l w v ( q d e o h & r q w u r o ' & + d o o v h q v r u l q w h u i d f h , 6 2 w u d q v f h l y h u 6 \ v w h p f r q w u r o f r q i l j x u d w l r q 6 d i l q j / r j l f q ) & 2 9 5 $ & 7 x ) x ) ' ! 0 ' 0 3 docid025869 rev 3 19/200 l9678, l9678-s start-up power control 199 4 start-up power control 4.1 power supply overview the l9678 ic contains a complete power management system able to provide all necessary voltages for an entry level airbag applicatio n. moreover l9678 power supply is user configurable allowing the design engineer to balance cost and performance per their particular application. the power supply block contains the following features: ? two 3.3 v internal regulators for operating internal logic (cvdd) and analog circuits (vint3v3). an external cvdd pin is used to provide filtering capacitance to digital section supply rail. ? energy reserve supply (erboost) achieved through an integrated switching boost regulator. the design of this boost regulator is intended to be a cost effective solution with respect to traditional boost regulators because it makes use of a low value inductor with an operative frequency of 1. 882 mhz. switching output is erbstsw pin, while voltage feedback input pin is erboost. the output voltage could be set to either 23 v5% or 33 v5%. ? energy reserve capacitor connected to ver pi n. to control in-rush current, a dedicated current generator is implemented between erboost pin and ver pin. ? capability to drive an external safing fet (n-ch type) by means of an internal voltage regulator on vsf pin, where a 20 v level is given (configurable to 25v via spi command). ? the integrated current limited er switch requ ires no external components. this switch is controlled through the integrated power control state machine and is enabled either once a loss of battery is detected or a shutdown command is received. under the same conditions also the discrete digital pin covr act is activated allowing the control of an external optional cross-over switch. ? one linear regulator vdd5 (5 v nominal, 4% tolerance) requiring external power transistor and capacitors. vdd5 is used as micro-controller supply (in case of 5 v family controllers) and, in any ca se, as supply for vdd3v3 rail. ? one integrated linear regula tor vdd3v3 (3.3 v nominal, 4% tolerance) requiring external capacitors. vdd3v3 is used as micro- controller supply (in case of 3.3 v family controllers). ? vddq pin to provide output voltage rail refe rence. vddq could be connected to either vdd5 or vdd3v3 to enable 5 v or 3.3 v digital communication between device and micro-controller. ? capability to drive an external power transi stor connected to vin to provide a 7.2 v rail on vsup pin. this voltage rail could be used to supply psi-5 remote sensor. ? battery voltage sense input comparator wit h hysteresis connected to vbatmon pin. power-up and operation states are carefully handled with respect to the battery level to provide the most effective power supply configuration. ? all voltage rails (vin, erboost, ver, vresdiag, vdd5, vdd3v3, vsup and vsf) can be monitored through internal adc diagnostics. start-up power control l9678, l9678-s 20/200 docid025869 rev 3 4.2 power mode control start-up and power down of t he l9678 are co ntrolled by the wakeup pin, vbatmon pin, vin pin device status and the spi interface. there are four main power modes: power-off, sleep, active and passive mode. each power mode is described below and repr esented in the state flow diagram shown in figure 3 . the descriptions include references to conditions and sometimes nominal values. the absolute values for each condition are lis ted in the electrical specifications section. figure 3. power control state flow diagram ' ! 0 ' 0 3 3 2 : ( 5 2 ) ) 0 2 ' ( $ o o v x s s o l h v g l v d e o h g 3 $ 6 6 , 9 ( 0 2 ' ( $ & 7 , 9 ( 0 2 ' ( 6 / ( ( 3 0 2 ' ( 3 2 : ( 5 2 ) ) v w d w h : $ . ( 8 3 0 2 1 , 7 2 5 v w d w h $ : $ . ( 6 w d w h : $ . ( 8 3 ! : 8 b r q 6 7 $ 5 7 8 3 v w d w h 5 8 1 v w d w h ( 5 v w d w h 9 % $ 7 p r q ! 9 % * 2 2 ' e o d q n l q j w l p h p v : $ . ( 8 3 ! : 8 b p r q : $ . ( 8 3 : 8 b p r q > : $ . ( 8 3 : 8 b r i i $ 1 ' : d n h 8 s ) l o w @ : d n h 8 s ) l o w $ 1 ' 9 , 1 ! 9 , 1 * 2 2 ' 9 , 1 9 , 1 * 2 2 ' : d n h 8 s ) l o w 2 5 9 , 1 9 , 1 % $ ' 7 z d n h x s ! p v : d n h 8 s ) l o w $ 1 ' 3 2 : ( 5 0 2 ' ( 6 + 8 7 ' 2 : 1 v w d w h 9 , 1 9 , 1 * 2 2 ' : d n h 8 s ) l o w $ 1 ' 6 3 , b 6 / ( ( 3 : d n h 8 s ) l o w $ 1 ' 6 3 , b 6 / ( ( 3 : d n h 8 s ) l o w $ 1 ' 9 , 1 ! 9 , 1 * 2 2 ' 3 2 5 ) u r p d q \ v w d w h 7 z d n h x s 7 l p h u & o h d u h g l i 6 w d w h : $ . ( 8 3 0 2 1 , 7 2 5 r u $ : $ . ( d q g : d n h 8 s ) l o w docid025869 rev 3 21/200 l9678, l9678-s start-up power control 199 4.2.1 power_off mode during the power-off mode all supplies are disabled keeping the system in a quiescent state with very low current draw from battery. as soon as wakeup > wu_mon the ic will move to sleep mode. 4.2.2 sleep mode during the sleep mode the vint3v3 and cvdd internal regulators are turned on and the ic is ready for full activation of all the other s upplies. as soon as battery voltage is over a minimum threshold, all the other supplies are turned on and the ic enters the active mode. 4.2.3 active mode this is the normal operating mode for the system. all power supplies are enabled and the energy reserve boost converter starts to increase the voltage at erboost. likewise, the vdd5 regulator is turned on. once the vdd5 has reached a good value, the vdd3v3 regulator starts up. once the vdd3v3 regulator is in regulation, reset is released allowing the syst em microcontroller and other components to begin their power-on sequence. among these, al so the er charge current generator can be enabled by the microcontroller via a dedicated spi command. the active mode can be left when either wa keup pin or vin voltage drop down. for the very first 9 ms after havi ng entered the ac tive mode, the wakeup pin low would immediately cause the ic to switch back to sleep mode. af ter that time, wakeup pin low must be first confirmed by a mcuspi_sleep co mmand prior to cause the system to switch to passive mode. passive mode is also entered in case of vin voltage low. 4.2.4 passive mode in this state, the energy reserve charge current is disabled and the erboost boost converter is disabled only if the sys_cfg(keep_erbst_ on)=0. when in passive mode the device automatically activates both the covract output pin and the integrated er switch to allow vin to be connected to the er capacitor. in this time, vin is supposed to be increased up to almost ver level and the syst em operation relies on energy from the er capacitor. two scenarios are possible: high or low battery. if vin < vingood, the device moved from run state in active mode to the er state. here, the er capacitor is depleted while supplying all the regulators until the por on internal regulator occurs. the threshold to decide the er switch activation is based on vin, because vin is the supply voltage rail for all regulators. if the device has still a good battery level, it entered the powermode shutdown thanks to wakeup pin and mcu co mmand to switch off. in this case, the ver node will be discharged down to approx imately vin level, which then will be supplied out of the battery line. system will continue to run up to a dedicated spi command which will lead the device to enter the poweroff state. the wake-up pin is filtered to suppress undesired state changes resulting from transients or glitches. typical conditions are shown in the chart below and summarized by state. start-up power control l9678, l9678-s 22/200 docid025869 rev 3 figure 4. wake-up input signal behaviour condition summary: 1. no change of sleep mode state but current consumption may exceed specification for sleep mode. 2. the sleep mode current returns within the specified limits. 3. power supply exits sleep mode. switchers start operating if applicable voltages exceed under voltage lockouts. as t wakeup time-out is not elapse d, a low level at wakeup instantaneously sends the system back to sleep. 4. sleep reset is released and the entire system starts operating. a spi command to enter sleep state would be ignored. 5. no change in system status, a spi command to enter sleep state would be ignored. 6. no change in system status, but a spi command to turn off switchers would be accepted and turn the system off. with the below table, all the functionalities of the device are shown wit h respect of the power states. when one function is flag ged, the related circuitry cannot be activated on that state. ' ! 0 ' 0 3 : $ . ( 8 3 w p v p v p v p v p v 6 / ( ( 3 0 2 ' ( $ & 7 , 9 ( 0 2 ' ( 3 $ 6 6 , 9 ( 0 2 ' ( : 8 b r q : 8 b r i i : d n h 8 s ) l o w w table 4. functions disabling by state function power off wake-up monitor awake start-up run power mode shutdown er wakeup detector x - - - - - - internal regulator x x - - - - - erboost regulator x x x - - x x vsup regulator (l9678-s only) x x x - - - - er cap charge current source x x x - - x x er switch x x x x x - - covract output x x x x x - - vdd5 regulator x x x - - - - vdd3v3 regulator x x x - - - - deployment drivers x x x - - - - vsf safing fet regulator x x x - - - - remote sensor interfaces (l9678-s only) xx x - - - - docid025869 rev 3 23/200 l9678, l9678-s start-up power control 199 4.2.5 power-up and power-down sequence the behavior of the ic during normal power-up and power-down is shown in figure 5 to figure 8 . the following sequences represent just a subset of all possible power-up and power-down scenarios. in figure 5 a normal ic power-up c ontrolled by the state of the wakeup pin is shown. figure 5. normal power-up sequence - wakeup controlled watchdog x x x - - - - diagnostics x x x - - - - dc sensor interface x x x - - - - gpo drivers x x x - - - - safing logic x x x - - - - iso9141 x x x - - - - table 4. functions disabling by state (continued) function power off wake-up monitor awake start-up run power mode shutdown er 9 , 1 f x u u h q w 9 % $ 7 9 % $ 7 p r q : $ . ( 8 3 9 , 1 7 & 9 ' ' 3 2 5 ( 5 % 2 2 6 7 : 8 b p r q : 8 b r q 9 ' ' 9 ' ' 9 9 ' ' 9 b 8 9 5 ( 6 ( 7 5 ( 6 ( 7 + r o g 7 l p h 6 3 , ( 5 f k d u j h r q 9 ( 5 9 % * 2 2 ' * $ 3 * 3 6 start-up power control l9678, l9678-s 24/200 docid025869 rev 3 figure 6. normal power-up sequence - vin controlled two different scenarios for power-down of the ic are here below shown. figure 7 describes the powering down for the case when wakeup pin is released. as soon as a spi_sleep command is received by the mcu the system will immediately move to the energy reserve (passive mode). in figure 8 , vin release begins the shutdown process. 9 , 1 f x u u h q w 9 % $ 7 9 , 1 : $ . ( 8 3 9 , 1 7 & 9 ' ' 3 2 5 ( 5 % 2 2 6 7 : 8 b p r q : 8 b r q 9 ' ' 9 ' ' 9 9 ' ' 9 b 8 9 5 ( 6 ( 7 5 ( 6 ( 7 + r o g 7 l p h 6 3 , ( 5 f k d u j h r q 9 ( 5 9 , 1 * 2 2 ' * $ 3 * 3 6 docid025869 rev 3 25/200 l9678, l9678-s start-up power control 199 figure 7. normal power down sequence - wakeup and spi controlled : $ . ( 8 3 3 2 5 : 8 b r i i 9 ' ' 9 ' ' 9 9 ' ' 9 8 9 5 ( 6 ( 7 9 ( 5 9 % $ 7 9 % $ 7 0 2 1 9 % % $ ' 9 % * 2 2 ' : 8 b r q 6 3 , b 6 / ( ( 3 f r p p d q g 6 3 , 6 3 , b 2 ) ) f r p p d q g 7 k l v s h u l r g r i w l p h f d q e h k r o g i r u o r q j w l p h e h f d x v h e d w w h u \ l v j r r g 7 k h v \ v w h p z d l w v x q w l o d g h g l f d w h g i u d p h w r v z l w f k r i i ( 5 6 z l w f k h q d e o h & 2 9 5 $ & 7 9 , 1 7 & 9 ' ' 9 , 1 7 & 9 ' ' 8 9 * $ 3 * 3 6 start-up power control l9678, l9678-s 26/200 docid025869 rev 3 figure 8. normal power down sequence - vin controlled 4.2.6 operating states different states can be identified while oper ating the device. these states allow safe and predictable initialization, test, operation and end of line disposal of the part (scrapping). as soon as the reset signal is de-asserte d at the beginning of the active mode, the microcontroller powers up. at this stage, l9678 is in the init state: during this state the device must be initialized by the controller. in particular, th e watchdog timer window can be programmed during this state. when the watchdog service begins (upon the first successful watchdog feed), the device switches to diag state for diagnostics purposes. the remaining configuration of the device is allowed in this state, in particular for sa fing records and deploym ent masks. several tests are also enabled while in this state and all thes e tests are mutually exclusive to one another. hs and ls switch tests of the squib drivers c an only be processed during this diag state. also high side safing fet can only be run during this state. when not in diag state, any 9 , 1 7 & 9 ' ' 3 2 5 9 ' ' 9 ' ' 9 9 ' ' 9 8 9 5 ( 6 ( 7 9 % $ 7 : $ . ( 8 3 9 , 1 9 , 1 * 2 2 ' ( 5 6 z l w f k h q d e o h & 2 9 5 $ & 7 9 ( 5 9 , 1 7 & 9 ' ' 8 9 * $ 3 * 3 6 docid025869 rev 3 27/200 l9678, l9678-s start-up power control 199 commands for squib driver swit ch tests will be ignored. other checks are also performed: on the arming output to check for no n stuck-at conditions on the pin and for the configured firing time. the ssm remains in this state until commanded to transition into the safing state or scrap state via the dedicated spi commands. upon reception of the safing_state command while in diag state, the device enters safing state. this is the primary run-time stat e for normal operation, and the logic performs the safing function, including monitoring of s ensor data and setting of the arm signal. the only means of exiting safing state is by the assertion of the ssm_reset signal. the scrap state is entered upon reception of the scrap_state command while in diag state. while in scrap state, the part allows the main microcontroller to in itiate a transition to arming state, and monitoring of the remote sensor spi interface (in l9678-s) and the safing logic is disabled. from scrap state, t he device can transition to arming state only, and the only means of moving back to init state is through an ssm_reset. in order to protect from inadvertent entry in to arming state, and to prevent undesired activation of the safing signals, a dedicated me chanism is used to control entry into, and exit from arming state. this mechanism is described further in section 10.7: additional communication line . while in arming state, the arming output is asserted. exit from arming state occurs when the time-out is reached wit hout a correct acl signal or when ssm_reset is asserted. upon exit, the device re-enters sc rap state, except for the case of ssm_reset, which results in entry into init state. system operating states are shown in figure 9 . figure 9. system operating state diagram ' ! 0 ' 0 3 # o n f i g u r a t i o n e n a b l e d f o r 7 a t c h d o g t i m i n g t h r e s h o l d s ! 2 - i n o u t s e l e c t 2 3 5 o u t p u t t y p e ' m 3 7 $ i a g s a m p l e s e l e c t 6 3 & v o l t a g e s e l e c t ! 2 - 6 3 & d e t e r m i n e d b y s a f i n g e n g i n e 3 3 - 2 e s e t 7 $ / 6 % 2 2 ) $ % 3 0 ) 3 ! & ) . ' ? 3 4 ! 4 % 3 0 ) 3 # 2 ! 0 ? 3 4 ! 4 % 7 $ 2 5 . ) n i t 3 t a t e $ i a g 3 t a t e 3 a f i n g 3 t a t e 3 c r a p 3 t a t e ! r m i n g 3 t a t e ! # , ' / / $ ! # , " ! $ ! 2 - x 6 3 & ! 2 - x 6 3 & 4 e s t i n g e n a b l e d f o r ! 2 - x 6 3 & $ e p l o y t i m e ( 3 , 3 ( 3 3 & % 4 # o n f i g u r a t i o n e n a b l e d f o r 3 a f i n g r e c o r d s a n d c o n t r o l $ e p l o y m a s k ( 3 , 3 ' 0 / start-up power control l9678, l9678-s 28/200 docid025869 rev 3 4.3 configurable s ystem power control the overall operating voltage requirements of the device are different considering the l9678 device (without vsup regulator and remote sensor interface) or the l9678-s device (with vsup regulator and remote sensor interface). performance for the l9678-s device is influenced by the psi-5 remote sensor interfac es. this function requires a minimum voltage at the channel's input (vsup) to ensure a proper functionality for the sensor. an integrated current generator (30 ma nominal) is used to charge the external energy reserve capacitor connected to ver pin. any system load (regulators, interfaces, squib driver diagnostics) operate directly from batter y until battery is lost . upon detecting low or loss of battery, the crossover switch en ables operation from energy reserve. 4.3.1 erboost switching regulator the l9678 ic uses an advanced energy reserve switching regulator operating at 1.882 mhz nominal. the higher switching frequency enables the user to select smaller less expensive inductors and moves the operating frequency to permit easier compliance with system emissions. the energy reserve boost regulator charges the external system tank capacitor through an integrated fixed current source significantly re ducing in-rush currents typical of large energy reserve capacitors. the boost circuit provid es energy for the reserve capacitor with assumed run time load of less than 20 ma and to the vsf regulator. once system shutdown is initiated or a loss of battery condition is diagnosed, the boost regulator is disabled so that system power can be taken from the energy reserve capacitor. the energy reserve boost regulator defaults to 23 v at power-on and can be set to 33 v nominal by the user through an spi command. th e boost converter can also be disabled by the user through an spi command. enabling, disabling and setting the boost output voltage is done through the sy stem control (sys_ctl) register . boost converter diagnostics include over voltage and under voltage. the under voltage condition is reported by the er_bst_nok bit in the power_state register . the integrated fet featuring the boost switch is protected against short to battery by means of a thermal shutdown circuit. when thermal fault is detected the fe t is switched off and latched in this state until the related fault flag erbst_ot in the fltsr register is read. in case of loss of ground the fet is switched off and automatically reactivated as soon as ground connection is restored. over- voltage protection from load dump and inductive flyback is provided via an active clamp and an er_boost disable circuitry, see figure 10 . figure 10. erboost block diagram * $ 3 * 3 6 & r p s ( 5 % 6 7 ' u l y h u & r q w u r o & / $ 0 3 h q d e o h ( 5 % 6 7 6 : ( 5 % 2 2 6 7 % 6 7 * 1 ' & / $ 0 3 b ( 1 7 + ( 5 % 6 7 b ' , 6 $ % / ( 7 + 9 , 1 docid025869 rev 3 29/200 l9678, l9678-s start-up power control 199 normal run time power for the syst em is provided directly from the battery input, not from the boost. boost energy is available to the system through the energy reserve crossover switch once battery is lost or a commanded system sh utdown is initiated. by default, the erboost regulator is switched off once enetered in pass ive mode. to keep active the erboost also in passive mode the spi bit sys_cfg( keep_erbst_on) must be set to 1. figure 11. erboost control behaviour 4.3.2 energy reserve capacitor charging circuit the energy reserve capacitor connected to ve r pin can be charged in an efficient way by means of a current generator. its capability is 30 ma no minal, so that fo r example a 2.2 mf capacitor can be charged in approximately 2 s to 24 v. the current generator is activated or deactivated by spi command only while in active mode. when not in active mode, the generator is always switched off in order to decouple erboost node voltage from ver reserve voltage. figure 12. er cap charging circuit ' ! 0 ' 0 3 ( 5 % 6 7 2 1 $ f w l y h b p r g h $ 1 ' 9 % $ 7 0 2 1 ! 9 % * 2 2 ' $ 1 ' 9 , 1 ! 9 , 1 * 2 2 ' $ 1 ' 6 < 6 b & 7 / ( 5 b % 6 7 b ( 1 $ 1 ' * 1 ' % 2 2 6 7 b o r v v $ 1 ' ( 5 % 6 7 b 2 7 $ 1 ' ( 5 % 6 7 b ' , 6 $ % / ( ' h i d x o w 6 < 6 b & 7 / ( 5 b % 6 7 b ( 1 d w 3 2 5 ( 5 % 2 2 6 7 s r z h u p r g h f r q w u r o ( 5 % 6 7 2 ) ) ( 5 % 6 7 b 2 7 ( 5 % 6 7 2 7 6 3 , b ) / 7 6 5 5 ( $ ' $ 1 ' ( 5 % 6 7 b 2 7 ( 5 % 6 7 6 7 % < 6 3 , b 6 < 6 b & 7 / ( 5 b % 6 7 b ( 1 $ 1 ' ( 5 % 6 7 b 2 7 3 2 : ( 5 2 ) ) b 0 2 ' ( 2 5 6 / ( ( 3 b 0 2 ' ( > $ f w l y h b p r g h 2 5 9 % $ 7 0 2 1 9 % % $ ' $ 1 ' ( 5 b v w d w h 2 5 6 < 6 b & ) * . ( ( 3 b ( 5 % 6 7 b 2 1 @ 2 5 9 , 1 9 , 1 % $ ' 2 5 6 < 6 & 7 / ( 5 b % 6 7 b ( 1 2 5 * 1 ' % 2 2 6 7 b o r v v 2 5 ( 5 % 6 7 b ' , 6 $ % / ( ' ! 0 ' 0 3 ( 5 b f k d u j h b 2 1 ( 5 b f k d u j h b 2 1 $ f w l y h b p r g h $ 1 ' 6 < 6 b & 7 / ( 5 b & 8 5 b ( 1 ' h i d x o w 6 < 6 b & 7 / ( 5 b & 8 5 b ( 1 d w 6 6 0 b 5 ( 6 ( 7 $ f w l y h b p r g h 2 5 6 < 6 b & 7 / ( 5 b & 8 5 b ( 1 ( 5 & $ 3 f k d u j h f r q w u r o 6 6 0 b 5 h v h w start-up power control l9678, l9678-s 30/200 docid025869 rev 3 4.3.3 er switch and covract pin l9678 has an integrated circuit that c an operate as a crossover switch with r ds(on) = 1.5 ? nominal. the er switch is automatically activated up on entering the passive mode. voltage difference between vin and ver is monitored in order to prevent ver back-feeding when vin exceeds ver by 0.1v max. the er s witch is automatically deactivated upon the above mentioned overvoltage detection. the er control implements a thermal protection and a current limitation guard to avoid in-rush charge current at er switch enabling or at fault condition for short to ground. during passive mode the discrete digital output pin covract is activated to allow for extern al optional cross-over switch control. figure 13. er switch control behaviour ' ! 0 ' 0 3 3 d v v l y h b p r g h $ 1 ' ( 5 b 6 : b 2 9 3 d v v l y h b p r g h 2 5 ( 5 b 6 : b 2 9 ( 5 b v z l w f k b 2 1 ( 5 b v z l w f k b 2 ) ) 3 2 5 ( 5 b v z l w f k b 2 ) ) b 2 7 7 7 l p h r x w ( 5 b 6 : b 2 9 l i 9 , 1 9 ( 5 9 ( 5 b v z l w f k b 6 7 % < 6 w d u w 7 p v ( 5 b 6 : , 7 & + b 7 6 ' ( 5 b 6 : , 7 & + b 7 6 ' $ 1 ' 3 g h s o r \ p h q w q r w l q s u r j u h v v ( 5 b 6 : , 7 & + b 7 6 ' $ 1 ' 3 g h s o r \ p h q w q r w l q s u r j u h v v 3 ' h s o r \ p h q w l q s u r j u h v v docid025869 rev 3 31/200 l9678, l9678-s start-up power control 199 4.3.4 vdd5 linear regulator the vdd5 linear regulator provides 5 v system voltage derived directly from battery line with an external power transistor to reduce in tegrated circuit power dissipation. this voltage rail is used in case a 5 v micro-controller is adopted. the stab ility of the regulation loop is guaranteed by use of a small external capacitor. current limitation is provided by means of controlling output current on bvdd5 pin. the exte rnal pass transistor gives the flexibility to easily address different current loads in case of different micro-controllers. the vdd5 regulator is enabled in the active mode and continues operation in the passive mode using power from energy reserve. vdd5 supply is monitored for system reset (see power on reset and reset); voltage monitoring is based on a second redundant bandgap voltage reference. figure 14. vdd5 control behavior ' ! 0 ' 0 3 9 ' ' b u d p s x s 6 w d u w 7 p v 9 ' ' b 8 9 6 ' p d v n l q j 9 ' ' b 2 ) ) & o h d u 9 ' ' b 2 9 $ & 7 , 9 ( b 0 2 ' ( 2 5 3 $ 6 6 , 9 ( b 0 2 ' ( 9 ' ' b 2 1 9 ' ' 6 + 8 7 ' 2 : 1 6 w d u w 7 p v / d w f k 9 ' ' b 2 9 9 ' ' b 8 9 / 2 5 9 ' ' b 2 9 2 5 9 ' ' 9 b 2 9 7 w l p h r x w 9 ' ' b 8 9 / $ 1 ' 7 w l p h r x w 9 ' ' s r z h u p r g h f r q w u r o 3 2 : ( 5 2 ) ) b 0 2 ' ( 2 5 6 / ( ( 3 b 0 2 ' ( 9 ' ' b 8 9 6 ' $ 1 ' 7 w l p h r x w 2 5 9 ' ' b 2 9 start-up power control l9678, l9678-s 32/200 docid025869 rev 3 4.3.5 vdd3v3 linear regulator the fully integrated vdd3v3 linear regulator pr ovides 3.3 v system voltage derived directly from vdd5. this voltage rail is used in case a 3.3 v micro-controller is adopted. the stability of the regulation loop is guaranteed by use of a small external capacitor. current limitation is implemented and its maximum current cap ability on vdd3v3 is 125 ma. the vdd3v3 regulator is enabled in the active mode and continues operation in the passive mode using power from energy reserve. vdd3v3 supply is monitored for system reset (see power on reset and reset); voltage monitoring is based on a second redundant bandgap voltage reference. note that if the vddq pin (digital outputs supply) is connected to the vdd3v3, and any of the digital output pins are connected to 5 v l ogic, there is no internal blocking diode to prevent back-feeding this 3.3 v supply. figure 15. vdd3v3 control behaviour ' ! 0 ' 0 3 9 ' ' 9 2 ) ) , q 9 ' ' b 2 1 v w d w h 9 ' ' 9 b 2 1 9 ' ' 9 6 + 8 7 ' 2 : 1 6 w d u w 7 p v 1 r w l q 9 ' ' b 2 1 v w d w h 7 w l p h r x w 9 ' ' 9 s r z h u p r g h f r q w u r o 3 2 : ( 5 2 ) ) b 0 2 ' ( 2 5 6 / ( ( 3 b 0 2 ' ( docid025869 rev 3 33/200 l9678, l9678-s start-up power control 199 4.3.6 vsup linear re gulator (optional) the vsup linear regulator can be used to prov ide 7 v derived directly from battery line with an external power transistor. this voltage rail can be used mainly to supply psi-5 remote sensor interface. the stability of the regulation loop is guaranteed by use of a small external capacitor. current limitation is provided by means of co ntrolling output current on bvsup pin. the external pass transistor gives the flex ibility to easily address different current loads. the vsup regulator is enabled in the acti ve mode and continues operation in the passive mode using powe r from energy reserve. in the ca se of l9678 (no remote sensor interfaces), vsup can be externally connected to ground. figure 16. vsup control behavior 4.3.7 vsf linear regulator the fully integrated vsf linear regulator provides a 20v voltage nominal (configurable to 25v via spi command) derived directly from erboost. this voltage rail is used in case an external n-ch safing fet has to be used. the stability of the regulation loop is guaranteed by use of a small external capacitor. current limitation is implemented. a minimum drop-out of 2v between erboost and vsf is needed. vsf is enabled by the assertion of any armxint signal, or by the assertion of (fenh and not (fenl)), as shown in figure 17 ' ! 0 ' 0 3 9 6 8 3 u d p s x s 6 w d u w 7 p v 9 6 8 3 b 8 9 p d v n l q j 9 6 8 3 2 ) ) $ & 7 , 9 ( b 0 2 ' ( 2 5 3 $ 6 6 , 9 ( b 0 2 ' ( $ 1 ' 6 < 6 b & 7 / 9 6 8 3 b ( 1 9 6 8 3 b 2 1 9 6 8 3 6 + 8 7 ' 2 : 1 6 w d u w 7 p v 9 6 8 3 b 8 9 7 w l p h r x w 9 6 8 3 b 8 9 $ 1 ' 7 w l p h r x w 9 6 8 3 b 8 9 $ 1 ' 7 w l p h r x w 9 6 8 3 s r z h u p r g h f r q w u r o 3 2 : ( 5 2 ) ) b 0 2 ' ( 2 5 6 / ( ( 3 b 0 2 ' ( ' h i d x o w 6 < 6 b & 7 / 9 6 8 3 b ( 1 d w 3 2 5 6 < 6 b & 7 / 9 6 8 3 b ( 1 start-up power control l9678, l9678-s 34/200 docid025869 rev 3 figure 17. vsf control logic 4.4 reset functions the device provides reset logic to safely cont rol system operation in the event of internal ecu failures. several internal reset signals are generated depending on the type of failure detected. in the following figure, the voltage monitoring diagram is shown. bg_err reports error on the bandgap reference voltage, vreg_err reports errors on any of the internal regulators (vint3v3 for 3.3 v analog circuitry, cvdd for 3.3 v digital circuitry), vdd3v3_err and vdd5_err report errors on vdd3v3 and vdd5 regulators, respectively. figure 18. internal voltage errors ' ! 0 ' 0 3 ! 2 - ) . 4 ! 2 - ) . 4 & % . ( & % . , 6 3 & ? % . 3 ! & ) . ' 3 4 ! 4 % $ ) ! ' 3 4 ! 4 % $ 3 4 % 3 4 6 3 & ! 2 - ) . ' 3 4 ! 4 % 3 ! & % 3 % , ! 2 - ? % . ' ! 0 ' 0 3 9 , 1 7 9 9 , 1 7 b 2 9 9 , 1 7 9 0 r q l w r u 9 , 1 7 b 8 9 9 ' ' b 2 9 9 ' ' 0 r q l w r u 9 ' ' b 8 9 9 ' ' 9 5 ( * b ( 5 5 9 ' ' 9 b 2 9 9 ' ' 9 b ( 5 5 9 ' ' 9 b 8 9 9 ' ' 9 0 r q l w r u 9 ' ' 9 9 ' ' b 2 9 9 ' ' b ( 5 5 9 ' ' b 8 9 9 ' ' 0 r q l w r u 9 ' ' 9 % * 0 0 r q l w r u * 1 ' $ 0 r q l w r u * 1 ' $ * 1 ' ' * 1 ' 6 8 % [ * 1 ' ' 0 r q l w r u * 1 ' $ b ( 5 5 * 1 ' ' b ( 5 5 * 1 ' b ( 5 5 9 % * b 5 ( $ ' < 5 h i h u h q f h i r u & r q w u r o o l q j d o o v x s s o l h v 9 % * 5 5 h i h u h q f h docid025869 rev 3 35/200 l9678, l9678-s start-up power control 199 an active low pin output (reset pin) is driven from the l9678 to allow resetting of external devices such as the microcontroller, se nsors, and other ics within the ecu. three internal reset signals are generated by the device: ? por power on reset - this reset is asserted when a failure is detected in the internal supplies or bandgap circuits. when active, all other resets are asserted. ? wsm_reset watchdog state machine reset - this reset is generated when the por is active. ? ssm_reset system state machine reset - this reset is asserted when the por or the wsm_reset are active, or wh en a failure is detected in either wa tchdog state machine. the reset pin is the active-low signal driven on the output pin, and is an inverted form of ssm_reset. the cause of a reset activation is latched and reported in to the fault status register fltsr and cleared on spi reading. the reset logic shall be controlled as shown in the diagram below: figure 19. reset control diagram gnd_err is a general fault signal with the pu rpose of driving the device into por when either gnda or gndd are shifted more than 300 mv nominal with respect to the reference ground pins gndsub. ' ! 0 ' 0 3 3 2 5 6 6 0 b 5 h v h w 9 ' ' 9 b ( 5 5 : 6 0 b 5 h v h w 5 ( 6 ( 7 s l q : ' 5 ( 6 ( 7 v w d w h p v v w u h w f k 9 5 ( * b ( 5 5 * 1 ' b ( 5 5 9 % * b 5 ( $ ' < & / . ) 5 ( 5 5 9 ' ' b ( 5 5 6 < 6 b & ) * ' , 6 b 9 ' ' b ( 5 5 spi interface l9678, l9678-s 36/200 docid025869 rev 3 5 spi interface the l9678 system solution device has many us er selectable features controlled through serial communications by the integrated mi crocontroller. the spi interface provides configuration, control and status functions fo r the device. the global spi interface consists of an input shift register, output shift register and four control signals. spi_mosi is the data input to the input shift register. spi_miso is th e data output from the output shift register. spi_sck is the clock source input while spi_ cs is the active-low chip select input. ? all spi communications are executed in exact 32 bit increments. the general format of the 32 bit transmission is shown in table 5 . data to the ic (i.e. spi_mosi) consists of a ta rget read register id (rid), a target write register id (wid), write data pa rity (wpar) and 16 bits of data (write). write data is the data to be written to the target write register indicated by wid. data returned from the ic (i.e. spi_miso) consists of a global status word (gsw), read data parity (rpar) and 20 bits of data (read). read data will be the contents of the target read register as indicated by the rid bits. the parity bits wpar and rpar cover all the 32 bits of the mosi and miso frames, respectively. odd parity type is used. the communications is controlled through spi _cs, enabling and disabling communication. when spi_cs is at logic high, all spi communication i/o is tri-stated and no data is accepted. when spi_cs is low, data is latched on the rising edge of spi_sck and data is shifted on the falling edge. the spi_mosi pin re ceives serial data fr om the master with msb first. likewise for spi_miso, data is read msb first, lsb last. the l9678 ic contains a data validation method through the spi_sck input to keep transmissions with not exactly 32 bits from being written to the device. the spi_sck input counts the number of received clocks and should the clock counter exceed or count fewer than 32 clocks, the received message is discarded and a spi_flt bit is flagged in the global status word (gsw). the spi_flt bit is al so set in case of pari ty error detected on the mosi frame. any attempt access to a register with a forbidden access mode (read or write) is not leading to changes to the internal registers but the spi_flt bit is not set in this case. the spi interface consists of several 32-bit re gisters to allow for configuration, control and status of the ic as well as special manufact uring test modes. the register definition is defined by the read register id (rid) and the write register id (wid) as shown in table 5 - global spi register table. global id bit (g id) is used to extend available register addresses, but it is shared between rid an d wid; only rid and wid with the same gid value can be addressed within the same spi wo rd. the operating states here show in which states the spi write command is processed. table 5. spi register r/w spi register r/w 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 spi_mosi gid rid[6:0] wid[6:0] wpar spi_miso gsw[10:0] rpar read[19:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 spi_mosi write[15:0] spi_miso read[15:0] docid025869 rev 3 37/200 l9678, l9678-s spi interface 199 the l9678 checks the validity of the received wid and rid fields in the spi_mosi frame. should a spi write command with wid matching a writeable register be received in an illegal operating state, the co mmand will be discarded and t he err_wid bit will be flagged in the next global status word gsw. the err_wid flag is not set in case wid is addressing a read/only register. should a spi read command be received containing an unused rid address, the command will be discar ded and the err_rid bit will be flagged in the current gsw. spi interface l9678, l9678-s 38/200 docid025869 rev 3 table 6. global spi register map gid rid / wid hex r/w name description operating state (1) init diag ssafing scrap arming 0 0 0 0 0 0 0 0 $00 r fltsr global fault status register 0 0000001$01r/w sys_cfg power supply configuration (regulators' output voltage selection, enable internal safing engine) x 0 0 0 0 0 0 1 0 $02 r/w sys_ctl register to control the power management (enable for tests in diag state, enable for power mode control bits) xx x x x 0 0 0 0 0 0 1 1 $03 w spi_sleep sleep mode command x x x x x 0 0 0 0 0 1 0 0 $04 r sys_state read register to report in which state the power control state machine is and also in which operating state we are. 0 0000101$05 r power_state power state register (feedback on regulators' status and voltage thresholds) 0 0 0 0 0 1 1 0 $06 r/w dcr_0 deployment configuration register xx x x 0 0 0 0 0 1 1 1 $07 r/w dcr_1 x x x x 0 0 0 0 1 0 0 0 $08 r/w dcr_2 x x x x 0 0 0 0 1 0 0 1 $09 r/w dcr_3 x x x x 0 0001010$0a 0 0001011$0b 0 0001100$0c 0 0001101$0d 0 0001110$0e 0 0001111$0f 0 0010000$10 0 0010001 $11 0 0 0 1 0 0 1 0 $12 r/w depcom deployment command register x x l9678, l9678-s spi interface docid025869 rev 3 39/200 0 0010011$13 r dsr_0 deployment status register 0 0010100$14 r dsr_1 0 0010101$15 r dsr_2 0 0010110$16 r dsr_3 0 0010111$17 0 0011000$18 0 0011001$19 0 0011010$1a 0 0011011$1b 0 0011100$1c 0 0011101$1d 0 0011110$1e 0 0011111$1f r dcmts01 deployment current monitor register 0 0100000$20 r dcmts23 0 0100001$21 0 0100010$22 0 0100011$23 0 0100100$24 0 0 1 0 0 1 0 1 $25 r/w spidepen lock/unlock command x x 0 0 1 0 0 1 1 0 $26 r lp_gndloss loss of ground fault for squib loops 0 0 1 0 0 1 1 1 $27 r version_id device version 0 0 1 0 1 0 0 0 $28 r/w wd_retry_conf watchdog retry configuration x 0 0101001$29 0 0 1 0 1 0 1 0 $2a r/w wdtcr watchdog timer configuration x 0 0 1 0 1 0 1 1 $2b r/w wd1t watchdog key transmission & test mode x x x x x table 6. global spi register map (continued) gid rid / wid hex r/w name description operating state (1) init diag ssafing scrap arming spi interface l9678, l9678-s 40/200 docid025869 rev 3 0 0101100$2c r wd_state watchdog state 0 0 1 0 1 1 0 1 $2d r/w clk_conf clock configuration x 0 0101110$2e 0 0101111$2f 0 0 1 1 0 0 0 0 $30 w scrap_state scrap state command x 0 0 1 1 0 0 0 1 $31 w safing_state safing state command x 0 0110010$32 0 0110011$33 0 0110100$34 0 0 1 1 0 1 0 1 $35 w wd_test watchdog first and second level test x x x x x 0 0 1 1 0 1 1 0 $36 r/w sysdiagreq diagnosti c command for system safing x 0 0110111$37 r lpdiagstat diagnostic results register for deployment loops 0 0111000$38r/w lpdiagreq diagnostic configuration command for deployment loops xx x x 0 0 1 1 1 0 0 1 $39 r/w swctrl dc sensor diagnostic configuration x x x x 0 0111010$3ar/w diagctrl_a in wid is atod converter control register a. in rid is atod result a request. xx x x 0 0111011$3br/w diagctrl_b in wid is atod converter control register b. in rid is atod result b request. xx x x 0 0111100$3cr/w diagctrl_c in wid is atod converter control register c. in rid is atod result c request. xx x x 0 0111101$3dr/w diagctrl_d in wid is atod converter control register d. in rid is atod result d request. xx x x 0 0111110$3e 0 0111111$3f 0 1000000$40 table 6. global spi register map (continued) gid rid / wid hex r/w name description operating state (1) init diag ssafing scrap arming l9678, l9678-s spi interface docid025869 rev 3 41/200 0 1000001$41 0 1 0 0 0 0 1 0 $42 r/w gpocr general purp ose output configuration x x 0 1 0 0 0 0 1 1 $43 r/w gpoctrl0 general purp ose output control register x x x x x 0 1 0 0 0 1 0 0 $44 r/w gpoctrl1 general purp ose output control register x x x x x 0 1000101$45 0 1 0 0 0 1 1 0 $46 r gpofltsr general purpos e output fault status register 0 1 0 0 0 1 1 1 $47 r isofltsr iso9141 fault status register 0 1001000$48 0 1001001$49 0 1 0 0 1 0 1 0 $4a r/w rscr1 psi5 configuration register x 0 1001011$4br/w rscr2 x 0 1001100$4c 0 1001101$4d 0 1 0 0 1 1 1 0 $4e r/w rsctrl remote se nsor control register x x x x 0 1001111$4f 0 1 0 1 0 0 0 0 $50 r rsdr1 remote sensor data and fault flag registers 0 1010001$51 r rsdr2 0 1010010$52 0 1010011$53 0 1010100$54 0 1010101$55 0 1010110$56 0 1010111$57 0 1011000$58 0 1011001$59 table 6. global spi register map (continued) gid rid / wid hex r/w name description operating state (1) init diag ssafing scrap arming spi interface l9678, l9678-s 42/200 docid025869 rev 3 0 1011010$5a 0 1011011$5b 0 1011100$5c 0 1011101$5d 0 1011110$5e 0 1011111$5f 0 1100000$60 0 1100001$61 0 1100010$62 0 1100011$63 0 1100100$64 0 1100101$65 0 1 1 0 0 1 1 0 $66 r/w saf_algo_conf safing al gorithm configuration register x 0 1100111$67 0 1101000$68 0 1101001$69 0 1101010$6a r arm_state status of internal arming signals fenh, fenl, armx 0 1101011$6b 0 1101100$6c 0 1101101$6d 0 1 1 0 1 1 1 0 $6e r/w loop_matrix_arm1 assignment of arm 1 pin to which loops x 0 1 1 0 1 1 1 1 $6f r/w loop_matrix_arm2 assignment of arm 2 pin to which loops x 0 1110000$70 0 1110001$71 table 6. global spi register map (continued) gid rid / wid hex r/w name description operating state (1) init diag ssafing scrap arming l9678, l9678-s spi interface docid025869 rev 3 43/200 0 1110010$72 0 1 1 1 0 0 1 1 $73 r aepsts_arm1 arming pulse stretch timer value 0 1 1 1 0 1 0 0 $74 r aepsts_arm2 0 1110101$75 0 1110110$76 0 1110111$77 0 1111000$78 0 1111001$79 0 1111010$7a 0 1111011$7b 0 1111100$7c 0 1111101$7d 0 1111110$7e 0 1 1 1 1 1 1 1 $7f r/w saf_enable safing record enable x x x x 1 0 0 0 0 0 0 0 $80 r/w saf_req_mask_1 safing record request mask x 1 0 0 0 0 0 0 1 $81 r/w saf_req_mask_2 x 1 0 0 0 0 0 1 0 $82 r/w saf_req_mask_3 x 1 0 0 0 0 0 1 1 $83 r/w saf_req_mask_4 x 1 0000100$84 1 0000101$85 1 0000110$86 1 0000111$87 1 0001000$88 1 0001001$89 1 0001010$8a table 6. global spi register map (continued) gid rid / wid hex r/w name description operating state (1) init diag ssafing scrap arming spi interface l9678, l9678-s 44/200 docid025869 rev 3 1 0001011$8b safing record request mask 1 0001100$8c 1 0001101$8d 1 0001110$8e 1 0001111$8f 1 0010000$90 1 0010001$91 1 0010010$92 1 0 0 1 0 0 1 1 $93 r/w saf_req_target_1 safing record request target x 1 0 0 1 0 1 0 0 $94 r/w saf_req_target_2 x 1 0 0 1 0 1 0 1 $95 r/w saf_req_target_3 x 1 0 0 1 0 1 1 0 $96 r/w saf_req_target_4 x 1 0010111$97 1 0011000$98 1 0011001$99 1 0011010$9a 1 0011011$9b 1 0011100$9c 1 0011101$9d 1 0011110$9e 1 0011111$9f 1 0100000$a0 1 0100001$a1 1 0100010$a2 1 0100011$a3 table 6. global spi register map (continued) gid rid / wid hex r/w name description operating state (1) init diag ssafing scrap arming l9678, l9678-s spi interface docid025869 rev 3 45/200 1 0100100$a4 safing record request target 1 0100101$a5 1 0 1 0 0 1 1 0 $a6 r/w saf_resp_mask_1 safing record response mask x 1 0 1 0 0 1 1 1 $a7 r/w saf_resp_mask_2 x 1 0 1 0 1 0 0 0 $a8 r/w saf_resp_mask_3 x 1 0 1 0 1 0 0 1 $a9 r/w saf_resp_mask_4 x 1 0101010$aa 1 0101011$ab 1 0101100$ac 1 0101101$ad 1 0101110$ae 1 0101111$af 1 0110000$b0 1 0110001$b1 1 0110010$b2 1 0110011$b3 1 0110100$b4 1 0110101$b5 1 0110110$b6 1 0110111$b7 1 0111000$b8 1 0 1 1 1 0 0 1 $b9 r/w saf_resp_target_1 safing record response target x 1 0 1 1 1 0 1 0 $ba r/w saf_resp_target_2 x 1 0 1 1 1 0 1 1 $bb r/w saf_resp_target_3 x 1 0 1 1 1 1 0 0 $bc r/w saf_resp_target_4 x table 6. global spi register map (continued) gid rid / wid hex r/w name description operating state (1) init diag ssafing scrap arming spi interface l9678, l9678-s 46/200 docid025869 rev 3 1 0111101$bd safing record response target 1 0111110$be 1 0111111$bf 1 1000000$c0 1 1000001$c1 1 1000010$c2 1 1000011$c3 1 1000100$c4 1 1000101$c5 1 1000110$c6 1 1000111$c7 1 1001000$c8 1 1001001$c9 1 1001010$ca 1 1001011$cb 1 1 0 0 1 1 0 0 $cc r/w saf_data_mask_1 safing record data mask x 1 1 0 0 1 1 0 1 $cd r/w saf_data_mask_2 x 1 1 0 0 1 1 1 0 $ce r/w saf_data_mask_3 x 1 1 0 0 1 1 1 1 $cf r/w saf_data_mask_4 x 1 1010000$d0 1 1010001$d1 1 1010010$d2 1 1010011$d3 1 1010100$d4 1 1010101$d5 table 6. global spi register map (continued) gid rid / wid hex r/w name description operating state (1) init diag ssafing scrap arming l9678, l9678-s spi interface docid025869 rev 3 47/200 1 1010110$d6 safing record data mask 1 1010111$d7 1 1011000$d8 1 1011001$d9 1 1011010$da 1 1011011$db 1 1011100$dc 1 1011101$dd 1 1011110$de 1 1 0 1 1 1 1 1 $df r/w saf_threshold_1 safing record threshold x 1 1 1 0 0 0 0 0 $e0 r/w saf_threshold_2 x 1 1 1 0 0 0 0 1 $e1 r/w saf_threshold_3 x 1 1 1 0 0 0 1 0 $e2 r/w saf_threshold_4 x 1 1100011$e3 1 1100100$e4 1 1100101$e5 1 1100110$e6 1 1100111$e7 1 1101000$e8 1 1101001$e9 1 1101010$ea 1 1101011$eb 1 1101100$ec 1 1101101$ed 1 1101110$ee table 6. global spi register map (continued) gid rid / wid hex r/w name description operating state (1) init diag ssafing scrap arming spi interface l9678, l9678-s 48/200 docid025869 rev 3 1 1101111$efr/w saf_control_1 safing record control x 1 1110000$f0r/w saf_control_2 x 1 1110001$f1r/w saf_control_3 x 1 1110010$f2r/w saf_control_4 x 1 1110011$f3 1 1110100$f4 1 1110101$f5 1 1110110$f6 1 1110111$f7 1 1111000$f8 1 1111001$f9 1 1111010$fa 1 1111011$fb 1 1111100$fc 1 1111101$fd 1 1111110$fe 1 1111111$ff r saf_cc safing record compare complete 1. a check mark indicates in which op erating state a write-command is valid. table 6. global spi register map (continued) gid rid / wid hex r/w name description operating state (1) init diag ssafing scrap arming docid025869 rev 3 49/200 l9678, l9678-s spi interface 199 5.1 global spi register a summary of all the read/write registers co ntained within the spi map are shown below and are further referenced throughout the spec ification as they apply. the spi register tables also specify the effect of the internal reset signals assertion on each bit field (the symbol '-' is used to indicate that the register is not affected by the relevant reset signal). global status word l9678 contains an 11-bit word that returns global status information. the gsw is the most significant 11 bits of spi_miso data. id r/w/rw -r register name description gsw global status word miso bit31 30 29 28 27262524232221 miso spiflt depok rsflt wdtdis_s erstate powerflt flt convrdy2 convrdy1 err_wid err_rid gsw bit 10 9 8 7 6543210 table 7. global status word (gsw) bit name por wsm ssm description 10 spiflt 0 0 0 spi fault, set if previous spi frame had wrong parity check or wrong number of bits, cleared upon read 0 no fault 1 fault 9 depok 0 0 0 general deployment successful flag, logical or of the corresponding chxds bits (bit 15) in dsrx registers 0 all the dsrx-chds bits are 0 1 at least one of the dsrx-chds bits is 1 8rsflt 000 remote sensor interface fault present, logical or of the corresponding fltbit bits (bit 15) in rsdrx registers 0 all the rsdrx-fltbit bits are 0 1 at least one of the rsdrx-fltbit bits is 1 7 wdtdis_s 0 0 0 state of wdtdis pin 0 wdtdis = 0 1 wdtdis = 1 spi interface l9678, l9678-s 50/200 docid025869 rev 3 6erstate 0 0 0 set when power mode state machine is in er state 0 power mode state machine is not in er state 1 power mode state machine is in er state 5powerflt 0 0 0 fault present in power state register, logical or between bits from 18 to 9 of power_state register 0 all the bits from 18 to 9 in the power_state registers are 0s 1 at least one of the bits from 18 to 9 in the power_state registers is 1 4flt 111 fault present in fault status register (fltsr), logical or between all bits of fltsr 0 all the bits in the fault status register (fltsr) are 0s 1 at least one of the bits in the fault status register (fltsr) is 1 3 convrdy2 0 0 0 adc conversion of request 3 or 4 has been completed so new results are available 0 no new data available 1 new data available 2 convrdy1 0 0 0 adc conversion of request 1 or 2 has been completed so new results are available 0 no new data available 1 new data available 1 err_wid 0 0 0 write address of previous spi frame is not permitted in current operating phase (init, diag, saf ing, scrap, arming) 0 no error 1 error 0 err_rid 0 0 0 read address received in the actual spi frame is unused so data in the response is don't care 0 no error 1 error table 7. global status word (gsw) (continued) bit name por wsm ssm description docid025869 rev 3 51/200 l9678, l9678-s spi interface 199 read/write register 5.1.1 fault status register (fltsr) address: 00 type: r buffer: $0000 reset: - 191817161514131211109876543210 mosi - xxxxxxxxxxxxxxxx miso 00 erbst_ot clkfrerr -000 otpcrc_err 000 wd1_lo wd1_tm wd1_wdr 0 wsmrst ssmrst 0 por por wsm ssm ebst_ot 0 - - er boost ov er-temperature bit set when over-temp condition detect ed, cleared on spi read or por=1 0 no fault 1 fault clkfrerr 0 - - internal oscilla tor cross-check error bit set when osc error detected, cleared on spi read or por=1 0 no fault 1 fault otpcrc_err 0 - - otp crc error bit set when otp error detected (tested at release of por), cleared by por=1 0 no fault 1 fault wd1_lo 0 0 - wd1 lockout - reflects wd1 lockout state set and cleared per watchdog timer flow diagram 0 wd1 lockout inactive 1 wd1 lockout active wd1_tm 0 0 0 wd1 test mode - reflects wd1tm signal state set and cleared per watchdog timer flow diagram 0 wd1tm=0 1 wd1tm=1 spi interface l9678, l9678-s 52/200 docid025869 rev 3 wd1_wdr 0 0 - wd1 reset latch set and cleared per watchdog timer flow diagram 0 wd1_wdr signal = 0 1 wd1_wdr signal = 1 wsmrst 1 1 - watchdog state machine reset set when wsm reset goes to '1', cleared upon spi read 0 wsm reset has not occurred 1 wsm reset has occurred ssmrst 1 1 1 safing state machine reset set when ssm reset goes to '1', cleared upon spi read 0 ssm reset has not occurred 1 ssm reset has occurred por 1 - - power on reset set when por goes to '1', cleared upon spi read 0 por reset has not occurred 1 por reset has occurred docid025869 rev 3 53/200 l9678, l9678-s spi interface 199 5.1.2 system configurat ion register (sys_cfg) address: 01 type: rw buffer: $0100 reset: $0002 191817161514131211109876543210 mosi - en_auto_switch_off dis_vdd5_err x keep_erbst_on x v_diag - sqmeas vmeas x safesel vsf_v x wd1_tovr miso 0000 en_auto_switch_off dis_vdd5_err 0 keep_erbst_on 0 v_diag - sqmeas vmeas 0 safesel vsf_v 0 wd1_tovr por wsm ssm en_auto_switc h_off 000 enable auto switch off isrc current source and dcs regulator after measurement completion 0 auto switch off disabled 1 auto switch off enabled dis_vdd5_err 0 0 - disable vdd5 ov/uv to generate reset 0 ov/uv generate reset 1 ov/uv don?t generate reset keep_erbst_on 0 0 0 er boost b ehaviour during er state 0 er boost is disabled 1 er boost stay enabled hi_lev_diag_tim e 0 0 0 selection of duration of high level squib diagnostics 0 short time (see high level diag diagram) 1 long time (see high level diag diagram) sqmeas 00 00 00 sample number in dc sensor, squib measurement and temperature conversions updated by ssm_reset or spi write spi interface l9678, l9678-s 54/200 docid025869 rev 3 0 8 samples 1 16 samples 10 4 samples 11 1 sample vmeas 00 00 00 sample number in any other voltage measurement conversions updated by ssm_reset or spi write updated by ssm_reset or spi write 0 4 samples 1 16 samples 10 8 samples 11 1 sample safesel 1 1 1 safing engine mode select updated by ssm_reset or spi write 0 internal safing engine 1 external safing engine vsf_v 0 0 0 vsf voltage select updated by ssm_reset or spi write 0 20v 1 25v wd1_tovr 0 0 - override of initial 500m s time-out of wd1 state machine set and cleared per watchdog timer flow diagram 0 time-out is active 1 time-out is disabled docid025869 rev 3 55/200 l9678, l9678-s spi interface 199 5.1.3 system control register (sys_ctl) address: 02 type: rw buffer: $0200 reset: $0004 191817161514131211109876543210 mosi - xxx vin_th_sel vbatmon_th_sel er_bst_v x er_cur_en er_bst_en vsup_en spi_off xxxx miso 0000 - 00 vin_th_sel vbatmon_th_sel er_bst_v 0 er_cur_en er_bst_en vsup_en spi_off 0000 por wsm ssm vin_th_sel 0 0 0 vin comparators threshold selector 0 5.5v 1 7.5v vbatmon_th_se l 00 00 00 vbatmon comparators threshold selector 00 6v 01 6.8v 10 8v 11 8.8v er_bst_v 0 0 0 er boost voltage select updated by ssm_reset or spi write 0 set 23v boost 1 set 33v boost er_cur_en 0 0 0 er charge / discharge control updated by ssm_reset or spi write 0 er current source off request 1 er current source on request er_bst_en 1 1 1 boost enable updated by ssm_reset or spi write spi interface l9678, l9678-s 56/200 docid025869 rev 3 5.1.4 spi sleep comman d register (spi_sleep) address: 03 type: w buffer: - reset: $0006 0 er_boost off request 1 er_boost on request vsup_en 0 0 0 supplemental supply for satellites updated by ssm_reset or spi write 0 vsup commanded off 1 vsup spi_off 0 0 0 go to power off state from powermode shutdown state updated by ssm_reset or spi writ e while in powermode shutdown state 0 no effect 1 transition to power off state 191817161514131211109876543210 mosi - $3c95 miso 0000 - 000000000000000 por wsm ssm sleep_mode n/a n/a n/a non-latched comma nd that allows transition into powermode_shutdown state accord ing to the power control state flow diagram docid025869 rev 3 57/200 l9678, l9678-s spi interface 199 5.1.5 system status register (sys_state) address: 04 type: r buffer: $0400 reset: - 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso 0 0 0 0 0 0 0 0 0 oper_ctl_state 00000 power_ctl_state por wsm ssm oper_ctl_stat e[2:0] 000 000 000 reports operating control state updated per power up phases diagram 000 = init 001 = diag 010 = safing 011 = scrap 100 = arming 101 unused 110 unused 111 unused power_ctl_sta t e[2:0] 000 - - reports power control state updated per power control state flow diagram 000 = awake 001 = startup 010 = run 011 = er 100 = power mode shutdown 101 unused 110 unused 111 unused spi interface l9678, l9678-s 58/200 docid025869 rev 3 5.1.6 power state register (power_state) address: 05 type: r buffer: $0500 reset: - 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso wakeup vbbad not_vbgood vinbad not_vingood vdd3v3_uv vdd3v3_ov er_bst_nok vdd5_uv vdd5_ov vsup_nok er_bst_on er_chrg_on 00 er_sw_on vdd5_act vsup_act vdd3v3_act vsf_act por wsm ssm wakeup - - - wakeup pin status set and cleared based on voltage 0 wakeup pin < wu_off 1 wakeup pin > wu_on vbbad - - - vbatmon bad pin status set and cleared based on voltage 1 vbatmon < vbbad 0 vbatmon > vbbad not_vbgood - - - vbatmon good pin status set and cleared based on voltage 1 vbatmon < vbgood 0 vbatmon > vbgood vinbad - - - vin bad pin status set and cleared based on voltage 0 vin > vinbad 1 vin < vinbad not_vingood - - - vin good pin status set and cleared based on voltage 0 vin > vingood 1 vin < vingood vdd3v3_uv - - - vdd3v3 bad pin status docid025869 rev 3 59/200 l9678, l9678-s spi interface 199 set based on voltage, cleared on spi read 0 vdd3v3 > vdd3v3_uv 1 vdd3v3 < vdd3v3_uv vdd3v3_ov - - - vdd3v3 bad pin status set based on voltage, cleared on spi read 0 vdd3v3 < vdd3v3_ov 1 vdd3v3 > vdd3v3_ov er_bst_nok - - - erboost pin status set and cleared based on voltage 1 v_erboost < erboost_ok 0 v_erboost > erboost_ok vdd5_uv - - - vdd5_uv status set based on voltage, cleared on spi read 0 vdd5 > vdd5_uv 1 vdd5 < vdd5_uv vdd5_ov - - - vdd5_ov status set based on voltage, cleared on spi read 0 vdd5 < vdd5_ov 1 vdd5 > vdd5_ov vsup_nok - - - vsup status set and cleared based on voltage 0 vsup > vsup_ok 1 vsup < vsup_ok er_bst_on 0 - - erboost_on state updated according to er_boost control behavior diagram 0 rboost_off or erboost_ot state or er_bst_stby state (boost ? not running) 1 erboost_on state (boost running) er_chrg_on 0 0 0 ercharge_on state updated according to er_charge power mode control diagram 0 ercharge_on = 0 1 ercharge_on = 1 spi interface l9678, l9678-s 60/200 docid025869 rev 3 er_sw_on 0 - - er_switch state updated according to er switch state diagram 0 er_switch_off 1 er_switch_on vdd5_act 0 - - vdd5 active state updated according to vdd5 power mode control state diagram 0 vdd5 supply in vdd5_off or vdd5_shutdown states 1 vdd5 supply in vdd5_rampup or vdd5_on states vsup_act 0 0 0 vsup active state updated according to vsup power mode control state diagram 0 vsup supply in vsup_off or vsup_shutdown states 1 vsup supply in vsup_rampup or vsup_on states vdd3v3_act 0 - - vdd3v3 active state updated according to vdd3v3 power mode control state diagram 0 vdd3v3 supply in vdd3v3_off or vdd3v3_shutdown states 1 vdd3v3 supply in vsup_on state vsf_act 0 0 0 vsf active state updated according to vsf control logic diagram 0 vsf_en = 0 1 vsf_en = 1 docid025869 rev 3 61/200 l9678, l9678-s spi interface 199 5.1.7 deployment configur ation registers (dcr_x) channel 0 (dcr_0) channel 1 (dcr_1) channel 2 (dcr_2) channel 3 (dcr_3) address: 06 (dcr_0) ? 07 (dcr_1) ? 08 (dcr_2) ? 09 (dcr_3) type: rw buffer: $0600 (dcr_0) ? $0700 (dcr_1) ? $0800 (dcr_2) ? $0900 (dcr_3) reset: $000c (dcr_0) ? $000e (dcr_1) ? $0010 (dcr_2) ? $0012 (dcr_3) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x deploy_time dep_current dep_expire_time xx miso 00000 00 0 0 000 deploy_time dep_current dep_expire_time 00 por wsm ssm deploy_time[1:0] 00 00 00 default deployment time select updated by ssm_reset or spi write while in diag state 00 unused (no deploy, 8 us pulse output on arm1 pin during pulse test) 01 0.5 ms 10 0.7 ms 11 2.0 ms dep_current[1:0] 00 00 00 deployment current limit select updated by ssm_reset or spi write while in diag state 00 unused (no deploy) spi interface l9678, l9678-s 62/200 docid025869 rev 3 01 1.75a min 10 1.2a min 11 unused (no deploy) dep_expire_time[1: 0] 00 00 00 deploy command expiration timer select updated by ssm_reset or spi write while in diag state 00 500ms 01 250ms 10 125ms 11 0ms docid025869 rev 3 63/200 l9678, l9678-s spi interface 199 5.1.8 deployment command (depcom) address: 12 type: rw buffer: $1200 reset: $0024 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x ch3depreq ch2depreq ch1depreq ch0depreq miso 00000000 00000000 ch3dep ch2dep ch1dep ch0dep por wsm ssm chxdepreq n/a n/a n/a channel x deploy request - non-latched channel-specific deploy request 0 no change to deployment control for channel x 1 clear and start expiration timer if in arming or safing state and in deploy_enabled state chxdep 0 0 0 channel x deployment expiration timer enable set when s pi_depcom(chxdepreq=1) and in arming or safing state and in dep_enabled state cleared on ssm_reset or when in dep_disabled state or when deploy expiration timer x reaches time-out threshold 0 expiration timer enabled - deploy command still valid 1 expiration timer disabled - deploy command no more valid spi interface l9678, l9678-s 64/200 docid025869 rev 3 5.1.9 deployment confi guration registers (dsr_x) channel 0 (dsr_0) channel 1 (dsr_1) channel 2 (dsr_2) channel 3 (dsr_3) address: 13 (dsr_0) ? 14 (dsr_1) ? 15 (dsr_2) ? 16 (dsr_3) type: r buffer: $1300 (dsr_0) ? $1400 (dsr_1) ? $1500 (dsr_2) ? $1600 (dsr_3) reset: - 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso 0 0 0 0 chxds chxstat chxdd dcrxerr 00000 0 dep_chx_exptimer por wsm ssm chxds 0 0 0 channel x deployment successful updated according to deployment driver control logic (set when deployment terminates on ch x due to deploy timer time-out, cleared on ssm_reset or when deployment starts on ch x) 0 deployment not successful 1 deployment successful chxstat 0 0 0 (set when deployment starts on ch x, cleared on ssm_reset or when deployment terminates due to deploy timer time-out, ls over current or gnd loss) 0 deployment not in progress 1 deployment in progress chxdd 0 0 0 default deploy flag on channel x updated by ssm_reset, or when the depl oyment configurat ion register is written with an incorr ect configuration docid025869 rev 3 65/200 l9678, l9678-s spi interface 199 5.1.10 deployment current moni tor status registers (dcmtsxy) channels 0, 1 (dcmts01) channels 2, 3 (dcmts23) address: 1f (dcmts01)) 20 (dcmts23) type: r buffer: $1f00 (dcmts01) $2000 (dcmts23) reset: - 0 correct time/current combination selected 1 incorrect time/current combination selected (default time/current is set) dcrxerr 0 0 0 deployment configuration register err 0 deploy configuration change accepted and stored in memory 1 deploy configuration change rejected because deploy is in progress (or dep_expire_time changed when in dep_enabled state) dep_chx_exptimer [5:0] 0000 00 0000 00 0000 00 channel x deployment expiration timer value 8ms/count updated according to deployment driver control logic (cleared on ssm_reset or when exp timer times out or when spi_depreqx is received while in dep_enabled state and in arming or safing states) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso 0 0 0 0 current_mon_timer_y[7:0] current_mon_timer_x[7:0] por wsm ssm current_mon_time r_y[7:0] $00 $00 $00 channel y current monitor timer value corresponding to spi command dcmtsxy. set to default (cleared) on ssm_reset or when a new deployment starts on channel y. increments each 16s while deployment current exceeds monitor threshold on channel y current_mon_time r_x[7:0] $00 $00 $00 channel x current monitor timer value corresponding to spi command dcmtsxy. set to default (cleared) on ssm_reset or when a new deployment starts on channel x. increments each 16s while deployment current on channel x exceeds monitor threshold spi interface l9678, l9678-s 66/200 docid025869 rev 3 5.1.11 deploy enable register (spidepen) address: 25 type: rw buffer: $2500 reset: $004a 5.1.12 squib ground loss register (lp_gndloss) address: 26 type: r buffer: $2600 reset: - 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - depen_wr[15:0 miso 0 0 0 0 depen_state[15:0] por wsm ssm depen_wr[15:0] n/a n/a n/a non-l atched encoded value for lock / unlock command $0ff0 lock - enter dep_disabled state $f00f unlock - enter dep_enabled state depen_state[15: 0] $0ff0$0ff0$0ff0 deploy enabled state updated according to global spi deployment enable state diagram $0ff0 in dep_disabled state $f00f in dep_enabled state 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso 00000000 00000000 gndloss3 gndloss2 gndloss1 gndloss0 por wsm ssm gndlossx 0 0 0 loop x squib ground loss docid025869 rev 3 67/200 l9678, l9678-s spi interface 199 5.1.13 device version re gister (version_id) address: 27 type: r buffer: $2700 reset: - 5.1.14 watchdog retry configurat ion register (wd_retry_conf) address: 28 type: rw buffer: $2800 reset: $0050 cleared upon ssm_reset or spi read. set when gnd loss is detected during deployment or loop diag's (hs sw test, ls sw test, squib resistance) 0 loss of ground not detected 1 loss of ground detected 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso 0 0 0 0 0 0 0 0 0 device id 0 0 versn por wsm ssm device id - - - identification of the device static value - never updated 001 low end 010 medium end 011 high end versn - - - identification of the silicon version 0 00011 cb version other codes previous versions 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - wd1_retry_th miso 00000000 000000000wd1_retry_th por wsm ssm wd1_retry_th 77 - wd1 retry counter threshold (number of wd errors permitted before latching wd1_lockout=1) spi interface l9678, l9678-s 68/200 docid025869 rev 3 5.1.15 watchdog timer confi guration register (wdtcr) address: 2a type: rw buffer: $2a00 reset: $0054 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x wd1_mode wdtmin[6:0] wdtdelta[6:0] miso 00000 wd1_mode wdtmin[6:0] wdtdelta[6:0] por wsm ssm wd1_mode 0 0 - wd1 mode updated by wsm_reset or spi write while in wd1_init state 0 fast wd1 mode - nominal 8s timer resolution (2ms max value) 1 slow wd1 mode - nominal 64s timer resolution (16.3ms max value) wdtmin[6:0] $32 $32 - wd1 window minimum value - resolution according to wd1_mode bit ($32 = 40 0s in wd1 fast mode) updated by wsm_reset or spi write while in wd1_init state wdtdelta[6:0] $19 $19 - wd1 window delta value - wdtmax=wdtmin+wdtdelta - resolution accord ing to wd1_mode bit ($19 = 200s in wd1 fast mode) updated by wsm_reset or spi write while in wd1_init state docid025869 rev 3 69/200 l9678, l9678-s spi interface 199 5.1.16 wd1 timer control register (wd1t) address: 2b type: w buffer: $2b00 reset: $0056 5.1.17 wd1 state register (wdstate) address: 2c type: r buffer: $2c00 reset: - 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x wd1ctl[1:0] miso 0 0 0 0 wd1_timer 0 0 0 0 0 0 wd1ctl[1:0] por wsm ssm wd1ctl[1:0] 00 00 00 wd1 control command updated by ssm_reset or spi write 00 nop 01 code 'a' 10 code 'b' 11 nop wd1_timer $00 $00 $00 wd1 window timer value cle ared by ssm_reset or by wd1 refr esh, incremented every 8s or 64s while in wd1_run or wd1_test states 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso 0 0 0 0 0 wd1_err_cnt[3:0] wd_state[2:0] 0 0 0 0 0 0 0 0 por wsm ssm wd1_err_cnt[3:0] 000 000 - watchdog error counter updated according to watchdog state diagram wd1_state[2:0] 000 000 - watchdog state updated according to watchdog state diagram 000 initial spi interface l9678, l9678-s 70/200 docid025869 rev 3 5.1.18 clock configurat ion register (clk_conf) address: 2d type: rw buffer: $2d00 reset: $005a 001 run 010 test 011 reset 100 override 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x aux_ss_dis main_ss_dis erbst_f_sel[1:0] miso 00000000 00000000 aux_ss_dis main_ss_dis erbst_f_sel por wsm ssm aux_ss_dis 1 - - auxiliary 3.75mhz oscillator spread spectrum disable updated by por or spi write while in init state 0 spread spectrum enabled 1 spread spectrum disabled main_ss_dis 0 - - main 16mhz oscillator spread spectrum disable upd ated by por or spi write while in init state 0 spread spectrum enabled 1 spread spectrum disabled erbst_f_sel[1:0] 00 - - er boost switching frequency select upd ated by por or spi write while in init state 00 1.88 mhz 01 2.13 mhz 10 2.00 mhz 11 2.00 mhz docid025869 rev 3 71/200 l9678, l9678-s spi interface 199 5.1.19 scrap state entry comm and register (scrap_state) address: 30 type: w buffer: - reset: $0060 5.1.20 safing state entry co mmand register (safing_state) address: 31 type: w buffer: - reset: $0062 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - $3535 miso 00000000 000000000000 por wsm ssm n/a n/a n/a non-latched scrap state entry command enter scrap state from diag state 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - $acac miso 00000000 000000000000 por wsm ssm n/a n/a n/a non-latched safing state entry command enter safing state from diag state and clear arming pulse stretch counter (if received in diag or safing state) spi interface l9678, l9678-s 72/200 docid025869 rev 3 5.1.21 wd1 test comman d register (wd1_test) address: 35 type: w buffer: - reset: $006a 5.1.22 system diagnostic register (sysdiagreq) address: 36 type: rw buffer: $3601 reset: $006c 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - $3c x x x x x x x x miso 00000000 000000000000 por wsm ssm n/a n/a n/a non-latched wd1 test command wd1_test spi command as described in figure 36: watchdog state diagram . 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x dstest[3:0] miso 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 dstest[3:0] por wsm ssm dstest[3:0] 0000 0000 0000 diagno stic state test selection updated by ssm_reset or spi write while in diag state 0000 = all outputs inactive 0001 = arm pin active 0010 = all outputs inactive 0011 = all outputs inactive 0100 = all outputs inactive 0101 = all outputs inactive 0110 = vsf regulator active docid025869 rev 3 73/200 l9678, l9678-s spi interface 199 0111 = hs squib driver fet active 1000 = ls squib driver fet active 1001 = output deployment timing pul ses on arm1 (separated by 8 ms) 1010 = st reserved 1011 - 1111 = all outputs inactive spi interface l9678, l9678-s 74/200 docid025869 rev 3 5.1.23 diagnostic result register for deployment l oops (lpdiagstat) address: 37 type: r buffer: $3700 reset: - 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso diag_level tip 0fp feton st_reserved hsr_hi hsr_lo res_meas_chsel/ high_lev_diag_selected sbl stg stb sqp leak_chsel por wsm ssm diag_level 0 0 0 diagnostic mode selector not present for low level diagnostic updated by ssm_reset or spi write to lpdiagreq 0 low level mode 1 high level mode tip 0 0 0 high level diagnostic test is running updated by ssm_reset or loops diagnostic state machine 0 high level diagnostic ? test is not running 1 high level diagnostic ? test is running fp 0 0 0 fault present before requested diagnostic updated by ssm_reset or loops diagnostic state machine 0 fault not present ? before requested ? diagnostic 1 fault present before ? requested diagnostic feton 0 0 0 fet activation during diagnostic docid025869 rev 3 75/200 l9678, l9678-s spi interface 199 updated by ssm_reset or loops diagnostic state machine or when hs or ls fet is activated during diag state 0 fet is off during diagnostic 1 fet is on during diagnostic st_reserved 0 0 0 st_reserved hsr_hi 0 0 0 hsr diagnostic - high range updated by ssm_reset or loops diagnostic state machine or when squib resistance test is run 0 hsr measurement ? < hsr high value 1 hsr measurement ? > hsr high value hsr_lo 0 0 0 hsr diagnostic - low range updated by ssm_reset or loops diagnostic state machine or when squib resistance test is run 1 hsr measurement< hsr low value 0 hsr measurement > hsr low value res_meas_chsel [3:0] 0000 0000 0000 channel selected for resistance measurement updated by ssm_reset or loops diagnostic state machine or as determined by squib resistance channel selected 0000 = ch 0 0001 = ch 1 0010 = ch 2 0011 = ch 3 0100 - 1111 none selected high_lev_diag_ selected[3:0] 0000 0000 0000 0000 no diagnostic selected 0001 vrcm check 0010 leakage check 0011 short between loops check 0100 unused 0101squib resistance range check 0110 squib resistance measurement 0111 fet test 1000 - 1111 unused spi interface l9678, l9678-s 76/200 docid025869 rev 3 sbl 0 0 0 short between loop state updated by ssm_reset or loops diagnostic state machine 0 short between squib loops is not present 1 short between squib loops is present stg 0 0 0 short to ground test status updated by ssm_reset or loops diagnostic state machine or as determined by squib leakage diagnostic 0 stg not detected 1 1 stg detected stb 0 0 0 short to battery test status updated by ssm_reset or loops diagnostic state machine or as determined by squib leakage diagnostic 0 stb not detected 1 stb detected sqp 0 0 0 squib pin where leakage test has been performed updated by ssm_reset or loops diagnostic state machine or as determined by squib leakage diagnostic 0 srx 1 sfx leak_chsel[3:0] 0000 0000 0000 channel selected for leakage measurement updated by ssm_reset or loops diagnostic state machine or as determined by squib leakage diagnostic 0000 = ch 0 0001 = ch 1 0010 = ch 2 0011 = ch 3 0100 - 1111 none selected docid025869 rev 3 77/200 l9678, l9678-s spi interface 199 5.1.24 loops diagnostic configurati on command register for low level diagnostic (lpdiagreq) address: 38 type: rw buffer: $3800 reset: $0070 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - diag_level isrc_curr_sel pd_curr isrc [1:0] isink vrcm[1:0] res_meas_chsel[3:0] leak_chsel[3:0] miso 0000 diag_level isrc_curr_sel pd_curr isrc [1:0] isink vrcm[1:0] res_meas_chsel[3:0] leak_chsel[3:0] por wsm ssm diag_level 0 0 0 diagnost ic mode selector updated by ssm_reset or spi write 0 low level mode 1 n/a - see description below isrc_curr_sel 0 0 0 selection of isrc current value 0 40ma 1 8ma pd_curr 0 0 0 pull down current control updated by ssm_reset or spi write 0 request off only for channels connected to vrcm or isink or isrc, ? on for all other channels 1 request off for all channels isrc [1:0] 00 00 00 high side current source fo r channel selected in res_meas_chsel[3:0] updated by ssm_reset or spi write 00 = off 01 = on 40 ma current for chan nel selected in res_meas_chsel, ? off on all other channels spi interface l9678, l9678-s 78/200 docid025869 rev 3 10 = on bypass current for channel selected in res_meas_chsel, ? off on all other channels 11 = off isink 0 0 0 low side current sink control (max 50ma) updated by ssm_reset or spi write 0 all channels off 1 on for channel selected by res_meas_chsel[3:0], off on all other ? channels vrcm[1:0] 00 00 00 voltage regulator current monitor control updated by ssm_reset or spi write 00 vrcm not connected 01 vrcm connected to sfx of channel selected by leak_chsel[3:0] 01 vrcm connected to sfx of channel selected by leak_chsel[3:0] ? and pull down current of the same channel disabled 10 vrcm connected to srx of channel selected by leak_chsel[3:0] ? and pull down current of the same channel enabled (isink and isrc ? must be switched res_meas_chs el[3:0] 0000 0000 0000 squib resistance measurement channel select - selects the channel and muxes for the resistance test, and the channel for hs driver test (full path fet test) activation updated by ssm_reset or spi write 0000 channel 0 0001 channel 1 0010 channel 2 0011 channel 3 0100 - 1111 none selected leak_chsel[3:0] 0000 0000 000 0 squib leakage measurement channel select - selects the channel and muxes for the leakage test, and the channel for hs/ls fet test activation. updated by ssm_reset or spi write 0000 channel 0 0001 channel 1 0010 channel 2 0011 channel 3 0100 - 1111 none selected docid025869 rev 3 79/200 l9678, l9678-s spi interface 199 5.1.25 loops diagnostic configurati on command register for high level diagnostic (lpdiagreq) address: 38 type: rw buffer: $3800 reset: $0070 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - diag_level xx x xxxx high_level_diag_sel sqp loop_diag_chsel[3:0] miso 0000 diag_level 00 0 0000 high_level_diag_sel sqp loop_diag_chsel[3:0] por wsm ssm diag_level 0 0 0 diagnostic mode selector 0 0 n/a - see description above 1 1 high level mode high_level_diag _sel 000 000 000 selection of high level squib diagnostic updated by ssm_reset or spi write 000 no diagnostic selected 001 vrcm check 010 leakage check 011 short between loops check 100 unused 101 squib resistance range check 110 squib resistance measurement 111 fet test sqp 0 0 0 squib pin select for all leakage diagnostic updated by ssm_reset or spi write spi interface l9678, l9678-s 80/200 docid025869 rev 3 0 srx 1 sfx loop_diag_chse l[3:0] 0000 0000 0000 channel select - selects the channel and muxes for all squib diagnostic. ? updated by ssm_reset or spi write 0000 channel 0 0001 channel 1 0010 channel 2 0011 channel 3 0100 - 1111 none selected docid025869 rev 3 81/200 l9678, l9678-s spi interface 199 5.1.26 dc sensor diagnos tic configuration command register (swctrl) address: 39 type: rw buffer: $3900 reset: $0072 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x dcs_pdcurr swoen xx chid[3:0] miso 00000 00 0 0 000 dcs_pdcurr swoen 00 chid[3:0] por wsm ssm dcs_pdcurr 0 0 0 disable of all pull down current for dc sensor updated by ssm_reset or spi write 0 off for channel under voltage or cu rrent measurement, on for all other channels 1 off for all channels swoen 0 0 0 switch output enable updated by ssm _reset or spi write 0 off 1 on (40ma) chid[3:0] 0000 0000 0000 channel id - selects dc sensor channel for output activation updated by ssm _reset or spi write 0000 channel 0 0001 channel 1 0010 channel 2 0011 channel 3 0100 - 1111 none selected spi interface l9678, l9678-s 82/200 docid025869 rev 3 5.1.27 adc request and da ta registers (diagctrl_x) adc a control command (diagctrl_a) address: 3a type: rw buffer: $3a00 reset: $0074 adc b control command (diagctrl_b) address: 3b type: rw buffer: $3b00 reset: $0076 adc c control command (diagctrl_c) address: 3c type: rw buffer: $3c00 reset: $0078 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x adcreq_a[6:0] miso newdata_a 0 0 adcreq_a[6:0] adcres_a[9:0] 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x adcreq_b[6:0] miso newdata_b 0 0 adcreq_b[6:0] adcres_b[9:0] 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x adcreq_c[6:0] miso newdata_c 0 0 adcreq_c[6:0] adcres_c[9:0] docid025869 rev 3 83/200 l9678, l9678-s spi interface 199 adc d control command (diagctrl_d) address: 3d type: rw buffer: $3d00 reset: $007a 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x adcreq_d[6:0] miso newdata_d 0 0 adcreq_d[6:0] adcres_d[9:0] por wsm ssm newdata_x 0 0 0 new data available from convertion updated by ssm_reset or adc state machine 0 cleared on read 1 convertion finished adcreq_x[6:0] $00 $00 $00 adc request select command updated by ssm_reset or spi write to diagctrl_x measurement $00 unused $01 ground ref $02 full scale ref $030 dcsx voltage $04 dcsx current $05 dcsx resistance $06 squib x resistance $07 internal bg re ference voltage (bgr) $080 internal bg monitor voltage (bgm) $09 unused $0a temperature $0b dcs 0 voltage $0c dcs 1 voltage $0d dcs 2 voltage $0e dcs 3 voltage $20 vbatmon pin voltage $21 vin pin voltage $22 internal analog supply voltage (vint) $23 internal digital supply voltage (vdd) spi interface l9678, l9678-s 84/200 docid025869 rev 3 $24 erboost pin voltage $25 unused $26 ver pin voltage $27 vsup voltage $28 vddq voltage $29 wakeup pin voltage $2a vsf pin voltage $2b wdtdis pin voltage $2c gpod0 pin voltage $2d gpos0 pin voltage $2e gpod1 pin voltage $2f gpos1 pin voltage $30 unused $31 unused $32 rsu0 pin voltage $33 rsu1 pin voltage $34 unused $35 unused $36 ss0 pin voltage $37 ss1 pin voltage $38 ss2 pin voltage $39 ss3 pin voltage $3a unused $3b unused $3c unused $3d unused $3e unused $3f unused $40 unused $41 unused $42 vresdiag voltage $43 vdd5 voltage $44 vdd3v3 voltage $45 isok voltage $46 sf0 $47 sf1 $48 sf2 $49 sf3 $4a - $7f unused adcres_x[9:0] $000 $000 $000 10-bit adc result value corresponding to adcreq_x request updated by ssm_reset or adc state machine docid025869 rev 3 85/200 l9678, l9678-s spi interface 199 5.1.28 gpo configurat ion register (gpocr) address: 42 type: rw buffer: $4200 reset: $0084 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x gpo1ls gpo0ls miso 00000000 0000000000 gpo1ls gpo0ls por wsm ssm gpoxls 0 0 0 gpo driver configuration bit updated by ssm_reset or spi write 0 high-side driver configuration for gpox (er_boost_ok is required to enable gpo as hs) 1 low-side driver configuration for gpox (er_boost_ok is not required to enable gpo as ls) spi interface l9678, l9678-s 86/200 docid025869 rev 3 5.1.29 gpo configurati on register (gpoctrlx) channel 0 (gpoctrl0) channel 1 (gpoctrl1) address: 43 (gpoctrl0) ? 44 (gpoctrl1) type: rw buffer: $4300 (gpoctrl0) ? $4400 (gpoctrl1) reset: $0086 (gpoctrl0) ? $0088 (gpoctrl1) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x gpoxpwm[5:0] miso 00000000 000000 gpoxpwm[5:0] por wsm ssm gpoxpwm 000000 000000 000000 6 bit value for pwm% with scaling of 1.6% per count updated by ssm_reset or spi write docid025869 rev 3 87/200 l9678, l9678-s spi interface 199 5.1.30 gpo fault status register (gpofltsr) address: 46 type: r buffer: $4600 reset: - 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso 0 gpo1disable gpo0disable 0 gpo_not_conf 00 0 00 gpo1temp gpo1lim gpo1opn 00 gpo0temp gpo0lim gpo0opn 00 por wsm ssm gpo1disable 1 1 1 gpo 1 disable state 0 gpo enable to work 1 gpo disabled due to thermal fault or configuration not received or erboost not ok (only hs mode) gpo0disable 1 1 1 gpo 0 disable state 0 gpo enable to work 1 gpo disabled due to thermal fault or configuration not received or erboost not ok (only hs mode) gpo_not_conf 1 1 1 gpo configuration status 0 gpo hs/ls configured (activation is permitted) 1 gpo not yet configured (activation is denied) gpo1temp 0 0 0 gpo 1 thermal fault cleared by ssm_reset or spi read , set by detection circuit 0 fault not detected 1 fault detected gpo1lim 0 0 0 gpo 1 current limit flag cleared by ssm_reset or spi read, se t by detection circuit while on 0 fault not detected 1 fault detected gpo1opn 0 0 0 gpo 1 open detection cleared by ssm_reset or spi read, se t by detection circuit while on 0 fault not detected spi interface l9678, l9678-s 88/200 docid025869 rev 3 5.1.31 iso fault status register (isofltsr) address: 47 type: r buffer: $4700 reset: - 1 fault detected gpo0temp 0 0 0 gpo 0 thermal fault cleared by ssm_reset or spi read , set by detection circuit 0 fault not detected 1 fault detected gpo0lim 0 0 0 gpo 0 current limit flag ok cleared by ssm_reset or spi read, set by detection circuit while on 0 fault not detected 1 fault detected gpo0opn 0 0 0 gpo 0 open detection ok cleared by ssm_reset or spi read, set by detection circuit while on 0 fault not detected 1 fault detected 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso 00000000 0000000000 isotemp isolim por wsm ssm isotemp 0 0 0 iso thermal fault cleared by ssm_reset or spi read , set by detection circuit 0 fault not detected 1 fault detected isolim 0 0 0 iso current limit flag cleared by ssm_reset or spi read, set by detection circuit while on (isok=0) 0 fault not detected 1 fault detected docid025869 rev 3 89/200 l9678, l9678-s spi interface 199 5.1.32 remote sensor conf iguration register (rscrx) remote sensor configuration register 1 (rscr1) remote sensor configuration register 2 (rscr2) address: 4a (rscr1) ? 4b (rscr2) type: rw buffer: $4a00 (rscr1) ? $4b00 (rscr2) reset: $0094 (rscr1) ? $0096 (rscr2) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x slowtrack startbitsmeas_disable xx blktxsel xx x xxx stsx[3:0] miso 00000 slowtrack startbitsmeas_disable 00 blktxsel 00 0 000 stsx[3:0] por wsm ssm slowtrack 0 0 0 reduce frequen cy of base current tracking 0 8s/1s 1 16s/2s startbitsmeas_ disable 0 0 0 disable of start bits period measure to decode data bits 0 period of start bits used to decode following data bits 1 period of start bits not used to decode following data bits blktxsel 0 0 0 current limiting blanking time select for channel x updated by ssm_reset or spi write 0 blanking time = 5ms 1 blanking time = 10ms spi interface l9678, l9678-s 90/200 docid025869 rev 3 5.1.33 remote sensor control register (rsctrl) address: 4e type: r/w buffer: $4e00 reset: $009c por wsm ssm stsx[3:0] 0000 0000 0000 remote sensor type select updated by ssm_reset or spi write 0000 async psi5, parity, 8-bit, 125k (a8p-228/1l) 0001 async psi5, parity, 8-bit, 189k (a8p-228/1h) 0010 async psi5, parity, 10-bit, 125k (a10p-228/1l) 0011 async psi5, parity, 10-bit, 189k (a10p-228/1h) 0100-1111 async psi5, parity, 10-bit, 189k (a10p-228/1h) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x ch1en x ch0en x miso 00000000 00000000 ch1en 0 ch0en 0 por wsm ssm chxen 0 0 0 channel x output enable updated by ssm_reset or spi write 0 off 1 on docid025869 rev 3 91/200 l9678, l9678-s spi interface 199 5.1.34 remote sensor data/fau lt registers w/o fault (rsdrx) remote sensor 0 data and fault flag register (rsdr0) remote sensor 1 data and fault flag register (rsdr1) note: the value in bit15 (flt) will re-define the use of the other bi ts, hence the info rmations below are divided into two groups. bit 15 = 0 no fault condition address: 50 (rsdr0) ? 51 (rsdr1) type: r buffer: $5000 (rsdr0) ? $5100 (rsdr1) reset: - 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso crc 0 flt=0 on/off lcid [3:0] data [9:0] por wsm ssm crc[2:0] 000 000 000 crc based on bits [16:0] updated based on bits [16:0] flt 1 1 1 fault status - depending on fault status, the data bits are defined differently cleared when all of the following bits are '0': stg, stb, current_hi, opendet, rstemp, nodata set when any of the following bits are '1': stg, stb, current_hi, opendet, rstemp, nodata 0 no fault 1 fault on/off 0 0 0 channel on/off status cleared by ssm_reset or when channel is commanded off via spi rsctrl or when the stg bit is set or the rstemp bit is set set when channel is commanded on by spi rsctrl 0 off 1 on lcid[0:3] 0000 0000 0000 logical channel id spi interface l9678, l9678-s 92/200 docid025869 rev 3 bit 15 = 1 faulted condition address: 50 (rsdr0) ? 51 (rsdr1) type: r buffer: $5000 (rsdr0) ? $5100 (rsdr1) reset: - updated based on spi read request 0000 rsu0 0100 rsu1 data[9:0] $000 $000 $000 10-bit data from manchester decoder cleared by ssm_reset or spi read or when channel is commanded off via spi rsctrl updated when a valid psi5 frame is received 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso crc x flt=1 on/off lcid [3:0] stg stb current_hi opendet rstemp invalid nodata 0xx por wsm ssm crc[2:0] 000 000 000 crc based on bits [16:0] updated based on bits [16:0] flt 1 1 1 fault status - depending on fault status, the data bits are defined differently cleared when all of the following bits are '0': stg, stb, current_hi, opendet, rstemp, nodata set when any of the following bits are '1': stg, stb, current_hi, opendet, rstemp, nodata 0 no fault 1 fault on/off 0 0 0 channel on/off status cleared by ssm_reset or when channel is commanded off via spi rsctrl or when the stg bit is set or the rstemp bit is set set when channel is commanded on by spi rsctrl 0 off docid025869 rev 3 93/200 l9678, l9678-s spi interface 199 1 on lcid[0:3] 0000 0000 0000 logical channel id updated based on spi read request 0000 rsu0 0100 rsu1 stg 0 0 0 short to ground (in current limit condition) cleared by ssm_reset or when channel is commanded off via spi rsctrl 0 no fault 1 fault stb 0 0 0 short to battery cleared by ssm_reset or spi read or when channel is commanded off via spi rsctrl - not cleared by channel off caused by stg or rstemp set when channel voltage exceeds vsup for a time greater than tstbth 0 no fault 1 fault current_hi 0 0 0 current high cleared by ssm_reset or spi read or when channel is commanded off via spi rsctrl set when channel current exceeds ilkgg for a time determined by an up/down counter 0 no fault 1 fault opendet 0 0 0 open sensor detected cleared by ssm_reset or spi read or when channel is commanded off via spi rsctrl set when channel current exceeds ilkgb for a time determined by an up/down counter 0 no fault 1 fault rstemp 0 0 0 over temperature detected cleared by ssm_reset or when channel is commanded off via spi rsctrl set when over-temp condition is detected 0 no fault 1 fault spi interface l9678, l9678-s 94/200 docid025869 rev 3 invalid 0 0 0 invalid data cleared by ssm_reset or spi read or when channel is commanded off via spi rsctrl or if one of the foll owing is set: stg, stb, current_hi, open_det, rstemp set when two valid start bits are received and a manchester error (# of bits, bit timing) or parity error is detected 0 no fault 1 fault nodata 1 1 1 no data in buffer cleared when a valid psi frame is received or if one of the following is set: stg, stb, current_hi, open_det, rstemp set upon spi read of rsdrx if fifo em pty and none of the following bits are set: stg, stb, current_hi, open_det, rstemp 0 no fault 1 fault docid025869 rev 3 95/200 l9678, l9678-s spi interface 199 5.1.35 safing algorithm configur ation register (saf_algo_conf) address: 66 type: r/w buffer: $6600 reset: $00cc 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - no_data x armn_th armp_th sub_val add_val miso 0000 no_data 0 armn_th armp_th sub_val add_val por wsm ssm no_data 0 0 0 event counter no data select updated by ssm_reset or spi write while in diag state 0 event counter reset to 0 if cc=0 when spi read of saf_cc bit is performed (end of sample cycle) 1 event counter decremented by sub_val if cc=0 when spi read of saf_cc bit is performed (end of sample cycle) armn_th 0011 0011 0011 negative event counter threshold to assert arming updated by ssm _reset or spi write while in diag state 0000 negative event counter disabled armp_th 0011 0011 0011 positive event counter threshold to assert arming updated by ssm _reset or spi write while in diag state 0000 positive event counter disabled sub_val 011 011 011 decremental step size of the event counter updated by ssm _reset or spi write while in diag state add_val 001 001 001 incremental step size of the event counter updated by ssm _reset or spi write while in diag state spi interface l9678, l9678-s 96/200 docid025869 rev 3 5.1.36 arming signals register (arm_state) address: 6a type: r buffer: $6a00 reset: - 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso 00000 00 0 0 000 acl_pin_state acl_valid 00 armint_2 armint_1 fenl fenh por wsm ssm acl_valid 0 0 0 valid acl detection 0 cleared when acl_bad=2 1 set when acl_good=3 acl_pin_state - - - echo of acl pin armint_x 0 0 0 state of armint signals upd ated per safing engine output logic diagram fenh/fenl - - - state of external arming control signals upd ated based on pin state docid025869 rev 3 97/200 l9678, l9678-s spi interface 199 5.1.37 armx assignment regi sters (loop_matrix_armx) assignment of arm1 to specific loops ( loop_matrix_arm 1) assignment of arm2 to specific loops ( loop_matrix_arm 2) address: 6e (loop_matrix_arm1) ? 6f (loop_matrix_arm2) type: rw buffer: $6e00 (loop_matrix_arm1) ? $6f00 (loop_matrix_arm2) reset: $00dc (loop_matrix_arm1) ? $00de (loop_matrix_arm2) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x armx_l3 armx_l2 armx_l1 armx_l0 miso 00000000 00000000 armx_l3 armx_l2 armx_l1 armx_l0 por wsm ssm armx_ly 0 0 0 configures armx for loop_y updated by ssm_reset or spi write while in diag state 0 armx signal is not associated with loopy 1 armx signal is associated with loopy spi interface l9678, l9678-s 98/200 docid025869 rev 3 5.1.38 armx pulse stretc h registers (aepsts_armx) arm1 enable pulse stretch timer status (aepsts_arm1) arm2 enable pulse stretch timer status (aepsts_arm2) address: 73 (aepsts_arm1) ? 74 (aepsts_arm2) type: rw buffer: $7300 (aepsts_arm1) ? $7400 (aepsts_arm2) reset: - (aepsts_arm1) ? - (aepsts_arm2) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso 0 0 0 0 0 0 0 0 0 0 timer count[9:0] por wsm ssm timer count 0000 0000 0000 10-bit arming enable pulse stretcher timer value cleared by ssm_reset loaded with initial value based on armx bit and dwell[1:0] of saf_control_y while safing is met for record y provided current value is < dwell[1:0] value decremented every 2ms while > 0 contains remaining pulse stretcher timer value docid025869 rev 3 99/200 l9678, l9678-s spi interface 199 5.1.39 safing records enable register (saf_enable) address: 7f type: rw buffer: $7f00 reset: $00fe 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x en_saf4 en_saf3 en_saf2 en_saf1 miso 00000 00 0 0 000 en_saf4 en_saf3 en_saf2 en_saf1 por wsm ssm en_safx 0 0 0 safing record enable updated by ssm_reset or spi write 0 disable 1 enable spi interface l9678, l9678-s 100/200 docid025869 rev 3 5.1.40 safing records request mask registers (saf_req_mask_x) safing record request mask for record 1 (saf_req_mask_1) safing record request mask for record 2 (saf_req_mask_2) safing record request mask for record 3 (saf_req_mask_3) safing record request mask for record 4 (saf_req_mask_4) address: 80 (saf_req_mask_1) ? 81 (saf_req_mask_2) ? 82 (saf_req_mask_3) ? 83 (saf_req_mask_4) type: rw buffer: $8000 (saf_req_mask_1) ? $8100 (saf_req_mask_2) ? $8200 (saf_req_mask_3) ? $8300 (saf_req_mask_4) reset: $8000 (saf_req_mask_1) ? $8002 (saf_req_mask_2) ? $8004 (saf_req_mask_3) ? $8006 (saf_req_mask_4) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - saf_req_maskx[15:0] miso 0 0 0 0 saf_req_maskx[15:0] por wsm ssm saf_req_maskx [15:0] 0000 0000 0000 safing request mask for safing record x - 16-bit request mask that is bit-wise anded with mosi data from spi monitor updated by ssm_reset or spi write while in diag state docid025869 rev 3 101/200 l9678, l9678-s spi interface 199 5.1.41 safing records request ta rget registers (s af_req_target_x) safing record request mask for record 1 (saf_req_target_1) safing record request mask for record 2 (saf_req_target_2) safing record request mask for record 3 (saf_req_target_3) safing record request mask for record 4 (saf_req_target_4) address: 93 (saf_req_target_1) ? 94 (saf_req_target_2) ? 95 (saf_req_target_3) ? 96 (saf_req_target_4) type: rw buffer: $9300 (saf_req_target_1) ? $9400 (saf_req_target_2) ? $9500 (saf_req_target_3) ? $9600(saf_req_target_4) reset: $8026 (saf_req_target_1) ? $8028 (saf_req_target_2) ? $802a (saf_req_target_3) ? $802c (saf_req_target_4) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - saf_req_targetx[15:0] miso 0 0 0 0 saf_req_targetx[15:0] por wsm ssm saf_req_targetx [15:0] 0000 0000 0000 safing request target for safing record x - 16-bit request target that is compared to the bit-wise and resu lt of the saf_req_maskx and mosi data from spi monitor updated by ssm_reset or spi write while in diag state spi interface l9678, l9678-s 102/200 docid025869 rev 3 5.1.42 safing records response mask registers (saf_resp_mask_x) safing record response mask for record 1 (saf_resp_mask_1) safing record response mask for record 2 (saf_resp_mask_2) safing record response mask for record 3 (saf_resp_mask_3) safing record response mask for record 4 (saf_resp_mask_4) address: a6 (saf_resp_mask_1) ? a7 (saf_resp_mask_2) ? a8 (saf_resp_mask_3) ? a9 (saf_resp_mask_4) type: rw buffer: $a600 (saf_resp_mask_1) ? $a700 (saf_resp_mask_2) ? $a800 (saf_resp_mask_3) ? $a900 (saf_resp_mask_4) reset: $804c (saf_resp_mask_1) ? $804e (saf_resp_mask_2) ? $8050 (saf_resp_mask_3) ? $8052 (saf_resp_mask_4) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - saf_resp_maskx[15:0] miso 0 0 0 0 saf_resp_maskx[15:0] por wsm ssm saf_resp_maskx [15:0] 0000 0000 0000 safing response mask for safing record x - 16-bit response mask that is bit- wise anded with miso data from spi monitor updated by ssm_reset or spi write while in diag state docid025869 rev 3 103/200 l9678, l9678-s spi interface 199 5.1.43 safing records response ta rget registers (s af_resp_target_x) safing record response target for record 1 (saf_resp_target_1) safing record response mask for record 2 (saf_resp_target_2) safing record response mask for record 3 (saf_resp_target_3) safing record response mask for record 4 (saf_resp_target_4) address: b9 (saf_resp_target_1) ? ba (saf_resp_target_2) ? bb (saf_resp_target_3) ? bc (saf_resp_target_4) type: rw buffer: $b900 (saf_resp_target_1) ? $ba00 (saf_resp_target_2) ? $bb00 (saf_resp_target_3) ? $bc00 (saf_resp_target_4) reset: $8072 (saf_resp_target_1) ? $8074 (saf_resp_target_2) ? $8076 (saf_resp_target_3) ? $8078 (saf_resp_target_4) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - saf_resp_targetx[15:0] miso 0 0 0 0 saf_resp_targetx[15:0] por wsm ssm saf_resp_targetx [15:0] 0000 0000 0000 safing response target for safing record x - 16-bit response target that is compared to the bit-wise and resu lt of the saf_resp_ maskx and miso data from spi monitor updated by ssm_reset or spi write while in diag state spi interface l9678, l9678-s 104/200 docid025869 rev 3 5.1.44 safing records data m ask registers (saf_data_mask_x) safing record data mask for record 1 (saf_data_mask_1) safing record data mask for record 2 (saf_data_mask_2) safing record data mask for record 3 (saf_data_mask_3) safing record data mask for record 4 (saf_data_mask_4) address: cc (saf_data_mask_1) ? cd (saf_data_mask_2) ? ce (saf_data_mask_3) ? cf (saf_data_mask_4) type: rw buffer: $cc00 (saf_data_mask_1) ? $cd00 (saf_data_mask_2) ? $ce00 (saf_data_mask_3) ? $cf00 (saf_data_mask_4) reset: $8098 (saf_data_mask_1) ? $809a (saf_data_mask_2) ? $809c (saf_data_mask_3) ? $809e (saf_data_mask_4) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - saf_data_maskx[15:0] miso 0 0 0 0 saf_data_maskx[15:0] por wsm ssm saf_data_maskx [ 15:0] 0000 0000 0000 safing data mask for safing record x - 16-bit data mask that is bit-wise anded with miso data from spi monitor updated by ssm_reset or spi write while in diag state docid025869 rev 3 105/200 l9678, l9678-s spi interface 199 5.1.45 safing records thres hold registers (saf_threshold_x) safing record threshold for record 1 (saf_threshold_1) safing record threshold for record 2 (saf_threshold_2) safing record threshold for record 3 (saf_threshold_3) safing record threshold for record 4 (saf_threshold_4) address: df (saf_threshold_1) ? e0 (saf_threshold_2) ? e1 (saf_threshold_3) ? e2 (saf_threshold_4) type: rw buffer: $df00 (saf_threshold_1) ? $e000 (saf_threshold_2) ? $e100 (saf_threshold_3) ? $e200 (saf_threshold_4) reset: $80be (saf_threshold_1) ? $80c0 (saf_threshold_2) ? $80c2 (saf_threshold_3) ? $80c4 (saf_threshold_4) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - saf_thresholdx[15:0] miso 0 0 0 0 saf_thresholdx[15:0] por wsm ssm saf_thresholdx [15:0] $ffff$ffff $ffff safing threshold for safing record x - 16-bit threshold used for safing data comparison updated by ssm_reset or spi write while in diag state spi interface l9678, l9678-s 106/200 docid025869 rev 3 5.1.46 safing control registers (saf_control_x) safing control register for record 1 (saf_control_1) safing control register for record 2 (saf_control_2) safing control register for record 3 (saf_control_3) safing control register for record 4 (saf_control_4) address: $ef (saf_control_1) ? $f0 (saf_control_2) ? $f1 (saf_control_3) ? $f2 (saf_control_4) type: rw buffer: $ef00 (saf_control_1) ? $f000 (saf_control_2) ? $f100 (saf_control_3) ? $f200 (saf_control_4) reset: $80de (saf_control_1) ? $80e0 (saf_control_2) ? $80e2 (saf_control_3) ? $80e4 (saf_control_4) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - armselx spifldselx lim selx lim enx combx dwellx[1:0] xx arm2x arm1x csx[2:0] ifx miso 0000 armselx spifldselx lim selx lim enx combx dwellx[1:0] 00 arm2x arm1x csx[2:0] ifx por wsm ssm armselx 00 00 00 armint select for safing reco rd x - correlates armi nt 1 and armint2 (as determined by arm1x and arm2x bits) to armp and armn updated by ssm_reset or spi write while in diag state 00 armp or armn 01 armp 10 armn 11 armp or armn spifldselx 0 0 0 spi field select for safing record x - determines which 16-bit field in long spi messages (>31 bit) to use for response on miso of spi monitor. in case of messages less than 32 bits this bit is don't care. docid025869 rev 3 107/200 l9678, l9678-s spi interface 199 updated by ssm_reset or spi write while in diag state 0 first 16 bits of spi miso frame used for response mask and data ? mask bit-wise and 1 last 16 bits of spi miso frame used for response mask and data ? mask bit-wise and lim selx 0 0 0 data range limit select for safi ng record x - when enabled, determines the range limit used for incoming sensor data updated by ssm_reset or spi write while in diag state 0 8-bit data range limit - incoming |dat a| >120d is not recognized as valid ? data 1 10-bit data range limit - incomi ng |data| > 480d is not recognized as ? valid data lim enx 0 0 0 data range limit enable for safing record x updated by ssm_reset or spi write while in diag state 0 data range limit disabled 1 data range limit enabled combx 0 0 0 combine function enable for safing record x updated by ssm_reset or spi write while in diag state 0 combine function disabled 1 combine function enabled for record pairs = x,x+1, the comparison for record x uses |data(x) + ? data(x+1)| and the comparison for record x+1 uses |data(x) - data(x+1)| record pairs are 1,2 and 6,7 dwellx[1:0] 00 00 00 safing dwell extension time select for safing record x updated by ssm_reset or spi write while in diag state 00 2048 ms 01 256 ms 10 32 ms 11 0 ms arm2x 0 0 0 arm2int select for safing record x - correlates safing result to arm2int updated by ssm_reset or spi write while in diag state 0 safing record x not assigned to arm2int 1 safing record x assigned to arm2int arm1x 0 0 0 arm1int select for safing record x - correlates safing result to arm1int updated by ssm_reset or spi write while in diag state spi interface l9678, l9678-s 108/200 docid025869 rev 3 0 safing record x not assigned to arm1int 1 safing record x assigned to arm1int csx[2:0] 000 000 000 spi monitor cs select for safing record x updated by ssm_reset or spi write while in diag state 000 none selected for record x 001 saf_cs0 selected for record x 010 saf_cs1 selected for record x 011 none selected for record x 100 none selected for record x 101 spi_cs selected for record x 110 none selected for record x 111 none selected for record x ifx 0 0 0 spi format select for safing record x - selects re sponse protocol for spi monitor updated by ssm_reset or spi write while in diag state 0 out of frame response for record x 1 in frame response for record x docid025869 rev 3 109/200 l9678, l9678-s spi interface 199 5.1.47 safing record compar e complete register (saf_cc) address: ff type: r buffer: $ff00 reset: - 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi - x x x x x x x x x x x x x x x x miso 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cc_4 cc_3 cc_2 cc_1 por wsm ssm cc_xx 0 0 0 indicates compare complete status of each of the 4 safing records, and defines the end of the sample cycle for safing cleared by ssm_reset or spi read, set by safing engine when request, response mask and target registers match the incoming spi frame 0 compare not completed for record x 1 compare completed for record x deployment drivers l9678, l9678-s 110/200 docid025869 rev 3 6 deployment drivers the squib deployment block consists of 4 independent high side drivers and 4 independent low side drivers. squib deployment logic requires a deploy command received through spi communications and either an arming condition processed by safing logic or a proper fenh and fenl input pin assessment, depending on whet her the internal safing engine is used or not. fenh signal is used to enable high side squib drivers and is active high, while fenl enables low side drivers and is active low. both conditions must exist in order for the deployment to occur. on ce a deployment is initiated, it can only be termin ated by a reset event. l9678 allows all 4 squib loops to be deployed at the very same time or in other possible timing sequence. deployment drivers are capabl e of granting a successful deployment also in case of short to ground on lo w-side circuit (srx pins). firing voltage capability across high side circuit is maximum 25 v. high side and low side drivers account for a maximum series total resistance of 2 ? . each loop is granted for a minimum number of deployments of 50, under all normal operating conditions and with a deployment repetition time higher than 10s. 6.1 control logic a block diagram representing the deployment dr iver logic is shown below. deployment driver logic features include: ? deploy command logic ? deployment current selection ? deployment current monitoring and deploy success feedback ? diagnostic control and feedback figure 20. deployment driver control blocks ' ! 0 ' 0 3 ' h s o r \ 5 h t x h v w 9 d o l g d w l r q ' h s o r \ p h q w & r q w u r o 7 l p l q j + l j k 6 l g h ) ( 7 / r z 6 l g h ) ( 7 & x u u h q w 0 r q l w r u ' & 5 ' 6 5 [ ' ( 3 & 2 0 ' h s o r \ p h q w & r p p d q g 5 h j l v w h u ' h s o r \ p h q w & r q i l j x u d w l r q 5 h j l v w h u ' & 0 7 6 [ ; ) ( 1 / ' h s o r \ p h q w & r q i l j x u d w l r q 5 h j l v w h u ' & 5 ' h s o r \ p h q w & r q i l j x u d w l r q 5 h j l v w h u ' & 5 ' h s o r \ & x u u h q w 0 r q l w r u 6 w d w x v ' h s o r \ p h q w 6 w d w x v 5 h j l v w h u ; 6 ) [ ; 6 5 [ l q w f o n , 7 + ' ( 3 / 6 d i l q j ( q j l q h 3 u r j u d p p d e o h / r r s $ v v l j q p h q w v ; ) ( 1 + , q w ( [ w v d i l q j h q j l q h , q w ( [ w v d i l q j h q j l q h ; $ 5 0 docid025869 rev 3 111/200 l9678, l9678-s deployment drivers 199 figure 21. deployment driver control logic - enable signal figure 22. deployment driver control logic - turn-on signals the high level block diagram for the deployment drivers is shown below: ' ! 0 ' 0 3 ) ( 1 + $ 5 0 , 1 * 6 7 $ 7 ( $ 5 0 , 1 7 $ 5 0 b / [ $ 5 0 , 1 7 $ 5 0 b / [ ) ( 1 / ( 1 $ % / ( b + 6 [ ( 1 $ % / ( b / 6 [ $ q d o r j ' h s o r \ p h q w % o r f n 6 $ ) , 1 * 6 7 $ 7 ( 6 $ ) ( 6 ( / / 3 ' , $ * 5 ( 4 / ( $ . b & + 6 ( / [ ' 6 7 ( 6 7 / 6 ) ( 7 b 7 ( 6 7 ' , $ * 6 7 $ 7 ( / 3 ' , $ * 5 ( 4 / ( $ . b & + 6 ( / [ ' 6 7 ( 6 7 + 6 ) ( 7 b 7 ( 6 7 ' , $ * 6 7 $ 7 ( $ 5 0 b ( 1 ' ! 0 ' 0 3 8 s & w u ( 1 & / 5 ' ( 3 b ' , 6 $ % / ( ' 6 7 $ 7 ( 6 $ ) , 1 * 6 7 $ 7 ( $ 5 0 , 1 * 6 7 $ 7 ( ' ( 3 b ( 1 $ % / ( ' 6 7 $ 7 ( 6 3 , b ' ( 3 5 ( 4 [ ( 1 $ % / ( b + 6 [ ( 1 $ % / ( b / 6 [ ' , $ * 6 7 $ 7 ( ' 6 7 ( 6 7 3 8 / 6 ( ( [ s l u d w l r q 7 l p h u ' h s o r \ 7 l p h u / 3 ' , $ * 5 ( 4 / ( $ . b & + 6 ( / [ $ 1 $ / 2 * ' h s o r \ p h q w % / 2 & . + 6 b 2 1 [ / 6 b 2 1 [ / 6 b 2 9 ( 5 b & 8 5 [ 6 6 0 5 ( 6 ( 7 6 5 6 5 ( ; 3 b 7 k u h v k 6 5 8 s & w u ( 1 & / 5 6 6 0 5 ( 6 ( 7 * 1 ' b / 2 6 6 [ ' 6 7 ( 6 7 + 6 ) ( 7 b 7 ( 6 7 ' 6 7 ( 6 7 / 6 ) ( 7 b 7 ( 6 7 ' ( 3 b 7 k u h v k & + [ 6 7 $ 7 & + [ ' ( 3 6 5 & + [ ' 6 6 5 deployment drivers l9678, l9678-s 112/200 docid025869 rev 3 figure 23. deployment driver block 6.1.1 deployment current selection deployment current is programmed for all chann els using the deploy configuration register (dcrx) shown in ?deployment configuration register (dcrx). if 1.75 a deployment current is selected, the 2 ms deployment time cannot be chosen. if a spi command with 2 ms and 1.75 a selection is received, l9678 will discard it and switch to a 500 s and 1.2 a selection instead. this misuse is flagged with the chxdd bit in the deploy status register (dsr). 6.1.2 deploy command expiration timer deploy commands are received for all channels using spi communications. once a deploy command is received, it will rema in valid for a specified time period selected in the deploy configuration register (dcrx). the deploy stat us and deploy expiration timer can be read through the deploy status register (dsrx). th e deploy expiration timer is 6 bits and the maximum time is 500 ms nominal. * $ 3 * 3 6 6 6 [ \ 6 ) [ 6 5 [ 6 * [ \ q ) q ) 5 v t x l e / 6 b 2 1 , o l p l w ! $ w \ s + 6 b 2 ) ) 7 r g h s o r \ f x u u h q w ! f r x q w h u 5 5 5 p 7 2 3 z l w k v z l w f k l q j 2 i i v h w f r p s h q v d w l r q , 5 ( ) p $ [ , 5 ( ) 2 s h q w r v k r u w f r p s 5 9 f o d p s ! 9 6 d p h s r z h u w u d q v l v w r u ( q d e o h b / 6 [ 9 ( q d e o h b + 6 [ ( 1 b , 6 , 1 . 2 3 s k d v h 2 3 s k d v h / 6 b 2 & b & r p s * 1 ' 6 8 % / r v v j u r x q g g l r g h / 6 b / r v v b * q g , s x o o g r z q , o l p l w p $ w \ s docid025869 rev 3 113/200 l9678, l9678-s deployment drivers 199 6.1.3 deployment control flow deployment control logic requires the following conditions to be true to successfully operate a deployment: ? por = 1 ? ssm to be either in safing state or arming state ? a valid arming condition processed by safing logic or fenh and fenl signals to be set (depending on selection of internal or external safing engine) ? "channel-specific deploy command request bits to be set via spi in the deploy command register (depcom) ? a global deployment state has to be active, as described in the following figure. figure 24. global spi deployment enable state diagram in case a multiple deployment request would be needed, i.e. deploying the same channel in sequence, a toggle on d ep_disabled has to be performed and a new depcom command on the same channel has to be sent. the spi depcom command is ignored if the dev ice is in the dep_disabled state and the deploy command is not set. while in dep_enabl ed state, the following functionalities that could be active are forced to their reset state: ? all squib and dc sensor diagnostic current or voltage sources ? all squib, dc sensor and adc diagnos tic mux settings, state machine, etc. the spi_lock and spi_unlock signals ar e available in the spidepen command: high-side and low-side enablers by internal/external safing are global and apply to all channels. the deploy commands in the depl oy command register (depcom) are channel specific. deployment requires a valid arming command from safing logic or the fenh and fenl signals to be set any time before, during or af ter the specific sequenc e of deploy commands is received. it is feasible for a deploy command to be received without a valid arming command from safing logic or the fenh and fenl being set. in this case, the deploy command will be terminated acco rding to the deploy command expiration timer described in section 6.1.2 . likewise, a valid arming command or the fenh and fenl signals can be set without receiving a deploy command. in this case, th e enabling signals will remain active according to the arming enable pulse st retch timer or the fenx enabling state. the arming enable pulse stretch timers is available in the aepsts register. ' ! 0 ' 0 3 ' ( 3 b ( 1 $ % / ( ' ' ( 3 b ' , 6 $ % / ( ' 6 3 , b 6 3 , ' ( 3 ( 1 ' ( 3 ( 1 b : 5 8 1 / 2 & . 6 6 0 b 5 h v h w 6 3 , b 6 3 , ' ( 3 ( 1 ' ( 3 ( 1 b : 5 / 2 & . deployment drivers l9678, l9678-s 114/200 docid025869 rev 3 6.1.4 deployment success deploy success flag is set when the deploy time r elapses. this bit (chxds) is contained in the deploy status register. within the global status word register (gsw), a single bit (depok) is also set once any of the four deployment channels sets a deploy success flag. 6.2 energy reserve - deployment voltage one deployment voltage source pin is used for channels 0 and 1 (ss01) and one for channels 2 and 3 (ss23). these pins are directly connected to the high side drivers for each channel. 6.3 deployment ground return there are dedicated power ground connections for deployment current, sgx pins. one ground connection is sufficient for two deployments occurring simultaneously. 6.4 deployment driver protections 6.4.1 delayed low-side deactivation to control voltage spikes at the squib pins during drivers deactivation at the end of a deployment, the low side driver is switched off after t del_sd_ls delay time with respect to the high side deactivation. 6.4.2 low-side voltage clamp the low side driver is protected against overvo ltage at the srx pins by means of a clamping structure as shown in figure 23 . when the low side driver is turned off, voltage transients at the srx pin may be caused by squib inductance. in this case a low side fet drain to gate clamp will reactivate the low side fet allowing for residual inductance current recirculation, thus preventing potential low side fet damage by overvoltage. 6.4.3 short to battery the low side driver is equipped with current limit ation and overcurrent protection circuitry. in case of short to battery at the squib pins, the short circuit current is limited by the low side driver to i lim_sr . if this condition lasts for longer than t flt_ilim_ls deglitch filter time then the low and high-side drivers will be switched off and latched in th is state until a new deployment is commanded after spi_depen is re triggered. 6.4.4 short to ground the squib driver is designed to stand a short to ground at the squib pins during deployment. in particular, the current flowing through the shor t circuit is limited by the high side driver (deployment current) and the high-side fet is sized to handle the related energy. in case the short to ground during deployment occurs after an open circuit, a protection against damage is also available. the high side current regulator would have normally reacted to the open circuit by increasing the vgs of the high side fet. thanks to a dedicated docid025869 rev 3 115/200 l9678, l9678-s deployment drivers 199 fast comparator detecting the open condition, the driver is able to discharge the fet gate quickly in order to reduce current overshoot and prevent potential driver damage when the short to ground occurs. 6.4.5 intermittent open squib a dedicated protection is also available in ca se of intermittent open load during deployment. in this case, if load is restored after an open circuit, due to slow reaction of the high-side current regulation loop, the current through the squib is limited only to i limsrx by the low side driver. if this condition lasts for longer than t limos then the high side is turned off for t hsoffos and then reactivated. by this feature, intermittent open squib and short to battery faults may be distinguished and handled properly by the drivers. 6.5 diagnostics the l9678 provides the following diagnostic feedback for all deployment channels: ? high voltage leakage test for oxide isolation check on sfx and srx ? leakage to battery and ground on both sfx and srx pins with or without a squib ? loop to loop short diagnostics ? squib resistance measurement with leakage cancellation ? high squib resistance with range from 500 ? to 2000 ? ? ssxy, sfx and ver voltage status ? high and low side fet diagnostics ? high side driver diagnostics ? loss of ground return diagnostics ? high side safing fet diagnostics ? deployment timer diagnostic the above diagnostic results are processed thro ugh a 10 bit analog to digital algorithmic converter. these tests can be addressed in two different ways, with a high level approach or a low-level one. the main difference between the two approaches is that with the low level approach the user is allowed to precisely cont rol the diagnostic circuitry, also deciding the proper timings involved in the different tests. on the other hand, the high level approach is an automatic way of getting diagnostic results for which an internal state machine is taking care of instructions and timings. the following is the block diag ram of the squib diagnostics. deployment drivers l9678, l9678-s 116/200 docid025869 rev 3 figure 25. deployment loop diagnostics the leakage diagnostic includes short to batter y, short to ground and shorts between loops. the test is applied to each sfx and srx pin so shorts can be detected regardless of the resistance between the squib pins. 6.5.1 low level diagnostic approach in this approach, each of the test steps described in the sections below requires user intervention by issuing the proper spi command. high voltage leakage test for oxide isolation check this test is mandatory to address possible le akages that could not be experienced at low voltages on sfx or srx pins. the i source current generator (isrc) is enabled on the chosen sfx pin. to confirm that the sfx pin has then reached a suitable voltage level, a dedicated adc measurement on the sfx pin can be requested. once this test is performed, a leakage test on sfx and srx pins can be issued to double check possible leakages. leakage to battery/ground diagnostics prior to the real test, the voltage regulator current monitor block (vrcm) has to be tested and validated. the validation of vrcm goes into verifying both the short to battery and short to ground flags. the i source current generator (isrc) is first connec ted to sfx pin to raise its voltage to vresdiag. then, the voltage regulator current monitor block (vrcm) is enabled and connected to the selected sfx pin. the i sink current limited switch (isn k) is turned off, as * $ 3 * 3 6 6 6 [ \ 6 ) [ 6 5 [ 6 * [ q ) q ) q ) , o l p l w p $ p $ * d l q 9 r i i v h w $ w r ' e l w 7 r w h u u ? / 6 % / 6 % 9 6 t x l e u h v l v w r u + , * + 6 t x l e u h v l v w r u / 2 : + 9 d q d o r j 0 8 ; 9 u h i y 9 u h i y 6 k r u w w r * 1 ' 5 o h d n ! . 7 7 q r g h w h f w l r q g h w h f w l r q 5 o h d n . 5 o h d n ! . 7 7 q r g h w h f w l r q g h w h f w l r q 5 o h d n . 6 k r u w w r % $ 7 9 5 & 0 y r o w d j h u h j x o d w r u f x u u h q w p r q l w r u 6 t x l e u h v l v w d q f h p h d v x u h v \ v w h p h u u r u 5 v t x l e w r 7 7 9 r x w 9 j q g r u 9 % d w 5 / h d n 5 / h d n 6 t x l e o r r s g u l y h u d q g g l d j q r v w l f e o r f n v [ 1 9 5 ( 6 ' , $ * , 6 5 & 9 ( 5 s l q i u r p ( q h u j \ 5 h v h u y h 6 d i l q j w u d q v l v w r u 9 j q g r u 9 % d w % \ s d v v , 6 , 1 . , s x o o g r z q , p $ * 1 ' $ docid025869 rev 3 117/200 l9678, l9678-s deployment drivers 199 well as the pull-down current generator. if the vrcm block works properly, the short to battery flag would be asserted. then, the i sink current limited switch (isnk) is conne cted to srx pin, the voltage regulator current monitor block (vrcm) is enabled and connected to the selected srx pin. the i source current generator (isrc) is turned off, as well as the pull-down current generator. if the vrcm block works properly, the short to ground flag would be asserted. figure 26. srx pull-down enable logic once the vrcm block is validated, the real leakage tests can be performed. isrc and isnk currents have to be kept switched off. the vrcm shall be connected to the desired pin (either sfx or srx pins); by doing this, also the pull-down current on the selected srx pin is automatically deactivated). during the test , if no leakage is present the voltage on the selected sfx or srx pin will be forced by the vrcm to the vref level and no current is detected or sourced by the v rcm. if there is leakage to gr ound or battery, the vrcm will sink or source curren t trying to maintain vref. two cu rrent comparators, istb and istg, will detect the abnormal current flow and the relative fl ags will be given in the lpdiagstat (these flags are not latched and report the real time status of the relevant comparators in case of low-level leaka ge diagnostic test). in lpdiagstat register are also reported the channel and the pin (sfx or srx) under test, re spectively with leak_ chsel and sqp bit fields. the pull-down currents on the other srx pins are still active. therefore, the leakage test that would show a leakage to ground may be depending on a real leakage on the pin under test or on a short between loops. short between loops diagnostics in case the previous test has reported a leakage to ground fault, the short between loops diagnostics shall be run. the same procedure is followed as described for normal leakage tests except the fact that in this case a ll the pull-down current generators have to be deactivated (not only t he one for the pin under test), by means of the pd_curr bit in the diagnostic request register (lpd iagreq). if a leakage or ground fault is not present, then the channel under test has a short to another squib loop. * $ 3 * 3 6 / 3 ' , $ * 5 ( 4 3 ' b & 8 5 5 + 6 b 2 1 [ / 6 b 2 1 [ / 3 ' , $ * 5 ( 4 / 2 2 3 b ' , $ * b & + 6 ( / [ / 3 ' , $ * 5 ( 4 + , * + b / ( 9 ( / b ' , $ * b 6 ( / d q g / 3 ' , $ * 5 ( 4 / ( $ . b & + 6 ( / [ / 3 ' , $ * 5 ( 4 , 6 1 . ( 1 b 3 ' b & 8 5 5 [ / 3 ' , $ * 5 ( 4 , 6 5 & r u / 3 ' , $ * 5 ( 4 9 5 & 0 r u / 3 ' , $ * 5 ( 4 5 ( 6 b 0 ( $ 6 b & + 6 ( / [ / 3 ' , $ * 5 ( 4 ' , $ * b / ( 9 ( / deployment drivers l9678, l9678-s 118/200 docid025869 rev 3 the condition of two open channels, i.e. with out squib resistance connecting sfx to srx, that have a short between loops on sfx cannot be detected. if only one of the two shorted sfx pins is open, the fault is indicated on the open channel. squib resistance measurement during a resistance measurement, a two-step pr ocess is performed. at the first step, both isrc current generator and isnk current limit ed switch are enabled and connected to the selected sfx and srx channel, through isrc, isnk an d res_meas_chsel bit fields in the loop diagnostic request register (lpdia greq). a differential voltage is created between the sfx and srx pin based in the isrc current and squib resistance between the pins. the spi interface will provide the first resistance measurement voltage (vout1) based on the amplifying factor of the differential amplifier and a 10 bit internal adc conversion. the second measurement step (bypass measurement) is performed redirecting isrc to the selected srx pin, while keepin g isnk on; this way, the diff erential amplifier and following adc will output the offset measur ement through spi (vout2). micr ocontroller is then allowed to calculate the mathematical difference between first and second measurements to obtain the real squib resistance value. the current sources isrc and isnk used for squib resistance measurements are completely controlled by the user via spi. optionally, an automatic control by the ic for current sources switch-off after adc reading can be activated by enabling the en_auto_swit ch_off bit in the sys_cfg register. v out1 gi source r leak r sq u r leak r sq + ------------------------------- ? 1 ? r sq r leak r sq + ------------------------------- v gnd v refsql ? + u u gv offset u + = v out2 gr sq u r leak r sq + ------------------------------- v gnd v refsql ? u gv offset u + = r sq v out ' gi src u ------------------- -= (assuming r leak >> r sq ) where: g = differential amplifier gain. the simplification in the calcul ation method reported above can result in some amount of error that is already incorporated in t he overall tolerance of the squib resistance measurement reported in the el ectrical parameters table. table 8. short between loops diagnostics decoding fault condition on squib channel channel leakage diagnostics with pd_curr on (for other channels than the one under test channel leakage diagnostics with pd_curr off (for all channels) no shorts no fault no fault short to battery stb fault stb fault short to ground stg fault stg fault short between loops stg fault no fault docid025869 rev 3 119/200 l9678, l9678-s deployment drivers 199 values of each measurement step can be requ ired addressing the proper adcreqx code in the diagnostic control command (diagctrl) on table 11: diagnostics control register (diagctrlx) on page 159 . this calculation is tolerant to leakages and, than ks to a dedicated emi low-pass filter, also to high frequency noises on squib lines. moreover, l9678 features a slew rate control on the isrc current generator to mitigate emissions. high squib resistance diagnostics with this test, the device is able to under stand if the squib resistance value is below 200 ? , between 500 ? and 2000 ? or beyond 5000 ? . during a high squib resistance diagnostics, vrcm and isnk are enabled and connected re spectively to sfx and srx on the selected channel. vref voltage level outputs on sfx. current flowing on sfx is measured and compared to i srlow and i srhigh thresholds to identify if th e resistance is above or below r srlow or r srhigh levels. the results are reported in the lpdiagstat register. the relative flags (hsr_hi and hsr_lo) are not latched and reflect the current status of the comparators. high and low side fet diagnostics this couple of tests can only be run during the diagnostic mode of the power-up sequence ( figure 9 ). tests are performed individually for hs driver or ls driver, with two dedicated commands. prior to either the hs or ls fet diagnostics being run, the vrcm has to be first enabled. within the command to enable th e vrcm, also the channel onto which the fet test will be run has to be selected with the leak_chsel bit field. running the leakage diagnostics with the appropriate delay time prior to either the hs or ls fet diagnostics will precondition the squib pin to the appropriate voltage level. when the fet diagnostic command is issued with the diagnostic regi ster spi command (sysdiagreq), the vrcm flags will be cleared. the device monitors the current through the vrcm. if the fet is working properly, this current will exceed i stb (hs test) or i stg (ls test) and the driver under test is turned off immediately. if the current does not exceed i stb or i stg then the test will be terminat ed and the output is anyway turned off within t fettimeout . during t fettimeout period, the bit stating that the fet is enabled will be set (feton=1) and will be cleared as soon as the fet is switched back off. for all conditions the curren t on sfx/srx will not exceed i lim_vrcm_x , the vrcm block current limitation value. there may be higher currents on the squib lines due to the presence of filter capacitors. during these fet tests, energy available to the squib is limited to less than e fettest . for high side fet diagnostics, if no faults were indicated in the preceding leakage diagnostics then a normal result would be [s tb=1, stg=0]. if the retu rned result for the high side fet test is not as the previous then either the fet is not functional, a short to ground occurred during the test, or there is a missing ssxy connection for that channel. for low side fet diagnostics if no faults were indicated in the preceding leakage diagnostics then a normal result would be [stb =0, stg=1]. if the returned result for the low side fet test is not as the previous one then either the fet is not functional or a short to battery occurred during the test. in case of sgx loss the low-side fet diagnostic would not indicate a fetfault. deployment drivers l9678, l9678-s 120/200 docid025869 rev 3 the vrcm flags will be given in the lpdiagstat register. the status of the vrcm flags after fet test is latched and can be cleared upon either lpdiagreq or sysdiagreq spi commands. loss of ground return diagnostics this diagnostics is available during a squib me asurement or a high side driver diagnostics. this test is based on the voltage drop across the ground return, if the voltage drop exceeds v sgopen , ground connection is considered as lost. should the ground connection on the squib driver circuit be missing, the bit related to the channel under test by the two above diagnostics will be activated in the lp_gndloss register. the flag is latched after a proper filter time t sgopen and cleared upon read. high side safing fet diagnostics this test has to be issued during t he diag state of the power-up sequence ( figure 9 ). safing fet has to be switched on with the proper code in dstest bit field of the sysdiagreq. therefore, when the command is received, the de vice activates vsf regu lator to supply the external safing fet controller. the user can measure the voltage levels of both the vsf regulator and the ssxy nodes. if the safing fet is properly switched on, the voltage on ssxy is regulated. the measurement request is done via diagn ostic control command (diagctrlx), while results are reported through adcresx bit fields, as shown in table 11 . deployment timer diagnostic this test allows verifying the correct functionality and duration of the timers used to control the deployment times. this test can be executed only when the ic is in the diag state by setting the appropriate code in the dstest fi eld of the sysdiagreq register. when the test is launched, the ic sequent ially triggers the activation of the deployment timers of the various channels (each of them separated by 8ms idle time) and outputs the relevant waveform to the arm output discrete pin. see the sequence detail in figure 27 . the mcu can therefore test the deployment times by meas uring the duration of the high pulses sent by the ic on the arm pin. the deployment time configuration used during this test is the latest one programm ed in the dcrx registers. in case th e test is run on a channel with no dcrx deployment time previously configured, a default 8us high pulse is output on arm for the relevant channel. docid025869 rev 3 121/200 l9678, l9678-s deployment drivers 199 figure 27. deployment timer diagnostic sequence loop diagnostics control and results registers diagnostic tests and channels for each test are controlled through the loop diagnostic request register (lpdiagreq), diagnostic results are stored in the loop diagnostic status register (lpdiagstat). 6.5.2 high level diagnostic approach in this approach, the test steps described in the sections below are coded into a dedicated state machine that helps reducing the user intervention to a minimum. the high-level diagnostic commands are co ntained in the lpdiagreq, loop_diag_sel, and loop_diag_chsel registers. these settin gs are described in the spi table for these commands in read/write register . the high-level diagnostic response is availa ble in the lpdiagstat register. these are described in the spi table for this command in read/write register . the concept is depicted in the following figures. * $ 3 * 3 6 3 7 b : $ , 7 6 6 0 b 5 ( 6 ( 7 3 8 / 6 ( b 7 ( 6 7 [ ) u r p d q \ v w d w h ' , $ * v w d w h 6 3 , b 6 < 6 5 ( 4 ' 6 7 ( 6 7 3 8 / 6 ( 3 8 / 6 ( b 7 ( 6 7 [ 3 7 3 7 3 7 3 7 b 7 0 5 p v 3 7 b 7 0 5 3 8 / 6 ( b 7 ( 6 7 [ 3 8 / 6 ( b 7 ( 6 7 3 7 b 7 0 5 p v 3 7 b 7 0 5 3 8 / 6 ( b 7 ( 6 7 [ 3 8 / 6 ( b 7 ( 6 7 3 7 b 2 ) ) 3 7 b 7 0 5 p v 3 8 / 6 ( b 7 ( 6 7 [ 3 7 b 7 0 5 p v 3 7 b 7 0 5 3 8 / 6 ( b 7 ( 6 7 [ 3 8 / 6 ( b 7 ( 6 7 3 7 3 7 b 7 0 5 p v 3 7 b 7 0 5 3 8 / 6 ( b 7 ( 6 7 [ 3 8 / 6 ( b 7 ( 6 7 deployment drivers l9678, l9678-s 122/200 docid025869 rev 3 figure 28. high level loop diagnostic flow1 ' ! 0 ' 0 3 , o w l e v e l d i a g n o s t i c i s s e l e c t e d b i t o f , 0 $ ) ! ' 2 % 1 i s l o w / 2 a n i n v a l i d h i g h l e v e l d i a g n o s t i c i s s e l e c t e d / 2 w e a r e i n $ % 0 ? % . ! " , % $ s t a t e , e a k a g e t e s t t i m e e l a p s e d , e a k a g e t e s t t i m e e l a p s e d 3 " , f l a g i s a s s e r t e d i f 3 4 ' i s n o m o r e p r e s e n t ! . $ & % 4 t e s t i s s e l e c t e d ! . $ . / l e a k a g e i s p r e s e n t , e a k a g e t e s t t i m e e l a p s e d ! . $ , % ! + ! ' % t e s t / 2 3 " , a n d n o l e a k a g e i s p r e s e n t / 2 & % 4 t e s t a n d l e a k a g e i s p r e s e n t , a t c h 3 4 " 3 4 ' f l a g s & 0 i f & % 4 t e s t i s s e l e c t e d 6 2 # - c h e c k t i m e e l a p s e d ! . $ 6 2 # - # ( % # + t e s t i s s e l e c t e d / 2 6 2 # - f a i l s , a t c h 3 4 " 3 4 ' f l a g s & 0 i f , % ! + ! ' % o r & % 4 4 t e s t s a r e s e l e c t e d , e a k a g e t e s t t i m e e l a p s e d ! . $ 3 " , i s s e l e c t e d ! . $ l e a k a g e i s p r e s e n t 4 ) 0 % n a b l e 6 2 # - $ i s a b l e ) 3 2 # a n d ) 3 ) . + $ i s a b l e ! , , p u l l d o w n c u r r e n t s 4 ) 0 4 ) 0 % n a b l e 6 2 # - $ i s a b l e ) 3 2 # a n d ) 3 ) . + 4 ) 0 % n a b l e 6 2 # - $ i s a b l e ) 3 2 # a n d ) 3 ) . + 4 ) 0 % n a b l e 6 2 # - $ i s a b l e ) 3 2 # a n d ) 3 ) . + % n a b l e ( 3 o r , 3 & % 4 i f a l s o $ 3 4 % 3 4 o r 4 ) 0 / f f t i m e e l a p s e d ! . $ n e w d i a g n o s t i c r e q u e s t i s 6 2 # - ? # ( % # + / 2 , % ! + ! ' % / 2 3 " , / 2 & % 4 t e s t s / f f t i m e ? s . e w h i g h l e v e l d i a g n o s t i c r e q u e s t b i t o f , 0 $ ) ! ' 2 % 1 i s h i g h 7 a i t e n a u g h t i m e t o b e s u r e t h a t a l l c u r r e n t s a n d v o l t a g e s s u p p l i e s s t a r t i n / & & s t a t e & % 4 t e s t t i m e o u t ? s , e a k a g e t e s t t i m e ? s , e a k a g e t e s t t i m e ? s & % 4 4 % 3 4 $ ) ! ' ? / & & 7 ! ) 4 ? / & & , % ! + ! ' % ? 4 % 3 4 ? , % ! + ! ' % ? 4 % 3 4 ? 6 2 # - c h e c k t i m e ? s ? s 6 2 # - ? # ( % # + , e a k a g e i s d e t e c t e d d u e t o t h e f a c t t h a t & % 4 s w o r k p r o p e r l y / 2 & % 4 t e s t t i m e o u t e l a p s e d docid025869 rev 3 123/200 l9678, l9678-s deployment drivers 199 figure 29. high level loop diagnostic flow2 ' ! 0 ' 0 3 , o w l e v e l d i a g n o s t i c i s s e l e c t e d b i t o f , 0 $ ) ! ' 2 % 1 i s l o w / 2 a n i n v a l i d h i g h l e v e l d i a g n o s t i c i s s e l e c t e d / 2 w e a r e i n $ % 0 ? % . ! " , % $ s t a t e % n d o f s e t t i n g t i m e % n d o f s e t t i n g t i m e % n d o f c o n v e r s i o n 3 t o r e r e s u l t i n ! $ # 2 % 3 ! % n d o f c o n v e r s i o n 3 t o r e r e s u l t i n ! $ # 2 % 3 " / f f t i m e e l a p s e d ! . $ n e w d i a g n o s t i c r e q u e s t i s 3 1 5 ) " 2 % 3 ) 3 4 ! . # % 2 ! . ' % t e s t 2 e s i s t a n c e t e s t s e t t i n g t i m e ? s ? s 4 ) 0 2 e s i s t a n c e r a n g e t e s t t i m e e l a p s e d , a t c h ( 3 2 ? ( ) ( 3 2 ? , / f l a g s 4 ) 0 4 ) 0 % n a b l e ) 3 ) . + % n a b l e ) 3 2 # " 9 0 ! 3 3 ) 3 2 # o n 3 2 x 4 ) 0 % n a b l e 6 2 # - % n a b l e ) 3 ) . + % n a b l e ) 3 2 # o n 3 & x % n a b l e ) 3 ) . + 4 ) 0 / f f t i m e e l a p s e d ! . $ n e w d i a g n o s t i c r e q u e s t i s 3 1 5 ) " 2 % 3 ) 3 4 ! . # % m e a s u r e t e s t / f f t i m e ? s . e w h i g h l e v e l d i a g n o s t i c r e q u e s t b i t o f , 0 $ ) ! ' 2 % 1 i s h i g h 7 a i t e n o u g h t i m e t o b e s u r e t h a t a l l c u r r e n t s a n d v o l t a g e s s u p p l i e s s t a r t i n / & & s t a t e 2 e s i s t a n c e r a n g e t e s t s e t t i n g t i m e ? s ? s 3 1 5 ) " 2 % 3 2 ! . ' % 4 % 3 4 $ ) ! ' ? / & & 7 ! ) 4 ? / & & 3 1 5 ) " 2 % 3 - % ! 3 3 % 4 4 , % 2 e s i s t a n c e t e s t s e t t i n g t i m e ? s ? s 3 1 5 ) " 2 % 3 - % ! 3 3 % 4 4 , % 3 1 5 ) " 2 % 3 - % ! 3 # / . 6 3 1 5 ) " 2 % 3 - % ! 3 # / . 6 remote sensor interface l9678, l9678-s 124/200 docid025869 rev 3 7 remote sensor interface the l9678-s contains 2 remote sensor interf aces, capable of supporting psi-5 protocol (standard voltage range). a block diagram of the interface is shown below. the circuitry consists of a power interface that demodulates current flowing in the external sensor and transmits these current states to the decod er, which produces a digital value for each satellite channel. data are then output th rough the remote sens or data registers (rsdrx). the power interface also contains error detection circuitry. when a fault is detected, the error code is stored in a global spi data buffer in the remote sensor data registers (rsdrx). figure 30. remote sensor interface logic blocks the remote sensor configuration register s (rscrx) allow for configuration of the particular psi5 protocol adopted by the sensor and the transceiver current limit blanking time. the remote sensor control register (rsctrl) allow for interface chan nels to be switched on and off via spi. rsu interface has 2 registers per channel, which can report either data or fault information, that can be readout by sending 2 consecutive read commands of the remote sensor data register (rsdrx). it is a fifo, so the first spi reading contains the oldest received data and the next spi reading contains the most recent one. spi accesses both from the same address, i.e. the mcu should do 2 reads of the same rid to get both data samples. the couple of registers will retain only the last two received messages, regardless they have been qualified as valid or invalid data. in case of driver fault (short to ground, short to battery, over-current, open detection, over-tem perature) any message is lost. to re-start a correct reception of messages, it is needed to have no more fault present and fault flag read by mcu. if the device detects an error on the sensor interface, the faul t bit in rsdrx (fltbit) will be set to '1' and the following bits will be used to report the detected errors. otherwise, the register will contain only data information. detailed information on data and fault reporting are explained in the following sections. when a fault condition is detected, the rsflt bi t of the global status word (gsw) is set to 1, except in the case the register is empt y for which nodata faul t bit will be set instead. data are cleared upon reading the rsdrx register. rsu interface is supplied by vsup regulator as showed in figure 31 . to avoid a too low rsu output voltage in case of battery loss, the upper vingood and vbatmond ' ! 0 ' 0 3 ; 3 r z h u , q s x w 3 u r w h f w l r q 0 d q f k h v w h u ' h f r g h u ) d x o w ' h w h f w l r q 5 h p r w h 6 h q v r u ) d x o w 6 w d w x v 5 h j 5 6 ) 6 5 ) d x o w 6 w d w x v 5 h j ) / 7 6 5 5 h p r w h 6 h q v r u & r q i l j x u d w l r q 5 h j 5 6 & 5 5 h p r w h 6 h q v r u ' d w d 5 h j ; 5 6 ' 5 [ 5 6 8 [ docid025869 rev 3 125/200 l9678, l9678-s remote sensor interface 199 thresholds must be selected. in this way the device will detect the battery lo ss condition in time to guarantee the minimum rsu output voltage required. figure 31. remote sensor interface block diagram 7.1 psi-5 protocol all channels are compliant to the psi-5 v1.3 specification as described below: ? two-wire current interface ? manchester coded digital data transmission ? high data transmission speeds of 125 kbps and 189 kbps ? variable data word length (8 & 10 bit only) ? 1-bit parity ? asynchronous operation mode * $ 3 * 3 6 , 6 $ 7 , 6 $ 7 q ) q ) 7 ( 0 , i l o w h u p 9 6 k r u w w r 9 % $ 7 f r p s 9 6 8 3 3 6 , f x u u h q w f r p s d u d w r u 5 6 8 [ 6 k r u w w r * 1 ' f r p s 5 6 8 b 6 7 % 5 6 8 b 2 & 6 $ 7 ' l j l w d o z r u g 6 d w h o o l w h % d v h f x u u h q w 8 s ' r z q f r x q w h u i v d p s o h , w k u h v k r o g e l w v , e d v h 5 ; 6 $ 7 6 < 1 & r u & 2 0 3 % $ 6 ( 2 8 7 5 6 8 b ( q d e o h 9 5 ( ) remote sensor interface l9678, l9678-s 126/200 docid025869 rev 3 an example of the data format for one possible psi-5 protocol configuration is shown below. data size may vary, but the presence of 2 sync start bits (referenced be low as sync bits) and t gap time is consistent regardless. figure 32. psi-5 remote sensor protocol (10-bit, 1-bit parity) 7.1.1 functional descripti on - remote sensor modes the remote sensor interface block provides a hardware connection between the microcontroller and up to two remote sensors. each channel is independent of the other, and is not influenced by fault conditions, such as short circuits to ground or vehicle battery, on the other channel. each channel supplies an independently current limited dc voltage to its remote sensor derived from vsup, and mo nitors the current draw to extract encoded data. the remote sensors modulate the current draw to transmit manchester-encoded data back to the receiver. the current level detecti on threshold for all channels is automatically set by the integrated current adjust feature in or der to adapt to the quiescent current draw of the sensors. all channels can be enabled or disabled in dependently via spi commands. the operational status of all channels can also be read via spi command. the message bits are encoded using a manc hester format, in which logic values are determined by a current transition in the mi ddle of the bit time. the interface supports manchester 2 encoding as shown in figure 33 . figure 33. manchester bit encoding the received message data are stored in inpu t data registers that are read out by the microcontroller via the spi interface. all bits of these registers are simultaneously updated upon reception of the remote sensor message to prevent partial frame data from being sampled via the spi interface. after the data for a given channel is read via the spi ' ! 0 ' 0 3 $ a t a 4 r a n s m i s s i o n - a n c h e s t e r # o d e 4 r a n s m i s s i o n o f x % x % b f r a m e d u r a t i o n 4 " ) 4 4 ' ! 0 3 3 $ $ $ $ $ $ $ $ $ $ 0 ' ! 0 ' 0 3 , o g i c g g , o g i c g g - a n c h e s t e r 0 3 ) % l w w l p h ? ? ? ? ? & x u u h q w 3 t a r t b i t s docid025869 rev 3 127/200 l9678, l9678-s remote sensor interface 199 interface, subsequent re quests for data from this channel will result in an error response (nodata fault). the remote sensor interface is also able to detect faults occurring on the sensor interface. the remote sens or data register (rsdrx) will report multiple fault flags. when the number of bits decoded is incorrect (either too many or too few), a bit error is indicated. when any bit error is detected (bit time, too many bits or too few bits), the message is discarded. error bit invalid is an or-ed combination of the following errors: ? data length error or stop bit error ? parity error of received remote sensor message ? bit time error (a data bit edge is not received inside the expected time window) should one or more of the channel faults (stg, stb, current_hi, opendet and rstemp) be set, the invalid and nodata bits are cleared. 7.1.2 rsu data fields and crc the remote sensor interface reports both data information and fault information in the remote sensor data register (rsdrx). in dependent data registers are defined for each remote sensor interface and the data containe d therein is formatted differently based on whether a fault is detected. see spi command in remote sensor data/fault registers w/o fault (rsdrx) on page 91 . the data available in the rsdrx register is separated into several bit fields. the logical channel id is a 4-bit field to identify the sa tellite sensor. the data bi ts are appended to the lcid at the output of the ma nchester decoder. the 3-bit crc bi t field is computed on the entire data packet of fields, bits[16:0], which also includes the chxon and fltbit. to satisfy safety requirements, the lcid, data and crc bit fields propagate through the same data path as a single item to the spi output. the polynomial calculation implemented for psi 5 data is described as in psi5 specification g(x)=1+x+x^3 with the initializ ation value equal to "111". below are the equations to calcul ate the crc in combinatorial way: crc[2] = crcext[0]+d[0]+d[1]+d[3]+d[6]+d[7]+d[8]+d[10]+d[13]+d[14]+d[15] crc[1] = crcext[2]+d[0]+d[1]+d[2]+d[4]+d[7]+d[8]+d[9]+d[11]+d[14]+d[15]+d[16] crc[0] = crcext[1]+crcext[0]+d[0]+d[2]+d[ 5]+d[6]+d[7]+d[9]+d[12]+d[13]+d[14]+d[16] where d[16:0]= rsdr[16:0] and crcext[n] are the starting seed values (all '1'). 7.1.3 detailed description manchester decoding the manchester decoder will support remote sensor communication as per psi specification rev 1.3 for the modes configurabl e via the sts bits in the rscrx registers.. the manchester decoder checks the duty-cycle and period of the start bits to determine their validity, depending on the configurat ion of the period_meas_disable bit in the rscrx registers. the expected time windows fo r the mid bit transitions of each subsequent bit within the received frame is determined by means of the in ternal oscillator time base. glitches shorter than 25% of the minimum bit time duration are rejected. remote sensor interface l9678, l9678-s 128/200 docid025869 rev 3 figure 34. manchester decoder state diagram , ' / ( 5 , 6 , 1 * b ( ' * ( ? 6 w u r e h 5 ( 6 ( 7 b & 1 7 3 ( 5 , 2 ' b b 6 w u r e h 5 ( & b ( 1 ' 6 w u r e h 5 ( 6 ( 7 b & 1 7 f k h f n 3 $ 5 , 7 < b ( 5 5 $ 1 < d q g 3 ( 5 , 2 ' b b r u q r w ) , 5 6 7 3 ( 5 , 2 ' b b 6 w u r e h 5 ( 6 ( 7 b & 1 7 6 w u r e h 0 $ 1 < % , 7 6 6 w u r e h 5 ( 6 ( 7 b & 1 7 $ 1 < d q g 3 ( 5 , 2 ' b b 6 w u r e h 5 ( 6 ( 7 b & 1 7 5 , 6 , 1 * d q g 3 ( 5 , 2 ' b b 6 w u r e h 5 ( 6 ( 7 b & 1 7 $ 1 < d q g q r w 3 ( 5 , 2 ' b b d q g 3 ( q g r i p h v v d j h g h i l q l w l r q i r u x v h l q w l p h v o r w f r q w u r o ( 2 0 7 7 7 7 d 7 e ( 5 , 2 ' b b d q g q r w 6 7 $ 7 ( & b 1 % 6 w u r e h 5 ( 6 ( 7 b & 1 7 6 w u r e h 1 ( ; 7 % , 7 3 ( 5 , 2 ' b b d q g $ 1 < v w u r e h & + ( & . b 7 , 0 ( 6 w u r e h 5 ( 6 ( 7 b & 1 7 $ 1 < d q g q r w 3 ( 5 , 2 ' b b d q g q r w ) , 5 6 7 b ( ' * ( 6 w u r e h 5 ( 6 ( 7 b & 1 7 6 w u r e h & + ( & . b 7 , 0 ( $ 1 < d q g 3 ( 5 , 2 ' b b d q g 6 7 $ 7 ( & b 1 % 6 w u r e h 5 ( 6 ( 7 b & 1 7 6 w u r e h 1 ( ; 7 % , 7 $ & ' ( % $ % & % ( ' ' d w d ) l o w ) l o w h u h g 5 d z ' d w d 5 ; 6 $ 7 i u r p & x u u h q w ' h p r g x o d w r u d i w h u g h j o l w f k h u 5 , 6 , 1 * b ( ' * ( ' d w d ) l o w q q 3 ) $ / / , 1 * b ( ' * ( ' d w d ) l o w q q 3 $ 1 < 5 , 6 , 1 * b ( ' * ( r u ) $ / / , 1 * b ( ' * ( & b 1 % e l w i u d p h f r q i l j x u d w h g " 6 7 $ 7 ( ^ # , ' / ( # 6 7 $ 7 % , 7 ' ( 7 # 7 6 7 $ 7 ( # 7 [ ( # : $ , 7 [ ) # ( 5 5 2 5 ` % l w & r x q w h u 5 ( 6 ( 7 b & 1 7 " % l w & r x q w h u 3 h u l r g b b % l w & r x q w h u ! % l w 3 h u l r g 3 h u l r g b b % l w & r x q w h u ! % l w 3 h u l r g 3 h u l r g b b % l w & r x q w h u ! % l w 3 h u l r g ) , 5 6 7 b ( ' * ( 3 h u l r g b b " $ 1 < " ) , 5 6 7 b ( ' * ( d i w h u d g h o d \ r i 7 f n 5 h p d u n q r w d f r p e l q d w r u l d o v l j q d o 5 ( 6 ( 7 b ' ( & 2 ' ( 5 ? 6 w u r e h 5 ( 6 ( 7 b & 1 7 3 h u l r g b b d q g $ 1 < b ( ' * ( ? 6 w u r e h 5 ( 6 ( 7 b & 1 7 i l u v w s x o v h g x w \ f \ f o h f k h f n ) $ / / , 1 * b ( ' * ( e h i r u h s h u l r g b b ? 6 w u r e h 5 ( 6 ( 7 b & 1 7 5 , 6 , 1 * b ( ' * ( 3 h u l r g b b ? 6 w u r e h 5 ( 6 ( 7 b & 1 7 : $ , 7 7 * $ 3 ' $ 7 $ 5 ( & ( 5 5 2 5 6 7 $ 5 7 % , 7 ' ( 7 7 d 7 7 7 7 7 7 7 7 e 7 7 7 7 3 ( 5 , 2 ' b b d q g q r w $ 1 < v w u r e h & + ( & . b 7 , 0 ( $ 7 d 7 e % 3 h u l r g b b d q g q r w $ 1 < b ( ' * ( * $ 3 * 3 6 docid025869 rev 3 129/200 l9678, l9678-s remote sensor interface 199 a manchester decoder error occurs if one or more of the following conditions are true: ? two valid start bits are detected, and at leas t one of the expected 13 mid-bit transitions are not detected ? two valid start bits are detected, and more than 13 mid-bit transitions are detected ? when the number of bits decoded is incorrect (either too many or too few), a bit error is indicated. when any bit error is detected (b it time, too many bits, too few bits), the decoder will revert to the minimum bit time of the selected range and the message is discarded. all errors are readable through the sensor fault status register and the rsflt bit in the global status word register. when a valid message is correctly decoded, the 10/8 data bits are stored into the appropriate rsdrx register together with th e related lcid. the rsdrx register contains the 10/8 bits data as they are received from the sensor (no data range check/mask is done at this stage). the 8-bit data word is right-just ified inside the 10-bit data field in the rsdrx registers. current sensor with auto-adjust trip current the current sensor is responsible for translating the current drawn by the sensor into a digital state (refer to figure 35 ). each satellite channel has a dedicated current sensor with hysteresis. figure 35. remote sensor current sensing auto adjust the auto adjust feature uses a 7 bit d/a to converter to step up and down the threshold level for detecting the base current through the remote sensor before start bits are transmitted. once start bits are received, the counter stops and the d/a value remains fixed until the remote sensor message is received. this procedure is repeated for each cycle of the remote sensor. the auto adjust circuit uses the following equation: i base = i offset + (d/a counts) * 300 a where i offset is fixed to 2.5 ma ' ! 0 ' 0 3 ) s a t ) b a s e ) t r i p c o u n t 2 x 3 a t ? s e g m ! m ! m ! ? s remote sensor interface l9678, l9678-s 130/200 docid025869 rev 3 the converter default count value is 42, therefore, i base = 2.5 ma + 42 * 300 a i base = 15 ma i trip = i base + threshold where threshold is a fixed at 12 ma thanks to this implementation, i base can span from 2.5 ma up to 41 ma covering psi-5 specification range. as an example, for a re mote sensor that operates at 10 ma base current, i trip = 23 ma. 7.2 remote sensor inte rface fault protection 7.2.1 short to ground, current limit each output is short circuit protected by an independent current limit circuit. should the output current level reach or exceed the ilimth for a time period gr eater than tilimth the output stage is disabled and an internal up-down counter will coun t in 25 s increment up to tilimth. the filter time is chosen in order to avoid false current limit detection for in-rush current that may happen at interface switch-on. when the output is turned off due to current limit, the appropriate fault code stg is set in the remote sensor data register (rsdr). the fault timer latch is cleared when the sens or channel is first disabled and then re- enabled through the remote sensor configurat ion register (rscr). this fault condition does not interfere with the normal operation of the ic, nor with the operation of the other channels. when a sensor fault is detected, the rsflt bit of the gsw is set indicating a fault occurred and can be decoded by addressing the rsfsr register. in order to fulfil the blanking time require ment at channel activation as per psi-5 specification, a dedicated masking time is app lied to the current limitation fault detection each time a channel is activated. 7.2.2 short to battery all outputs are independently protected against a short to battery condition. short to battery protection disconnects the channel from its supply rail to guarantee that no adverse condition occurs within the ic. th e short-to-battery detection circuit has input offset voltage (10 mv, minimum) to prevent disconnecting of th e output under an open circuit condition. a short to battery is detected when the output rsux pin voltage increases above vsup supply pin voltage for a t stbth time. an internal up-c ounter will count in 1.5 s increment up to t stbth . the counter will be cleared if the short condition is not present for at least 1.5 s. short to battery protection blocks the ba ttery condition to guarantee that no adverse condition occurs within the ic. the channel in short to battery is not shut down by this condition. other channels are not affected in case of short of one output pin. as in the case previously described, the stb fault code can be read from rsdr bits and any fault will set the rsflt bit of the global status word regi ster (gsw). the stb bit is cleared upon read. 7.2.3 cross link the device provides also the capability of a cross link check between outputs, in order to reveal conditions where two output channels ar e in short. this functionality is allowed by enabling one output channel, while asking for voltage measurement on any of the other ones. docid025869 rev 3 131/200 l9678, l9678-s remote sensor interface 199 7.2.4 leakage to battery, open condition the remote sensor interface offers detectio n of an open sensor condition. the auto- adjusting counter for remo te sensor current sensing will drop to 0 in case the current flowing through rsux pin is lower than 3 ma. the ope ndet fault flag is asserted when the fault condition lasts for longer than t rsuop_filt deglitch filter time. this fault flag can be read from rsdr bits and any fault will set the rsflt bit of the global status word register (gsw). the channel in this condition is not shutdown. 7.2.5 leakage to ground the sensor interface offers as well the detect ion of a leakage to ground condition, that will possibly raise the sensor current higher than 36 ma. the current_hi fault flag is asserted when the fault condition lasts for longer than t rsuch_filt deglitch filter time. this fault flag can be read from rsdr bits and any fault will set the rsflt bit of the global status word register (gsw). the channel in this condition is not shutdown. 7.2.6 thermal shutdown each output is protected by an independent over-temperature detection circuit should the remote sensor interface thermal protection be triggered the output stage is disabled and a corresponding thermal fault is latched and reported through the rstemp flag in the remote sensor data register (rsdrx). the thermal faul t flag is cleared when the sensor channel is first disabled and then re-enabled through the remote sensor configuration register (rscrx). watchdog timer l9678, l9678-s 132/200 docid025869 rev 3 8 watchdog timer this device offers a watchdog implementati on by means of a temporal wd. window times are spi programmable and a couple of specific c odes has to be written within this window in order to serve the wd control. 8.1 temporal watchdog the temporal watchdog ensures the system software is operating correctly by requiring periodic service from the microcontroller at a programmable rate. this service (watchdog refresh) must occur within a time window, and if serviced too early or too late will enter an error state (wd1_error) reported via th e wd1_wdr bit of the fltsr register. the overall wd1 functionality is described in the state diagram reported in figure 36 . figure 36. watchdog state diagram ' ! 0 ' 0 3 : ' , 1 , 7 , $ / : ' 5 8 1 : ' 7 ( 6 7 6 3 , : ' b 7 ( 6 7 : ' u h i u h v k 2 . : ' b : ' 5 : ' b ( 5 5 b 7 + b : ( , i : ' b ( 5 5 b & 1 7 : ' b ( 5 5 b 7 + : ' b / 2 & . 2 8 7 : ' u h i u h v k 2 . : ' 5 ( 6 ( 7 : ' b ( 5 5 2 5 : ' b ( 5 5 2 5 : ' b / 2 & . 2 8 7 : ' b ( 5 5 b & 1 7 : ' 2 9 ( 5 5 , ' ( : ' 7 7 0 ! 9 : ' b 2 9 ( 5 5 , ' ( $ 1 ' 6 3 , : ' b 7 ( 6 7 : ' b / 2 & . 2 8 7 : 6 0 b 5 h v h w ) u r p d q \ v w d w h : ' b / 2 & . 2 8 7 : ' b : ' 5 : ' b ( 5 5 b & 1 7 : ' b ( 5 5 b 7 + b : ( p v : ' b : ' 5 p v $ 1 ' : ' b 7 2 9 5 : ' b / 2 & . 2 8 7 : ' b ( 5 5 b & 1 7 docid025869 rev 3 133/200 l9678, l9678-s watchdog timer 199 following the description of the above states: a single spi command (wd_test) is used to ac tivate test states for the watchdog circuitry. table 9. watchdog timer status description state/signal description wd1 initial default state entered from startup. while in this state, no watchdog service is required, and the ic may stay in this state indefinitely. for system safety, all arming signals are disabled during this state to prevent deployment. wd1 run normal run-time state where wd1 service is required. wd1 test a special state used to test the watchdog function. normally, this state will only be checked once per power cycle by t he software, but t here is no inherent restriction in the watchdog logic preventi ng periodic testing. this state allows testing of the watchdog refresh fu nction without setting wd1_lockout=1, which can only be cleared via wsm reset. deployment is inhibited when the wd state machine is in this state. wd1 reset state entered when a wd1_error occurs. th is is a timed-duration state that is automatically exited after 1ms. wd1 override a special state used to disable watchdog functionality for development purposes. other logic within the ic can use this state to emulate the wd1 run state without the need to service wd1. wsm_reset signal used to reset the wd1 state machine to the wd1 initial state and all signals to their inactive values wd1_refresh ok signal that is asserted only if the watchdog is refreshed ('a' - 'b' or 'b' - 'a' seq.) within the wd1 time window wd1_error signal that is asserted if the watchdog refresh fails to occur during the wd1 time window. wd1_wdr watchdog reset ? latched signal that is activated whenever a watchdog error is qualified. for wd1, this occurs when wd1 service is required, but not received. this signal is spi-readable. wd1_tm test mode ? a signal that indicates that wd1 is being tested. this signal is spi-readable. wd1_lockout a latched signal activated if an unexpected wd1 error occurs. this signal is permanently latched when set (until wsm_reset). when set, all arming signals are disabled, preventing deployment. this signal is spi-readable. spi_wd1_test spi command used to enter wd1 test state from wd1 run state, or to enter wd1 override state from initial stat e if wdt/tm pin voltage is greater than the threshold. this command has no effect in other states. wd1_err_cnt retry counter to let the microcontroll er fails multiple times before set lockout and prevent deployment. wd1_err_th spi configurable threshold for the retry counter. wd1_err_th_we signal to lock the writing of wd1_err_th when watchdog entered run state. watchdog timer l9678, l9678-s 134/200 docid025869 rev 3 8.1.1 watchdog timer configuration the watchdog timer can be configured on two different frequency modes: ? fast watchdog with maximum range of 2 ms and a resolution of 8 s; ? slow watchdog with maximum range of 16.3 ms and a resolution of 64 s. the watchdog window times are spi programmable. the configuration of watchdog timer frequency and window times can be done by setting the watchdog timer configuration register (wdtcr) with the appropriate values. ho wever, this configuration is accepted only when the device is in the init operating state, as shown in figure 9 . as soon as the diag state is entered, the watchdog control is enabled and the wa tchdog configuration is fixed and cannot be changed anymore. 8.1.2 watchdog timer operation while in the wd1_initial state, watchdog service must begin or a spi command with wd1_tovr=1 must be received within the first 50 0 ms. if the wd1 timer override bit is set, the device can stay in the wd1_initial st ate indefinitely without watchdog service. to refresh wd1, the logic must receive a watchdog timer register (wd1t) spi command containing the expected key value within the wd1 time window (wdtmin+wdtdelta). if it is received too early or too late the wd1_error signal will be asserted. the wd1_error will not be asserted in case a spi command containing the watchdog timer register (wd1t) with an incorr ect key value is received at any time relative to the window (wdtmin+wdtdelta). this allows the system software to repeatedly transmit the key value until it needs to cha nge to the correct key value. upon reception of the correct key value within the window, the logic will reset the watchdog timer to create a new window. the timer is cleared upon writing code 'a' and code 'b' (either in 'a' - 'b' or 'b' - 'a' sequences) to the wd1c tl[1:0] bits, in the wd1t register. the watchdog timer value can be read via the wd1t register. docid025869 rev 3 135/200 l9678, l9678-s watchdog timer 199 figure 37. watchdog timer refresh diagram 8.2 watchdog reset assertion timer upon a watchdog reset, the wa tchdog logic will momentarily as sert the reset pin for time duration t wdrst . when the reset pin has been as serted through the watchdog reset assertion timer, stored faults are maintained and can be read by the microcontroller via spi following the reset period. 8.3 watchdog timer di sable input (wdt/tm) this input pin has a passive pull-down and is us ed to disable the watchdog timer. the state of this pin can be read by spi through the wdtdis_s bit in the gsw register. when wdt/tm pin is asserted, the watchdog timer is disabled, the timer is reset to its starting value and no faults are generated. ' ! 0 ' 0 3 : ' , 1 , 7 : ' $ : ' % : ' % : ' $ : ' b ( 5 5 2 5 6 3 , b : ' b % 6 3 , b : ' b $ 6 6 0 b 5 ( 6 ( 7 7 0 5 ! 0 , 1 6 3 , b : ' b $ 7 0 5 6 w u r e h : ' u h i u h v k 2 . 7 0 5 ! 0 , 1 6 3 , b : ' b % 7 0 5 6 w u r e h : ' u h i u h v k 2 . 7 0 5 ! 0 $ ; 2 5 > 7 0 5 0 , 1 6 3 , b : ' b % @ 7 0 5 ! 0 $ ; 2 5 > 7 0 5 0 , 1 6 3 , b : ' b $ @ dc sensor interface l9678, l9678-s 136/200 docid025869 rev 3 9 dc sensor interface l9678 implements a circuitry able to interface with a variety of positioning sensors. the sensors that can be connected to the device ar e hall-effect, resistive or simple switches. range of measurements is: ? resistive sensor: 65 ? to 3 k ? ? hall-effect sensor: 2 ma to 20 ma. within the above ranges, accuracy of 15% is granted. a reduced accuracy is given in the range 1 ma to 2 ma. hall sensor and switch interface block diagram is shown below. figure 38. switch sensor interface block diagram the global spi contains several bits to contro l and configure the interface. the swoen bit is used to enable the output voltage on dcsx pins. the channel to be activated can be chosen by accordingly setting chid bits. the interface activation is completely controlled by user spi command. the interface could be op tionally configured for "automatic switch- off" immediately after the current or resistance measurement completion by setting the en_auto_switch_off bit in the sys_cfg register. ' ! 0 ' 0 3 , o l p 9 % * ' & 6 [ , ' & 6 , ' & 6 9 u h i y e l w v ' l j l w d o z r u g ' & [ y r o w d j h s l q r u , 6 $ 7 2 s h q o r d g l i , r x w ' & [ o r z h u w k d q p $ q ) q ) , u h i 9 * 1 ' f 9 9 5 ( 6 ' , $ * 9 u h i 9 l q 5 5 $ [ 5 5 / 9 d q d o r j p x [ % o r f n v v k d u h g p x o w l s o h [ h g d p r q j w k h w k h g l i i h u h q w f k d q q h o v 5 5 9 , 1 7 9 docid025869 rev 3 137/200 l9678, l9678-s dc sensor interface 199 the voltage and current for the selected channel are made available to the main adc by selecting the proper channel and enabling the measurement process by dedicated diagctrlx commands. the device offers the capability to actively keep all the dcsx lines discharged by means of a weak pull down. the pull down is active by default on all channels and it comes to be deactivated in either of the following cases: 1. when the voltage source is active on the relevant channel 2. when a voltage measurement is r equested on the relevant channel 3. if spi bit swctrl(dcs_pd_curr) is set ( global pull-down disable for all channels) in case of hall-effect sen sors, a single current measurement is processed. the current load needed for regulating the pin is internally refl ected to a reference resistance, whose voltage drop is then measured through the internal adc converter. when resistive or switch sensors are used, a m ore complex measurement is performed. in a first step the current information as above described is provided. then, also the information on the voltage level achieved on the output pin is provided via adc. by processing these two values, the micro-contro ller can understand the resistive value. the dcsx voltage is internally re scaled by a voltage divider into the adc converter voltage range as shown in figure 38 . additionally a positive voltage offset is internally applied to the scaled voltage in order to allow voltage m easurement c apability fo r dcsx down to -1v. in order to have accurate resistive information even in case of an external ground voltage shif t on the sensor of up to 1v, the voltage measurement step actually needs two dcsx voltage measurements. a first voltage measurement has to be done with selection of 6.25 v o n the output channel and a second one with the regulator switched off. the difference between the two measurements will cancel out the offsets (both external ground shift and internal offset). the dcsx current and voltage can be retrieved from adc readings according to the follow ing formulas and relate d parameters specified in section 15.19: dc sensor interface and section 15.23: voltage diagnostics (analog mux) : i dcsx 1 r ref1_idcsx ------------------------------------ adc ref_hi 2 adc res ------------------------------- diagctrln adcresn ? ? = @diagctrl(adcreqn = $04 v dcsx ratio vdcsx adc ref_hi 2 adc res ------------------------------- diagctrln adcresn v off_dcsx ? ? ? 1 ? ? = @diagctrl(adcreqn = $03 the dcsx sensor resistance can be calcul at ed according to the following formula: r sensor x v dcsx ' i dcsx --------------------- - v dcsx @(swctrl(swoen)=1 v dcsx @(swctrl(swoen)=0 ? i dcsx --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- - == @swctrl(chid) = x dc sensor interface l9678, l9678-s 138/200 docid025869 rev 3 the device provides also the capability of a cross link check between outputs, in order to reveal conditions where two output channels ar e in short. this functionality is allowed by enabling one output channel, while asking for voltage measurement on any of the other ones. all parametric requirements for this block can be found in specification tables. each output is protected against ? overload conditions by current limit ? ground offset between the ecu and the loads of up to 1 v. ? loss of ecu battery ? loss of ground ? shorts to ground docid025869 rev 3 139/200 l9678, l9678-s safing logic 199 10 safing logic 10.1 safing logic overview the integrated safing logic uses data from on-board and remote locations by decoding the various spi communications between the interfaces and the main microcontroller. the safing logic has several pr ogrammable features enabling its ability to decode spi transmissions and can process data from up to 4 sensors. the operating mode involves simple symmetrical data threshold compar isons, with the use of symmetrical or asymmetrical counters. a high level diagram is shown in the figure below. please note that this top-level diagram is simplified, and references to more detailed flowcharts to show a) message decoding, b) valid data limits, c) effects of the 'combine' function, d) comparison to thresholds and arming, and e) the setting of the 'compare complete bit. two independent arming outputs, arm1int and arm2int, are also mapped internally to any of the integrated squib drivers. figure 39. top level safing engine flow chart ' ! 0 ' 0 3 6 7 $ 5 7 6 3 , b 0 6 * 5 h f h l y h g " & 6 b * 6 3 , b 6 $ ) b & & 5 h d g " 0 6 * ' ( & $ % 1 < 1 & k h f n v z k h w k h u u h t x h v w d q g u h v s r q v h d u h j r r g i r u h d f k e l w v d i l q j u h f r u g w d n l q j l q w r d f f r x q w , ) e l w ' h w h u p l q h v ' $ 7 $ w d n l q j l q w r d f f r x q w 6 3 , ) / ' 6 ( / e l w < & & b 5 ( $ ' * + & 2 0 3 $ 5 ( ( ) & r p s d u h ' $ 7 $ w r w k u h v k r o g v x s g d w h h y h q w f r x q w h u v 8 s g d w h v h y h q w f r x q w h u v l i q r g d w d u h f h l y h g f o h d u v & & e l w v ' & 8 , & 6 d i l q j / r j l f 7 r s / h y h o 9 $ / ' $ 7 & ' & k h f n v z k h w k h u g d w d l v z l w k l q u d q j h l i f r q i l j x u h g & 2 0 % , 1 ( ' ( & r q y h u w v g d w d w r e h f r p s d u h g l q w r f r p e l q h g g d w d v x p d q g g l i i h u h q f h l i f r q i l j x u h g $ 5 0 , 1 * v h w $ 5 0 , 1 7 d q g $ 5 0 , 1 7 p d q d j h g z h o o w l p h u v 0 6 * ' ( & & k h f n v z k h w k h u u h t x h v w d q g u h v s r q v h d u h j r r g i r u h d f k e l w v d i l q j u h f r u g w d n l q j l q w r d f f r x q w , ) e l w % & safing logic l9678, l9678-s 140/200 docid025869 rev 3 10.2 spi sensor data decoding sensor data is regularly communicated with the main microcontroller through multiple spi messages. since not all communications between sensors and the microcontroller contain data, it is important for the decoder to properly sort the communications and extract only the targeted data. the solution involves defining specific masking functions, contained within independent safing records, programmed by the user. the following figures detail the spi message decoding methodology and the ensui ng comparisons of valid sensor data to the programmed thresholds. figure 40. safing engine - 16-bit message decoding flow chart ' ! 0 ' 0 3 l & & > l @ " & 6 > l @ f v b d f w l y h " , ) > l @ " 1 < < 1 < p d w f k > l @ p d w f k & & > l @ p d w f k > l @ l < 1 1 l 1 " < 1 2 x w s x w v w r 9 $ / ' $ 7 i x q f w l r q g d w d u h v x o w > l @ u h t b r n > l @ p d w f k > l @ $ % ( 1 b 6 $ ) l " < 1 0 6 * ' ( & 6 3 , ) / ' 6 ( / > l @ " 5 ( 6 3 7 $ 5 * > l @ v w > 0 , 6 2 @ 5 ( 6 3 0 $ 6 . > l @ 5 ( 6 3 7 $ 5 * > l @ q g > 0 , 6 2 @ 5 ( 6 3 0 $ 6 . > l @ v w u h t b r n > l @ " 1 < q g g d w d u h v x o w > l @ v w > 0 , 6 2 @ ' $ 7 $ 0 $ 6 . > l @ g d w d u h v x o w > l @ q g > 0 , 6 2 @ ' $ 7 $ 0 $ 6 . > l @ 1 < 5 ( 4 7 $ 5 * > l @ 0 6 > 0 2 6 , @ 5 ( 4 0 $ 6 . > l @ " < 1 p d w f k > l @ p d w f k > l @ < 1 6 3 , ) / ' 6 ( / > l @ " 5 ( 6 3 7 $ 5 * > l @ v w > 0 , 6 2 @ 5 ( 6 3 0 $ 6 . > l @ 5 ( 6 3 7 $ 5 * > l @ q g > 0 , 6 2 @ 5 ( 6 3 0 $ 6 . > l @ v w q g g d w d u h v x o w > l @ v w > 0 , 6 2 @ ' $ 7 $ 0 $ 6 . > l @ g d w d u h v x o w > l @ q g > 0 , 6 2 @ ' $ 7 $ 0 $ 6 . > l @ 1 < p d w f k > l @ u h t b r n > l @ p d w f k > l @ u h t b r n > l @ u h t b r n > l @ u h t b r n > l @ 5 ( 4 7 $ 5 * > l @ 0 6 > 0 2 6 , @ 5 ( 4 0 $ 6 . > l @ " < 1 p d w f k > l @ p d w f k & & > l @ u h t b r n > l @ l 6 d i l q j 5 h f r u g l q g h [ 6 5 6 5 6 5 6 5 1 / 1 / 1 / docid025869 rev 3 141/200 l9678, l9678-s safing logic 199 figure 41. safing engine - 32-bit message decoding flow chart & & > l @ " & 6 > l @ f v b d f w l y h " , ) > l @ " 1 < < 1 < p d w f k > l @ p d w f k > l @ l < 1 1 2 x w s x w v w r 9 $ / ' $ 7 i x q f w l r q g d w d u h v x o w > l @ p d w f k > l @ % & ( 1 b 6 $ ) l " < 1 0 6 * ' ( & 5 ( 6 3 7 $ 5 * > l @ 0 , 6 2 5 ( 6 3 0 $ 6 . > l @ u h t b r n > l @ " 1 < g d w d u h v x o w > l @ 0 , 6 2 ' $ 7 $ 0 $ 6 . > l @ 5 ( 4 7 $ 5 * > l @ 0 2 6 , 5 ( 4 0 $ 6 . > l @ " < 1 u h t b r n > l @ u h t b r n > l @ 5 ( 4 7 $ 5 * > l @ 0 2 6 , 5 ( 4 0 $ 6 . > l @ " < 1 l 6 d i l q j 5 h f r u g l q g h [ 6 5 6 5 6 5 6 5 1 / 1 / / l 1 " p d w f k > l @ < 1 5 ( 6 3 7 $ 5 * > l @ 0 , 6 2 5 ( 6 3 0 $ 6 . > l @ g d w d u h v x o w > l @ 0 , 6 2 ' $ 7 $ 0 $ 6 . > l @ 0 d w f k > l @ p d w f k > l @ u h t b r n > l @ 1 < l " l < / v n l s v e l w u h f r u g v 1 * $ 3 * 3 6 safing logic l9678, l9678-s 142/200 docid025869 rev 3 figure 42. safing engine - validate data flow chart l & l 6 d i l q j 5 h f r u g l q g h [ 6 5 6 5 6 5 6 5 2 x w s x w v w r & 2 0 % , 1 ( i x q f w l r q & & > l @ y d o g d w > l @ y d o & & > l @ 9 $ / ' $ 7 / , 0 ( 1 > l @ " / , 0 6 ( / > l @ " $ e v g d w d u h v x o w > l @ g " $ e v g d w d u h v x o w > l @ g " < < 1 1 1 y d o g d w > l @ y d o & & > l @ y d o g d w > l @ y d o & & > l @ y d o g d w > l @ y d o & & > l @ y d o g d w > l @ y d o & & > l @ y d o g d w > l @ y d o & & > l @ l / " ' < 1 < 1 1 / 1 / 1 / 1 < 0 d w f k > l @ & 2 0 % > l @ & & > l @ " < l = & 2 0 % > l @ 1 < 0 r g l & k h f n v i r u f r p e l q d e o h u h f r u g v = / = / = / & k h f n v i r u r g g l q g l f h v < 1 < 1 0 d w f k > l @ 0 d w f k & & > l @ 0 d w f k > l @ 0 d w f k & & > l @ & & > l @ 1 1 < < l 1 " < 1 l l l * $ 3 * 3 6 docid025869 rev 3 143/200 l9678, l9678-s safing logic 199 figure 43. safing engine - combine function flow chart ' ! 0 ' 0 3 l < < 1 l l w h p s g d w d u h v x o w > l @ g d w d u h v x o w > l @ w h p s g d w d u h v x o w > l @ 1 ' ( 2 x w s x w v w r & 2 0 3 $ 5 ( i x q f w l r q g d w d u h v x o w > l @ & & > l @ f r p s > l @ 9 d o & & > l @ y d o & & > l @ " < 1 & 2 0 % , 1 ( & 2 0 % > l @ " < w h p s g d w d u h v x o w > l @ g d w d u h v x o w > l @ w h p s g d w d u h v x o w > l @ 1 & 2 0 % > l @ " l 1 " l 6 d i l q j 5 h f r u g l q g h [ 6 5 6 5 6 5 6 5 1 / 1 / 1 / safing logic l9678, l9678-s 144/200 docid025869 rev 3 figure 44. safing engine threshold comparison ' ! 0 ' 0 3 1 0 d w f k > l @ y d o g d w > l @ ( l ) g d w d u h v x o w > l @ ? 6 $ ) b 7 + 5 ( 6 + > l @ 3 2 6 b & 2 8 1 7 > l @ " 1 3 2 6 b & 2 8 1 7 > l @ 3 2 6 b & 2 8 1 7 > l @ $ ' ' b 9 $ / < 9 d o g d w > l @ " < 1 & 2 0 3 $ 5 ( 3 2 6 b & 2 8 1 7 > l @ 3 2 6 b & 2 8 1 7 > l @ 6 8 % b 9 $ / 3 2 6 b & 2 8 1 7 > l @ < 1 g d w d u h v x o w > l @ ? 6 $ ) b 7 + 5 ( 6 + > l @ 1 ( * b & 2 8 1 7 > l @ " 1 1 ( * b & 2 8 1 7 > l @ 1 ( * b & 2 8 1 7 > l @ $ ' ' b 9 $ / < 1 ( * b & 2 8 1 7 > l @ 1 ( * b & 2 8 1 7 > l @ 6 8 % b 9 $ / 1 ( * b & 2 8 1 7 > l @ < p d w f k > l @ " 1 2 b ' $ 7 $ > l @ " < 1 3 2 6 b & 2 8 1 7 > l @ 3 2 6 b & 2 8 1 7 > l @ 3 2 6 b & 2 8 1 7 > l @ 6 8 % b 9 $ / 1 ( * b & 2 8 1 7 > l @ 1 ( * b & 2 8 1 7 > l @ 6 8 % b 9 $ / < 1 1 ( * b & 2 8 1 7 > l @ " < 1 1 ( * b & 2 8 1 7 > l @ 3 2 6 b & 2 8 1 7 > l @ " < 1 1 ( * b & 2 8 1 7 > l @ 3 2 6 b & 2 8 1 7 > l @ ' d w d r x w r i u d q j h f d v h 1 r p d w f k f d v h 3 2 6 b & 2 8 1 7 > l @ ! $ 5 0 3 b 7 + " 3 2 6 b & 2 8 1 7 > l @ $ 5 0 3 b 7 + < 1 ( * b & 2 8 1 7 > l @ ! $ 5 0 1 b 7 + " 1 ( * b & 2 8 1 7 > l @ $ 5 0 1 b 7 + < 1 1 l / " < 1 1 / 1 / 1 / l 1 " < 1 l l l docid025869 rev 3 145/200 l9678, l9678-s safing logic 199 figure 45. safing engine - compare complete ' ! 0 ' 0 3 & & > l @ " < 1 & & > l @ y d o & & > l @ p d w f k & & > l @ l * l + 2 x w s x w v & & > l @ p d w f k > l @ p d w f k & & > l @ 3 2 6 b & 2 8 1 7 > l @ 1 ( * b & 2 8 1 7 > l @ & & b 5 ( $ ' 1 2 b ' $ 7 $ > l @ " 3 2 6 b & 2 8 1 7 > l @ 3 2 6 b & 2 8 1 7 > l @ 3 2 6 b & 2 8 1 7 > l @ 6 8 % b 9 $ / 1 ( * b & 2 8 1 7 > l @ 1 ( * b & 2 8 1 7 > l @ 6 8 % b 9 $ / < 1 1 ( * b & 2 8 1 7 > l @ " < 1 1 ( * b & 2 8 1 7 > l @ 3 2 6 b & 2 8 1 7 > l @ " < 1 1 ( * b & 2 8 1 7 > l @ 3 2 6 b & 2 8 1 7 > l @ < l / " < 1 1 / 1 / 1 / l 1 " < 1 l safing logic l9678, l9678-s 146/200 docid025869 rev 3 each safing record has spi accessible registers defined in the spi command tables and summarized below: ? request mask and request target - to understand what sensor the microcontroller is addressing ? response mask and response target - to identify the sensor response ? data mask - to extract relevant sensor data from the response. sensor data is extracted as a bit-wise and result of the saf_data_maskx and monitored spi_miso data ? the extracted data is then right-justified into a 16-bit register for 16-bit safing records, respectively, prior to further processing steps which assume data is signed - two-s complement represented ? safing threshold - specific value that sets the comparator limit for successful arming ? control: ? if, in frame - to indicate serial data response is "in frame". there are two types of potential serial data responses, "in-frame" and "out of frame" ? cs - to align safing record with a specific spi cs. the device contains 2 spi cs inputs for the safing function (saf_cs0 and saf_cs1) ? arm - there are two internal arming signals, each active record is assigned or mapped to any arming signal. several safing records can be mapped to a single arming output ? dwell - once an arming condition is detected, the safing record remains armed for the specified dwell time ? comb (combined data) - specific solution fo r dual axis high-g sensors specifically oriented off-axis ? lim en (limit enable) - to en able psi5 out-of-range control ? lim sel (limit select) - to select psi5 out-of-range thresholds between 8-bit and 10-bit protocol ? spifldsel (spi field select) a?? to determine which 16-bit field in long spi messages (>31 bit) to use for respon se on miso of spi monitor. if the spifldsel bit is set to 0 the message bits from 0 (first bit received) to 15 are processed, while if set to 1 the message bits from 16 to 31 are processed. spifldsel bit will not help l9678 device to work with sensor that places data across this boundary or has response and data in separate 'fields'. ? in case of message less than 32-bit, alwa ys the first 16bits received will be processed regardless of the spifldsel value. if input packet matches multiple safing records, the safing engine should process all of them and treat them independently. safing record can only be evaluated on the first matching input packet. any further data packet matches are ignored (i.e. once cc is set, record can't be processed until is cleared). the en (record enable) bit for an y record is programmable as on or off at any time and will enable/disable the record itself upon the following sensor sampling period. all cc bits are available in one register (saf_cc) for access in one single spi read. safing engine must not process sensor data in any state but safing state (refer to figure 9 ). all safing records are cleared on ssm reset. docid025869 rev 3 147/200 l9678, l9678-s safing logic 199 comb (combined data) bit allows combining x and y for off-axis oriented sensors. in this case, it is typical for such orientations to add or subtract the sensor response to translate the sensor signal to an on-axis response. only c ouples of 16-bit long records have this feature (i.e. 1&2, 3&4). records are added and subtracted and results compare against two thresholds. safing engine will process data as follows: ? use record (n) and record (n+1), where n = 1, 3. ? the matching inputs used for math combinations are processed only after both are captured. ? the sum of the two matching inputs will be compared to the thre shold of record (n). ? the difference of the two records will be co mpared to the threshold of record (n+1). ? if the comb feature was enabled on only on e of the two records in a couple, math would be performed only on it as shown in figure 43 . example: in this example the arm and dwell assignments for record1 only would be asserted. all items in the safing records, except en(record enable) bit, can be configured only in diag state (refer to figure 9 ). additionally, the global bit to select internal or external safing engine is set in diag state. table 10. records results compare against two threshold combine bit data resulting value record threshold (assume armp) arming result record 1 0 12 12 48 0 record 2 0 50 50 48 1 record 3 0 12 12 48 0 record 4 1 50 50 ? 12 = 38 48 0 record 1 1 12 12 + 50 = 62 48 1 record 2 0 50 50 48 1 record 3 1 12 12 + 50 = 62 48 1 record 4 1 50 50 ? 12 = 38 48 0 safing logic l9678, l9678-s 148/200 docid025869 rev 3 10.3 in-frame and out-of-frame responses some sensors will communicate da ta within the current communi cation frame while others will send data on the next communication frame. sometimes this is sensor specific and sometimes this is due to the am ount of data to be transmitted. a simplified diagram shows the basic communication differences of in and out of frame responses. figure 46. in-frame example figure 47. out of frame example synchronization between clock domains relies upon inter-frame gap. 10.4 safing stat e machine operation state machine operation is disabled when the sa fing state machine reset signal is active as described in the power supply diagnostics an d controls section of this document. the outputs of the state machine are arm1int and arm2int. as previously stated, there is a maximum of 4 safing records available to the state machine. inputs to the safety state machine are programmed safing records and sensor data. the configuration of the state machine is common to all sensors. 10.4.1 simple threshol d comparison operation in this mode, sensor data received through the sensor spi interface and validated by the safing record is passed to th e safing algorithm. the simple threshold comparison algorithm compares the received data to two threshol ds, saf_th (positive threshold) and (-saf_th) (negative threshold). if the sensor data is gr eater than saf_th or is less than (-saf_th) then and event is flagged and the event coun ter is incremented based on the programmed value of add_val. if sensor data does not trigger the saf_th comparators, the counter is decremented by sub_val. sub_val is programmed by the user and can be same or different than add_val. this feature allows for an asymmetrical co unter function making the system either more or less sensitive to sensor data. since sensor data can indicate a positive or negative event, the algorithm ma intains separate even t counters, pos_count and neg_count. the add_val and sub_val programmed values are the same for all safing sources. on each sensor sample, the event counters, both pos_count and neg_count, are updated. each event counter is then compared with a corresponding arming threshold. in this case, pos_count value is compared to armp_th and neg_count to armn_th. armp_th and armn_th are programmable thresholds set by the user. the compared result will set armp and armn to either "1" or "0" depending on the comparison status. if ' ! 0 ' 0 3 - / 3 ) - ) 3 / 2 e q u e s t n 2 e s p o n s e n 3 t a t u s 5 n u s e d ' ! 0 ' 0 3 - / 3 ) 2 e q u e s t n 2 e q u e s t n - ) 3 / 2 e q u e s t n 2 e s p o n s e n docid025869 rev 3 149/200 l9678, l9678-s safing logic 199 armp_th or armn_th are set to 0, the arming will be activated immediately entering in safing state. pos_count and neg_count are not updated if microcontroller stops reading saf_cc bits (this must be avoided otherwise ar ming set and reset will not be possible). by way of the assignment of the add_val, sub_val, armp_th and armn_th settings, the safing engine can be configured to assert arming for either a simple accumulation of counts in a non-consecutive manner, or it could be set to require some number of consecutive samples. 10.5 safing engine output logic (armxint) spi messages are monitored and mapped to spec ific safing records. ea ch safing record is configured with its own threshold, dwell time and the appropriate armxint internal signal to activate if safing criteria are met. any enabled safing record can be programmed to an arming signal. all safing records arming status is logically "or'd" to its prog rammed arming signal. for example, if safing records 1, 2, 4 are programmed to armint1 and the records are enabled, any of the records can set the armint1 signal. configuration of safing record mapping to armxint signals is specified in the saf_control_x register (refer to safing control registers (saf_control_x) on page 106 ). while in diag state, l9678 allows diagnostics of the squib driver hs and ls fets, arm pin, vsf output and firing timers. the arm and vsf output tests are mutually exclusive. for safety purposes, the safing logic circuitry is physically separated from the circuitry that contains the deployment logic. safing logic l9678, l9678-s 150/200 docid025869 rev 3 figure 48. safing engine arming flow diagram l l 1 " 3 2 6 b & 2 8 1 7 > l @ ! $ 5 0 3 b 7 + " $ 5 0 3 < 1 $ 5 0 6 ( / > l @ r u " $ 5 0 > l @ 7 , 0 ( 5 b & 1 7 ' : ( / / > l @ $ 5 0 > l @ 7 , 0 ( 5 b & 1 7 ' : ( / / > l @ 7 , 0 ( 5 b & 1 7 ' : ( / / > l @ 7 , 0 ( 5 b & 1 7 ' : ( / / > l @ < < 1 1 1 $ 5 0 3 $ 5 0 6 ( / > l @ r u " < < < 7 , 0 ( 5 b & 1 7 ! " $ 5 0 , 1 7 $ 5 0 , 1 7 < 1 7 , 0 ( 5 b & 1 7 ! " $ 5 0 , 1 7 $ 5 0 , 1 7 < 1 1 ( * b & 2 8 1 7 > l @ ! $ 5 0 1 b 7 + " $ 5 0 1 < 1 $ 5 0 1 1 l 1 7 , 0 ( 5 b & 1 7 [ l v d e l w g r z q f r x q w h u d o z d \ v u x q q l q j d w p v 7 , 0 ( 5 b & 1 7 [ f r q w u r o h [ w h q g v w r i r u k l j k p l g $ 5 0 [ , 1 7 f r q w u r o h [ w h q g v w r i r u k l j k p l g 6 7 $ 5 7 1 / 1 / 1 / * $ 3 * 3 6 docid025869 rev 3 151/200 l9678, l9678-s safing logic 199 figure 49. safing engine diagnostic logic a configurable mask for each in ternal armxint signal is avail able for all of the integrated deployment loops (refer to armx assignment registers (loop_matrix_armx) on page 97 ). the un-masked armxint signal for eac h loop will enable the respective loop drivers (refer to figure 21 ). activation of vsf (regulation rail for high side safing fet) occurs upon armxint or fenh/fenl, depending on spi configuration (refer to figure 17 ). actual high side safing fet activation still requires microcontroller signal. l9678 is able to provide arming signals to external deployment loops by means of the discrete output arm pin. the arm pin can eith er output an arming signal generated by the integrated safing engine or an arming signal made by the combination of fenh and fenl input signals, coming from external safing logic. figure 50. arm output control logic ' ! 0 ' 0 3 6 3 , ' h f r g h 7 k u h v k r o g & r p s d u h 6 & / . b * 0 2 6 , b * 0 , 6 2 b * & 6 b * 6 $ ) b & 6 6 $ ) b & 6 3 x o v h 6 w u h w f k ' 6 7 ( 6 7 9 6 ) ' , $ * 6 7 $ 7 ( ' 6 7 ( 6 7 $ 5 0 $ 5 0 , 1 7 $ 5 0 , 1 * 6 7 $ 7 ( $ 5 0 , 1 7 ' 6 7 ( 6 7 3 8 / 6 ( & + 3 8 / 6 ( & + 3 8 / 6 ( & + 3 8 / 6 ( & + 3 8 / 6 ( ' ! 0 ' 0 3 $ 5 0 : ' b / 2 & . 2 8 7 6 6 0 b 5 ( 6 ( 7 $ 5 0 , 1 7 : ' b 5 8 1 6 d i l q j ( q j l q h : ' b 2 9 ( 5 5 , ' ( $ 5 0 , 1 7 ) ( 1 / ) ( 1 + 6 $ ) ( 6 ( / $ 5 0 b ( 1 safing logic l9678, l9678-s 152/200 docid025869 rev 3 10.6 arming pulse stretch upon a valid command processed by the safing logic, the dwell bits to stretch the arming time assertion (dwell time) ap ply to each safing record a nd is used to help safe the deployment sequence to avoid undesired behaviour. once dwell time has started, it will continue, regardless of the en (record enable) bit. dwell will be truncated in case of ssm reset. dwell va lues in the safing reco rds are transferred to the arm signal. a dedicated counter is designed for arm output pin. if different dwell values are assigned to arm, the longer val ue is used. dwell times can only be extended, not reduced. if the remaining dwell time is less than the ne w dwell extension setting, the new setting will be loaded into the dwell counter. dwell times are user programmable. the behavior of the pulse st retch timer is shown in figure 51 . figure 51. pulse stretch timer example 10.7 additional communication line the acl pin is the additional communication li ne input that provides a means of safely activating the arming outputs (arm and vsf) for disposal of restraints devices at the end of vehicle life. a valid acl detection (as described below) allows l9678 to transition from scrap state to arming state. to remain in arming state l9 678 must receive the correct acl signal; this must occur before the scrap time-out timer expires (t diseol ). while the system operating state machine is in arming state, the arming outputs are asserted (arm=1, vsf on). if the acl is not corr ectly received before the time-out expires, the system operating state machine reverts back to the scrap state, and the arming outputs are deactivated. ' ! 0 ' 0 3 $ u p l q j 6 d i l q j / r j l f 3 u r f h v v h g u h v x o w $ u p l q j ( q d e o h 3 x o v h 6 w u h w f k 3 x o v h 6 w u h w f k 7 l p h / h v v 7 k d q 3 x o v h 6 w u h w f k 7 l p h 3 x o v h 6 w u h w f k 7 l p h docid025869 rev 3 153/200 l9678, l9678-s safing logic 199 figure 52. scrap acl state diagram a specific waveform needs to be present on this input in order to instruct l9678 to arm all deployment loops. l9678 is designed to s upport the additional communication line (acl) aspect of the iso-26021 standard, which requires an independent hardwired signal (acl) to implement the scrapping feature. the disposal signal may come from either the vehicle's service connector, or the systems main microcontroller, depending on the end customer's requirements. the arming function monitors the disposal pw m input (acl pin) for a command to arm all loops for vehicle end-of-life airbag disposal. the disposal signal charac teristic is shown in figure 53 . to remain in arming state, at least three cycles of the acl signal must be qualified. for the device to qualify the perio dic acl signal, the period and duty cycle are checked. two consecutive cycles of invalid disp osal signal are to be received to disqualify the acl signal. figure 53. disposal pwm signal the disposal pwm signal cycle time and on time parameters can be found in the electrical parameters tables. ' ! 0 ' 0 3 $ & / + , * + $ & / 7 0 5 6 6 0 b 5 ( 6 ( 7 2 5 1 2 7 6 & 5 $ 3 v w d w h $ 1 ' 1 2 7 $ 5 0 , 1 * v w d w h $ & / * 2 2 ' $ & / % $ ' ) d o o l q j h g j h $ & / 7 0 5 ! k l j k p l q $ & / / 2 : $ & / 7 0 5 ! s h u l r g p l q u l v l q j h g j h $ & / * 2 2 ' $ & / % $ ' $ & / 7 0 5 $ & / ( 5 5 2 5 5 l v l q j h g j h 2 5 $ & / 7 0 5 ! s h u l r g p d [ $ & / 7 0 5 $ & / 7 0 5 ! k l j k p d [ 2 5 ) d o o l q j h g j h $ & / 7 , 0 ( 5 k l j k p l q $ & / * 2 2 ' $ & / % $ ' $ & / 7 0 5 ! s h u l r g p d [ $ & / * 2 2 ' $ & / % $ ' $ & / 7 0 5 5 l v l q j h g j h $ & / 7 0 5 $ & / * 2 2 ' $ & / % $ ' ' ! 0 ' 0 3 & \ f o h w l p h 2 q w l p h general purpose output (gpo) drivers l9678, l9678-s 154/200 docid025869 rev 3 11 general purpose output (gpo) drivers the l9678 contains two gpo drivers configurab le either as high-side or low-side modes, controlled in on-off mode or in pwm mode setting the desired duty cycle value through the gpo control regi ster (gpoctrlx). for low side driver configuration, the gpodx pi n is the equivalent drain connection of the internal mosfet and it is the current sink for the output driver. the gposx pin is the source connection of the gpo driver and is externally connected to ground. figure 54. gpo driver block diagram - ls configuration for high side driver configur ation, the gpodx pin will be co nnected to battery and gposx pin will be connected to the load high side. ( 5 % 2 2 6 7 * 3 2 ' [ * 3 2 6 [ 9 u h i 9 l q 9 e l w v 6 h o * 3 2 ' [ 2 1 & x u u h q w o l p l w d w l r q 9 % d w w q ) / 2 $ ' & x u u h q w v h q v h 3 : 0 b & / . x v ' u l y h u z l w k 6 o h z 5 d w h & r q w u r o c 3 : 0 & 7 / ( 1 2 8 7 & 7 / * 3 2 ) / 7 6 5 * 3 2 [ ' , 6 $ % / ( * 3 2 & 7 5 / [ > @ * 3 2 & 5 * 3 2 [ / 6 ( 5 % 2 2 6 7 b 2 . 4 4 6 ( 7 & / 5 6 5 6 3 , : , ' ? * 3 2 & 5 ? 6 6 0 b 5 ( 6 ( 7 7 h p s h u d w x u h v h q v r u 7 m v g 4 4 6 ( 7 & / 5 6 5 4 4 6 ( 7 & / 5 6 5 * 3 2 & 7 5 / [ > @ k 6 6 0 b 5 ( 6 ( 7 * 3 2 ) / 7 6 5 * 3 2 [ 7 ( 0 3 4 4 6 ( 7 & / 5 6 5 4 4 6 ( 7 & / 5 6 5 6 6 0 b 5 ( 6 ( 7 6 3 , 5 , ' ? * 3 2 ) / 7 6 5 ? , r s h q o r d g , o l p * 3 2 ) / 7 6 5 * 3 2 [ 2 3 1 * 3 2 ) / 7 6 5 * 3 2 [ / , 0 * $ 3 * 3 6 docid025869 rev 3 155/200 l9678, l9678-s general purpose output (gpo) drivers 199 figure 55. gpo driver block diagram - hs configuration the drivers have to be configured in one of the two modes through the gpo configuration register (gpocr) register before being activa ted. this hardware co nfiguration is only allowed during the init and diag states. when configured as high-side, the drivers need er boost voltage to be above the verbst_ok threshold to be enabled. the default state of both drivers is off. the drivers can be independently activated via spi control bits on gpo control register (gpoctrlx). in addition, a set point on the gpoctrlx will control the outp ut drivers in pwm with a 125h z frequency. if pwm control is desired, user should set the needed set po int in the gpoxpwm bits of the gpoctrlx while activating the interface. when all bits are set to '0', the gpox output will be disabled. pwm control is based on a 125 hz frequency. 6 bits of gpoctrlx are reserved to this mode, in order to contro l the drivers with 64 total levels from a 0% to a full 100% duty cycle. ? when both gpo channels are used in pwm mode at the same frequency they are synchronized to provide para llel configuration capability. pwm control is implemented through a careful slew rate control to mitigate emc emissions while operating the interface. the driver output structure is designed to stand -1v on its terminals and a +1v reverse voltage across source and drain. the gpo driver is protected against short ci rcuits and thermal overload conditions. the output driver contains diagnostics available in the gpo fault status register (gpofltsr). all faults except for therma l overload will be latched until the gpofltsr register is read. * $ 3 * 3 6 ( 5 % 2 2 6 7 * 3 2 ' [ * 3 2 6 [ 9 u h i 9 l q 9 e l w v 6 h o * 3 2 ' [ 2 1 & x u u h q w o l p l w d w l r q 9 l q q ) & x u u h q w v h q v h 3 : 0 b & / . x v ' u l y h u z l w k 6 o h z 5 d w h & r q w u r o c 3 : 0 & 7 / ( 1 2 8 7 & 7 / * 3 2 ) / 7 6 5 * 3 2 [ ' , 6 $ % / ( * 3 2 & 7 5 / [ > @ * 3 2 & 5 * 3 2 [ / 6 ( 5 % 2 2 6 7 b 2 . 4 4 6 ( 7 & / 5 6 5 6 3 , : , ' ? * 3 2 & 5 ? 6 6 0 b 5 ( 6 ( 7 7 h p s h u d w x u h v h q v r u 7 m v g 4 4 6 ( 7 & / 5 6 5 4 4 6 ( 7 & / 5 6 5 * 3 2 & 7 5 / [ > @ k 6 6 0 b 5 ( 6 ( 7 * 3 2 ) / 7 6 5 * 3 2 [ 7 ( 0 3 4 4 6 ( 7 & / 5 6 5 4 4 6 ( 7 & / 5 6 5 6 6 0 b 5 ( 6 ( 7 6 3 , 5 , ' ? * 3 2 ) / 7 6 5 ? , r s h q o r d g , o l p * 3 2 ) / 7 6 5 * 3 2 [ 2 3 1 * 3 2 ) / 7 6 5 * 3 2 [ / , 0 / 2 $ ' general purpose output (gpo) drivers l9678, l9678-s 156/200 docid025869 rev 3 thermal overload faults will remain active afte r reading the gpofltsr register should the temperature remain above the thermal fault cond ition. for current limit faults, the output driver will operate in a linear mode (ilim) until a thermal fa ult condition is detected. the device offers also an open load diagnosti cs while in on state. the diagnostics is run comparing the current through the output stage with a reference threshold i openload : should the output current be lower than the threshold, the open detection flag is asserted. docid025869 rev 3 157/200 l9678, l9678-s iso9141 transceiver 199 12 iso9141 transceiver a block diagram of the function is show n below. data transmitted by the main microcontroller is sent via the isotx pin and data is received via the isorx pin. the bus output is isok. figure 56. iso9141 block diagram when the isotx pin is asserted , logic high, the isok output will be disabled (pulled high by an external resistor). when th e isotx pin is deasserted, logic low, the isok output will be enabled (pulled low by the internal driver). this input pin contains an internal pull-up to command the output to the disabled state in the event of an open circuit condition. the isorx pin has a push-pull output stage re ferenced to vddq voltage. this output is asserted high when the voltage on the isok pin is above the isok input receiver threshold, vbatmon, as defined in the electrical tables. this output is deasserted low when the voltage on the isok pin is below the isok input receiver threshold with hysteresis. isok output is a low side driver co mpatible with iso9141 physical layer. the output stage is protected against short ci rcuits and diagnostics provide feedback for current limit and thermal shutdo wn. while in current limit, the output stage will continue to function until thermal limit is r eached. should therma l limit occur, the output stage will shut down until the temperature decreases below th e limit threshold with hysteresis. the fault status is reported in the iso9141 fault status register (isofltsr). ' ! 0 ' 0 3 y g g t 9 , + ) / 7 6 5 , / , 0 ; & 9 5 ) / 7 6 5 2 7 ; & 9 5 , 6 2 . 9 % $ 7 7 k h u p d o 6 k x w g r z q * d w h & r q w u r o ) l o w h u , 6 2 7 ; , 6 2 5 ; w g , o l q 9 , 1 7 system voltage diagnostics l9678, l9678-s 158/200 docid025869 rev 3 13 system voltage diagnostics l9678 has an integrated dedicated circuitry to provide diagnostic feedback and processing of several inputs. these inputs are addressed with an internal analog multiplexer and made available through the spi digital interface with the diagnostic data commands. in order to avoid saturation of high voltage internal signal s, an internal voltage divider is used. the diagnostics circuitry is activa ted by four spi diagnostics control commands (diagctrlx); each of them can address all the availabl e nodes to be monitor ed, except for what mentioned in table 11: diagnostics control register (diagctrlx) on page 159 . diagctrlx spi command bit fields are structured in the following way: diagctrl_a (address hex 3a) diagctrl_b (address hex 3b) diagctrl_c (address hex 3c) diagctrl_d (address hex 3d) adcreq[a-d] bit fields, used to address the different measurements offered, are listed in table 11: diagnostics control register (diagctrlx) on page 159 for reference. l9678 diagnostics are structured to take four automatic conversions at a time. in order to get four measurements, four different spi commands have to be sent (diagctrl_a, diagctrl_b, diagctrl_c and diagctrl _d), in no particular order. 19 1817161514131211109876543210 mosi xxxxxxxxx a dcreq_a[6:0] miso newdata_a 0 0 adcreq_a[6:0] adcres_a[9:0] 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi x x x x x x x x x adcreq_b [6:0] miso newdata_b 0 0 adcreq_b [6:0] adcres_b [9:0] 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mosi x x x x x x x x x adcreq_c [6:0] miso newdata_c 0 0 adcreq_c [6:0] adcres_c [9:0] 19 1817161514131211109876543210 mosi xxxxxxxxx a dcreq_d [6:0] miso newdata_d 0 0 adcreq_d [6:0] adcres_d [9:0] docid025869 rev 3 159/200 l9678, l9678-s system voltage diagnostics 199 in case the voltage to be measured is not i mmediately available, the desired inputs for conversion have to be programmed by spi in advance, to allow them to attain a stable voltage value. this case applies to the squib resistance measurement and diagnostics (refer to loop diagnostics control and results registers ) and to the switch sensor measurement (refer to section 9: dc sensor interface ). convrdy_0 bit in gsw is equal to (new data_a or newdata_b), while convrdy_1 bit in gsw corresponds to (newdata_c or newdata_d). each newdatax flag is asserted when conversi on is finished and cleared when result is read out. however result is cl eared only when new result for that register is available. when a new request is received it is que ued if other conversions are ongoing. the conversions are executed in the same order as their request arrived. the queue is 4 measures long so it's possible to send all 4 re quests at the same time and then wait for the results. if a diagctlrx command is received t wice, the second conversion request will overwrite the previous one. requests are sent to the l9678 ic via t he adc measurement registers (adcreqx) as shown in table 11: diagnostics control register (diagctrlx) on page 159 . all diagnostics results are available on the adcresx registers, when addressed by the related adcreqx register (e.g. data reque sted by adcreqa would be written to adcresa). table 11. diagnostics control register (diagctrlx) adc request (adcreqx) voltage measurement selection adc results (adcresx) bit [6:0] hex bit [9:0] 0000000 0 $00unused 0000001 1 $01adc test pattern 1 gro und reference 0000010 2 $02adc test pattern 2 full scale reference 0000011 3 $03dc sensor ch. selected, voltage dcsv_selected 0000100 4 $04dc sensor ch. selected, current dcsi_selected 0000101 5 $05dc sensor ch. selected, resistance (1) dcsv and dcsi selected 0000110 6 $06squib measurement l oop selected voutx 0000111 7 $07bandgap reference voltage vbgr 0001000 8 $08bandgap reference monitor voltage vbgm 0001001 9 $09unused 000101010 $0atemperature measurement temp 000101111 $0bdc sensor ch 0, voltage dcsv_0 000110012$0cdc sensor ch 1, voltage dcsv_1 000110113$0ddc sensor ch 2, voltage dcsv_2 000111014 $0edc sensor ch 3, voltage dcsv_3 000111115 $0funused 001000016 $10unused 001000117 $11unused 001001018 $12unused system voltage diagnostics l9678, l9678-s 160/200 docid025869 rev 3 001001119 $13unused 001010020 $14unused 001010121 $15unused 001011022 $16unused 001011123 $17unused 001100024 $18unused 001100125 $19unused 001101026 $1aunused 001101127 $1bunused 001110028$1cunused 001110129$1dunused 001111030 $1eunused 001111131 $1funused 010000032 $20battery monitor voltage vbatmon 010000133 $21device battery voltage vin 010001034 $22analog internal supply voltage vint3v3 010001135 $23digital internal supply voltage cvdd 010010036 $24erboost voltage erboost 010010137 $25unused 010011038 $26ver voltage ver 010011139 $27vsup volt age vsup 010100040 $28vddq voltage vddq 010100141 $29w akeup voltage wakeup 010101042 $2avsf regulator voltage vsf 010101143 $2bwdt/tm voltage wdtdis 010110044$2cgpo driver 0 drain voltage gpod0 010110145$2dgpo driver 0 source voltage gpos0 010111046 $2egpo driver 1 drain voltage gpod1 010111147 $2fgpo driver 1 source voltage gpos1 011000048 $30unused 011000149 $31unused 011001050 $32remote sensor interface voltages ch. 0 rsu0 011001151 $33remote sensor interface voltages ch. 1 rsu1 table 11. diagnostics control re gister (diagctrlx) (continued) adc request (adcreqx) voltage measurement selection adc results (adcresx) bit [6:0] hex bit [9:0] docid025869 rev 3 161/200 l9678, l9678-s system voltage diagnostics 199 proper scaling is necessary for various voltage measurements. the divider ratios vary by measurement and are summarized by function in the table below. 011010052 $34unused 011010153 $35unused 011011054 $36ssxy voltage ch. 0 ss01 011011155 $37ssxy voltage ch. 1 ss01 011100056 $38ssxy voltage ch. 2 ss23 011100157 $39ssxy voltage ch. 3 ss23 011101058 $3aunused 011101159 $3bunused 011110060$3cunused 011110161$3dunused 011111061 $3eunused 011111163 $3funused 100000064 $40unused 100000165 $41unused 100001066 $42vresdiag vresdiag 100001167 $43vdd5 vdd5 100010068 $44vdd3v3 vdd3v3 100010169 $45isok output voltage isok 100011070 $46sf0 voltage sf0 100011171 $47sf1 voltage sf1 100100072 $48sf2 voltage sf2 100100173 $49sf3 voltage sf3 1. the dc sensor resistance measurement can only be addressed through diagcrtl _a command. results are available through diagctrl_a and diagctrl_b, where adcres_a wi ll contain dcsi and adcres_b will contain dcsv. table 11. diagnostics control re gister (diagctrlx) (continued) adc request (adcreqx) voltage measurement selection adc results (adcresx) bit [6:0] hex bit [9:0] table 12. diagnostics divider ratios measurements divider ratio 15:1 10:1 7.125:1 7:1 4:1 1:1 ver x erboost x vsf x ssxy x system voltage diagnostics l9678, l9678-s 162/200 docid025869 rev 3 for measurements other than voltage (current, resistance, temperature etc.) the ranges are specified in the electrical parameters section of the relevant block. 13.1 analog to digital algorithmic converter the device hosts an integrated 10 bit analog to digital converter, running at a clock frequency of 16mhz. the adc output is proc essed by a d to d conv erter with the following functions: ? use of trimming bits to recover adc offset and gain errors; ? digital low-pass filtering; ? conversion from 12 to 10 bits. 10 bits data are filtered inside the digital sect ion. the number of samples that are filtered vary depending on the chosen conversion. as per section 5.1.2: system configuration register (sys_cfg) , the number of used samples in converting dc sensor, squib or temperature measurements defaults to 8. the number of samples for all other measurements defaults to 4. the sample nu mber can be configured by accessing the sys_cfg register. after low pass filter, the resid ual total error is 4 l sb. this error figure sfx x vresdiag x gpodx x gposx x vin x vbatmon x wakeup x isok x vsup x wdtdis x rsux x dcsx x vddq x vdd5 x vdd3v3 x vint3v3 x bandgap (bgr/bgm) x temp x table 12. diagnostics di vider ratios (continued) measurements divider ratio 15:1 10:1 7.125:1 7:1 4:1 1:1 docid025869 rev 3 163/200 l9678, l9678-s system voltage diagnostics 199 applies to the case of a precise reference voltage: the spread of reference voltage causes a proportional error in the conversion output. the reference voltage of the adc is set to 2.5 v. the conversion time is comprised of several factors: the number of measurements loaded into the queue, the number of samples taken for any measurement, and the various settling times. an example of conversion time calculation for a full adc request queue is reported in figure 57 . the timings reported in figure 57 are nominal ones, min/max values can be obtained by considering the internal oscillator frequency variation reported in the dc characteristics section. figure 57. adc conversion time ' ! 0 ' 0 3 3 u h $ ' & 6 7 b 6 & , 4 3 r v w $ ' & 6 7 b 6 & , 4 6 7 b 6 & , 4 6 7 b 6 & ' , $ * & 7 5 / b $ ' , $ * & 7 5 / b % ' , $ * & 7 5 / b & ' , $ * & 7 5 / b ' 3 u h $ ' & , q l w l d o $ ' & 6 h w w o l q j 7 l p h x v 6 r i 6 d p s o h v g h i d x o w i r u y r o w d j h r q o \ p h d v x u h p h q w v 7 b 6 & 6 l q j o h 6 d p s o h & r q y h u v l r q 7 l p h x v , 4 , q w u d 4 x h x h 6 h w w o l q j 7 l p h x v 3 r v w $ ' & ) l q d o $ ' & 6 h w w o l q j 7 l p h x v temperature sensor l9678, l9678-s 164/200 docid025869 rev 3 14 temperature sensor the l9678 provides an internal analog temperature sensor. the sensor is aimed to have a reference for the average juncti on temperature on silicon surface. t he sensor is placed far away from power dissipating stages and squib deployment drivers. the output of the temperature sensor is available via spi through adc conversion, as shown in table 11 . the formula to calculate temperature from adc reading is the following one: t q c 180 220 1.652 -------------- - ? 1 adc ref_hi 2 adc res ------------------------------- diagctrln adcresn ? ? 1 ? 0.739 ? ? ? ? ? - ? ?= @ diagctrln(adcreqn) = 0a hex all parametric requirements for this block can be found in specification tables. docid025869 rev 3 165/200 l9678, l9678-s electrical characteristics 199 15 electrical characteristics every parameter in this chapt er is fulfilled down to vin good(max) . no device damage is granted to occur down to vin bad (min). gnda pin is used as ground reference for th e voltage measurements performed within the device, unless otherwise stated. all table or parameter declared "design info" are not tested during production testing 15.1 configuration and control all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good (max) ? vin ? 35 v. table 13. configuration and control dc specifications n symbol parameter condition min typ max unit 1v nov normal operating voltage design info depending on power supply configuration 61318v 2v jsv jump start voltage design info -40 c ta 50 c 18.00 - 26.50 v 3v ldv load dump voltage transient design info 26.50 - 40 v 4wu_mon wakeup monitor threshold ---1.5v 5 wu_off wakeup off threshold - 2 2.5 3 v 6 wu_on wakeup on threshold - 4 4.5 5 v 7wu rpd wakeup pull-down resistor - 120 300 480 k ? 8vb good1 vbatmon input voltage thresholds sys_ctl(vbatmon_th_sel)=0 0 5.5 - 6 v 9vb bad1 sys_ctl(vbatmon_th_sel)=0 0 5-5.5v 10 vb good2 sys_ctl(vbatmon_th_sel)=0 1 6.3 - 6.8 v 11 vb bad2 sys_ctl(vbatmon_th_sel)=0 1 5.8 - 6.3 v 12 vb good3 sys_ctl(vbatmon_th_sel)=1 0 7.5 - 8 v 13 vb bad3 sys_ctl(vbatmon_th_sel)=1 0 7-7.5v 14 vb good4 sys_ctl(vbatmon_th_sel)=11 8.3 - 8.8 v 15 vb bad4 sys_ctl(vbatmon_th_sel)=11 7.8 - 8.3 v electrical characteristics l9678, l9678-s 166/200 docid025869 rev 3 16 i lkg_vbatmon_off vbatmon input leakage device off -5 5 a 17 i lkg_vbatmon_on device on design info 20 24 30 a 18 r pd_vbatmon vbatmon pull-down resistance device on vbatmon < 10v design info 125 250 375 k ? 19 i lkg_vbatmon_tot vbatmon total input leakage i lkg_vbatmon_on + r pd_vbatmo vbatmon = 18v 35 70 105 a 20 vin good1 vin input voltage thresholds sys_ctl(vin_th_sel)=0 5 - 5.5 v 21 vin bad1 sys_ctl(vin_th_sel)=0 4.5 - 5 v 22 vin good2 sys_ctl(vin_th_sel)=1 7 - 7.5 v 23 vin bad2 sys_ctl(vin_th_sel)=1 6.5 - 7 v 24 vin fastslope_h vin thresholds used to change boost regulator transition time -9.39.810.3v 25 vin fastslope_l -99.510v 26 vin fastslope_hys - 0.2 0.3 0.4 v 27 i lkg_vin_off vin input leakage device off, vin = 40v -10 - 10 a 28 i lkg_vin_on device on, vin = 12v - - 30 ma 29 c vin external vin capacitor - 1 - - - 30 i lkg_ver_off ver input leakage device off, ver = 40 v -5 - 5 a 31 i lkg_ver_on_l device on erboost > ver -5 - 5 a 32 i lkg_ver_on_h device on erboost < ver --200a 33 v wd_override_th wdt/tm threshold - 10 12 14 v 34 v wdtdis_hyst wdt/tm hysteresis - 0.2 0.4 0.5 v 35 i pd_wdtdis wdt/tm pull-down current v wdtdis 5 v 204570a 36 i lkg_bat battery line input leakage total leakage at rt from vin, vbatmon, erbstsw, erboost, bvdd5, vdd5, vddq, bvsup, vsup vbat = 12 v guaranteed by design --100a 37 t j junction temperature design info - - 150 c table 13. configuration and contro l dc specifications (continued) n symbol parameter condition min typ max unit docid025869 rev 3 167/200 l9678, l9678-s electrical characteristics 199 15.2 internal analog reference all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35 v. table 14. configuration and control ac specifications no symbol parameter con dition min typ max units 1t flt_vbatmonth vbatmon thresholds deglitch filter time -263034s 2t flt_vinth vin thresholds deglitch filter time - 3 3.5 4 s 3t flt_wakeup wakeup deglitch filter time - 0.95 1.05 1.15 ms 4t latch_wakeup wakeup latch time - 9.7 10.8 11.9 ms 5t don power-up delay time ? ? wake-up to reset released ---10ms table 15. open ground detection dc specifications n symbol parameter con dition min typ max unit 1 gnda open gnda threshold gndsubx=0 100 200 300 mv 2gndd open gndd threshold gndsubx=0 100 200 300 mv 3 bstgnd open bstgnd threshold gndsubx=0 100 200 300 mv 4i pu_bstgnd bstgnd pull-up current - 80 120 160 a table 16. open ground detection ac specifications n symbol parameter condition min typ max unit 1t flt_gndrefopen gnda and gndd open deglitch filter time -71116s 2t flt_bstgndopen bstgnd latch filter time - 1.9 2.3 2.7 s table 17. internal analog reference n symbol parameter condition min typ max unit 1v bg1 bandgap reference - -1% 1.2 +1% v 2v bg2 bandgap monitor - -1% 1.2 +1% v 3v adc_ground adc ground reference - -3% 103 +3% mv 4v adc_fullscale adc full scale reference - -1.5% 2.5 +1.5% v electrical characteristics l9678, l9678-s 168/200 docid025869 rev 3 15.3 internal regulators all electrical characteristics are valid for the following conditions unless otherwise noted: -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35 v. 15.4 oscillators all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, 3.14 ? cvdd ? 3.46. table 18. internal regulators dc specifications n symbol parameter condition min typ max unit 1v out_vint3v3 vint3v3 output voltage - 3.14 3.3 3.46 v 2v ov_vint3v3 vint3v3 over voltage - 3.47 - 3.7 v 3v uv_vint3v3 vint3v3 under voltage - 2.97 - 3.13 v 4v out_vdd vdd output voltage - 3.14 3.3 3.46 v 5i out_vdd vdd current capability external load is not allowed - - 50 ma 6i lim_vdd vdd current limit - 80 - - ma 7v ov_vdd vdd over voltage - 3.47 - 3.7 v 8v uv_vdd vdd under voltage - 2.7 - 2.9 v 9c vdd vdd output capacitance design info 60 100 140 nf table 19. internal regulators ac specifications n symbol parameter condition min typ. max unit 1t flt_ vint_vdd_ov internal regulator ov deglitch filter time - 7 11 16 s 2t flt_ vint_vdd_uv internal regulator uv deglitch filter time -71116v table 20. oscillators ac specifications no symbol parameter conditions / comments min typ max unit 1f osc main oscillator average frequency - 15.2 16 16.8 mhz 2f mod_osc main oscillator modulation frequency spi_clk_cnf(main_ss_dis=0) design info --mhz 3i mod_osc main oscillator modulation index spi_clk_cnf(main_ss_dis=0) 3 4 5 % 4f aux aux oscillator average frequency - 7.125 7.5 7.87 5 mhz 5f mod_aux aux oscillator modulation frequency spi_clk_cnf(aux_ss_dis=0) design info --mhz ? osc 128 -------------- - ? osc_aux 128 ---------------------------- docid025869 rev 3 169/200 l9678, l9678-s electrical characteristics 199 15.5 watchdog all electrical characteristics are valid for the following conditions unless otherwise noted: -40 c ? ta ? +95 c,vin good1 (max) ? vin ? 35 v 15.6 reset all electrical characteristics are valid for the following conditions unless otherwise noted: -40 c ? ta ? +95 c; vin good1 (max ) ? vin ? 35 v, vddx(min) ? vddx ? vddx(max), vddq = vdd5 or vdd3v3 6i mod_aux aux oscillator modulation index spi_clk_cnf(aux_ss_dis=0) 3 4 5 % 7f osc_low_th main oscillator low frequency detection threshold ---mhz table 20. oscillators ac specifications (continued) no symbol parameter conditions / comments min typ max unit 128 174 --------- - ? aux ? 1t wdt1_timeout temporal watchdog timeout - - - 2.00 ms --16.3ms 2t wdt1_rst temporal watchdog reset time -0.9-1.1ms table 22. reset dc specifications n symbol parameter condition min typ max unit 1v oh_reset reset output voltage i load = -0.5 ma vddq -0.6 - vddq v 2v ol_reset i load = 2.0 ma 0 - 0.4 v 3r pd_reset reset pull down resistance reset=vddq, device off 65 100 135 k ? table 23. reset ac specifications n symbol parameter condition min typ max unit 1t rise_reset rise time 80pf load, 20%-80% - - 1.00 s 2t fall_reset fall time 80pf load, 20%-80% - - 1.00 s 3t hold_reset reset hold time - 0.45 0.5 0.55 ms electrical characteristics l9678, l9678-s 170/200 docid025869 rev 3 15.7 spi interface all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35 v, vddx(min) ? vddx ? vddx(max) vddq = vdd5 or vdd3v3. table 24. spi dc specifications n symbol parameter condition min typ max unit 1v ih_cs spi_cs high level input voltage -2--v 2v il_cs spi_cs low level input voltage ---0.8v 3i pu_cs spi_cs pull up current spi_cs = 0v -70 -45 -20 a 4v ih_mosi mosi high level input voltage -2--v 5v il_mosi mosi low level input voltage ---0.8v 6i pd_mosi spi_mosi pull down current spi_mosi = vddq 20 45 70 a 7v ih_sck sck high level input voltage -2--v 8v il_sck sck low level input voltage ---0.8v 9i pd_sck spi_sck pull down current spi_sck = vddq 20 45 70 a 10 v oh_miso spi_miso high level output voltage i load = -800a vddq -0.5 - vddq v 11 v ol_miso spi_miso low level output voltage i load = 2.0ma - - 0.4 v 12 v ih_miso spi_miso high level input voltage -2--v 13 v il_miso spi_miso low level input voltage ---0.8v 14 i lkg_miso spi_miso tri-state leakage spi_miso= vddq or 0v -10 - 10 a docid025869 rev 3 171/200 l9678, l9678-s electrical characteristics 199 note: all timing is shown with respect to 10% and 90% of the actual delivered vddq voltage. figure 58. spi timing diagram table 25. spi ac specifications n symbol parameter condition min typ max unit 1f sclk spi transfer frequency - - 8 8.08 mhz 2t sclk spi_sck period - 123.8 - - ns 3t lead enable lead time - 250 - - ns 4t lag enable lag time - 50 - - ns 5t high_sclk spi_sck high time - 50 - - ns 6t low_sclk spi_sck low time - 50 - - ns 7t setup_mosi spi_mosi input setup time -20--ns 8t hold_mosi spi_mosi input hold time -20--ns 9t acc_miso spi_miso access time 80pf load - - 60 ns 10 t dis_miso spi_miso disable time 80pf load - - 100 ns 11 t valid_miso_out spi_miso output valid time 80pf load - - 30 ns 12 t hold_miso_out spi_miso output hold time 80pf load 0 - - ns 13 t setup_miso_in spi_miso input setup time 20 ns 14 t hold_miso_in spi_miso input hold time 20 ns 15 t hold_sclk spi_sck hold time - 20 - - ns 16 t flt_cs spi_cs noise glitch rejection time -50-300ns 17 t nodata spi interframe time - 400 - - ns ' ! 0 ' 0 3 6 3 , b & 6 6 3 , b 6 & / . 6 3 , b 0 2 6 , 6 3 , b 0 , 6 2 0 6 % 2 8 7 / 6 % , 1 ' $ 7 $ ' $ 7 $ / 6 % 2 8 7 ' 2 1 ? 7 & $ 5 ( 0 6 % , 1 electrical characteristics l9678, l9678-s 172/200 docid025869 rev 3 15.8 er boost all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 18 v. table 26. er boost converter dc specifications n symbol parameter condition min typ max unit 1 v o_erbst boost output voltage across all line and i o_bst load (steady state) erbst33v=0 ? test conditions: i o_bst = 0.1 & 40ma 22.4 23.8 25 v 2 across all line and i o_bst load (steady state) erbst33v=1 ? test conditions: i o_bst = 0.1 & 20ma 31.4 33 35 v 3 i o_erbst boost output current bst33v = 0 0.1 - 60 ma 4 bst33v = 1 0.1 - 40 ma 5dv sr_ac line transient response all line, load; dt=100us; bst33v = 0/1 design info -8% - 8% % 6dv lr_ac load transient response all line, load; dt=100us; bst33v = 0/1 design info -8% - 8% % 7r dson_erbst power switch resistance - - - 1 ? 8i oc_erbst over current detection - 550 - 800 ma 9i lkg_erbst erboost leakage current erboost=40v device off --5a 10 v erbst_ok erboost voltage threshold bst33v = 0 18 20 22 v 11 bst33v = 1 26 28 30 v 12 v erbst_ov erboost over voltage threshold bst33v = 0 22.6 25 v 13 bst33v = 1 31.65 35 v 14 v erbst_dis_th voltage difference between vin and erboost to deactivate the er boost regulator vin ? erboost 1.6 2.2 2.5 v 15 v clamp_en_th voltage difference between erbstsw and erboost to activate the er boost clamp erbstsw ? erboost 1.6 2.2 2.5 v 16 t jsd_erbst thermal shutdown - 150 175 190 c 17 t hys_tsderbst -51015c docid025869 rev 3 173/200 l9678, l9678-s electrical characteristics 199 table 27. er boost converter ac specifications n symbol parameter condition min typ max unit 1f sw_erbst erboost switching frequency - 1.8 1.882 2.0 mhz 2 t rise_erbstsw_slow t fall_erbstsw_slow erbstsw transition time 10% to 90% voltage on erbstsw vin vin fastslope_l = 10.3 v iload = 60ma erboost settings 23 v guaranteed by design 10 15 - 25 35 ns 3 t rise_erbstsw_fast t fall_erbstsw_fast 10% to 90% voltage on erbstsw vin vin fastslope_h = 9 v iload=60ma erboost settings 23 v guaranteed by design 10 - 25 ns 4t on_erbst erboost charge-up time c erboost = 2.2f, vin =12v, i o_erbst = 5ma bst33v = 1 measured from cs edge to v o_erbst (min) --5ms 5t flt_tsd_erbst thermal shutdown filter time - - 10 s table 28. er boost converter external components (design info) n symbol parameter condition min typ max unit 1l erbst inductance - 8 10 - h 2esl erbst inductance resistance - - - 0.1 ? 3c blk_erbst output bulk capacitance to ensure regulator stability min capacitance value including derating factors 12.2 f 4 esr cblk_erbst bulk capacitor esr - - - 0.1 ? 5v fstr_erbst steering diode forward voltage i f =100 ma - - 0.85 v 6i lkgstr_erbst steering diode reverse leakage ta = 9 5 c - - 1 0 0 a electrical characteristics l9678, l9678-s 174/200 docid025869 rev 3 15.9 er charge all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35 v, 8 v ? erboost. 15.10 er switch all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35 v. table 29. er current generator dc specifications n symbol parameter condition min typ max unit 1i er_charge er charge current erboost ? ver ? 3 v -33 -30 -27 ma 2r dson_ercharge er charge power resistance (v erboost - v ver ) / i ver i ver = 10ma --22 ? table 30. er current generator ac specifications n symbol parameter con dition min typ max unit 1t on_ercap energy reserve capacitor charge-up time c ver ? 4.7mf nominal, bst33v = 0; design info --6s table 31. er switch dc specifications n symbol parameter condition min typ max unit 1r dson ersw power switch resistance i lim,ersw (min) 0.5 - 3 ? 2i lim,ersw er switch current limit - 400 - 600 ma 3t jsd_ersw thermal shutdown - 150 175 190 c 4t hys_tsdersw -51015c table 32. er switch ac specifications n symbol parameter condition min typ max unit 1t on_ersw er turn-on ti me (time to reach either r dson_ersw or i lim_ersw ) c vin = 10f - - 5 s 2t flt_tsd_ersw thermal shutdown filter time - - - 10 s 3t blk_ersw er switch activation blanking time after thermal shutdown --1-ms docid025869 rev 3 175/200 l9678, l9678-s electrical characteristics 199 15.11 covract all electrical characteristics are valid for the following conditions unless otherwise noted: -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35 v, vddx(min) ? vddx ? vddx(max), vddq = vdd5 or vdd3v3 15.12 vdd5 regulator all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35 v. table 33. covract dc specifications n symbol parameter con dition min typ max unit 1v oh_covract covract output voltage i load = -0.5 ma vddq -0.6 -vddqv 2v ol_covract i load = 2.0 ma 0 - 0.4 v table 34. covract ac specifications n symbol parameter con dition min typ max unit 1t rise_covract rise time 80pf load, 20%-80% - - 0.5 s 2t fall_covract fall time 80pf load, 20%-80% - - 0.5 s table 35. vdd5 regulator dc specifications n symbol parameter condition min typ max unit 1v o_vdd5 output voltage across all line and load, steady state 4.85 5 5.15 v 2i o_bvdd5 base driver current limit vdd5 > vdd5 uvl 4710ma 3i o_bvdd5_low base driver current limit low level vdd5 < vdd5 uvl 2-5ma 4i o_vdd5 output load current - 0.5 - 200 ma 5dv sr_ac line transient response all load i o_vdd5 ; vin=6v to 18v @ dt = 1 s; design info 4.5 - 5.5 v 6dv lr_ac load transient response all line; i o_vdd5 = 1ma to 100ma @dt = 1 s; design info 4.5 - 5.5 v 7i of_vdd5 open feedback current on vdd5 active only during vdd5_rampup state 55 80 105 a 8vdd5 ov over voltage detection - 5.2 - 5.50 v electrical characteristics l9678, l9678-s 176/200 docid025869 rev 3 9 vdd5 uv under voltage detection - 4.5 - 4.8 v 10 vdd5 uvl under voltage detection low level - 1.822.2v table 35. vdd5 regulator dc specifications n symbol parameter condition min typ max unit table 36. vdd5 regulato r ac specifications n symbol parameter condition min typ max unit 1t softst_vdd5 soft start time from 10% to 90% 1 2 3 ms 2t flt_vdd5ov over voltage detection deglitch filter time - 273033s 3t flt_vdd5uv under voltage detection deglitch filter time - 273033s 4t flt_vdd5uvl under voltage low detection deglitch filter time - 1.5 2 2.5 s table 37. vdd5 regulator external components (design info) n symbol parameter condition min typ max unit 1h fe_pnp output transistor gain - 50 250 500 a/a 2f t_pnp output transistor transit frequency -30--mhz 3r vdd5be output transistor base- emitter pull-up resistance --3-k ? 4c blk _ vdd5 output bulk capacitance min 4.7f nominal 3 - 30 f 5 esr cblk_vdd5 bulk capacitor esr - - - 50 m ? docid025869 rev 3 177/200 l9678, l9678-s electrical characteristics 199 15.13 vdd3v3 regulator all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vdd5(min) ? vdd5. table 38. vdd3v3 regulator dc specifications n symbol parameter con dition min typ max unit 1v o_vdd3v3 output voltage across all line and load, steady state 3.2 3.3 3.4 v 2i o_vdd3v3 output load current capability - 0.5 - 125 ma 3i o_lim_vdd3v3 output load current limit - 150 - - ma 6dv sr_ac line transient response all load io_vdd3v3; vin = 6 v to 18 v @ dt = 1 s; guaranteed by design 3-3.6v 7dv lr_ac load transient response all line; i o_vdd3v3 = 1ma to 100ma @dt = 1 s; guaranteed by design 3-3.6v 4 vdd3v3 ov over-voltage threshold - 3.43 - 3.6 v 5 vdd3v3 uv under voltage reset threshold -3-3.17v table 39. vdd3v3 regulat or ac specifications n symbol parameter condition min typ max unit 1t softst_vdd3 soft start time from 10% to 90% 1 2 3 ms 2t flt_vdd3ov over voltage detection deglitch filter time - 273033s 3t flt_vdd3uv under voltage detection deglitch filter time - 273033s table 40. vdd3v3 regulator external components (design info) n symbol parameter con dition min typ max unit 1c blk _ vdd3 output bulk capacitance min 4.7f nominal 3 - 30 f 2 esr cblk_vdd3 bulk capacitor esr - - - 50 m ? electrical characteristics l9678, l9678-s 178/200 docid025869 rev 3 15.14 vsup regulator all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good2 (max) ? vin ? 35 v. table 41. vsup regulator dc specifications n symbol parameter condition min typ max unit 1v o_vsup output voltage across all line and load, steady state 6.5 6.8 7.1 v 2i o_bvsup base driver current limit - 4 7 10 ma 3i o_vsup output load current - 0.5 200 ma 4dv sr_ac line transient response all load i o_vdd5 ; vin = 6 v to 18 v @ dt = 1 s; design info 6.2 7.4 v 5dv lr_ac load transient response all line; i o_vdd5 = 1ma to 100ma @dt = 1s; design info 6.2 7.4 v 6 vsup ov over voltage detection - 7.6 8 v 7 vsup uv under voltage detection - 1.8 2 2.2 v table 42. vsup ac specifications n symbol parameter condition min typ max unit 1t softst_vsup soft start time from 10% to 90% 1 2 3 ms 2t flt_vsupov over voltage deglitch filter time -273033s 3t flt_vsupuv under voltage deglitch filter time -273033s table 43. vsup regulator external components (design info) n symbol component conditions min typ max unit 1h fe_pnp output transistor gain - 50 250 500 a/a 2f t_pnp output transistor transit frequency -30--mhz 3r vsupbe output transistor base- emitter pull-up resistance --3-k ? 4c blk _ vsup output bulk capacitance min 4.7f nominal 3 - 30 f 5 esr cblk_vsup bulk capacitor esr - - - 50 m ? docid025869 rev 3 179/200 l9678, l9678-s electrical characteristics 199 15.15 vsf regulator all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c d ta d +95 c, vin good1 (max) d vin d 35 v, vsf + 2v d erboost ? vsf = 25v ? sys_cgf(vsf_v)= 0 table 44. vsf regulator dc specifications n symbol parameter con dition min typ max unit 1 vsf output voltage all line, load, i o_vsf up to 6 ma sys_cfg(vsf_v)= 0 18 20 22 v 2 all line, load, i o_vsf up to 6 ma bst33v = 1, sys_cfg(vsf_v)= 1 23 25 27 v 3i lim_vsf output load current limit test conditions: vsf = 0 7 10 13 ma 4v do_vsf drop-out voltage v(erboost-vsf) - - 2 v 5c vsf output capacitance design info. 2.9 - 14 nf 6i lkg_vsf_off vsf input leakage device off -5 5 a 7r pd_vsf vsf pull-down resistance device on vsf regulator off or on 1.5v docid025869 rev 3 181/200 l9678, l9678-s electrical characteristics 199 11 i lkg_sf_on sf leakage current device on, ? vresdiag = vssxy = 35 v, sfx = 0v-35 v -50 - 50 a 12 i lkg_sf_off device off, ? vresdiag = open, vssxy = open but all ssxy pins connected, sex = 0 v - 35 v -50 - 50 a 13 i lkg_sr_on sr leakage current device on, ? vresdiag = vssxy = 35 v, sfx = 0v-35 v - - 50 a 14 i lkg_sr_off device off, ? vresdiag = open, ? vssxy = open but all ssxy pins connected, sex = 0 v - 35 v - - 50 a 15 l depl load inductance maximum load inductance design information (2) 0 - 60 h 16 c sfx load capacitance maximum capacitance to gnd design information 13 - 455 nf 17 c srx 13 - 455 nf 18 c ssxy ssxy capacitance maximum capacitance to gnd connected directly to ssxy pin design information - - 10 nf 19 r sflx load impedance design information - - 6.5 ? 20 - wire length squib loops containing a clockspring shall be limited to a maximum length of 3m 1-10m 21 r wirex wire resistance design information 16.8 - 63.4 m ? /m 22 l wirex wire inductance design information 0.6 - 1.8 h/m 23 r csx clock spring resistance maximum number of clock springs is 3 for any ic design information 0-0.7 ? 24 l csx clock spring inductance design information 0 - 42.9 h 25 k l_cs1 ? l_cs2 clocks pring coupling design information 0.739 - 0.903 - 26 l emi squib emi protection design information 0 - 7.7 h 1. in case of an unsupplied device and shorted deployment pins (e.g. to battery voltage ), the dynamic reverse current through the high side power stage depends on cssxy. 2. ldepl could be calculated in the following way: ? - non-clockspring loops ? l depl(max ) = lwire(10m*2) + l emi = (3.6 h/m * 10m) + 7.7 h = 43.7 h - clockspring loops ? l depl(max) = l wire (3m*2) + l csx + l emi = (3.6h/m * 3m) + [42.9 h * (1 - 0.739)] + 7.7 h = 29.7 h - clockspring loops with short to ground ? l depl(max) = l wire (3m) + l csx + l emi = (1.8h/m * 3m) + 42.9h + 7.7h = 56 h. table 46. deployment drivers - dc specifications (continued) n symbol parameter con dition min typ max unit electrical characteristics l9678, l9678-s 182/200 docid025869 rev 3 figure 59. deployment drivers diagram ' ! 0 ' 0 3 % 3 $ % - ) 0 r o t e c t i o n 3 q u i b % - ) 0 r o t e c t i o n 3 q u i b , o a d 2 ? 3 q u i b , ? % - ) , ? # 3 2 ? # 3 , ? # 3 2 ? # 3 # l o c k 3 p r i n g ) m p e d a n c e 3 y s t e m 7 i r i n g ) m p e d a n c e 2 ? 7 i r e 7 i r e , e n g h t m k , ? # 3 8 , ? 7 i r e 2 ? 7 i r e , ? 7 i r e # ? 3 & x 3 & x 3 2 x # ? 3 2 x table 47. deployment drivers - ac specifications n symbol parameter condition min typ max unit 1t depl_lo deployment time 1.209 a rising to 1.209 a falling 2 - 2.268 ms 2 t depl_hi 1.764 a rising to 1.764 a falling 0.7 - 0.832 ms 3 0.5 - 0.613 ms 4t dep_res deployment current counter resolution -0-16s 5t rise_idepl rise time 10% - 90% of i depl ssxy = 25 v; r sq = 2.2 ? , ? c = 22 nf, l = 44 h --32s 6t del_idep delay time spi_cs to 90% i depl --65s 7t fall_idepl fall time 90% - 10% i depl --32s 8t del_sd-ls low-side shutdown delay time (with respect to high-side deactivation) -50--s 9t flt_lim_ls low-side overcurrent to low-side deactivation deglitch time in short to battery condition - 80 100 120 s 10 t off_os_hs low-side overcurrent to high-side deactivation deglit ch time in case of intermittent open squib condition ---20s 11 t off_os_hs high-side off time in case of intermittent open squib condition -4-12s docid025869 rev 3 183/200 l9678, l9678-s electrical characteristics 199 15.17 squib diagnostic 15.17.1 squib resistance measurement all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35 v, 6 v ? ssxy ? 35 v; 7v ? vresdiag ? 35v. table 48. deployment drivers diagnostics (squib resistance) n symbol parameter condition min typ max unit 1r sq_range_1 squib resistance range 1 lpdiagreq(isrc_curr_sel)= 0 0 - 10 ? 2r sq_range_2 squib resistance range 2 lpdiagreq(isrc_curr_sel)= 1 0 - 50 ? 3g rsq squib resistance measurement differential amplifier gain - -2% 5.2 +2% v/v 4v off_rsq squib resistance measurement differential amplifier output offset v out_rsq = g rsq x (v sf ? v sr ) + v off_rsq 200 - 400 mv 5 i src_hi_sf i src_hi_sr squib resistance measurement high current source r sq_range = 1 ? ? to 10 ? lpdiagreq(isrc_curr_sel) = 0 lpdiagreq(isrc) = "01" or "10" -5% 40 +5% ma 6 i src_lo_sf i src_lo_sr squib resistance measurement low current source r sq_range = 1 ? ? to 50 ? lpdiagreq(isrc_curr_sel) = 1 lpdiagreq(isrc) = "01" or "10" -10% 8 +10% ma 7i src_delta squib resistance measurement delta current source --5%32+5%ma 8sr isrc squib resistance measurement current source slew- rate -47.511ma/s 9v srx_rm srx voltage during resistance measurement lpdiagreq(isrc) = ?01? or ?10? ? lpdiagreq(isink) = 1 0.5 0.7 1 v 10 i sink_hi_sr srx current sink limit high level lpdiagreq(isrc_curr_sel) = 0 lpdiagreq(isink) = 1 50 70 90 ma 11 i sink_lo_sr srx current sink limit low level lpdiagreq(isrc_curr_sel) = 1 lpdiagreq(isink) = 1 10 17.5 25 ma 12 i pd_sr srx current pull down - 0.7 1 1.3 ma 13 r lkg_sf leakage resistance on sfx leakage to gnd 1 v or to battery from 6 v to 18 v. design info 1- - k ? electrical characteristics l9678, l9678-s 184/200 docid025869 rev 3 15.17.2 squib leakage test (vrcm) all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35 v, ? vdd3v3(min) ? vdd3v3 ? vdd3v3(max). 14 r sq_acc accuracy of digital resistance measurement after software calculation all errors included rsq between 1.0 ? and 10.0 ? ? with high current source (40ma) -8 - +8 % 15 - emi input low-pass filter design info 50 - 100 khz table 48. deployment drivers diagnos tics (squib resistance) (continued) n symbol parameter condition min typ max unit table 49. squib leakage test (vrcm) n symbol parameter condition min typ max unit 1 v out_vrcm output voltage on sf or sr pins during leakage test i out = 0 ma -10% 2.5 +10% v 2i out = 6.6 ma -8.7% 2.3 +8.7% v 3r lkg_gsq_th detection threshold, leakage to gnd leakage detected if r lkg_gsq ? 1 k ? and not detected if r lkg_gsq ? 10 k ? design info 1-10k ? 4i lkg_gsq_th equivalent to resistance range -15% 450 +15% a 5r lkg_bsq_th detection threshold, leakage to battery leakage detected if lkg_bsq ? 1 k ? and not detected if r lkg_bsq ? 10 k ? ? design info 1-10k ? 6i lkg_bsq_th equivalent to resistance range -15% 1.8 +15% ma 7i lim_vrcm_src vrcm current limitation - -20 - -10 ma 8i lim_vrcm_sink -10-20ma 9v shift external ground or battery shift design info -1 - 1 v 10 r sq_low_th detection threshold for ?resistance too low? design info 200 - 500 ? 11 i rsq_low_th equivalent to resistance range -12% 6 +12% ma 12 r sq_high_th detection threshold for ?resistance too high? design info 2 - 5 k ? 13 i rsq_high_th equivalent to resistance range -15% 700 +15% a 14 t flt_lkg leakage test deglitch filter time -8s docid025869 rev 3 185/200 l9678, l9678-s electrical characteristics 199 15.17.3 high/low side fet test all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35 v, 6 v ? ssxy ? 35 v, 7v ? vresdiag ? 35v. 15.17.4 deployment timer test all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35 v table 50. high/low side fet test n symbol parameter condition min typ max unit 1i hs_fet_th detection threshold (hs fet test) - -10% 1.8 +10% ma 2i ls_fet_th detection threshold low side fet test - -10% 450 +10% a 3e fet_test energy transferred to squib during hs/ls fet tests design info - - 170 j 4 t flt_hs_fet_th t flt_ls_fet_th fet test deglitch filter time -1.31.51.7s 5 t fettimeout hs/ls fet test time-out - 190 200 210 s 6sgxy _open squib open ground detection gndsubx as ground reference 300 450 600 mv 7t flt_sgopen squib open ground detection filter time -465054s table 51. deployment timer test no symbol parameter comments / conditions min typ max unit 1t pulse _ idle deployment timer pulse test idle time sysdiagreq(dstest)=pulse 7 8 9 ms 2i pulse_high_00 deployment timer pulse test high time sysdiagreq(dstest)=pulse dcr_x(deploy_time) = 00 -5% 8 +5% s 3i pulse_high_01 sysdiagreq(dstest)=pulse dcr_x(deploy_time) = 01 -5% 584 +5% s 4i pulse_high_10 sysdiagreq(dstest)=pulse dcr_x(deploy_time) = 10 -5% 792 +5% s 5i pulse_high_11 sysdiagreq(dstest)=pulse dcr_x(deploy_time) = 11 -5% 2160 +5% s electrical characteristics l9678, l9678-s 186/200 docid025869 rev 3 15.18 remote sensor interface all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good2 (max) ? vin ? 35v, vsup(min) ? vsup ? vsup(max). table 52. remote sensor i/f dc parameters n symbol parameter condition min typ max unit 1i s_low interface quiescent current (low signal current level) according to psi-5 v1.3, section 5.1.2 - parameter #4 design info -19 - -4 ma 2 ? is delta signal current i s_high - i s_low according to psi-5 v1.3, section 5.4 - parameter #6 design info 22 - 30 ma 3v lim_rsu output voltage limitation vsup = vin according to psi-5 v1.3, section 5.1.1 - parameter #1 --11v 4r dson_rsu rsu power switch resistance (v vsup ? v rsu ) / i rsu i rsux = 4-50 ma according to psi-5 v1.3, section 6.2 - parameter #3 --12.5 ? 5v stb_rsu output short to battery threshold - 10 50 100 mv 6i stb_rsu static reverse current into rsu pin v rsu > v vsup + v stb_rsu --5ma 7i oc_rsu over current detection threshold interface disabled after t flt_std_rsu according to psi-5 v1.3, section 5.1.2 - parameter #8-9 -105 - -50 ma 8i lim_rsu current limitation rsu = 0 according to psi-5 v1.3, section 5.1.2, parameter #8-9 -105 - -65 ma 9 i lim_oc_rsu difference between current limitation and oc threshold i lim_rsu - i oc_rsu 0.1 - - ma 10 i b0_rsu internal base current starting value default value of internal 7 bit counter -18 -15 -13 ma 11 i s _ th_rsu trigger point for signal current threshold i rsu = i low_rsu = -19ma to ? -4ma i b_rsu + (12-11%) i b_rsu + 12 i b_rsu + (12+11%) ma 12 i lkgg_rsu trigger point for fault current detection leakage to gnd; detected by i b -48 - -36 ma 13 i lkgb_rsu leakage to battery; detected by i b -3.5 - -1.5 ma 14 i ol_rsu output open load detection threshold rsu open i lkgb(min) -i lkgb(max) - docid025869 rev 3 187/200 l9678, l9678-s electrical characteristics 199 15 dac res dac resolution design info - 7 - bit 16 i lsb lsb current - 270 - 330 a 17 c rsu emc capacitor 22nf nominal design info 13 - - nf 18 t jsd_erbst thermal shutdown - 150 175 190 c 19 t hys_tsderbst -51015c table 52. remote sensor i/f dc parameters (continued) n symbol parameter condition min typ max unit table 53. psi-5 remote sensor transceiver - ac specifications n symbol parameter condition min typ max unit 1 t flt_std_rsu over current shutdown filter time normal operation 500 - 600 s t blk_oc_rsu over current shutdown filter time at interface power on (blktxsel = 0) according to psi-5 v1.3, section 5.2 - parameter #1 4.6 - 5.4 ms 2 3 at interface power on (blktxsel = 1) according to psi-5 v1.3, section 5.2 - parameter #2 9.4 - 10.8 ms 4 t stb_rsu short to battery comparator response time guaranteed by design - - 200 ns 5 t stb_rec_rsu short to battery recovery time - 12 - 16 s 6 t flt_tsd_rsu thermal shutdown filter time --10 s 7 t flt_open_rsu open detection deglitch filter time - 10 - 15 s 8 t flt_lkg_rsu leakage deglitch filter time - 10 - 15 s electrical characteristics l9678, l9678-s 188/200 docid025869 rev 3 15.19 dc sensor interface all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good2 (max) ? vin ? 35v, 8.5 v ? vresdiag ? 35 v. table 54. dc sensor inte rface specifications n symbol parameter condition min typ max unit 1v out_dcsreg output voltage regulation mode dcs regulator enabled -10% 6.25 +10% v 2i lim_dcsreg current limitation regulation mode dcs regulator enabled dcs = 0 24 27 30 ma 3v dcs_range1 voltage measurement range1 first voltage measurement (v dcs_meas1 ) to compensate external ground shift and internal offset -1 - 1.4 v 4v dcs_acc1 voltage measurement accuracy 1 v dcs = v dcs_range1 included adc error -15 - 15 % 5v dcs_range2 voltage measurement range 2 -1.5-10v 6v dcs_acc2 voltage measurement accuracy 2 v dcs = v dcs_range2 included adc error -8 - +8 % 7i dcs_range1 current measurement range 1 -1-2ma 8i dcs_acc1 current measurement accuracy 1 i dcs = i dcs_range1 included adc error -30 - +30 % 9i dcs_range2 current measurement range 2 -2-22ma 10 i dcs_acc2 current measurement accuracy 2 i dcs = i dcs_range2 included adc error -12 - +12 % 11 i dcs_range3 current measurement range 3 regulator in current limitation -i lim_dcsreg -ma 12 i dcs_acc3 current measurement accuracy 3 dcs = 0 included adc error -12 - +12 % 13 r dcs_range resistance measurement range design info 65 - 3000 ? 14 r dcs_acc accuracy of digital resistance measurement performing both voltage measurements 1 and 2 after software calculation all errors included -15 15 % docid025869 rev 3 189/200 l9678, l9678-s electrical characteristics 199 15.20 safing engine all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35v, vddx(min) ? vddx ? vddx(max), vddq = vdd5 or vdd3v3. 15 i pd_dcs pull down current v dcs = 1.5v 70 100 130 a 16 r pd_dcs pull down resistance device on, dcs pull down current disabled 90 150 210 k ? 17 i tot_pd_dcs total pull down current i tot_pd_dcs = i pd_dcs + r pd_dcs v dcs = 6.5v 100 140 200 a 18 c dcs output capacitance design info 10 - nf 19 i ref_idcs internal current reference for dcs current measurement - -5% 300 +5% a 20 ratio_vdcs divider ratio for dcs voltage measurement - -3% 7.125 +3% v/v 21 v off_dcs internal offset during voltage measurement -- 4% 0.375 +4% v table 54. dc sensor interface specifications (continued) n symbol parameter condition min typ max unit table 55. arming interface - dc specifications n symbol parameter condition min typ max unit 1v th_h_acl acl input voltage thresholds - 2.33 - 2.42 v 2v th_l_acl - 1.58 - 1.67 v 3v hys_acl acl hysteresis - 0.6 0.75 0.9 v 4r pd_acl acl pull down resistance v acl = 3.3v 120 200 280 k ? 5v oh_arm arm output high voltage i load = -0.5 ma internal safing selected vddq -0.60 -vddqv 6v ol_arm arm output low voltage i load = 2.0 ma internal safing selected 0-0.4v 7r pd_arm arm pull down resistance - 65 100 135 k ? 14 v ih_ fenh fenh high level input voltage -2--v 15 v il_ fenh fenh low level input voltage ---0.8- 16 i pu_ fenh fenh pull down current fenh = vddq 20 45 70 a 14 v ih_ fenl fenl high level input voltage -2--v electrical characteristics l9678, l9678-s 190/200 docid025869 rev 3 15 v il_ fenl fenl low level input voltage ---0.8 16 i pu_ fenl fenl pull up current fenl = 0 -70 -45 -20 a 14 v ih_saf_csx saf_csx high level input voltage -2--v 15 v il_saf_csx saf_csx low level input voltage ---0.8- 16 i pu_saf_csx saf_csx pull up current saf_csx = 0v -70 -45 -20 a table 55. arming interface - dc specifications n symbol parameter condition min typ max unit table 56. arming interface - ac specifications n symbol parameter condition min typ max unit 1t arm sensor sampling period - 475 500 525 s 2t acl_hi acl period - 213 - 237 ms 3t acl_lo - 168 - 187 ms 4t on_acl_hi acl on-time - 154 - 171 ms 5t on_acl_lo -114-126ms 6t valid_eol scrap validation ? t acl and t on_acl valid - 3 - - cycles 7t dis_eol scrap timeout - 2 * t acl ms 8 t pulse_strech arming enable pulse stretch time ---0ms 9 - 30 32 34 ms 10 - 242 270 ms 11 - 1934 2162 ms 12 t rise_arm arm rise time 80pf load, 20% to 80% internal safing selected - - 1.00 s 13 t fall_arm arm fall time 80pf load, 20% to 80% internal safing selected - - 1.00 s docid025869 rev 3 191/200 l9678, l9678-s electrical characteristics 199 15.21 general purpose output drivers all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good1 (max) ? vin ? 35v; gpodx + 5v ? erboost. table 57. gpo interface dc specifications n symbol parameter con dition min typ max unit 1v sat_gpo output saturation voltage v gpod ? v gpos i load = 70 ma --0.5v 2i lim_gpo current limitation v gpod ? v gpos = 1.5 v 73 110 155 ma 3i oc_gpo over current detection threshold - 73 110 155 ma 4 i lim_oc_gpo difference between current limitation and oc threshold i lim_gpo - i oc_gpo 0.1 - - ma 5i ol_gpo open load current threshold gpo on condition; ls and hs configuration 0.1 1 3 ma 6i diag_gpo diagnostic current on load voltage measurement in progress through analog mux ? increased leakage for a short specified time (32 s) --130a 7i lkg_gpod_off gpod output leakage current v gpod = 18v v gpos = 0v power-off or sleep mode -5 - 5 a 8i lkg_gpod_on v gpod = 18v v gpos = 0v active or passive mode driver off --100a 9i lkg_gpos_off gpos output leakage current v gpod = 18v v gpos = 0v power-off or sleep mode or erboost = erboost_ok driver off -5 - 5 a 10 i lkg_gpos_on v gpod = 18v v gpos = 0v (active or passive mode) and erboost = erboost_ok driver off --100a 11 i rev_gpo reverse current v gpos = v gpod + 1v driver off -1ma 12 t jsd_gpo thermal shutdown - 150 175 190 c 13 t hys_tsd_gpo - 5 10 15 c 14 c gpo load capacitor min 10nf nominal design info 6- -nf electrical characteristics l9678, l9678-s 192/200 docid025869 rev 3 table 58. gpo driver interf ace - ac specifications n symbol parameter condition min typ max unit 1sr gpo output voltage slew rate 30% - 70%; r load = 273 ? , c load = 100nf 0.1 0.25 0.4 v/s 2t flt_oc_gpo over current detection filter time - 101214s 3t flt_ol_gpo open load detection filter time - 8 10 12 s 4t mask_on_gpo diagnostic mask delay after switch on c gpo = 100nf typ 40 50 60 s 5t flt_tsd thermal shutdown filter time ---10s 6f pwm_gpo pwm frequency - - 125 - hz 7dc pwm_gpo pwm duty cycle increment step = 1.6% 0 - 100 % docid025869 rev 3 193/200 l9678, l9678-s electrical characteristics 199 15.22 iso9141 in terface (k-line) all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good (max) ? vin ? 35v. table 59. iso9141 interface dc specifications n symbol parameter condition min typ max unit 1v ih_isotx isotx high level input voltage -2--v 2v il_isotx isotx low level input voltage ---0.8v 3v hys_isotx isotx hysteresis input voltage - 150 - 500 mv 4i pu_isotx isotx pull up current isotx = 0 -70 -45 -20 a 5c in_isotx isotx input capacitance design info - - 5 pf 6v th_dom_isok isok input receiver threshold isotx = 0v vin * 0.4 vin * 0.45 vin * 0.5 v 7v th_rec_isok isotx = vddq vin * 0.5 vin * 0.55 vin * 0.6 v 8v hys_isok - v in * 0.07 vin * 0.1 vin * 0.13 v 9v o_dom_isok isok output voltage isotx = 0v, i isok = 40ma --1.2v 10 i oc_isok isok over current detection - 50 - 100 ma 11 i lim_isok isok current limitation - 50 - 100 ma 12 i lim_oc_isok difference between current limitation and oc threshold i lim_isok - i oc_isok 0.1 - - ma 13 i sink_isok isok sink current capability design info 40 - - ma 14 i lkg_isok isok input leakage current vin < 18v, driver off (device is supplied) -10 - 10 a 15 v oh_isorx isorx output high voltage i load = -0.5 ma vdd q -0.60 - vdd q v 16 v ol_isorx isorx output low voltage i load = 2 ma 0 - 0.4 v 17 c in isok input capacitance design info - - 10 pf 18 t jsd_isok thermal shutdown - 150 175 190 c 19 t hys_tsd_isok -51015c electrical characteristics l9678, l9678-s 194/200 docid025869 rev 3 table 60. iso9141 interface transceiver ac specifications n symbol parameter condition min typ max unit 1t flt_tsd thermal shutdown filter time ---10s 2t blk_isok current limit fault blanking time -8-12s 3t rise_isorx isorx rise time 80pf load, 20%-80% - - 0.5 s 4t fall_isorx isorx fall time 80pf load, 20%-80% - - 0.5 s 5 - baud rate design info - 62.5 - kbd 6t pd_iltx propagation delay transmitter isotx high to low to isok = 70% * v o_rec_isok r isok =510 ? , c isok =470pf --1s 7t pd_ihtx isotx low to high to isok = 30% * v o_dom_isok r isok =510 ? , c isok =470pf --1.5s 8t pd_ilrx propagation delay receiver isok = v th_dom_isok to isorx high to low r isok =510 ? , c isok =470pf --1.5s 9t pd_ihrx isok = v th_rec_isok to isorx low to high r isok =510 ? , c isok =470pf --1.5s 10 t rise_isok isok rise time 30% to 70% risok=510 ? , cisok=470pf --1.5s 11 t fall_isok isok fall time 70% to 30% risok=510 ? , cisok=470pf --1.5s 12 t pdw_rx receiver pulse width symmetry t pd_ilrx - t pd_ihrx --1s 13 t pdw_tx transmitter pulse width symmetry (t pd_iltx + t fall_isok ) ? (t pd_ihtx + t rise_isok ) --1s docid025869 rev 3 195/200 l9678, l9678-s electrical characteristics 199 15.22.1 analog to digital converter all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good (max) ? vin ? 35v. table 61. analog to digital converter n symbol parameter condition min typ max unit 1v adc_range adc input voltage range - 0.1 - 2.5 v 2v adc_ref adc reference voltage - -1.5% 2.5 +1.5% v 3 adc_res adc resolution (1) design info - 10 - bit 4 dnl differential non linearity error (dnl) separation between adjacent levels, measured bit to bit of actual and an ideal output step. no missing codes -1 - +1 lsb 5inl integral non linearity error (inl) maximum difference between the actual analog value at the transition between 2 adjacent steps and its ideal value -3 - +3 lsb 6e quant quantization error design info -0.5 - 0.5 lsb 7 toterr total error includes inl, dnl, adc reference voltage tolerance and quantization error -15 - +15 lsb 8 toterr_0v1 adc total error for 0.1v input voltage --5-+5lsb 9 toterr_2v4 adc total error for 2.4v input voltage - -15 - +15 lsb 10 - pre-adc settling time - - 4.81 - s 11 - single conversion time - - 2.25 - s 12 - intra-queue settling time - - 3.5 - s 13 - post- adc settling time - - 3.44 - s 14 - adc conversion time - voltage 4x sampling for each of the 4 conversions in the queue design info - 54.75 - s 15 - adc conversion time ? current and voltage 8x sampling for dcs, temperature and squib loop resistance measurements + 4x sampling for remaining 2 conversions in the queue design info - 51.25 - s 1. lsb = (2.5 v / 1024) = 2.44 mv electrical characteristics l9678, l9678-s 196/200 docid025869 rev 3 15.23 voltage diagnostics (analog mux) all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good (max) ? vin ? 35v. 15.24 temperature sensor all electrical characteristics are valid for the following conditions unless otherwise noted. -40 c ? ta ? +95 c, vin good (max) ? vin ? 35v. table 62. voltage diagnostics (analog mux) dc specifications n symbol parameter condition min typ max units 1 ratio_1 divider ratios v in_range1 = 0.1v ? 2.5v - 1 - v/v 2 ratio_4 v input_range2 = 1v ? 10v ? (where applicable) -3% 4 +3% v/v 3 ratio_7 v input_range_3 = 1.5v ? 17.5v ? (where applicable) -3% 7 +3% v/v 4ratio_10 v input_range_4 = 2v ? 25v ? (where applicable) -3% 10 +3% v/v 5ratio_15 v input_range_5 = 3v ? 35v ? (where applicable) -3% 15 +3% v/v 6v offset_ratio_x divider offset high impedance -10 - 10 mv 7r ratio_4 multiplexer input resistance multiplexer input to gnda 80 - - k ? 8r ratio_7 multiplexer input to gnda 120 - - k ? 9r ratio_10 multiplexer input to gnda 160 - - k ? 10 r ratio_15 multiplexer input to gnda 200 - - k ? 11 i leak_ratio_x additional multiplexer on-state input leakage current for all divider ratio expect ratio_1 - - 60 a 12 v meas_acc voltage measurement accuracy all range all errors included -12 - +12 % table 63. temperature sensor specifications n symbol parameter condition min typ max units 1t mon_range monitoring temperature range - -40 - 150 c 2t mon_acc monitoring temperature accuracy --15-15c docid025869 rev 3 197/200 l9678, l9678-s quality information 199 16 quality information 16.1 otp trim bits the device has 43 fuse programmable bits which are used to tune and refine performance characteristics of the device and also provide detailed identification of each component. these bits are only available during producti on testing and require activation of a special test mode. these bit values are confirmed ev ery transition from por, and reported in section 5.1.1: fault status register (fltsr) if an error is found. the otp crc is implemented using the po lynomial calculatio n (g(x)=1+x+x^3 with initialization value equal to "111"). equivalent equations are: crc[2] = c0in + c1in + c2in + d1 + d11 + d12 + d13 + d15 + d18 + d19 + d20 + d22 + d25 + d26 + d27 + d29 + d32 + d33 + d34 + d36 + d39 + d4 + d40 + d41 + d5 + d6 + d8 crc[1] = c0in + c1in + d0 + d12 + d13 + d14 + d16 + d19 + d2 + d20 + d21 + d23 + d26 + d27 + d28 + d30 + d33 + d34 + d35 + d37 + d40 + d41 + d42 + d5 + d6 + d7 + d9 crc[0] = c1in + c2in + d0 + d10 + d11 + d12 + d14 + d17 + d18 + d19 + d21 + d24 + d25 + d26 + d28 + d3 + d31 + d32 + d33 + d35 + d38 + d39 + d4 + d40 + d42 + d5 + d7 where d[42:0] are the 43 otp bits and cxin are the starting seed values (all '1'). package information l9678, l9678-s 198/200 docid025869 rev 3 17 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 60. lqfp64 (10 x 10) mechanical data and package dimensions ' ! 0 ' 0 3 / 5 4 , ) . % ! . $ - % # ( ! . ) # ! , $ ! 4 ! ! ! ! " # % $ % % $ $ e + " 4 1 & 0 , , 3 e a t i n g 0 l a n e m m $ ) - m m i n c h - ) . 4 9 0 - ! 8 - ) . 4 9 0 - ! 8 ! ! ! " # $ $ $ e % % % , , + ? p l q ? p l q ? p d [ c c c , 1 & 0 x x m m ' c c c docid025869 rev 3 199/200 l9678, l9678-s revision history 199 18 revision history table 64. document revision history date revision changes 10-feb-2014 1 initial release. 19-feb-2014 2 updated features and table 1: device summary on page 1 . 22-may-2014 3 updated: figure 25: deployment loop diagnostics on page 116 and section 15.17.1: squib resi stance measurement on page 183 (conditions). l9678, l9678-s 200/200 docid025869 rev 3 ? please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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