integrated circuit systems, inc. general description features ics1886 block diagram phyceiver is a trademark of integrated circuit systems, inc. fddi / fast ethernet phyceiver tm ics1886revc120996 ? data and clock recovery for: 32.064 mb/s (japan) 34.368 mb/s (europe - e3) 125 mhz (ethernet) 139.264 mb/s (europe - e4) ? clock multiplication from either a crystal, differential or single-ended timing source ? continuous clock in the absence of data ? no external pll components ? lock/loss status indicator output ? loopback mode for system diagnostics ? selectable loop timing mode ? pecl drivers with settable sink current the ics1886 is designed to provide high performance clock recovery and generation for either 32.064 mb/s, 34.368 mb/s, 125 mb/s or 139.264 mb/s nrz or nrzi serial data streams. the ics1886 is ideally suited for lan transceiver applications in either european or japanese communication environments. the ics1886 also operates at the 100mbit ethernet frequency of 125 mhz. this is ideal for serial ethernet data applications where no serial to parallel conversion is required. clock and data recovery is performed on an input serial data stream or the buffered transmit data depending upon the state of the loopback input. a continuous clock source will continue to be present even in the absence of input data. all internal timing is derived from either a low cost crystal or an external clock module. the ics1886 utilizes advanced cmos phase-locked loop technology which combines high performance and low power at a greatly reduced cost. pin configuration 28-pin soic
2 ics1886 pin descriptions * active low input. cs1 cs0 loop input clock freq mode ref freq or crystal vss vss vss tx data 32.064 mhz japan 4.008 mhz vss vdd vss tx data 34.368 mhz europe - e3 4.296 mhz vdd vss vss tx data 125.000 mhz ethernet 25.000 mhz vdd vdd vss tx data 139.264 mhz europe - e4 17.408 mhz vss vss vdd rx data 32.064 mhz japan 4.008 mhz vss vdd vdd rx data 34.368 mhz europe - e3 4.296 mhz vdd vss vdd rx data 125.000mhz ehternet 25.000 mhz vdd vdd vdd rx data 139.264 mhz europe - e4 17.408 mhz table 1 - device clock selection pin number pin name type description 1 vss negative supply voltage. 2 lt~ loop timing mode select.* 3 cd~ carrier detect input.* 4 tx+ positive transmit serial data output. 5 tx- negative transmit serial data output. 6 vss negative supply voltage. 7 iprg1 pecl output stage current set (tx). 8 rx- negative receive serial data input. 9 rx+ positive receive serial data input. 10 lb~ loop back mode select.* 11 lock lock detect output. 12 cs1 clock select 1 input. 13 cs0 clock select 0 input. 14 vss negative supply voltage. 15 iprg2 pecl output stage current set (tc, rc and rd). 16 vss negative supply voltage. 17 rd+ positive recovered data output 18 rd- negative recovered data output. 19 rc+ positive recovered clock output. 20 rc- negative recovered clock output. 21 vdd positive supply voltage. 22 ref+ positive reference clock/crystal input. 23 ref- negative reference clock/crystal input. 24 vdd positive supply voltage. 25 tc- negative transmit clock output. 26 tc+ positive transmit clock output. 27 td- negative transmit data input. 28 td+ positive transmit data input.
3 ics1886 absolute maximum ratings v dd (measured to v ss ) . . . . . . . . . . . . . . . . . . 7.0 v ambient operating temperature . . . . . . . . . . . ? 55c to + 125c storage t emperature . . . . . . . . . . . . . . . . . . . . ? 65c to + 15 0 c junction temperature . . . . . . . . . . . . . . . . . . . 175c soldering temperature . . . . . . . . . . . . . . . . . . 260c recommended operating conditions stresses above those listed under absolute maximum ratings above may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operationa l sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. ics1886 fddi / fast ethernet application parameter symbol test conditions min max units ambient operating temp. t a 0+70 oc using a negitive supply v ss v dd -4.50 0.0 -5.50 0.0 v v using a positive supply v ss v dd 0.0 +4.50 0.0 +5.50 v v
4 ics1886 v dd = v min to v max , v ss = 0v, t a = t min to t max note: ref_in input switch point is 50% of vdd. dc characteristics parameter symbol conditions min max units supply current i ss v dd = +5.0v, v ss = 0.0v 50ma ecl input/output parameter symbol conditions min max units ecl input high voltage v ih v dd -1.16 v dd -0.88 v ecl input low voltage v il v dd -1.81 v dd -1.47 v ecl differential threshold voltage range v th 150 mv ecl input common mode voltage v cm 1.3 v dd -.4 v ecl output high voltage v oh v dd -1.02 v ecl output low voltage v ol v dd -1.62 v ttl input/output parameter symbol conditions min max units ttl input high voltage v ih vdd = 5.0v, vss = 0.0v 2.0 v ttl input low voltage v il vdd = 5.0v, vss = 0.0v 0.8 v ttl output high voltage v oh vdd = 5.0v, vss = 0.0v 2.7 v ttl output low voltage v ol vdd = 5.0v, vss = 0.0v 0.5 v ttl driving cmos output high voltage v oh vdd = 5.0v, vss = 0.0v 3.68 v ttl driving cmos output low voltage v ol vdd = 5.0v, vss = 0.0v 0.4 v ttl / cmos output sink current i ol vdd = 5.0v, vss = 0.0v 8 ma ttl / cmos output source current i oh vdd = 5.0v, vss = 0.0v -0.4 ma ref_in input parameter symbol conditions min max units input high voltage v ih vdd = 5.0v, vss = 0.0v 3.5 v input low voltage v il vdd = 5.0v, vss = 0.0v 1.5 v
5 ics1886 v dd = v min to v max , v ss = 0v, t a = t min to t max ac characteristics parameter symbol conditions min max units ecl outputs rise/fall time t r , t f 15pf load 1.4 1.7 ns recovered clock duty cycle t dc 15pf load 45 55 % output data setup t sv w.r.t. rc at 139.264mhz 2.2 3.3 ns output data hold t hd w.r.t. rc at 139.264mhz 3.9 4.5 ns transmit latency tl 139.264mhz 6 9 ns recieve latency rl 139.264mhz 1clock+15 1clock+20 ns phase-locked loop characteristics lock acquisition t acq 139.264mhz 5s capture range 139.264mhz 5 % of center freq. receive jitter tolerance t jt 139.264mhz .15% uip-p transmit clock stability 139.264mhz 17.408mhz crystal 6 ppm
6 ics1886 input pin descriptions transmit data input (td+ and td-) for normal operation this differential input is transferred to the tx output through a pecl buffer. in loopback testing mode, this input is multiplexed to the input of the device clock recovery section. receive data input (rx+ and rx-) the clock recovery and data regenerator from the receive buffer are driven from this pecl input. during loopback testing mode this input is ignored. clock select (cs0 and cs1) selects the operating frequency according to table 1. internal pull-up resistors set both inputs high when left unconnected. carrier detect (cd~) active low input which forces the vco to free run. upon receipt of a loss of input signal (such as from an optical-to-elec-trical transducer), the internal phase-lock loop will free-run at the selected operating frequency. also, when asserted, cd will set the lock output low. loop timing mode (lt~) active low input which routes the recovered receive clock to the tc outputs as well as the rc outputs. forces the transmit clock to be ?loop- timed? to the system clock derived from the incoming data. loopback mode (lb~) active low input which causes the clock recovery pll to operate using the transmit td input data and ignore the receive rx data. utilized for system loopback testing. external crystal or reference clock (ref+ and ref-) this oscillator input can be driven from either a fundamental mode crystal or a stable reference. for either method, the reference frequency is 1 8 the operating frequency. see t able 1 for more information. output pin descriptions transmit data differential ecl (tx+ and tx-) this differential output is buffered td data. this output remains active during loopback mode. transmit clock differential ecl (tc+ and tc-) differential output clock used by the pdh/atm processor for clocking out transmit data. this clock can be derived from either an independent clock source or from the recovered data clock (system loop time mode). receive data differential ecl (rd+ and rd-) the regenerated differential data derived from the serial data input. in loopback mode this data is regenerated from the transmit data input (td ). this data is phase-aligned with the negative edge of the rc clock output. receive clock differential ecl (rc+ and rc-) the differential clock recovered with the internal clock recov- ery pll. in loopback mode this clock is recovered from the transmit data (td ) input. this clock is phase-aligned with the rd data output. lock/loss detect (lock) set high when the clock recovery pll has locked onto the incoming data. set low when there is no incoming data, which in turn causes the pll to free-run. this signal can be used to indicate or ?alarm? the next receive stage that the incoming serial data has stopped. output description the differential output drivers are current mode and are de- signed to drive resistive terminations in a complementary fash-ion. the outputs are current-sinking only, with the amount of sink current programmable via the iprgx pins. the sink current is equal to four times the iprgx current. for most applications, a resistor from vdd to iprgx will set the current to the necessary precision. iprg1 supplies the current mirror for the tx output. iprg2 supplies the current mirrors for the rd , rc and tc outputs. the differential pecl output pins are incapble of sourcing current, so v oh must be set by the ratios of the termination resistors for each of these lines. r1 is a pull-up resistor con-nected from the pecl output to vss. r1 and r2 are electrically in parallel from an ac stand point. if we pick a target imped-ance of 50 w for our transmission line impedance, a value of 62 w for r1 and a value of 300 w for r2 would yield a thevenin equivalent characteristic impedance of 50 w and a v oh value of v dd -.88 volts, compatible with pecl circuits. to set a value for v ol , we must determine a value for iprg that will cause the output fet?s to sink an appropriate current. we desire v ol to be v dd -1.81 or greater. setting up a sink current of 19 milliamperes would guarantee this through out output terminating resistors. as this is controlled by a 4/1 current mirror, 4.75ma into iprg should set this current properly. an 910 w resistor from v dd to iprg should work fine.
7 ics1886 ics1886 pecl termination for 50w transmission lines
8 ics1886 the current ics1886 device provides a single ttl-compatible input, carrier detect (cd~). when carrier detect is asserted, the ics1886 locks to the incoming receive data. when carrier detect is deasserted, or if carrier detect is asserted and no data is present on the receive inputs, the pll will free run and continue to provide rxclk at the nominal 25 mhz frequency. this provides a continuous receive clock source, even if cd~ is always tied to ground. if a true signal detect is required by a chip that connects to the ics1886 , a simple, low cost pecl to cmos converter can be used. the following circuits implement this function: these circuits provide pecl to cmos conversion for less than $0.80 in single unit quantities. note that the lm393 has two amplifiers, so the unused one is tied inactive. a running production change will be made to the ics1886 to change the cd~ input to pecl. therefore, boards should be layed out with a direct normal pecl termination connection stuffing option. this allows either version of the part to be used by stuffing one of two sets of external components. a version of this circuit is shown in the diagram above. option 2 single-ended pecl to cmos conversion circuit option 1 differential pecl to cmos conversion circuit cd pecl input: board layout options
9 ics1886
10 ics1886 ordering information ics1886m soic package ics xxxx m package type m = soic device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: lead count 2 8l dimension l 0.704
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