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nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 1 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. 184pin two bank unbuffered ddr sdram module features ? 184 - pin unbuffered 8 - byte dual in - line memory module ? 64 mx64 double data rate (ddr) sdram dimm ? performance : pc1600 pc2100 speed sort - 8b - 75b - 7k dimm cas latency 2 2.5 2 unit f ck clock frequency 100 133 133 mhz t ck clock cycle 10 7.5 7.5 ns f dq dq burst frequency 200 266 266 mhz ? intended for 100 mhz and 133 mhz applications ? inputs and outputs are sstl - 2 compatible ? v dd = 2.5volt 0.2, v ddq = 2.5volt 0.2 ? single pulsed ras interface ? sdrams have 4 internal banks for concurrent operation ? module has two physical bank s ? differential clock inputs ? data is read or written on both clock edges ? dram d ll align s dq and dqs transitions with clock t ransitions. ? address and control signals are fully synchronous to positive clock edge ? programmable operation: - dimm cas latency: 2, 2.5 - b urst type: sequential or interleave - burst length: 2, 4, 8 - operation: burst read and write ? auto refresh (cbr) and self refresh modes ? automatic and controlled precharge commands ? 1 3 /10/2 addressing (row/column/bank) ? 7.8 m s max. average periodic r efresh interval ? serial presence detect ? gold contacts ? sdrams in 66 - pin tsop type ii package description nt 512 d64s8 h a0g is an unbuffered 184 - pin double data rate (ddr) synchronous dram dual in - line memory module (dimm), organized as a two - bank hig h - speed memory array. the 64 mx64 module is a dual - bank dimm that uses sixteen 32 mx8 ddr sdrams in 400 mil tsop packages. the dimm achieves high - speed data transfer rates of up to 266mhz. the dimm is intended for use in applications operating from 100 mhz t o 133 mhz clock speeds with data rates of 200 to 266 mhz. clock enable cke0 and/or cke1 controls all devices on the dimm. prior to any access operation, the device cas latency and burst type/ length/operation type must be programmed into the dimm by address inputs a0 - a1 2 and i/o inputs ba0 and ba1 using the mode register set cycle. these dimms are manufactured using raw cards developed for broad industry use as reference designs. the use of these common design files minimizes electrical v ariation between suppliers. the dimm uses serial presence detects implemented via a serial eeprom using the two - pin iic protocol. the first 128 bytes of serial pd data are programmed and locked during module assembly. the last 128 bytes are available to th e customer. all nanya 184 ddr sdram dimms provide a high - performance, flexible 8 - byte interface in a 5.25? long space - saving footprint. ordering information part number speed organization leads power 143mhz (7ns @ cl = 2.5 ) nt512d64s8ha0g - 7k 133mhz (7.5ns @ cl= 2 ) pc2100 133mhz (7.5ns @ cl= 2.5 ) nt512d64s8ha0g - 75b 100mhz (10ns @ cl = 2 ) pc2100 125mhz (8ns @ cl = 2.5 ) nt512d64s8ha0g - 8b 100mhz (10ns @ cl = 2 ) pc1600 64m x64 gold 2.5v
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 2 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. pin description ck0, ck 1, ck2 ck0 , ck1 , ck2 differential clock inputs dq0 - dq63 data input/output cke0 , cke1 clock enable ras row address strobe dqs0 - dqs7, dqs9 - dqs16 bidirectional data strobes cas column address strobe v dd power ( 2.5 v) we write enable v ddq supply voltage for dqs(2.5v) s0 , s1 chip selects v ss ground a0 - a9, a11 ,a12 address inputs nc no connect a10/ap address input/autoprecharge scl serial presence detect clock input ba0, ba1 sdram bank address inputs sda serial presence detect data input/output v ref ref. voltage for sstl_2 inputs sa0 - 2 serial presence detect address inputs v ddid v dd identification flag. v d dspd serial eeprom positive power supply(2.5v) pinout pin front pin back pin front pin back pin front pin back 1 v ref 93 v ss 32 a5 124 v ss 62 v ddq 154 ras 2 dq0 94 dq4 33 dq24 125 a6 63 we 155 dq45 3 v ss 9 5 dq5 34 v ss 126 dq28 64 dq41 156 v ddq 4 dq1 96 v ddq 35 dq25 127 dq29 65 cas 157 s0 5 dq s0 97 dq s9 36 dq s3 128 v ddq 66 v ss 158 s1 6 dq2 98 dq6 37 a 4 129 dqs12 67 dqs5 159 dqs14 7 v dd 99 dq7 38 v dd 130 a 3 68 dq42 160 v ss 8 dq 3 100 v ss 39 dq2 6 131 dq30 69 dq43 161 dq46 9 nc 101 nc 40 dq27 132 v ss 70 v dd 162 dq47 10 nc 102 nc 41 a 2 133 dq31 71 nc 163 nc 11 v ss 103 nc 42 v ss 134 nc 72 dq 48 164 v ddq 12 dq8 104 v ddq 43 a1 135 nc 73 dq49 165 dq 52 13 dq9 105 dq1 2 44 nc 136 v ddq 74 v ss 166 dq53 14 dq s1 106 dq1 3 45 nc 137 ck0 75 ck2 167 nc 15 v ddq 107 dqs10 46 v dd 138 ck0 76 ck2 168 v dd 16 ck1 108 v dd 47 nc 139 v ss 77 v ddq 169 dqs15 17 ck1 109 dq1 4 48 a0 140 nc 78 dqs6 170 dq54 18 v ss 110 dq1 5 49 nc 141 a10 79 dq 50 171 dq55 19 dq1 0 111 cke1 50 v ss 142 nc 80 dq 51 172 v ddq 20 dq1 1 112 v ddq 51 nc 143 v ddq 81 v ss 173 nc 21 c ke0 113 nc 52 ba1 144 nc 82 v ddid 174 dq60 22 v ddq 114 dq20 k ey key 83 dq56 175 dq61 23 dq1 6 115 a12 53 dq32 145 v ss 84 dq57 176 v ss 24 dq1 7 116 v ss 54 v ddq 146 dq36 85 v dd 177 dqs16 25 dq s2 117 dq21 55 dq33 147 dq37 86 dqs7 178 dq62 26 v ss 118 a11 56 dqs4 148 v dd 87 dq58 179 dq63 27 a9 119 dqs11 57 dq34 149 dq s13 88 dq59 180 v ddq 28 dq 18 120 v dd 58 v ss 150 dq38 89 v ss 181 sa0 29 a7 121 dq22 59 ba0 151 dq39 90 nc 182 sa1 30 v ddq 122 a8 60 dq35 152 v ss 91 sda 183 sa2 31 dq 19 123 dq23 61 dq40 153 dq44 92 scl 184 v ddspd note: nc=no connect; nu = not useable; d u = do not use. all pin assignments are consistent for all 8 - byte unbuffered versions.
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 3 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. input/output functional description symbol type polarity function ck0 , ck1, ck 2 (sstl) positive edge the positive line of the differential pair of system cl ock inputs which drives the input to the on - dimm pll. all the ddr sdram address and control inputs are sampled on the rising edge of their associated clocks. ck0 , ck1 , ck2 (sstl) negative edge the negative line of the differential pair of system clock inputs which drives the input to the on - dimm pll. cke0 , cke1 (sstl) active high activates the sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low init iates the power down mode, or the self refresh mode. s0 , s1 (sstl) active low enables the associated sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas , we (sstl) active low when sampled at the positive rising edge of the clock, ras , cas , we define the operation to be executed by the sdram. v ref supply reference voltage for sstl - 2 inputs v ddq supply isolated power supply for the ddr sdram output buffers to provide improved noise immunity ba0, ba1 (sstl) - selects whic h sdram bank is to be active. a0 - a9 a10/ap a11 ,a12 (sstl) - during a bank activate command cycle, a0 - a1 2 defines the row address (ra0 - ra1 2 ) when sampled at the rising clock edge. during a read or write command cycle, a0 - a 9 defines the column address (ca 0 - ca 9 ) when sampled at the rising clock edge. in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, autoprecharge is selected and ba0/ba1 define the bank to be precharged . if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0/ba1 to control which bank(s) to precharge. if ap is high all 4 banks will be precharged regardless of the state of ba0/ba1. if ap is low, then b a0/ba1 are used to define which bank to pre - charge. dq0 - dq63 , (sstl) - data and check bit input/output pins operate in the same manner as on conventional drams. dqs0 - dqs7 dqs9 - dqs16 (sstl) active high data strobes: output with read data, input with write data. edge aligned with read data, centered on write data. used to capture write data. v dd , v ss supply power and ground for the ddr sdram input buffers and core logic sa0 ? sa2 - address inputs. connected to either v dd or v ss on the system boar d to configure the serial presence detect eeprom address. sda - this bidirectional pin is used to transfer data into or out of the spd eeprom. a resistor must be connected from the sda bus line to v dd to act as a pullup. scl - this signal is used to c lock data into and out of the spd eeprom. a resistor may be connected from the scl bus time to v dd to act as a pullup. v ddspd supply serial eeprom positive power supply.
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 4 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. functional block diagram ( 2 bank, 32 mx8 ddr sdrams ) s0 dqs9 dq0 dq1 dq2 dq7 dq4 dq6 dq5 dq3 dq8 dq9 dq10 dq15 dq12 dq14 dq13 dq11 a0-a12 ras ba0-ba1 ba0 - ba1 : sdrams d0 -d15 a0 - a12 : sdrams d0 -d15 ras : sdrams d0 -d15 dq16 dq17 dq18 dq23 dq20 dq22 dq21 dq19 dq24 dq25 dq26 dq31 dq28 dq30 dq29 dq27 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d3 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d2 dqs0 dqs13 dqs4 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d0 dqs10 dqs1 dqs dqs11 dqs2 dqs12 dqs3 dqs dq32 dq33 dq34 dq39 dq36 dq38 dq37 dq35 dq40 dq41 dq42 dq47 dq44 dq46 dq45 dq43 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d1 dqs dqs5 dqs14 dq48 dq49 dq50 dq55 dq52 dq54 dq53 dq51 dq56 dq57 dq58 dq63 dq60 dq62 dq61 dq59 dqs6 dqs15 dqs7 dqs16 cke0 we cas cas : sdrams d0 -d15 cke0 : sdrams d0 -d7 we : sdrams d8 -d15 120 ohm sdram x 4 ck0 ck0 120 ohm sdram x 6 ck1 ck1 120 ohm sdram x 6 ck2 ck2 notes : 1. dq-to-i/o wring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships are maintained as shown. 3. dq/dqs/dm/dqs resistors are 22 ohms. 4. vddid strap connections (for memory device vdd, vddq): strap out (open): vdd = vddq strap in (vss): vdd is not equal to vddq. dqs s1 i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d8 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d9 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d10 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d11 dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d7 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d6 i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d4 dqs dqs i/o 7 i/o 6 i/o 3 i/o 4 i/o 5 i/o 0 i/o 1 i/o 2 dm cs d5 dqs dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d12 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d13 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d14 dqs i/o 0 i/o 1 i/o 4 i/o 3 i/o 2 i/o 7 i/o 6 i/o 5 dm cs d15 dqs v ddq v ss d0 - d15 d0 - d15 d0 - d15 d0 - d15 v dd v ref v ddid strap: see note 4 serial pd a0 a2 a1 scl wp sda sa0 sa2 sa1 we : sdrams d0 -d15 cke1
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 5 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. serial presence detect -- part 1 of 2 spd entry value serial pd data entry (hexadecimal) note byte description ddr266a - 7k ddr266b - 75b ddr200 - 8b ddr2 66a - 7k ddr266b - 75 ddr200 - 8b 0 number of serial pd bytes written during production 128 80 1 total number of bytes in serial pd device 256 08 2 fundamental memory type sdram ddr 07 3 number of row addresses on assembly 1 3 0d 4 number of column addresses on assembly 10 0a 5 number of dimm bank 2 0 2 6 data width of assembly x64 40 7 data width of assembly (cont?) x64 00 8 voltage interface level of this assembly sstl 2.5v 04 9 ddr sdram device cycle time at cl=2.5 7ns 7.5ns 8ns 70 75 80 10 ddr sdram device access time from clock at cl=2.5 0.75ns 0.75ns 0.8ns 75 75 80 11 dimm configuration type non - parity 00 12 refresh rate/type sr/1x( 7 . 8 us) 8 2 13 primary ddr sdram width x8 08 14 error checking ddr sdram device width n/a 00 15 ddr sdram device attr: min c l k delay, random col access 1 clock 01 16 ddr sdram device attributes: burst length supported 2,4,8 0e 17 ddr sdram device attributes: number of device banks 4 04 18 ddr sdram device attributes: cas latencies supported 2/ 2.5 2/2.5 2/2.5 0c 0c 0c 19 ddr sdram device attributes: cs latency 0 01 20 ddr sdram device attributes: we latency 1 02 21 ddr sdram device attributes: differential clock 20 22 ddr sdram device attributes: general +/ - 0.2v voltage tolerance 00 23 minimum clock cycle at cl=2 7.5ns 10ns 10ns 75 a0 a0 24 maximum data access time from clock at cl=2 0.75ns 0.75ns 0.8ns 75 75 80 25 minimum clock cycle time at cl=1 n/a 00 26 maximum data access time from clock at cl=1 n/a 00 27 minimum row precha rge time( t r p ) 20ns 20ns 20ns 50 50 50 28 minimum row active to row active delay ( t r rd ) 15ns 15ns 15ns 3c 3c 3c 29 minimum ras to cas delay ( t r cd ) 20ns 20ns 20ns 50 50 50 30 minimum ras pulse width ( t ras ) 45ns 45ns 50ns 2d 2d 32 31 module bank densi ty 256 mb 4 0 32 address and command setup time before clock 0.9ns 0.9ns 1.1ns 90 90 b0 33 address and command hold time after clock 0.9ns 0.9ns 1 .1 ns 90 90 b0 34 data input setup time before clock 0.5ns 0.5ns 0.6ns 50 50 60 35 data input hold time a fter clock 0.5ns 0.5ns 0.6ns 50 50 60 36 - 61 reserved undefined 00 62 spd revision initial initial initial 00 00 00 63 checksum data 90 c0 46
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 6 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. serial presence detect -- part 2 of 2 spd entry value serial pd data entry (hexadecimal) byte description ddr266a - 7k ddr266b - 75b ddr200 - 8b ddr266a - 7k ddr266b - 75 ddr200 - 8b note 64 - 71 manufacturer?s jeded id code nanya 7f7f7f0b 00000000 72 module manufacturing location n/a 00 73 - 90 module part number n/a n/a n/a 00 00 00 91 - 92 module revision code n/a 00 93 - 94 module manufacturing data year/week code yy/ww 1,2 95 - 98 module serial number serial number 00 99 - 255 reserved undefined 00 1. yy= binary coded decimal ye ar code, 0 - 99(decimal) , 00 - 63(hex) 2. ww= binary coded decimal year code, 01 - 52(decimal) , 01 - 34(hex)
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 7 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. absolute maximum ratings symbol parameter rating units v in , v out voltage on i/o pins relative to vss - 0.5 to v ddq +0.5 v v in voltage on input relative to vss - 0.5 to +3.6 v v dd voltage on vdd supply relative to vss - 0.5 to +3.6 v v dd q voltage on vddq supply relative to vss - 0.5 to +3.6 v t a operating temperature (ambient) 0 to+70 c t stg storage temperature (p lastic) - 55 to +150 c p d power dissipation 16 w i out short circuit output current 50 ma note : stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is stress rating only, and functional oper ation of the device at these or any other conditions above those indicated in the operational sec ti ons of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. capacitance paramete r symbol max. units notes input capacitance: ck0, ck0 , ck1, ck1 , ck2 , ck2 c i1 24 pf 1 input capacitance: a0 - a1 2 , ba0, ba1, we , ras , cas c i2 60 pf 1 input capacitance: cke0, cke1, s0 , s1 c i5 30 pf 1 input capacitance: sa0 - sa2, scl c i4 9 pf 1 input/output capacitance dq0 - 63; dqs0 - 7, 9 - 16 c io1 14 pf 1,2 input/output capacitance: sda c io3 11 pf 1. v d dq = v dd = 2.5v 0.2v, f = 100 mhz, t a = 2 5 c , v out (dc) = v ddq /2, v out (peak to peak) = 0.2v. 2. dqs inputs are grouped with i/o pins reflecting the fact that they are matched in loading to dq and dqs to facilitate trace matching at the board level.
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 8 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. dc electrical characteristics and operating conditions ( t a = 0 c ~ 7 0 c ; v ddq = 2.5v 0 .2v; v dd = 2.5v 0.2 v, see ac characteristics) symbol parameter min max units notes v dd supply voltage 2.3 2.7 v 1 v dd q i/o suppl y voltage 2.3 2.7 v 1 v ss , v ssq supply voltage , i/o supply voltage 0 0 v v ref /o reference voltage 0.49 x v dd q 0.51 x v dd q v 1,2 v tt i/o termination voltage (system) v ref ? 0 .04 v ref + 0.04 v 1,3 v ih(dc) input high (logic1) voltage v ref + 0.15 v ddq + 0.3 v 1 v il(dc) input low (logic0) voltage - 0.3 v ref - 0. 15 v 1 v in(dc) input voltage level, ck and ck inputs - 0.3 v ddq + 0.3 v 1 v id(dc) input differential voltage, ck and ck inputs 0.30 v ddq + 0.6 v 1,4 i i i nput leakage current any input 0v v in v dd ; (all other pins not under test = 0v) - 10 10 ua 1 i oz output leakage current (dqs are disabled; 0v v out v ddq - 10 10 ua 1 i oh output high current (v out = v ddq - 0.373v, min v ref , min v tt ) - 16.8 - ma 1 i o l output low current (v out = 0 .373, max v ref , max v tt ) 16.8 - ma 1 1. inputs are not recognized as valid until v ref stabilizes. 2. v ref is expected to be equal to 0.5 v ddq of the transmitting device, and to track variations in the dc level of the same . peak - to - peak noise on v ref may not exceed 2% of the dc value. 3. v tt is not applied directly to the dimm. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 4. v id is the magnitude of the difference between the input level on ck and the input level on ck .
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 9 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac characteristics (notes 1 - 5 apply to the following tables; electrical characteristics and dc operating con ditions, ac operating conditions, operating, standby, and refresh currents, and electrical characteristics and ac timing.) 1. all voltages referenced to v ss . 2. tests for ac timing, i dd , and electrical, ac and dc characteristics, may be conducted at nom inal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. outputs measured with equivalent load. refer to the ac output load circuit below. 4. ac timing and i dd tests may use a v il to v ih swing of up to 1.5v in the test environment, but input timing is still referenced to v ref (or to the crossing point for ck, ck), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between v il(ac) and v ih(ac) unless otherwise specified. 5. the ac and dc input level specifications are as defined in the sstl_2 standard (i.e. the receiver effectively switches as a result of the signal crossing the ac input level, and remains in that state as long as the signal does not ring back above (below) the dc input low (high) level. ac output load circuits timing reference point v tt 50 ohms 30 pf output v out ac operating conditions ( t a = 0 c ~ 7 0 c ; v ddq = 2.5v 0 .2v; v dd = 2.5v 0.2 v, see ac characteristics) symbol parameter/condition min max unit notes v ih(ac) input high (logic 1) voltage. v ref + 0.31 v 1, 2 v il(ac) input low (logic 0) voltage. v ref ? - 0.31 v 1, 2 v id(ac) input differential voltage, ck and ck inputs 0.62 v ddq + 0.6 v 1, 2, 3 v ix(ac) input differential pair cross point voltage, ck and ck inputs (0.5*v ddq ) - 0 .2 (0.5*v ddq ) + ? 0.2 v 1, 2, 4 1 . input slew rate = 1v/ n s . 2. inputs are not recognized as valid until v ref stabilizes. 3. v id is the magnitude of the difference between the input level on ck and the input level on ck. 4. the value of v ix is expected to equal 0.5*v ddq of the tran smitting device and must track variations in the dc level of the same.
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 10 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. operating, standby, and refresh currents ( t a = 0 c ~ 7 0 c ; v ddq = 2.5v 0 .2v; v dd = 2.5v 0.2 v, see ac characteristics) symbol parameter/condition pc1600 pc210 0 unit notes i dd0 operating current : one bank; active / precharge; t rc = t rc ( min ) ; t ck = t ck ( min ) ; dq, dm, and dqs inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 1024 1160 ma 1,2 i dd1 operating curr ent : one bank; active / read / precharge; burst = 2; t rc = t rc ( min ) ; cl=2.5; t ck = t ck ( min ) ; i out = 0ma; address and control inputs changing once per clock cycle 1113 1360 ma 1,2 i dd 2p precharge power - down standby current : all banks idle; power - down mode; cke v il ( max ) ; t ck = t ck ( min ) 240 240 ma 1,2 i dd2n idle standby current : cs 3 v ih ( min ) ; all banks idle; cke 3 v ih ( min ) ; t ck = t ck ( min ) ; address and control inputs changing once per clock cycle 480 560 ma 1,2 i dd3p active power - down standby current : one bank active; power - down mode; cke v il ( max ) ; t ck = t ck ( min ) 240 240 ma 1,2 i dd3n active standby current : one bank; active / precharge; cs 3 v ih ( min ) ; cke 3 v ih ( min ) ; t rc = t ras ( max ) ; t ck = t ck ( min ) ; dq, dm, and dqs in puts changing twice per clock cycle; address and control inputs changing once per clock cycle 800 960 ma 1,2 i dd4r operating current : one bank; burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; dq and dqs o utputs changing twice per clock cycle; cl = 2.5; t ck = t ck ( min ) ; i out = 0ma 1418 1800 ma 1,2 i dd4w operating current : one bank; burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; dq and dqs inputs changin g twice per clock cycle; cl=2.5; t ck = t ck ( min ) 1288 1680 ma 1,2 t rc = t rfc ( min ) 2256 2400 ma 1,2 i dd 5 auto - refresh current : t rc = 7.8 s 264 264 ma 1,2,4 i dd6 self - refresh current : cke ?0.2v 48 48 ma 1,2,3 1. i dd specifications are test ed after the device is properly initialized. 2. input slew rate = 1v/ n s . 3. enables on - chip refresh and address counters. 4. current at 7.8 s is time averaged value of i dd5 at t rfc ( min ) and i dd2p over 7.8 s.
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 11 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac timing speci fi cations fo r ddr sdram devices used on module ( t a = 0 c ~ 7 0 c ; v ddq = 2.5v 0 .2v; v dd = 2.5v 0.2 v, see ac characteristics) (part 1 of 2) - 7k - 75b - 8b symbol parameter min. max. min. max. min. max. unit note s t ac dq output access time from ck/ ck - 0.75 +0.75 - 0.75 +0.75 - 0.8 +0.8 ns 1,2,3,4 t dqsck dqs output access time from ck/ ck - 0.75 +0.75 - 0.75 +0.75 - 0.8 +0.8 ns 1,2,3,4 t ch ck high - level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck 1,2,3,4 t cl ck low - level width 0.45 0.55 0.45 0.55 0.45 0.55 t ck 1,2,3,4 t ck cl=2.5 7 12 7.5 12 8 12 ns 1,2,3,4 t ck clock cycle time cl=2 7.5 12 10 12 10 12 ns 1,2,3,4 t dh dq and dm input hold time 0.5 0.5 0.6 ns 1,2,3,4 ,1 5 , 16 t ds dq and dm input setup time 0.5 0.5 0.6 ns 1, 2,3,4 ,1 5 , 16 t dipw dq and dm input pulse width (each input) 1.75 1.75 2 ns 1,2,3,4 t hz data - out high - impedance time from ck/ ck - 0.75 +0.75 - 0.75 +0.75 - 0.8 +0.8 ns 1, 2, 3, 4, 5 t lz data - out low - impedance time from ck / ck - 0.75 +0.75 - 0.75 +0.75 - 0.8 +0.8 ns 1, 2, 3, 4, 5 t dqsq dqs - dq skew (dqs & associated dq signals) 0.5 0.5 0.6 ns 1,2,3,4 t dqsqa dqs - dq skew (dqs & all dq signals) 0.5 0.5 0.6 ns 1,2,3,4 t hp minimum half clk period for any given cycle; defined by clk high (t ch ) or clk low (t cl ) time t ch or t cl t ch or t cl t ch or t cl t ck 1,2,3,4 t qh data output hold time from dqs t hp - 0.75ns t hp - 0.75ns t hp - 1.0ns t ck 1,2,3,4 t dqss write command to 1st dqs latching transition 0.75 1.25 0.75 1 .25 0.75 1.25 t ck 1,2,3,4 t dqsl,h dqs input low (high) pulse width (write cycle) 0.35 0.35 0.35 t ck 1,2,3,4 t dss dqs falling edge to ck setup time (write cycle) 0.2 0.2 0.2 t ck 1,2,3,4 t dsh dqs falling edge hold time from ck (write cycle) 0.2 0. 2 0.2 t ck 1,2,3,4 t mrd mode register set command cycle time 14 15 16 ns 1,2,3,4 t wpres write preamble setup time 0 0 0 ns 1, 2, 3, 4, 7 t wpst write postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck 1, 2, 3, 4, 6 t wpre write preamble 0.25 0.25 0.25 t ck 1,2,3,4 t ih address and control input hold time (fast slew rate) 0.9 1.1 1.1 ns 2, 3, 4, 9 , 1 1 , 1 2 t is address and control input setup time (fast slew rate) 0.9 1.1 1.1 ns 2, 3, 4, 9 , 11 , 1 2 t ih address and control input hold time (slow sl ew rate) 1.0 1.1 1.1 ns 2, 3, 4, 1 0 , 1 1 , 1 2 , 14
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 12 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac timing specifications for ddr sdram devices used on module ( t a = 0 c ~ 7 0 c ; v ddq = 2.5v 0 .2v; v dd = 2.5v 0.2 v, see ac characteristics) (part 2 of 2) - 7k - 75b - 8b symbol parameter min. max. min. max. min. max. unit not e s t is address and control input setup time (slow slewrate) 1.0 1.0 1.1 ns 2, 3, 4, 1 0 , 1 1 , 12 , 14 t ipw input pulse width 2.2 2.2 - ns 2, 3, 4, 12 t rpre read preamble 0.9 1.1 0.9 1.1 0.9 1.1 t ck 1,2,3,4 t rpst r ead postamble 0.40 0.60 0.40 0.60 0.40 0.60 t ck 1,2,3,4 t ras active to precharge command 45 120,000 45 120,000 50 120,000 ns 1,2,3,4 t rc active to active/auto - refresh command period 65 65 70 ns 1,2,3,4 t rfc auto - refresh to active/auto - refresh command period 75 75 80 ns 1,2,3,4 t rcd active to read or write delay 20 20 20 ns 1,2,3,4 t rap active to read command with autoprecharge 20 20 20 ns 1,2,3,4 t rp precharge command period 20 20 20 ns 1,2,3,4 t rrd active bank a to active bank b comma nd 15 15 15 ns 1,2,3,4 t wr write recovery time 15 15 15 ns 1,2,3,4 t dal auto precharge write recovery + precharge time (t wr / t ck ) + (t rp / t ck ) (t wr / t ck ) + (t rp / t ck ) (t wr / t ck ) + (t rp / t ck ) t ck 1, 2, 3, 4, 1 3 t wtr internal write to rea d command delay 1 1 1 t ck 1,2 , 3,4 t xsnr exit self - refresh to non - read command 75 75 80 ns 1,2 , 3,4 t xsrd exit self - refresh to read command 200 200 200 t ck 1,2 , 3,4 t refi average periodic refresh interval 7.8 7.8 7.8 s 1, 2, 3, 4, 8
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 13 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. ac timing specification notes 1. input slew rate = 1v/ns. 2. the ck/ ck input reference level (for timing reference to ck/ ck ) is the point at which ck and ck cross: the input reference level fo r signals other than ck/ ck , is v ref . 3. inputs are not recognized as valid until v ref stabilizes. 4. the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 5. t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but specify when the device is no longer driving (hz), or begins driving (lz). 6. the maximum limit for thi s parameter is not a device limit. the device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. the specific requirement is that dqs be valid (high, low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previously in progress on the bus, dqs will be transitioning from hi - z to logic low. if a previous write was in progress, dqs could be high, low, or transitioning from high to low at this time, depending on t dqss . 8. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 9 . for command/address input slew rate >= 1.0 v/ns. slew rate is measured between v oh (ac) and v ol (ac). 10 . for command/address input slew rate >= 0.5 v/ns and < 1.0 v/ns. slew rate is measured between v oh (ac) and v ol (ac). 1 1 . ck/ ck slew rates are >= 1.0 v/ns. 1 2 . these parameters guarant ee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester characterization. 1 3 . for each of the terms in parentheses, if not already an integer, round to the next highest integer. t ck is equal to the actual system clock cycle time. for example, for pc2100 at cl= 2.5, t dal = (15ns/7.5ns) +(20ns/7.0ns) = 2 + 3 = 5. 1 4 . an input setup and hold time derating table is used to increase t is and t ih in the case where the input slew rate is below 0.5 v/n s. input slew rate ? delta ( t i s ) delta ( t ih ) unit note 0.5 v/ns 0 0 ps 1,2 0. 4 v/ns +50 0 ps 1,2 0. 3 v/ns +100 0 ps 1,2 1. input slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for ri sing transitions. 2. these derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 1 5 . an input setup and hold time derating table is used to increase t ds and t dh in the case where the i/ o slew rate is below 0.5 v/ns. input slew rate delta ( t d s ) delta ( t dh ) unit note 0.5 v/ns 0 0 ps 1,2 0. 4 v/ns +75 +75 ps 1,2 0. 3 v/ns +150 +150 ps 1,2 1. i/o slew rate is based on the lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. these derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device. 1 6 . an i/o delta rise, fall derating table is used to inc rease t ds and t dh in the case where dq, dm, and dqs slew rates differ. delta rise and fall rate delta ( t d s ) delta ( t dh ) unit note 0.0 ns/v 0 0 ps 1,2,3,4 0.25 ns/v +50 +50 ps 1,2,3,4 0.5 ns/v +100 +100 ps 1,2,3,4 1. input slew rate is based on th e lesser of the slew rates determined by either v ih (ac) to v il (ac) or v ih (dc) to v il (dc) , similarly for rising transitions. 2. input slew rate is based on the larger of ac to ac delta rise, fall rate and dc to dc delta rise, fall rate. 3. the delt a rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)] for example: slew rate 1 = 0.5 v/ns; slew rate 2 = 0.4 v/ns . delta rise, fall = (1/0.5) - (1/0.4) [ns/v] = - 0.5 ns/v using the table above, this would result in an increase in t ds a nd t dh of 100 ps. 4. these derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
nt 512d64s8ha0g 512mb : 64 m x 64 pc2100 / pc1600 u nbuffered dimm preliminary 1 0 / 2 001 14 ? nanya technology corp. nanya technology corp. reserves the right to change products and specifications without notice. package dimensions note : all dimensions are typical unless otherwise stated. 133.35 128.95 1.250 0.157 0.700 front side 0.394 1.27+/- 0.10 detail a 1.27 pitch detail b 1.00 width 3.99 detail a detail b 0.091 q 2.50 3.80 1.80 6.35 5.25 5.077 2.3 (2x)4.00 17.80 31.75 10.0 0.098 0.157 max. 0.050 +/- 0.004 0.05 0.039 0.071 0.250 0.150 4.00 0.157 back unit : inches millimeters

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