View EUP8218JIR1_7900330.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary eup8218 ds8218 ver 0.1 mar. 2012 1 2a single cell switchm ode li-ion/polymer battery charger with system power-path selection and automatic usb/charg er detection description the eup8218 is a highly integrated single cell li-i on and li-polymer battery charger. it integrates a constan t- frequency pwm controller with high accuracy regulation of input current, charge current, and voltage. it a lso provides battery detection, pre-conditioning, charg e termination, and charge status monitoring. the eup8218 provides power path selection function. when the qualified adapter is present, the system i s powered by the adapter. otherwise, the system is po wered by the battery. it also integrates an usb- connection-monitoring device used to determine if a standard usb device or a battery-charging device is connected. the eup8218 charges the battery in three phases: pre-conditioning, fast-charge constant current and constant voltage. in all stages, an internal control loop mo nitors the ic junction temperature and reduce charge current i f the internal temperature threshold (120c) is exceeded. additionally, a battery pack thermistor monitoring input (ts) is included that monitors battery temperature for safety charging. charge is terminated when the current reaches 10% o f the fast charge rate. a programmable charge timer offers a safety back up. the eup8218 automatically restarts the charge cycle if the battery voltage falls below an internal threshold, and enters a low-quiescent current sleep mode when the input voltage falls below the battery volt age. the eup8218 features dynamic power management (dpm) to reduce the charge current when the input p ower limit is reached to avoid over-loading the adapter. a highly-accurate current-sense amplifier enables precise measurement of input current from adapter to monito r overall system power. the eup8218 is available in a 28-pin, 4mm 4mm tqfn package. features 4.5v-20v input operating range high integration - automatic power path selector between adapter and battery - automatic usb/charger detection - dynamic power management - integrated 20v high side switching mosfet safety - thermal regulation loop throttles back current to limit tj=120 c - thermal shutdown - battery thermistor sense hot/cold charge suspend & battery detect - input over-voltage protection with programmable thereshold accuracy - 1% charge voltage regulation - 10% charge current regulation - 10% input current regulation less than 25 a battery current with adapter removed less than 5ma input current with adapter present and charge disabled 4mm 4mm tqfn-28 package rohs compliant and 100% lead (pb)-free halogen-free applications mobile and smart phones tablet pc handheld devices
preliminary eup8218 ds8218 ver 0.1 mar. 2012 2 typical application circuit figure 1. 1-cell typical application schematic with single ce ll battery (usb or adapter with input ovp 10.5v, 2 a charge current, 0.2a pre-charge current, 2.5a adapter current or ilim 0.9a limit current.r 5b use 3.8k for 0.5a limit current.)
preliminary eup8218 ds8218 ver 0.1 mar. 2012 3 block diagram figure 2.
preliminary eup8218 ds8218 ver 0.1 mar. 2012 4 pin configurations package type pin configurations tqfn-28 pin description pin tqfn-28 i/o/p description acn 1 i adapter current sense resistor negative input. a 0. 1 f ceramic capacitor is placed from acn to acp to provide differential-mode filter ing. an optional 0.1 f ceramic capacitor is placed from acn pin to agnd fo r common-mode filtering. acp 2 p/i adapter current sense resistor positive input. a 0. 1 f ceramic capacitor is placed from acn to acp to provide differential-mode filter ing. a 0.1 f ceramic capacitor is placed from acp pin to agnd for common-mode filt ering. cmsrc 3 o connect to the source of n-channel revfet. place 4k resistor from cmsrc pin to the source of revfet to control the turn-on spee d. acdrv 4 o ac adapter to pvcc switch driver output. connect to 4k resistor then to the gate of the revfet n-channel power mosfet. stat 5 o open-drain charge status pin with 1.5k pull up to power rail. the stat pin can be used to drive led or communicate with the host p rocessor. it indicates various charger operations: low when charge in progress. hi gh when charge is complete or in sleep mode. blinking at 0.5hz when fault occu rs, including charge suspend, input over-voltage, timer fault and battery absent. ts 6 i temperature qualification voltage input. connect a negative temperature coefficient thermistor. program the hot and cold temperature wi ndow with a resistor divider from vref to ts to agnd. the temperature qualificat ion window can be set to 5-40c or wider. the 103at thermistor is recommende d. ttc 7 o safety timer and termination control. connect a cap acitor from this node to agnd to set the fast charge safety timer (5.6min/nf). pr e-charge timer is internally fixed to 30 minutes. pull the ttc to low to disable the char ge termination and safety timer. pull the ttc to high to disable the safety t imer but allow the charge termination. vref 8 p 3.3v reference voltage output. place a 1f ceramic capacitor from vref to agnd pin close to the ic. this voltage could be used for programming iset and acset and ts pins. it may also serve as the pull-up rail of stat pin and cell pin. d+ 9 i d- 10 i d+ and d- connections for usb input adapter detecti on-when a charge cycle is initiated by the usb input , and a short is detecte d between d+ and d- , the flag1 is low and the input current limit set by acset sha ll not change. if a short is not detected, the flag1 is high and the input current l imit is changed to the predetermined usb2 or usb3 current limit. flag1 11 o charger/standard usb device detect flag-when an usb charger is plugged in, the flag1 is low. while a standard usb device is plugge d in, the flag is high.
preliminary eup8218 ds8218 ver 0.1 mar. 2012 5 pin description (continued) pin tqfn-28 i/o/p description iset 13 i fast charge current set point. use a voltage divide r from vref to iset to agnd to set the fast charge current: i chg =v iset /(20*r sr ) the pre-charge and termination current is internall y as one tenth of the charge current. the charger is disabled when iset pin volt age is below 40mv and enabled when iset pin voltage is above 120mv. cell 14 i cell selection pin. set cell pin low for 1-cell with a fixed 4.2v. srn 15 i battery sense input. a bypass capacitor of 20f is required to minimize ripple voltage. when vbat is within 90mv of avcc, the eup8 218 is forced into sleep mode. srp 16 i/p current amplifier sense input. a sense resistor, rs ense, must be connected between the srn and srp pins. acset 17 i input current set point. use a voltage divider from vref to acset to agnd to set this value: i dpm =v acset /(20*r ac ) ovpset 18 i valid input voltage set point. use a voltage divide r from input to ovpset to agnd to set this voltage. the voltage above interna l 1.6v reference indicates input over-voltage, and the voltage below internal 0.5v reference indicates input under-voltage. led driven by stat pin keeps blinkin g, reporting fault condition. comp 20 o compensation, soft-start pin. charging begins when the comp pin reaches 850mv. the recommended compensation components are a 2.2f (or larger) capacitor and a 0.5k series resistor. a 100a curre nt into the compensation capacitor also sets the soft-start slew rate. btst 21 p pwm high side driver positive supply. agnd 22 p analog ground. pgnd 23 p power ground. ground connection for high-current po wer converter node. on pcb layout, connect directly to ground connection o f input and output capacitors of the charger. only connect to agnd through the th ermal pad underneath the ic. sw 24,25 p switching node, charge current output inductor conn ection. connect the 0.047 f bootstrap capacitor from sw to btst. pvcc 26, 27 p charger input voltage. connect at least 10 f ceramic capacitor from pvcc to pgnd and place it as close as possible to ic. avcc 28 p/i ic power positive supply. place a 1 f ceramic capacitor from avcc to agnd and place it as close as possible to ic. place a 10 resistor from input side to avcc pin to filter the noise. for 5v input, a 5 resistor is recommended. nc 12,19 no connect thermal pad agnd p exposed pad beneath the ic. always solder thermal p ad to the board, and have vias on the thermal pad plane star-connecting to ag nd and ground plane for high-current power converter. it dissipates the hea t from the ic.
preliminary eup8218 ds8218 ver 0.1 mar. 2012 6 ordering information order number package type marking operating tempera ture range EUP8218JIR1 tqfn-28 xxxxx p8218 -40c to +85c eup8218 lead free code 1: lead free, halogen fr ee packing r: tape & reel operating temperature range i: industry standard package type j: tqfn
preliminary eup8218 ds8218 ver 0.1 mar. 2012 7 absolute maximum ratings (1) pvcc, avcc, acp, acn,acdrv, cmsrc,btst,srp, srn---- ---------------------------- -0.3v to 20v sw ------------------------------------------------ --------------------------------------------------- ----- -2v to 20v ovpset, ts,ttc, cell, comp, d+,d-,flag1 ----------- ------------------------------------ -0.3v to 7v vref, iset, acset, stat --------------------------- -------------------------------------------- -0.3v to 3.6v pgnd, agnd ---------------------------------------- ----------------------------------------------- -0.3v to 0.3v maximum difference voltage, srp-srn, acp-acn ------ ----------------------------------- -0.5v to 0.5v package thermal resistance ,tqfn-28 , ja -------------------------------------------------- --- 40c/w junction temperature range, t j -------------------------------------------------- ----------------------- 150c storage temperature range, tstg ------------------ ------------------------------------------- -65c to 150c lead temperature (soldering, 10s) ---------------- --------------------------------------------------- - 260c recommended operating conditions (2) min. max. unit input voltage v in 4.5 20 v output voltage v out 4.5 v output current (r sr 10m ) i out 0.5 4 a acp-acn -200 200 mv maximum difference voltage srp-srn -200 200 mv ambient temperature range , t a -40 85 c note (1): stress beyond those listed under absolut e maximum ratings may damage the device. note (2): the device is not guaranteed to function outside the recommended operating conditions. electrical characteristics 4.5v v(pvcc, avcc) 20v, C40c < t j <+ 125c, typical values are at t a = 25c, with respect to agnd (unless otherwise noted). eup8218 symbol parameter conditions min. typ. max. unit operating conditions v avcc_op avcc input voltage operating range during charging 4.5 20 v quiescent currents v avcc > v uvlo , v srn > v avcc (sleep), t j = 0c to 85c 25 btst, sw, srp, srn, v avcc > v uvlo , v avcc > v srn , iset < 40mv, v bat =4.2v, charge disabled 25 i bat battery discharge current (sum of currents into avcc, pvcc, acp, acn) btst, sw, srp, srn, v avcc > v uvlo , v avcc > v srn , iset > 120mv, v bat =4.2v, charge done 25 a v avcc > v uvlo , v avcc > v srn , iset < 40mv, v bat =4.2v, charge disabled 2.5 5 v avcc > v uvlo , v avcc > v srn , iset > 120mv, charge enabled, no switching 2.5 5 i ac adapter supply current (sum of current into avcc,acp, acn) v avcc > v uvlo , v avcc > v srn , iset > 120mv, charge enabled, switching 15 m a
preliminary eup8218 ds8218 ver 0.1 mar. 2012 8 electrical characteristics (continued) 4.5v v(pvcc, avcc) 20v, C40c < t j <+ 125c, typical values are at t a = 25c, with respect to agnd (unless otherwise noted). eup8218 symbol parameter conditions min. typ. max. unit charge voltage regulation v bat_reg srn regulation voltage cell to agnd, measured on srn 4.2 v charge voltage regulation accuracy t j = 0c to 85c C1% 1% current regulation fast charge v iset iset voltage range rsense = 10m 0.12 0.8 v k iset charge current set factor (amps of charge current per volt on iset pin) rsense = 10m 5 a/v chargecurrent regulation accuracy (with schottky diode on sw) v srp-srn = 20 mv -10% 10% v iset_cd charge disable threshold iset falling 40 50 mv v iset_ce charge enable threshold iset rising 100 120 mv i iset leakage current into iset viset = 2v 100 na input current regulation k dpm input dpm current set factor (amps of input current per volt on acset) rsense = 10m 5 a/v input dpm current regulation accuracy (with schottky diode on sw) v acp-acn = 60 mv -10% 10% i acset leakage current into acset pin vacset = 2v 100 na current regulation C pre-charge k iprechg precharge current set factor percentage of fast charge current 10% charge termination k term termination current set factor percentage of fast charge current 10% t term_deg deglitch time for termination (both edges) 100 ms t qual termination qualification time v srn > v rech and i chg < i term 250 ms i qual termination qualification current discharge current once termination is detected 2 ma input under-voltage lock-out comparator (uvlo) v uvlo ac under-voltage rising threshold measure on avcc 3.4 3.6 3.9 v v uvlo_hys ac under-voltage hysteresis, falling measure on avcc 300 mv sleep comparator (reverse discharging protection) v sleep sleep mode threshold v avcc C v srn falling 30 90 150 mv v sleep_hys sleep mode hysteresis v avcc C v srn rising 200 mv t sleep_fall_cd sleep deglitch to disable charge v avcc C v srn falling 1 ms
preliminary eup8218 ds8218 ver 0.1 mar. 2012 9 electrical characteristics (continued) 4.5v v(pvcc, avcc) 20v, C40c < t j <+ 125c, typical values are at t a = 25c, with respect to agnd (unless otherwise noted). eup8218 symbol parameter conditions min. typ. max. unit sleep comparator (reverse discharging protection) t sleep_fall _fetoff sleep deglitch to turn off input fets v avcc C v srn falling 5 ms t sleep_fall deglitch to enter sleep mode, disable vref and enter low quiescent mode v avcc C v srn falling 100 ms t sleep_pwrup deglitch to exit sleep mode, and enable vref v avcc C v srn rising 30 ms bat lowv comparator v lowv precharge to fast charge transition cell to agnd, measure on srn 2.85 2.9 2.95 v v lowv_hys fast charge to precharge hysteresis cell to agnd, measure on srn 200 mv t pre_to_fas vlowv rising deglitch delay to start fast charge c urrent 25 ms t fast_to_pre vlowv falling deglitch delay to start precharge cu rrent 25 ms recharge comparator v rechg recharge threshold, below regulation voltage limit, vbat_reg-vsrn cell to agnd, measure on srn 70 100 130 mv t rech_rise_deg vrechg rising deglitch v srn decreasing below vrechg 10 ms t rech_fall_deg vrechg falling deglitch v srn increasing above vrechg 10 ms bat over-voltage comparator v ov_rise over-voltage rising threshold as percentage of v bat_reg 104% v ov_fall over-voltage falling threshold as percentage of v srn 102% input over-voltage comparator (acov) v acov ac over-voltage rising threshold to turn off revfet ovpset rising 1.55 1.6 1.65 v v acov_hys ac over-voltage falling hysteresis ovpset falling 50 mv t acov_rise_deg ac over-voltage rising deglitch to turn off revfet and disable charge ovpset rising 1 s t acov_fall_deg ac over-voltage falling deglitch to turn on revfet ovpset falling 30 ms input under-voltage comparator (acuv) v acuv ac under-voltage falling threshold to turn off revfet ovpset falling 0.45 0.5 0.55 v v acuv_hys ac under-voltage rising hysteresis ovpset rising 100 mv
preliminary eup8218 ds8218 ver 0.1 mar. 2012 10 electrical characteristics (continued) 4.5v v(pvcc, avcc) 20v, C40c < t j <+ 125c, typical values are at t a = 25c, with respect to agnd (unless otherwise noted). eup8218 symbol parameter conditions min. typ. max. unit input under-voltage comparator (acuv) t acov_fall_deg ac under-voltage falling deglitch to turn off revfet and disable charge ovpset falling 1 s t acov_rise_deg ac under-voltage rising deglitch to turn on revfet ovpset rising 30 ms thermal regulation t j_reg junction temperature regulation accuracy iset > 120mv, charging 120 c t shut thermal shutdown rising temperature temperature rising 150 c thermal shutdown comparator t shut_rise_deg thermal shutdown rising deglitch temperature rising 100 s t shut_fall_deg thermal shutdown falling deglitch temperature falling 10 ms thermistor comparator v ltf cold temperature threshold, ts pin voltage rising threshold charger suspends charge. as percentage to v vref 71.5% 73.5% 75.5% v ltf_hys cold temperature hysteresis, ts pin voltage falling as percentage to v vref 0.4% v htf hot temperature ts pin voltage rising threshold as percentage to v vref 45.6% 47.2% 49.8% v tco cut-off temperature ts pin voltage falling threshold as percentage to v vref 43.2% 44.7% 46.2% t ts_chg_sus deglitch time for temperature out of range detection v ts > v ltf , or v ts < vtco , or v ts < vhtf 20 ms t ts_chg_resume deglitch time for temperature in valid range detection v ts < v ltf C v ltf_hys or v ts >v tco , or v ts => v htf 400 ms charge over-current comparator (cycle-by-cycle) v ocp_chrg charge over-current rising threshold, vsrp>2.2v current as percentage of fast charge current 160% bat short comparator v batsht battery short falling threshold measure on srn 2 v v batsht_hys battery short rising hysteresis measure on srn 200 mv t batsht_deg deglitch on both edges 1 s v batsht charge current during batshort percentage of fast charge current 10% vref regulator v vref_reg vref regulator voltage v avcc > v uvlo , no load 3.267 3.3 3.333 v i vref_lim vref current limit v vref = 0 v, v avcc > v uvlo 35 90 ma
preliminary eup8218 ds8218 ver 0.1 mar. 2012 11 electrical characteristics (continued) 4.5v v(pvcc, avcc) 20v, C40c < t j <+ 125c, typical values are at t a = 25c, with respect to agnd (unless otherwise noted). eup8218 symbol parameter conditions min. typ. max. unit ttc input t prechrg precharge safety timer precharge time before fault occurs 1620 1800 1980 sec t fastchrg fast charge timer range tchg=c ttc *k ttc 1 10 hr fast charge timer accuracy -10% 10% k ttc timer multiplier 5.6 min /nf v ttc_low ttc low threshold ttc falling 0.4 v i ttc ttc source/sink current 45 50 55 a v ttc_osc_hi ttc oscillator high threshold 1.5 v v ttc_osc_lo ttc oscillator low threshold 1 v ac switch (revfet) driver v acdrv_reg gate drive voltage on revfet v acdrv -v cmsrc when v avcc > v uvlo 4 v battery detection t wake wake timer max time charge is enabled 500 ms i wake wake current rsense = 10 m 50 125 200 m a t discharge discharge timer max time discharge current is appl ied 1 sec i discharge discharge current 8 m a i fault fault current after a timeout fault 2 m a v wake wake threshold with respect to vreg to detect battery absent during wake measure on srn 100 mv/c ell v disch discharge threshold to detect battery absent during discharge measure on srn 2.9 v/cell internal pwm fsw pwm switching frequency 450 500 550 khz charger section power-up sequencing t ce_delay delay from iset above 120mv to start charging battery 1.5 s logic io pin characteristics v out_lo stat output low saturation voltage sink current = 5ma 0.5 v logic io pin characteristics v cell_lo cell pin input low threshold, 1 cell cell pin voltage falling edge 0.5 v input characteristics i off d+ off leakage current d+=5v 1 a i off d- off leakage current d-=5v 1 a output characteristics v ol flag1 maximum low output voltage v avcc =5v, i ol =20a 0.3 v
preliminary eup8218 ds8218 ver 0.1 mar. 2012 12 electrical characteristics (continued) 4.5v v(pvcc, avcc) 20v, C40c < t j <+ 125c, typical values are at t a = 25c, with respect to agnd (unless otherwise noted). eup8218 symbol parameter conditions min. typ. max. unit output characteristics d+/d- threshold 1.025 1.300 1.400 v t off flag1 high to low 100pf load 10 ns t on flag1 low to high 100pf load 50 ns truth table connection state v avcc d- d+ flag1 std usb device 5v r to gnd r to v ref high usb charger 5v short to d+ short to d- low
preliminary eup8218 ds8218 ver 0.1 mar. 2012 13 operational flow chart figure 3.
preliminary eup8218 ds8218 ver 0.1 mar. 2012 14 functional description battery current regulation the iset input sets the maximum charging current. battery current is sensed by current sensing resist or rsr connected between srp and srn. the full-scale differential voltage between srp and srn is 40mv ma x. the equation for charge current is: (1) the valid input voltage range of iset is up to 0.8v . with 10m sense resistor, the maximum output current is 4a. with 20m sense resistor, the maximum output current is 2a. the charger is disabled when iset pin voltage is be low 40mv and is enabled when iset pin voltage is above 120mv. for 10m current sensing resistor, the minimum fast charge current must be higher than 600ma. under high ambient temperature, the charge current will fold back to keep ic temperature not exceeding 120 c. battery precharge current regulation on power-up, if the battery voltage is below the vlowv threshold, the eup8218 applies the pre-charge current to the battery. this pre-charge feature is intended to revive deeply discharged cells. if the vlowv threshold is not reached within 30 minutes of initi ating pre-charge, the charger turns off and a fault is indicated on the status pins. for eup8218, the pre-charge current is set as 10% o f the fast charge rate set by iset voltage. (2) input current regulation the total input current from an ac adapter or other dc sources is a function of the system supply current and the battery charging current. system current normally fluctuated as portions of the systems are powered u p or down. without dynamic power management (dpm), the source must be able to supply the maximum system current and the maximum available charger input cur rent simultaneously. by using dpm, the input current regulator reduces the charging current when the summation of system power and charge power exceeds the maximum input power. therefore, the current capability of the ac adapter can be lowered, reduci ng system cost. input current is set by the voltage on acset pin us ing the following equation: (3) the acp and acn pins are used to sense across rac with default value of 20m . however, resistors of other values can also be used. a larger sense resistor wi ll give a larger sense voltage and higher regulation accura cy, at the expense of higher conduction loss. charge termination, recharge, and safety timers the charger monitors the charging current during th e voltage regulation phase. termination is detected w hen the srn voltage is higher than recharge threshold a nd the charge current is less than the termination cur rent threshold, as calculated below: (4) where v iset is the voltage on the iset pin and rsr is the sense resistor. there is a 25ms deglitch time d uring transition between fast-charge and pre-charge. as a safety backup, the charger also provides an in ternal fixed 30 minutes pre-charge safety timer and a programmable fast charge timer. the fast charge tim e is programmed by the capacitor connected between the ttc pin and agnd, and is given by the formula: (5) where c ttc is the capacitor connected to ttc and k ttc is the constant multiplier. a new charge cycle is initiated when one of the following conditions occurs: ? the battery voltage falls below the recharge thre shold ? a power-on-reset (por) event occurs ? iset pin toggled below 40mv (disable charge) and above 120mv (enable charge) pull ttc pin to agnd to disable both termination an d fast charge safety timer (reset timer). pull ttc pi n to vref to disable the safety timer, but allow charge termination. power up the charge uses a sleep comparator to determine the source of power on the avcc pin, since avcc can be supplied either from the battery or the adapter. wi th the adapter source present, if the avcc voltage is grea ter than the srn voltage, the charger exits sleep mode. if all conditions are met for charging, the charger th en starts charge the battery (see the enabling and disabling charging section). if srn voltage is greater than avcc, the charger enters low quiescent current sleep mode to minimize current drain from the battery. during sle ep mode, the vref output turns off and the stat pin go es to high impedance. if avcc is below the uvlo threshold, the device is disabled. sr iset charge r 20 v i = sr iset precharge r 200 v i = ac acset dpm r 20 v i = sr iset term r 200 v i = ttc ttc ttc k c t =
preliminary eup8218 ds8218 ver 0.1 mar. 2012 15 input under-voltage lock-out (uvlo) the system must have a minimum avcc voltage to allow proper operation. this avcc voltage could com e from either input adapter or battery, since a condu ction path exists from the battery to avcc through d2. wh en avcc is below the uvlo threshold, all circuits on t he ic are disabled. input over-voltage/under-voltage protection acov provides protection to prevent system damage due to high input voltage. in eup8218, once the vol tage on ovpset is above the 1.6v acov threshold or below the 0.5v acuv threshold, charge is disabled and inp ut mosfets turn off. the eup8218 provides flexibility to set the input qualification threshold. enable and disable charging the following conditions have to be valid before charging is enabled: ? iset pin above 120mv ?device is not in under-voltage-lock-out (uvlo) mode (i.e. v avcc > v uvlo ) ? device is not in sleep mode (i.e. v avcc > v srn ) ? ovpset voltage is between 0.5v and 1.6v to qualif y the adapter ? 1.5s delay is complete after initial power-up ? vref ldo voltages are at correct levels ? thermal shut down (tshut) is not valid ? ts fault is not detected ? revfet turns on (see system power selector for details) one of the following conditions stops on-going char ging: ? iset pin voltage is below 40mv ? device is in uvlo mode ? adapter is removed, causing the device to enter s leep mode ? ovpset voltage indicates the adapter is not valid ? vref ldo voltage is overloaded ? tshut temperature threshold is reached ? ts voltage goes out of range indicating the batte ry temperature is too hot or too cold ? revfet turns off ? ttc timer expires or pre-charge timer expires system power selector the ic automatically switches adapter or battery po wer to the system load. the battery is connected to the system by default during power up or during sleep mode. when the adapter plugs in and the voltage is above the battery voltage, the ic exits sleep mode, the adapt er supply the system and battery. when the adapter is absent, the battery supply the system. the acdrv is used to drive a n-channel power mosfets between adapter and acp. the n-channel fet with the drain connected to the acp (q1) provid es reverse battery discharge protection, and minimizes system power dissipation with its low-rds on . converter operation the eup8218 employs a 500khz constant-frequency step-down switching regulator. the fixed frequency oscillator keeps tight control of the switching fre quency under all conditions of input voltage, battery volt age, charge current, and temperature, simplifying output filter design and keeping it out of the audible noise regi on. both the current loop and the voltage loop share a common, high impedance, compensation node (comp pin). a series capacitor and resistor on this pin compensates both loops. the resistor is included to provide a zero in the loop response and boost the p hase margin. the compensation capacitor also provides a soft-start function for the charger. upon start-up, then ramp at a rate set by the internal 100 a pullup current source and the external capacitor. battery charge c urrent starts ramping up when the comp pin voltage reaches 0.85v. with a 2.2 f capacitor, time to start charge is about 18ms. capacitance can be increased if a longe r start-up time is needed. charge over-current protection the charger monitors top side mosfet current by hig h side sense fet. when peak current exceeds mosfet limit, it will turn off the top side mosfet and kee p it off until the next cycle. the charger has a seconda ry cycle-to-cycle over-current protection. it monitors the charge current, and prevents the current from excee ding 160% of the programmed charge current. the high-sid e gate drive turns off when either over-current condi tion is detected, and automatically resumes when the curren t falls below the over-current threshold. charge under-current protection after the recharge, if the srp-srn voltage decrease s below 5mv, the low side fet will be turned off for the rest of the switching cycle. during discontinuous conduction mode (dcm), the low side fet will only turn on for a short period of time when high side f et turn on every four times to provide refresh charge for the capacitor. this is important to prevent negative in ductor current from causing any boost effect in which the input voltage increases as power is transferred from the battery to the input capacitors. this can lead to an over-v oltage on the avcc node and potentially cause damage to th e system. battery detection for applications with removable battery packs, ic provides a battery absent detection scheme to relia bly detect insertion or removal of battery packs. the b attery detection routine runs on power up, or if battery v oltage falls below recharge threshold voltage due to remov ing a battery or discharging a battery.
preliminary eup8218 ds8218 ver 0.1 mar. 2012 16 figure 4. once the device has powered up, a 8-ma discharge current is applied to the srn terminal. if the batt ery voltage falls below the lowv threshold within 1 sec ond, the discharge source is turned off, and the charger is turned on at low charge current (125ma). if the bat tery voltage gets up above the recharge threshold within 500ms, there is no battery present and the cycle re starts. if either the 500ms or 1 second timer time out befo re the respective thresholds are hit, a battery is detecte d and a charge cycle is initiated. figure 5. battery detect timing diagram care must be taken that the total output capacitanc e at the battery node is not so large that the discharge cur rent source cannot pull the voltage below the lowv threshold during the 1 second discharge time. the maximum output capacitances can be calculated according to the following equations: (6) where c max is the maximum output capacitance, idisch is the discharge current, t disch is the discharge time. battery short protection when srn pin voltage is lower than 2v it is conside red as battery short condition during charging period. the charger will shut down immediately for 1ms, then so ft start back to the charging current the same as prec harge current. this prevents high current may build in ou tput inductor and cause inductor saturation when battery terminal is shorted during charging. the converter works in non-synchronous mode during battery short. battery over-voltage protection the converter will not allow the high-side fet to t urn-on until the battery voltage goes below 102% of the regulation voltage. this allows one-cycle response to an over-voltage condition C such as occurs when the lo ad is removed or the battery is disconnected. a total 6ma current sink from srp/srn to agnd allows discharging the stored output inductor energy that is transferred to the output capacitors. if battery over-voltage condition lasts for more than 30ms, ch arge is disabled. temperature qualification the controller continuously monitors battery temper ature by measuring the voltage between the ts pin and agn d. a negative temperature coefficient thermistor (ntc) and an external voltage divider typically develop this voltage. the controller compares this voltage against its in ternal thresholds to determine if charging is allowed. to initiate a charge cycle, the battery temperature must be within the v ltf to v htf thresholds. if battery temperature is outside of this range, the controlle r v 9.2 v 1.4 t i c disch disch max - =
preliminary eup8218 ds8218 ver 0.1 mar. 2012 17 suspends charge and waits until the battery tempera ture is within the v ltf to v htf range. during the charge cycle the battery temperature must be within the v ltf to v tco thresholds. if battery temperature is outside of th is range, the controller suspends charge and waits until the battery temperature is within the v ltf to v htf range. the controller suspends charge by turning off the pwm charge mosfetss. figure 6 summarizes the operation. figure 6. assuming a 103at ntc thermistor on the battery pack as shown in figure 7, the values of rt1 and rt2 can be determined by using equation 7 and equation 8: (7) (8) select 0c to 45c range for li-ion or li-polymer battery, rth cold = 27.28 k rth hot = 4.911 k rt1 = 5.23 k rt2 = 30.1 k after select closest standard resistor value, by ca lculating the thermistor resistance at temperature threshold, the final temperature range can be gotten from thermist or datasheet temperature-resistance table. figure 7. ts resistor network mosfet short circuit and inductor short circuit protection the ic has a short circuit protection feature. its cycle-by-cycle current monitoring feature is achiev ed through monitoring the voltage drop across rdson of the mosfets. the charger will be latched off, but the revfet keep on to power the system. the only way to reset the charger from latch-off status is remove a dapter then plug adapter in again. meanwhile, stat is blin king to report the fault condition. thermal regulation and shutdown protection the tqfn package has low thermal impedance, which provides good thermal conduction from the silicon t o the ambient, to keep junctions temperatures low. the in ternal thermal regulation loop will fold back the charge c urrent to keep the junction temperature from exceeding 120 c. as added level of protection, the charger converter turns off and self-protects whenever the junction tempera ture exceeds the tshut threshold of 150c. the charger stays off until the junction temperatur e falls below 130c. timer fault recovery the ic provides a recovery method to deal with time r fault conditions. the following summarizes this met hod: condition 1: the battery voltage is above the recha rge threshold and a timeout fault occurs. recovery method: the timer fault will clear when th e battery voltage falls below the recharge threshold, and battery detection will begin. a por or taking iset below 40mv will also clear the fault. condition 2: the battery voltage is below the recha rge threshold and a timeout fault occurs. recovery method: under this scenario, the ic applie s the fault current to the battery. this small current is used to detect a battery removal condition and remains on a s long as the battery voltage stays below the recharg e threshold. if the battery voltage goes above the re charge threshold, the ic disabled the fault current and ex ecutes the recovery method described in condition 1. a por or taking iset below 40mv will also clear the fault. ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? ? ?? ? - - - - = 1 ltf v vref v cold rth 1 tco v vref v hot rth tco v 1 ltf v 1 hot rth cold rth vref v 2 rt cold ltf vref rth 1 2 rt 1 1 v v 1 rt + - =
preliminary eup8218 ds8218 ver 0.1 mar. 2012 18 charge status outputs the open-drain stat outputs indicate various charge r operations as listed in table 1. these status pins can be used to drive leds or communicate with the host processor. note that off indicates that the open-dr ain transistor is turned off. table 1. stat pin definition charge state stat charge in progress (including recharging) on charge complete, sleep mode, charge disabled off charge suspend, input over-voltage, battery over-voltage, timer fault, , battery absent, otp, ts-fault, ocp_hsfet blink usb/charger detection eup8218 sets the flag1 pin to high or low to indica te whether a standard usb device or a charger is conne cted to the usb port. the d- line connects a 5m pull-dow n resistor to ground and d+ line connects a 1m push-u p resistor to vref. when a condition exists where a charger is plugged into the usb port (d+/d- short), the voltage divider of 1m and 5m comes out a voltage of 2.75v on the d+/d- inputs. this makes flag1 low, indicating a charger is connected to usb port. in this condition, m0 (as sh own in figure1 at page2) is not turn on, and the input current limit set by acset shall not change. in a condition where a standard usb device is plugg ed into the usb port, the d+ input is pull up to vref and d- input is pull low, which makes flag1 high. in th is condition, m0 is turn on, the voltage of acset chan ges accordingly. the input limit current is changed to a predetermined usb2 or usb3 limit current which can be set by resistor r5b (as shown in figure1 at page 2). inductor, capacitor, and sense resistor selection guidelines table 2 provides a summary of typical lc components for various charge currents. table 2. typical values as a function of charge current charge current 1a 2a 3a 4a output inductor l 6.8 h 6.8 h 3.3 h 2.2 h output capacitor c 10 f 20 f 20 f 30 f application information inductor selection the eup8218 has a 500-khz switching frequency to allow the use of small inductor and capacitor value s. inductor saturation current should be higher than t he charging current (i chg ) plus half the ripple current (i ripple ): (9) inductor ripple current depends on input voltage (v in ), duty cycle (d = v out /v in ), switching frequency (fs), and inductance (l): (10) the maximum inductor ripple current happens with d = 0.5 or close to 0.5. usually inductor ripple is des igned in the range of 20% to 40% of the maximum charging current as a trade-off between inductor size and efficiency for a practical design. inductor capacitor the input capacitor should have enough ripple curre nt rating to absorb input switching ripple current. th e worst case rms ripple current is half of the charging cur rent when duty cycle is 0.5. if the converter does not o perate at 50% duty cycle, then the worst case capacitor rm s current icin occurs where the duty cycle is closest to 50% and can be estimated by the following equation: (11) a low esr ceramic capacitor such as x7r or x5r is preferred for the input decoupling capacitor and sh ould be placed as close as possible to the drain of the high-side mosfet and source of the low-side mosfet. the voltage rating of the capacitor must be higher than the normal input voltage level. a 25v rating or hig her capacitor is preferred for a 15v input voltage. a 2 0 f capacitance is suggested for a typical 3a to 4a cha rging current. output capacitor the output capacitor also should have enough ripple current rating to absorb output switching ripple cu rrent. the output capacitor rms current icout is given as: (12) the output capacitor voltage ripple can be calculat ed as follows: (13) ( ) ripple chg sat i 2/1 i i + 3 ( ) l fs d 1 d v i in ripple - = ( ) d 1 d i i chg cin - = ripple ripple cout i 29.0 3 2 i i ? = ? ?? ? ? ?? ? - = d in out 2 out o v v 1 lcfs 8 v v
preliminary eup8218 ds8218 ver 0.1 mar. 2012 19 at certain input/output voltages and switching frequencies, the voltage ripple can be reduced by increasing the output filter lc. the eup8218 has an internal loop compensator. to achieve good loop stability, the resonant frequency of the output inductor and output capacitor should be desi gned between 15 khz and 25 khz. the preferred ceramic capacitor has a 25v or higher rating, x7r or x5r. input filter design during adapter hot plug-in, the parasitic inductanc e and the input capacitor from the adapter cable form a s econd order system. the voltage spike at the avcc pin may be beyond the ic maximum voltage rating and damage the ic. the input filter must be carefully designed and tested to prevent an over-voltage event on the avcc pin. there are several methods to damping or limiting th e over-voltage spike during adapter hot plug-in. an electrolytic capacitor with high esr as an input ca pacitor can damp the over-voltage spike well below the ic maximum pin voltage rating. a high current capabili ty tvs zener diode can also limit the over-voltage lev el to an ic safe level. however, these two solutions may not be lowest cost or smallest size. a cost effective and small size solution is shown i n figure 8. r1 and c1 are composed of a damping rc network to damp the hot plug-in oscillation. as a r esult, the over-voltage spike is limited to a safe level. d1 is used for reverse voltage protection for the avcc pi n. c2 is the avcc pin decoupling capacitor and it should be placed as close as possible to the avcc pin. r2 and c2 form a damping rc network to further protect the ic from high dv/dt and high voltage spike. the c2 valu e should be less than the c1 value so r1 can dominant the equivalent esr value to get enough damping effect f or hot plug-in. r1 and r2 must be sized enough to hand le in-rush current power loss according to the resisto r manufacturers datasheet. the filter component valu es always need to be verified with a real application and minor adjustments may be needed to fit in the real application circuit. figure 8. input filter input revfet n-type mosfets are used as input revfet(q1) for better cost effective and small size solution,as sh own in figure 9. there is a surge current during q1 turn-o n period when a valid adapter is inserted. decreasing the turn-on speed of q1 can limit this surge current in desirable range by selecting a mosfet with relative bigger c gd and/or c gs . at the case q1 turn on too fast, we need add external c gd and/or c gs . for example, 4.7nf c gd and 47nf c gs are adopted on evm while using nexfet csd17313 as q1. figure 9. input revfet
preliminary eup8218 ds8218 ver 0.1 mar. 2012 20 packaging information tqfn-28 millimeters inches symbols min. max. min. max. a 0.70 0.80 0.028 0.031 a1 0.00 0.05 0.000 0.002 b 0.15 0.25 0.006 0.010 e 3.90 4.10 0.154 0.162 d 3.90 4.10 0.154 0.162 d1 1.90 2.65 0.075 0.104 e1 1.90 2.65 0.075 0.104 e 0.40 bsc 0.016 bsc l 0.30 0.50 0.012 0.020

▲Up To Search▲

Price & Availability of EUP8218JIR1

	To Download EUP8218JIR1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .