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blackfin and the blackfi n logo are registered tradem arks of analog devices, inc. blackfin dual core embedded processor adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without no tice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106 u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com features dual-core symmetric high-performance blackfin processor, up to 500 mhz per core each core contains two 16-bit macs, two 40-bit alus, and a 40-bit barrel shifter risc-like register and instruction model for ease of ? programming and comp iler-friendly support advanced debug, trace, an d performance monitoring pipelined vision processor prov ides hardware to process sig- nal and image algorithms used for pre- and co-processing of video frames in adas or other video processing applications accepts a range of supply voltages for i/o operation. see operating conditions on page 52 off-chip voltage regulator interface 349-ball bga package (19 mm 19 mm), rohs compliant memory each core contains 148k bytes of l1 sram memory (proces- sor core-accessible) with multi-parity bit protection up to 256k bytes of l2 sram memory with ecc protection dynamic memory controller prov ides 16-bit interface to a single bank of ddr2 or lpddr dram devices static memory controller with asynchronous memory inter- face that supports 8-bit and 16-bit memories 4 memory-to-memory dma streams, 2 of which feature crc protection flexible booting options from flash, sd emmc and spi mem- ories and from spi, link port and uart hosts memory management unit provides memory protection figure 1. processor block diagram system control blocks peripherals hardware functions external bus interfaces lpddr ddr2 crc pipelined vision processor pixel compositor dma system 3 ppi 4 link port 2 emac with 2 ieee 1588 emmc/rsi 3 sport 2 spi 2 uart 1 can 8 timer 2 pwm 1 counter 2 twi usb 2.0 hs otg l2 memory 256k byte ecc- protected sram 32k byte rom 112 gp i/o flash sram emulator test & control pll & power management fault management event control dual watchdog core 1 148k byte parity bit protected l1 sram instruction/data b 1 acm 16 16 dynamic memory controller static memory controller video subsystem core 0 148k byte parity bit protected l1 sram instruction/data b
rev. 0 | page 2 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 blackfin processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 instruction set description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 processor infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 memory architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 video subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 processor safety features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 additional processor peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power and clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 system debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 additional information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 related signal chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 adsp-bf60x detailed signal descriptions . . . . . . . . . . . . . . . . . . . 19 349-ball csp_bga signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 23 gp i/o multiplexing for 349-ball csp_bga . . . . . . . . . . . . . . . . . 33 adsp-bf60x designer quick reference . . . . . . . . . . . . . . . . . . . . . . 37 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 processor absolute maximum ratings . . . . . . . . . . . . . . . . . . 58 esd sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 processor package information . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 output drive currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 environmental conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 adsp-bf60x 349-ball csp_bga ball assignments . . . . . . 103 349-ball csp_bga ball assignme nt (numerical by ball number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 349-ball csp_bga ball assignme nt (alphabetical by pin name) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 349-ball csp_bga ball configuration . . . . . . . . . . . . . . . . . . . 107 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 surface-mount design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 automotive products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 revision history 6/13revision 0: initial version. rev. 0 | page 3 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 general description the adsp-bf60x processors ar e members of the blackfin ? family of products, incorporat ing the analog devices/intel micro signal architecture (msa). blackfin processors combine a dual-mac state-of-the-art signal processing engine, the advantages of a clean, orthog onal risc-like microprocessor instruction set, and single-instruction, multiple-data (simd) multimedia capabili ties into a single instruction-set architecture. the processors offer performance up to 500 mhz, as well as low static power consumpt ion. produced with a low-power and low- voltage design methodology, th ey provide world-class power management and performance. by integrating a rich set of indu stry-leading system peripherals and memory (shown in table 1 ), blackfin processors are the platform of choice for next-gener ation applications that require risc-like programmability, multimedia support, and leading- edge signal processing in one in tegrated package. these applica- tions span a wide array of markets, from au tomotive systems to embedded industrial, instrumentation and power/motor con- trol applications. blackfin processor core as shown in figure 1 , the processor integrates two blackfin pro- cessor cores. each core, shown in figure 2, contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit alus, four video alus, and a 40-bit shifter. the computation units process 8-, 16-, or 32-bit data from the register file. the compute register file contai ns eight 32-bit registers. when performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. all operands for compute operations come from the multiported register file and instruction constant fields. each mac can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. signed and unsigned formats, rounding, and saturation ? are supported. the alus perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. in addition, many special instructions are included to acce lerate various signal processing tasks. these include bit operations such as field extract and pop- ulation count, modulo 2 32 multiply, divide primitives, saturation and rounding, and sign/exponent detection. the set of video instructions include byte alignment and packing operations, ? 16-bit and 8-bit adds with cli pping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (saa) operations. also provided are the compare/select and vector search instructions. for certain instructions, two 16-bit alu operations can be per- formed simultaneously on register pairs (a 16-bit high half and 16-bit low half of a co mpute register). if the second alu is used, quad 16-bit operations are possible. table 1. processor comparison processor feature adsp-bf606 adsp-bf607 ADSP-BF608 adsp-bf609 up/down/rotary counters 1 timer/counters with pwm 8 3-phase pwm units (4-pair) 2 sports 3 spis 2 usb otg 1 parallel peripheral interface 3 removable storage interface 1 can 1 twi 2 uart 2 adc control module (acm) 1 link ports 4 ethernet mac (ieee 1588) 2 pixel compositor (pixc) no 1 1 pipelined vision processor ? (pvp) video resolution 1 no vga hd maximum pvp line buffer size n/a 640 1280 gpios 112 memory (bytes, per core) l1 instruction sram 64k l1 instruction sram/cache 16k l1 data sram 32k l1 data sram/cache 32k l1 scratchpad 4k l2 data sram 128k 256k l2 boot rom 32k maximum speed grade (mhz) 2 400 500 maximum sysclk (mhz) 250 package options 349-ball csp_bga 1 vga is 640 480 pixels per frame. hd is 1280 960 pixels per frame. 2 maximum speed grade is not available with every possible sysclk selection. table 1. processor comparison (continued) processor feature adsp-bf606 adsp-bf607 ADSP-BF608 adsp-bf609 rev. 0 | page 4 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 the 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions. the program sequencer controls the flow of instruction execu- tion, including instruction alignment and decoding. for program flow control, the sequ encer supports pc relative and indirect conditional jumps (with static branch prediction), and subroutine calls. hardware supports zero-overhead looping. the architecture is fully interlocked, meaning that the program- mer need not manage the pipeline when executing instructions with data dependencies. the address arithmetic unit prov ides two addresses for simulta- neous dual fetches from memory. it contains a multiported register file consisti ng of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer regist ers (for c-style indexed stack manipulation). blackfin processors support a modified harvard architecture in combination with a hierarchical memory structure. level 1 (l1) memories are those that typically operate at the full processor speed with little or no latency. at the l1 level, the instruction memory holds instructions only. the data memory holds data, and a dedicated scratchpad data memory stores stack and local variable information. in addition, multiple l1 memory blocks are provided, offering a configurable mix of sram an d cache. the memory manage- ment unit (mmu) provides memory protection for individual tasks that may be oper ating on the core and can protect system registers from unintended access. the architecture provides three modes of operation: user mode, supervisor mode, and emulation mode. user mode has restricted access to certain syst em resources, thus providing a protected software environment, while supervisor mode has unrestricted access to the system and core resources. instruction set description the blackfin processor instruction set has been optimized so that 16-bit opcodes represent the most frequently used instruc- tions, resulting in excellent co mpiled code density. complex dsp instructions are encoded into 32-bit opcodes, representing fully featured multifunction inst ructions. blackfin processors support a limited multi-issue ca pability, where a 32-bit instruc- tion can be issued in parallel with two 16-bit instructions, allowing the programmer to use ma ny of the core resources in a single instruction cycle. the blackfin processor family a ssembly language instruction set employs an algebraic syntax designed for ease of coding and readability. the instructions have been specifically tuned to pro- vide a flexible, densely encoded instruction set that compiles to figure 2. blackfin processor core sequencer align decode loop buffer 16 16 8 88 8 40 40 a0 a1 barrel shifter data arithmetic unit control unit r7.h r6.h r5.h r4.h r3.h r2.h r1.h r0.h r7.l r6.l r5.l r4.l r3.l r2.l r1.l r0.l astat 40 40 32 32 32 32 32 32 32 ld0 ld1 sd dag0 dag1 address arithmetic unit i3 i2 i1 i0 l3 l2 l1 l0 b3 b2 b1 b0 m3 m2 m1 m0 sp fp p5 p4 p3 p2 p1 p0 da1 da0 32 32 32 preg rab 32 to memory rev. 0 | page 5 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 a very small final memory size. th e instruction set also provides fully featured multifunction instructions that allow the pro- grammer to use many of the proce ssor core resources in a single instruction. coupled with many features more often seen on microcontrollers, this instruction set is very efficient when com- piling c and c++ source code. in addition, the architecture supports both user (algorithm/app lication code) and supervisor (o/s kernel, device drivers, debuggers, isrs) modes of opera- tion, allowing multiple levels of access to core ? processor resources. the assembly language, which takes advantage of the proces- sors unique architecture, offe rs the following advantages: ? seamlessly integrated dsp/mcu features are optimized for both 8-bit and 16-bit operations. ? a multi-issue load/store modified-harvard architecture, which supports two 16-bit mac or four 8-bit alu + two load/store + two pointer updates per cycle. ? all registers, i/o, and memory are mapped into a unified 4g byte memory space, prov iding a simplified program- ming model. ? control of all asynchronous and synchronous events to the processor is handled by two subsystems: the core event controller (cec) and the syst em event controller (sec). ? microcontroller features, such as arbitrary bit and bit-field manipulation, insertion, and ex traction; integer operations on 8-, 16-, and 32-bit data-typ es; and separate user and supervisor stack pointers. ? code density enhancements, wh ich include intermixing of 16-bit and 32-bit instructions (n o mode switching, no code segregation). frequently used instructions are encoded ? in 16 bits. processor infrastructure the following sections provide information on the primary infrastructure components of the adsp-bf609 processor. dma controllers the processor uses direct memo ry access (dma) to transfer data within memory spaces or between a memory space and a peripheral. the processor can spec ify data transfer operations and return to normal processing while the fully integrated dma controller carries out the data transfers independent of proces- sor activity. dma transfers can occur between memory and a peripheral or between one memory and another memory. each memory-to- memory dma stream uses two ch annels, where one channel is the source channel, and the second is the destination channel. all dmas can transport data to and from all on-chip and off- chip memories. programs can use two types of dma transfers, descriptor-based or register-bas ed. register-based dma allows the processor to directly progra m dma control registers to ini- tiate a dma transfer. on comple tion, the control registers may be automatically updated with their original setup values for continuous transfer. descriptor -based dma transfers require a set of parameters stored with in memory to initiate a dma sequence. descriptor-based dm a transfers allow multiple dma sequences to be chained together and a dma channel can be programmed to automatically set up and start another dma transfer after the curr ent sequence completes. the dma controller supports th e following dma operations. ? a single linear buffer th at stops on completion. ? a linear buffer with negative, positive or zero stride length. ? a circular, auto-refreshing buffer that interrupts when each buffer becomes full. ? a similar buffer that interrupts on fractional buffers (for example, 1/2, 1/4). ? 1d dma C uses a set of identical ping-pong buffers defined by a linked ring of two-word descriptor sets, each contain- ing a link pointer and an address. ? 1d dma C uses a linked list of 4 word descriptor sets con- taining a link pointer, an address, a length, and a configuration. ? 2d dma C uses an array of on e-word descriptor sets, spec- ifying only the base dma address. ? 2d dma C uses a linked list of multi-word descriptor sets, specifying everything. crc protection the two crc protection modules a llow system software to peri- odically calculate the signature of code and/or data in memory, the content of memory-mapped registers, or communication message objects. dedicated hard ware circuitry compares the signature with pre calculated values and triggers appropriate fault events. for example, every 100 ms the system software might initiate the signature calculation of the entire memory contents and compare these contents with expected, pre calculated values. if a mismatch occurs, a fault condit ion can be generated (via the processor core or the trigger routing unit). the crc is a hardware module based on a crc32 engine that computes the crc value of the 32-bit data words presented to it. data is provided by the source channel of the memory-to- memory dma (in memory scan mode) and is optionally for- warded to the destination chan nel (memory transfer mode). the main features of the crc peripheral are: ?memory scan mode ?memory transfer mode ?data verify mode ? data fill mode ? user-programmable crc32 polynomial ? bit/byte mirroring option (endianness) ? fault/error interrupt mechanisms ? 1d and 2d fill block to initialize array with constants. ? 32-bit crc signature of a block of a memory or mmr block. rev. 0 | page 6 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 event handling the processor provides event handling that supports both nest- ing and prioritization. nesting allows multiple event service routines to be active simultaneously. prioritization ensures that servicing of a higher-priority event takes precedence over ser- vicing of a lower-priority event. the processor provides support for five different types of events: ? emulation C an emulation ev ent causes the processor to enter emulation mode, allowing command and control of the processor via the jtag interface. ? reset C this event resets the processor. ? nonmaskable interrupt (nmi ) C the nmi event can be generated either by the software watchdog timer, by the nmi input signal to the proce ssor, or by software. the nmi event is frequently used as a power-down indicator to initiate an orderly sh utdown of the system. ? exceptions C events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). conditions such as data alignment violations and undefined instructions cause exceptions. ? interrupts C events that occur asynchronously to program flow. they are caused by inpu t signals, timers, and other peripherals, as well as by an explicit software instruction. core event controller (cec) the cec supports nine general-purpose interrupts (ivg15C7), in addition to the dedicated interrupt and exception events. of these general-purpose interrupts, the two lowest-priority interrupts (ivg15C14) are recomm ended to be reserved for software interrupt handlers. fo r more information, see the adsp-bf60x processor pr ogrammers reference. system event controller (sec) the sec manages the en abling, prioritization, and routing of events from each system interrup t or fault source. additionally, it provides notification and identi fication of the highest priority active system interrupt request to each core and routes system fault sources to its integrated fault management unit. trigger routing unit (tru) the tru provides system-level sequence control without core intervention. the tru maps trigge r masters (generators of trig- gers) to trigger slaves (receivers of triggers). slave endpoints can be configured to respond to tr iggers in various ways. common applications enabled by the tru include: ? automatically triggering the start of a dma sequence after a sequence from another dma channel completes ?software triggering ? synchronization of concurrent activities pin interrupts every port pin on the processor ca n request interrupts in either an edge-sensitive or a level-se nsitive manner with programma- ble polarity. interrupt functionality is decoupled from gpio operation. six system-level in terrupt channels (pint0C5) are reserved for this purpose. each of these interrupt channels can manage up to 32 interrupt pins. the assignment from pin to interrupt is not performed on a pi n-by-pin basis. rather, groups of eight pins (half ports) can be flexibly assigned to interrupt channels. every pin interrupt channel features a special set of 32-bit mem- ory-mapped registers that enab le half-port assignment and interrupt management. this includes masking, identification, and clearing of requests. these registers also enable access to the respective pin states and use of the interrupt latches, regardless of whether the interrupt is masked or not. most control registers feature multiple mmr address en tries to write-one-to-set or write-one-to-clear them individually. general-purpose i/o (gpio) each general-purpose port pin ca n be individually controlled by manipulation of the port control, status, and interrupt registers: ? gpio direction control register C specifies the direction of each individual gpio pin as input or output. ? gpio control and status regi sters C a write one to mod- ify mechanism allows any combination of individual gpio pins to be modified in a single instruction, without affecting the level of any other gpio pins. ? gpio interrupt mask register s C allow each individual gpio pin to function as an interrupt to the processor. gpio pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. ? gpio interrupt sensitivity registers C specify whether indi- vidual pins are level- or edge-sensitive and specifyif edge-sensitivewhether just the rising edge or both the ris- ing and falling edges of th e signal are significant. pin multiplexing the processor supports a flexible multiplexing scheme that mul- tiplexes the gpio pins with various peripherals. a maximum of 4 peripherals plus gpio function ality is shared by each gpio pin. all gpio pins ha ve a bypass path feature C that is, when the output enable and the input enable of a gpio pin are both active, the data signal before the pad driver is looped back to the receive path for the same gpio pin. for more information, see gp i/o multiplexing for 349-ball csp_bga on page 33. memory architecture the processor views memory as a single unified 4g byte address space, using 32-bit addresses. a ll resources, including internal memory, external memory, and i/o control registers, occupy separate sections of this common address space. the memory portions of this address space are arranged in a hierarchical structure to provide a good cost /performance balance of some very fast, low-latency core-acc essible memory as cache or sram, and larger, lower-cost an d performance interface-acces- sible memory systems. see figure 3 and figure 4 . rev. 0 | page 7 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 figure 3. adsp-bf606 internal/external memory map rev. 0 | page 8 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 figure 4. adsp-bf607/ADSP-BF608/adsp-bf609 internal/external memory map rev. 0 | page 9 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 internal (core-accessible) memory the l1 memory system is th e highest-performance memory available to the blackf in processor cores. each core has its own private l1 memory. the modified har- vard architecture supports two concurrent 32-bit data accesses along with an instruction fetc h at full processor speed which provides high bandwidth processo r performance. in each core a 64k-byte block of data memory partners with an 80k-byte memory block for instruction storage. each data block is multi- banked for efficient data exchange through dma and can be configured as sram. alternativel y, 16k bytes of each block can be configured in l1 cache mode . the four-way set-associative instruction cache and the 2 two-wa y set-associative data caches greatly accelerate memory access performance, especially when accessing external memories. the l1 memory domain also fe atures a 4k-byte scratchpad sram block which is ideal for storing local va riables and the software stack. all l1 memory is protected by a multi-parity bit concept, regardless of whether the memory is operating in sram or cache mode. outside of the l1 domain, l2 and l3 memories are arranged using a von neumann topology. the l2 memory domain is a unified instruction and data memory and can hold any mixture of code and data required by the system design. the l2 memory domain is accessible by both blackfin cores through a dedicated 64-bit interface. it operates at sysclk frequency. the processor features up to 256k bytes of l2 sram which is ecc-protected and organized in eight banks. individual banks can be made private to any of the cores or the dma subsystem. there is also a 32k-byte single-bank rom in the l2 domain. it contains boot code and safety functions. static memory controller (smc) the smc can be programmed to control up to four banks of external memories or memory-ma pped devices, with very flexi- ble timing parameters. each bank occupies a 64m byte segment regardless of the size of the devi ce used, so that these banks are only contiguous if each is fu lly populated with 64m bytes of memory. dynamic memory controller (dmc) the dmc includes a controller that supports jesd79-2e com- patible double data rate ( ddr2) sdram and jesd209a low power ddr (lpddr) sdram devices. i/o memory space the processor does not define a separate i/o space. all resources are mapped through the fl at 32-bit address space. on- chip i/o devices have their cont rol registers mapped into mem- ory-mapped registers (mmrs) at addresses near the top of the 4g byte address space. these are separated into two smaller blocks, one which contains the control mmrs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. the mmrs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. booting the processor has several mechan isms for automatically loading internal and external memory after a reset. the boot mode is defined by the sys_bmode input pins dedicated for this pur- pose. there are two categories of boot modes. in master boot modes, the processor actively load s data from parallel or serial memories. in slave boot modes, the processor receives data from external host devices. the boot modes are shown in table 2 . these modes are imple- mented by the sys_bmode bits of the reset configuration register and are sampled during power-on resets and software- initiated resets. video subsystem the following sections describe the components of the proces- sors video subsystem. these blocks are shown with blue shading in figure 1 on page 1 . video interconnect (vid) the video interconnect provides a connectivity matrix that interconnects the video subsystem: three ppis, the pixc, and the pvp. the interconnect uses a protocol to manage data transfer among these video peripherals. pipelined vision processor (pvp) the pvp engine provides hardware implementation of signal and image processing algorithms that are required for ? co-processing and pre-processing of monochrome video frames in adas applications, robotic systems, and other machine applications. the pvp works in conjunction with the blackfin cores. it is optimized for convolution and wavelet based object detection and classification, and tracking and verification algorithms. the pvp has the following processing blocks. ? four 5 5 16-bit convolution bl ocks optionally followed by down scaling ? a 16-bit cartesian-to-polar coordinate conversion block ? a pixel edge classifier that supports 1st and 2nd derivative modes ? an arithmetic unit with 32-bit addition, multiply and divide table 2. boot modes sys_bmode setting boot mode 000 no boot/idle 001 memory 010 rsi0 master 011 spi0 master 100 spi0 slave 101 reserved 110 lp0 slave 111 uart0 slave rev. 0 | page 10 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 ? a 32-bit threshold block with 16 thresholds, a histogram, and run-length encoding ? two 32-bit integral blocks that support regular and diago- nal integrals ? an up- and down-scaling unit with independent scaling ratios for horizontal and vertical components ? input and output formatters for compatibility with many data formats, including bayer input format the pvp can form a pipe of all the constituent algorithmic modules and is dynamically reconfigurable to form different pipeline structures. the pvp supports the simultaneous processing of up to four data streams. the me mory pipe stream operates on data received by dma from any l1, l2, or l3 memory. the three camera pipe streams operate on a common input received directly from any of the three ppi inputs. optionally, the pixc can convert color data received by the ppi and forward luma values to the pvps monochrome engine. each stream has a dedicated dma output. this pr eprocessing concept ensures careful use of available power and bandwidth budgets and frees up the processor cores for other tasks. the pvp provides for direct core mmr access to all control/sta- tus registers. two hardware inte rrupts interface to the system event controller. for optimal perf ormance, the pvp allows reg- ister programming through its control dma interface, as well as outputting selected status re gisters through the status dma interface. this mechanism enables the pvp to automatically process job lists completely inde pendent of the blackfin cores. pixel compositor (pixc) the pixel compositor (pixc) provides image overlays with transparent-color support, alpha blending, and color space con- version capabilities for output to tft lcds and ntsc/pal video encoders. it provides all of the control to allow two data streams from two separate da ta buffers to be combined, blended, and converted into appropriate forms for both lcd panels and digital video outputs. the main image buffer pro- vides the basic backgr ound image, which is presented in the data stream. the over lay image buffer allows the user to add multiple foreground text, graphi cs, or video objects on top of the main image or video data stream. parallel peripheral interface (ppi) the processor provides up to thre e parallel peripheral interfaces (ppis), supporting data widths up to 24 bits. the ppi supports direct connection to tft lcd pa nels, parallel analog-to-digital and digital-to-analog converters, video encoders and decoders, image sensor modules and othe r general-purpose peripherals. the following features are supported in the ppi module: ? programmable data length: 8 bits, 10 bits, 12 bits, 14 bits, 16 bits, 18 bits, and 24 bits per clock. ? various framed, non-framed, and general-purpose operat- ing modes. frame syncs can be generated internally or can be supplied by an external device. ? itu-656 status word error de tection and correction for itu-656 receive modes and it u-656 preamble and status word decode. ? optional packing and unpackin g of data to/from 32 bits from/to 8 bits, 16 bits and 24 bi ts. if packing/unpacking is enabled, endianness can be configured to change the order of packing/unpackin g of bytes/words. ? rgb888 can be converted to rgb666 or rgb565 for trans- mit modes. ?various de-interleaving/inte rleaving modes for receiv- ing/transmitting 4:2:2 ycrcb data. ?configurable lcd data enable (den) output available on frame sync 3. processor safety features the adsp-bf60x processor has be en designed for functional safety applications. while the level of safety is mainly domi- nated by the system concept, the following primitives are provided by the devices to bu ild a robust safety concept. dual core supervision the processor has been implemented as dual-core devices to separate critical task s to large independency. software models support mutual supervision of th e cores in symmetrical fashion. multi-parity-bit-protected l1 memories in the processors l1 memory sp ace, whether sram or cache, each word is protected by multiple parity bits to detect the single event upsets that occur in all rams. this applies both to l1 instruction and data memory spaces. ecc-protected l2 memories error correcting codes (ecc) are used to correct single event upsets. the l2 memory is protected with a single error correct- double error detect (sec-ded ) code. by default ecc is enabled, but it can be disabled on a per-bank basis. single-bit errors are transparently corrected. dual-bit errors can issue a system event or fault if enabled. ecc protection is fully trans- parent to the user, even if l2 memory is read or written by 8-bit or 16-bit entities. crc-protected memories while parity bit and ecc protecti on mainly protect against ran- dom soft errors in l1 and l2 memory cells, the crc engines can be used to protect against system atic errors (pointer errors) and static content (instruction code ) of l1, l2 and even l3 memo- ries (ddr2, lpddr). the processors feature two crc engines which are embedded in the me mory-to-memory dma control- lers. crc check sums can be calc ulated or compared on the fly during memory transfers, or one or multiple memory regions can be continuously scrubbed by single dma work unit as per dma descriptor chain instructio ns. the crc engine also pro- tects data loaded during the boot process. rev. 0 | page 11 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 memory protection the blackfin cores feature a memo ry protection concept, which grants data and/or instruction accesses from enabled memory regions only. a supervisor mode vs. user mode programming model supports dynamically varying access rights. increased flexibility in memory page si ze options supports a simple method of static memory partitioning. system protection all system resources and l2 memo ry banks can be controlled by either the processor cores, me mory-to-memory dma, or the system debug unit (sdu). a system protection unit (spu) enables write accesses to specific resources that are locked to any of four masters: core 0, core 1, memory dma, and the sys- tem debug unit. system protec tion is enabled in greater granularity for some modules (l2, sec and gpio controllers) through a global lock concept. watchpoint protection the primary purpose of watchpoints and hardware breakpoints is to serve emulator needs. when enabled, they signal an emula- tor event whenever user-defined system resources are accessed or a core executes from user -defined addresses. watchdog events can be configured such that they signal the events to the other blackfin core or to the fault management unit. dual watchdog the two on-chip watchdog timers each may supervise one blackfin core. bandwidth monitor all dma channels that operate in memory-to-memory mode (memory dma, pvp memory pipe dma, pixc dma) are equipped with a bandwidth monitor mechanism. they can sig- nal a system event or fault when transactions tend to starve because system buses are fully loaded with higher-priority traffic. signal watchdogs the eight general-purpose timers feature two new modes to monitor off-chip signals. the watchdog period mode monitors whether external signals toggle with a period within an expected range. the watchdog width mode monitors whether the pulse widths of external signals are in an expected range. both modes help to detect incorrect undesired toggling (or lack thereof) of ? system-level signals. up/down count mismatch detection the up/down counter can monitor external signal pairs, such as request/grant strobes. if the ed ge count mismatch exceeds the expected range, the up/down counte r can flag this to the proces- sor or to the fault management unit. fault management the fault management unit is part of the system event controller (sec). any system event, whether a dual-bit uncorrectable ecc error, or any peripheral status interrupt, can be defined as being a fault. additionally, the system events can be defined as an interrupt to the cores. if define d as such, the sec forwards the event to the fault management unit which may automatically reset the entire device for reb oot, or simply toggle the sys_ fault output pins to signal off-chip hardware. optionally, the fault management unit can delay the action taken via a keyed sequence, to provide a final chan ce for the blackfin cores to resolve the crisis and to prevent the fault action from being taken. additional processor peripherals the processor contains a rich set of peripherals connected to the core via several high-bandwidth buses, providing flexibility in system configuration as well as excellent overall system perfor- mance (see the block diagram on page 1 ). the processors contain high-speed serial and pa rallel ports, an interrupt con- troller for flexible management of interrupts from the on-chip peripherals or external sources, and power management control functions to tailor the performance and power characteristics of the processor and system to many application scenarios. the following sections describe additional peripherals that were not described in the previous sections. timers the processor includes several ti mers which are described in the following sections. general-purpose timers there is one gp timer unit and it provides eight general-pur- pose programmable timers. each timer has an external pin that can be configured either as a pulse width modulator (pwm) or timer output, as an input to clock the timer, or as a mechanism for measuring pulse widths and periods of external events. these timers can be synchronized to an external clock input on the tmrx pins, an external clock tmrclk input pin, or to the internal sclk0. the timer units can be used in conjunction with the uarts and the can controller to measure the width of the pulses in the data stream to provide a software auto-baud detect function for the respective serial channels. the timers can generate interrupts to the processor core, pro- viding periodic events for synchr onization to either the system clock or to external signals. timer events can also trigger other peripherals via the tru (for instance, to signal a fault). core timers each processor core al so has its own dedicated timer. this extra timer is clocked by the internal processor clock and is typically used as a system tick clock fo r generating periodic operating system interrupts. watchd og timers each core includes a 32-bit time r, which may be used to imple- ment a software watchdog function. a software watchdog can improve system availabi lity by forcing the processor to a known state, via generation of a hardwa re reset, nonmaskable interrupt (nmi), or general-purpose interrup t, if the timer expires before rev. 0 | page 12 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 being reset by software. the pr ogrammer initializes the count value of the timer, enables the appropriate interrupt, then enables the timer. thereafter, the software must reload the counter before it counts to ze ro from the programmed value. this protects the system from remaining in an unknown state where software, which would no rmally reset the timer, has stopped running due to an external noise condition or software error. after a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a status bit in the timer control register, which is set only upon a watchdog gener- ated reset. 3-phase pwm units the pulse width modulator (pwm ) module is a flexible and programmable wavefo rm generator. with minimal cpu inter- vention the pwm peripheral is capable of generating complex waveforms for motor control, pulse coded modulation (pcm), digital to analog conversion (dac), power switching and power conversion. the pwm modu le has 4 pwm pairs capable of 3-phase pwm generation for source inverters for ac induc- tion and dc brush less motors. the two 3-phase pwm generation units each feature: ? 16-bit center-based pwm generation unit ?programmable pwm pulse width ? single update mode with option for asymmetric duty ? programmable dead time and switching frequency ? twos-complement implementation which permits smooth transition to full on and full off states ? dedicated asynchronous pwm shutdown signal link ports four dma-enabled, 8-bit-wide link ports can connect to the link ports of other dsps or pr ocessors. link ports are bidirec- tional ports having eight data lines, an acknowledge line and a clock line. serial ports (sports) three synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral devices such as analog devices ad183x family of audio codecs, adcs, and dacs. the serial port s are made up of two data lines, a clock, and frame sync. the data lines can be pro- grammed to either transmit or receive and each data line has a dedicated dma channel. serial port data can be automa tically transferred to and from on-chip memory/external memory via dedicated dma chan- nels. each of the serial ports can work in conjunction with another serial port to provide tdm support. in this configura- tion, one sport provides two transmit signals while the other sport provides the two receive signals. the frame sync and clock are shared. serial ports operate in five modes: ? standard dsp serial mode ?multichannel (tdm) mode ?i 2 s mode ?packed i 2 s mode ? left-justified mode acm interface the adc control module (acm) provides an interface that synchronizes the controls betwee n the processor and an analog- to-digital converter (adc). the analog-to-digital conversions are initiated by the processor, based on external or internal events. the acm allows for flexible sche duling of sampling instants and provides precise sampling signals to the adc. figure 5 shows how to connect an external adc to the acm and one of the sports. the acm synchronizes the adc conversion process, generat- ing the adc controls, the adc conversion start signal, and other signals. the actual data acquisition from the adc is done by a peripheral such as a sport or a spi. the processor interfaces direct ly to many adcs without any glue logic required. general-purpose counters a 32-bit counter is provided that can operate in general-pur- pose up/down count modes and ca n sense 2-bit quadrature or binary codes as typically emitted by industrial drives or manual thumbwheels. count direction is either controlled by a level- sensitive input pin or by two edge detectors. figure 5. adc, acm, and sport connections sportx spt_ad1 spt_ad0 spt_clk spt_fs adc d out b d out a adsclk cs range sgl/diff a[2:0] acm acm_fs acm_clk acm_a4 acm_a3 acm_a[2:0] adsp-bf60x sport select mux rev. 0 | page 13 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 a third counter input can provide flexible zero marker support and can alternatively be used to input the push-button signal of thumb wheels. all three pins have a programmable debouncing circuit. internal signals forwarded to ea ch general-purpos e timer enable these timers to measure the intervals between count events. boundary registers enable auto-z ero operation or simple system warning by interrupts when programmable count values are exceeded. serial peripheral interface (spi) ports the processors have two spi-co mpatible ports that allow the processor to communicate with multiple spi-compatible devices. in its simplest mode, the spi inte rface uses three pins for trans- ferring data: two data pins (master output-slave input, mosi, and master input-slave output, miso) and a clock pin (serial clock, spi_clk). a spi chip select input pin (spi_ss ) lets other spi devices select the processor, and seven spi chip select out- put pins (spi_sel7C1 ) let the processor select other spi devices. the spi select pins are reconfig ured general-purpose i/o pins. using these pins, the spi port provides a full-duplex, synchro- nous serial interface, which su pports both master/slave modes and multimaster environments. in a multi-master or multi-slave spi system, the mosi and miso data output pins can be configured to behave as open drain outputs (using the odm bi t) to prevent contention and possible damage to pin drivers. an external pull-up resistor is required on both the mosi and mi so pins when this option is selected. when odm is set and the spi is configured as a master, the mosi pin is three-stated when the data driven out on mosi is a logic-high. the mosi pin is not three-stated when the driven data is a logic-low. similarly, when odm is set and the spi is configured as a slave, the miso pin is three-stated if the data driven out on miso is a logic-high. the spi ports baud rate and clock phase/polarities are pro- grammable, and it has integrated dma channels for both transmit and receive data streams. uart ports the processors provide two full -duplex universa l asynchronous receiver/transmitter (uart) port s, which are fully compatible with pc-standard uarts. each uart port prov ides a simpli- fied uart interface to other pe ripherals or hosts, supporting full-duplex, dma-supported, asynch ronous transfers of serial data. a uart port includes support for five to eight data bits, and none, even, or odd parity. op tionally, an additional address bit can be transferred to inte rrupt only addressed nodes in multi-drop bus (mdb) systems. a frame is terminates by one, one and a half, two or two and a half stop bits. the uart ports support automatic hardware flow control through the clear to send (cts) input and request to send (rts) output with programmab le assertion fifo levels. to help support the local inte rconnect network (lin) proto- cols, a special command causes th e transmitter to queue a break command of programmable bit leng th into the transmit buffer. similarly, the number of stop bits can be extended by a pro- grammable inter-frame space. the capabilities of the uarts are further extended with sup- port for the infrared data association (irda?) serial infrared physical layer link specification (sir) protocol. twi controller interface the processors include a 2-wire interface (twi) module for providing a simple exchange method of control data between multiple devices. the twi modu le is compatible with the widely used i 2 c bus standard. the tw i module offers the capabilities of simultaneous master and slave operation and support for both 7-bit addressing and multimedia data arbitra- tion. the twi interface utilizes two pins for transferring clock (twi_scl) and data (twi_sda) and supports the protocol at speeds up to 400k bits/sec. the twi interface pins are compati- ble with 5 v logic levels. additionally, the twi module is fully compatible with serial camera control bus (sccb) functionality for easier control of various cmos camera sensor devices. removable storage interface (rsi) the removable storage interface (r si) controller acts as the host interface for multimedia cards (mmc), secure digital memory cards (sd), secure digital inpu t/output cards (sdio). the fol- lowing list describes the main features of the rsi controller. ? support for a single mmc , sd memory, sdio card ? support for 1-bit and 4-bit sd modes ? support for 1-bit, 4-bit, and 8-bit mmc modes ? support for emmc 4.3 embedded nand flash devices ? a ten-signal external interf ace with clock, command, and up to eight data lines ? card interface clock generation from sclk0 ? sdio interrupt and read wait features controller area network (can) a can controller implements the can 2.0b (active) protocol. this protocol is an asynchronous communications protocol used in both industrial and au tomotive control systems. the can protocol is well suited for control applications due to its capability to communicate reliab ly over a network. this is because the protocol incorporat es crc checking, message error tracking, and fault node confinement. the can controller offers the following features: ? 32 mailboxes (8 receive only , 8 transmit only, 16 configu- rable for receive or transmit). ? dedicated acceptance masks for each mailbox. ? additional data filtering on first two bytes. ? support for both the standard (11-bit) and extended (29- bit) identifier (i d) message formats. rev. 0 | page 14 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 ? support for remote frames. ? active or passive network support. ? can wakeup from hibernation mode (lowest static power consumption mode). ? interrupts, including: tx complete, rx complete, error and global. an additional crystal is not required to supply the can clock, as the can clock is derived from a system clock through a pro- grammable divider. 10/100 ethernet mac the processor can directly connec t to a network by way of an embedded fast ethernet media access controller (mac) that supports both 10-baset (10m bits/sec) and 100-baset (100m bits/sec) operation. the 10/100 ethernet mac peripheral on the processor is fully compliant to the ieee 802.3-2002 standard and it provides programmable features designed to minimize supervision, bus use, or message processing by the rest of the processor system. some standard features are: ? support and rmii protocols for external phys ? full duplex and half duplex modes ? media access management (in half-duplex operation) ? flow control ? station management: generation of mdc/mdio frames for read-write access to phy registers some advanced features are: ? automatic checksum computat ion of ip header and ip payload fields of rx frames ? independent 32-bit descriptor-driven receive and transmit dma channels ? frame status delivery to me mory through dma, including frame completion semaphores for efficient buffer queue management in software ? tx dma support for separate descriptors for mac header and payload to eliminate buffer copy operations ? convenient frame alignment modes ? 47 mac management statistics counters with selectable clear-on-read behavi or and programmable interrupts on half maximum value ? advanced power management ? magic packet detection and wakeup frame filtering ? support for 802.3q tagged vlan frames ? programmable mdc clock rate and preamble suppression ieee 1588 support the ieee 1588 standard is a precision clock synchronization protocol for networked measurem ent and control systems. the processor includes hardware support for ieee 1588 with an integrated precision time protocol synchronization engine (ptp_tsync). this engine prov ides hardware assisted time stamping to improve the accuracy of clock synchronization between ptp nodes. the main features of the engine are: ? support for both ieee 1588-2002 and ieee 1588-2008 pro- tocol standards ? hardware assisted ti me stamping capable of up to 12.5 ns resolution ? lock adjustment ? automatic detection of ipv4 and ipv6 packets, as well as ptp messages ? multiple input clock sources (sclk0, rmii clock, external clock) ? programmable pulse per second (pps) output ? auxiliary snapshot to time stamp external events usb 2.0 on-the-go dual-r ole device controller the usb 2.0 otg dual-role device controller provides a low- cost connectivity solution for th e growing adoption of this bus standard in industrial applications, as well as consumer mobile devices such as cell phones, digi tal still cameras, and mp3 play- ers. the usb 2.0 controller allows these devices to transfer data using a point-to-point usb conn ection without the need for a pc host. the module can operat e in a traditional usb periph- eral-only mode as well as the host mode presented in the on- the-go (otg) supplement to the usb 2.0 specification. the usb clock (usb_clkin) is provided through a dedicated external crystal or crystal oscillator. the usb on-the-go dual-role device controller includes a phase locked loop with programm able multipliers to generate the necessary internal clocking frequency for usb. power and clock management the processor provides four operating modes, each with a dif- ferent performance/power profil e. when configured for a 0 v internal supply voltage (v dd_int ), the processor enters the hiber- nate state. control of clocki ng to each of the processor peripherals also reduces power consumption. see table 5 for a summary of the power se ttings for each mode. crystal oscillator (sys_xtal) the processor can be clocked by an external crystal, ( figure 6) a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external clock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the specified fr equency during normal opera- tion. this signal is connecte d to the processors sys_clkin pin. when an external clock is used, the sys_xtal pin must be left unconnected. alternatively, because the processor includes an on-chip oscillator circuit, an external crystal may be used. for fundamental frequency operat ion, use the circuit shown in figure 6 . a parallel-resonant, fundamental frequency, micro- processor grade crystal is conn ected across the sys_clkin and xtal pins. the on-chip resistance between sys_clkin and the xtal pin is in the 500 k ra nge. further parallel resistors are typically not recommended. rev. 0 | page 15 of 112 | june 2013 adsp-bf606/adsp-bf607/ADSP-BF608/adsp-bf609 the two capacitors and the series resistor shown in figure 6 fine tune phase and amplitude of the sine frequency. the capacitor and resistor va lues shown in figure 6 are typical values only. the capacitor values are dependent upon the crystal manufac- turers load capacitance recommendations and the pcb physical layout. the resistor value depends on the drive level specified by the crystal manufacturer. the user should verify the customized values based on careful investigat ions on multiple devices over temperature range. a third-overtone crystal can be used for frequencies above ? 25 mhz. the circuit is then modified to ensure crystal operation only at the third overtone by ad ding a tuned inductor circuit as shown in figure 6 . a design procedure fo r third-overtone oper- ation is discussed in detail in application note (ee-168) using third overtone crystals with the adsp-218x dsp on the ana- log devices website (www.analog.com)use site search on ? ee-168. usb crystal oscillator the usb can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock derived from an external clock oscillator. if an external cl ock is used, it should be a ttl compatible signal and must not be halted, changed, or operated below the specified frequency during normal operation. this signal is connected to the proc essors usb_xtal pin. alterna- tively, because the processor in cludes an on-chip oscillator circuit, an external crystal may be used. for fundamental frequency operat ion, use the circuit shown in figure 7 . a parallel-resonant, fund amental frequency, micro- processor grade crystal is connected between the usb_xtal pin and ground. a load capacitor is placed in parallel with the crystal. the combined capacitive value of the board trace para- sitic, the case capacitance of the crystal (from crystal manufacturer) and the parallel ca pacitor in the diagram should be in the range of 8 pf to 15 pf. the crystal should be chosen so that its rated load capacitance matches the nominal total capacitance on this node. a series resistor may be added between the usb_xtal pin and the par- allel crystal and capacitor comb ination, in order to further reduce the drive level of the crystal. the parallel capacitor and the series resistor shown in figure 7 fine tune phase and amplitude of the sine frequency. the capac- itor and resistor values shown in figure 7 are typical values only. the capacitor values are dependent upon the crystal man- ufacturers load capacitance recommendations and the pcb physical layout. the resistor va lue depends on the drive level specified by the crystal manufact urer. the user should verify the customized values based on careful investigations on multiple devices over temperature range. clock generation the clock generation unit (cgu ) generates all on-chip clocks and synchronization signals. mu ltiplication factors are pro- grammed to the pll to define the pllclk frequency. programmable values divide the pllclk frequency to generate the core clock (cclk), the syst em clocks (sysclk, sclk0 and sclk1), the lpddr or ddr2 cl ock (dclk) and the output clock (oclk). this is illustrated in figure 8 on page 53 . writing to the cgu control registers does not affect the behav- ior of the pll immediately. regi sters are first programmed with a new value, and the pll logic ex ecutes the changes so that it transitions smoothly from the current conditions to the new ones. sys_clkin oscillations start when power is applied to the v dd_ ext pins. the rising edge of sys_hwrst can be applied after all voltage supplies are within specifications (see operating condi- tions on page 52 ), and sys_clkin oscillations are stable. clock out/external clock the sys_clkout output pin has programmable options to output divided-down versions of the on-chip clocks. by default, the sys_clkout pin drives a buffered version of the sys_ clkin input. clock generation faults (for example pll unlock) may trigger a reset by hard ware. the clocks shown in table 3 can be outputs from sys_clkout. figure 6. external crystal connection sys_clkin to pll circuitry for overtone operation only: note: values marked with * must be customized, depending on the crystal and layout. please analyze carefully. for frequencies above 33 mhz, the suggested capacitor value of 18pf should be treated as a maximum, and the suggested 5 ( 6 , 6 7 2 5 9 $ / 8 ( 6 + 2 8 / ' % ( 5 ( ' 8 & |