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enpirion ? power datasheet ep5388qi 800ma powersoc synchronous buck regulator with integrated inductor product overview the ep5388qi is a synchronous buck converter with integrated inductor, pwm controller, mosfets, and compensation providing the smallest possible solution size. the ep5388qi requires only two small mlcc capacitors to make a complete solution. integration of the inductor greatly simplifies design, contains noise, reduces part count, and reduces solution footprint. low output ripple ensures compatibility with rf syste ms. the ep5388qi operates at a switching frequency of 4 mhz, enabling this unprecedented level of integration and small external components. type iii voltage mode control is used to provide high noise immunity and wide control loop bandwidth. the sma ll footprint makes this part ideal for space constrained portable applications. shutdown current of <1ua extends battery life output voltage level is programmed via a 3 - pin vid selector providing seven pre - programmed output voltages along with an option f or external resistor divider. applications ? noise sensitive rf applications ? area constrained applications ? wireless data applications ? portable gaming devices ? personal media players ? advanced mobile processors, dsp, io, memory, video, multimedia engines ordering information part number temp rating (c) package ep53 8 8qi - 40 to +85 16 - pin qfn t&r evb - e p 53 8 8 qi ep53 8 8qi evaluation board product highlights featuring integrated inductor technology ? 3mm x 3mm x 1. 1mm qfn package ? only two low cost mlcc caps required ? 4 mhz switching frequency ? high efficiency, up to 94% ? up to 8 00ma continuous output current ? wide 2.4v to 5.5v input range ? v out range 0.6v to v in ? 0. 5v ? 3- pin vid output voltage programming ? 100% duty cycle capable ? less than 1 a standby current ? low v out ripple for rf compatibility ? short circuit and over current protection ? uvlo and thermal protection ? rohs compliant; msl 3 260c reflow typical application circuit v in v sense v in v s1 v s2 v s0 ep 5388 qi 47uf 1206 4.7 f 0603 v out v out gnd enable v fb voltage select figure 1 . typical application circuit. www.altera.com/enpirion page 1 02377 october 11, 2013 rev d
ep5388qi pin description figure 2 . ep5388qi package pin - out . pin name function 1, 15, 16 nc(sw) no connect. these pins are internally connected to the common drain output of the internal mosfets. nc(sw) pins are not to be electrically connected to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or damage. 2,3 pgnd power ground 4 vfb feed back pin for external divider option. when using the external divider option (vs0=vs1=vs2= high) connect this pin to the center of the external divider. set the divider such that v fb = 0.6v. the ?ground? side of the external divider should be connected to agnd 5 vsense sense pin for preset output voltages. refer to application section for proper configuration 6 agnd analog ground. this is the quiet ground for the internal control circuitry 7,8 vout regulated output voltage. refer to application section for proper layout and decoupling. 9 nc no connect. this pin should not be electrically connected to any external signal, voltage, or ground. this pin may be connected internally. however, this pin must be soldered to the pcb. 10, 11, 12 vs0,vs1,vs2 output voltage select. vs2=pin10 vs1=pin11, vs0=pin12. selects one of seven preset output voltages or choose external divider by con necting pins to logic high or low. (refer to section on output voltage select for more detail). 13 enable output enable. enable = logic high, disable = logic low. 14 vin input voltag e pin. refer www.altera.com/enpirion page 2 02377 october 11, 2013 rev d
ep5388qi functional block diagram voltage select dac switch vref (+) (-) error amp v sense v fb v out vs0 vs1 vs2 package boundry p-drive n-drive uvlo thermal limit current limit soft start sawtooth generator (+) (-) pwm comp v in enable gnd logic compensation network nc(sw) figure 3. functional block diagram. www.altera.com/enpirion page 3 02377 october 11, 2013 rev d
ep5388qi absolute maximum ratings caution: absolute maximum ratings are stress ratings only. functional operation beyond recommended operating conditions is not implied. stress beyond absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. parameter symbol min m ax units input supply voltage v in - 0.3 7.0 v voltages on: enable, v sense , v s0 - v s2 - 0.3 v in + 0.3 v voltage on: v fb - 0.3 2.7 v storage temperature range t stg - 65 150 c reflow temp, 10 sec, msl3 jedec j - std - 020c 260 c esd rating (based on human body model) 2000 v recommended operating conditions parameter symbol min m ax units input voltage range v in 2.4 5.5 v output voltage range v out 0.603 v in ? 0.5 v output current i out 0 800 ma operating ambient temperature t a - 40 +85 c operating junction temperature t j - 40 +125 c thermal characteristics parameter symbol typ units thermal resistance: junction to ambient (0 lfm) ja 100 c/w thermal overload trip point t j - tp +150 c thermal overload trip point hysteresis 15 c electrical characteristics note: t a = - 40c to +85c unless otherwise noted. typical values are at t a = 25c, vin = 3.6v. c in = 4.7 p f 0603 mlc c , c ou t = 47uf 1206 mlc c. parameter sym bol test conditions min typ max units v out initial accuracy ' v out initl t a = 25c, 2.4v d v in d 5.5v - 2% +2% line regulation ' v out_linel 2.4v d v in d 5.5v 0.0566 %/v load regulation ' v out_load 0a d i load d 800ma 0.0003 %/ ma temperature variation ' v out templ - 40 c d t a d +85 c 0.0078 %/ c overall v out accuracy (line, load, and temperature combined) ' v out _all 2.4v d v in d 5.5v - 40c d t a d +85 c 0a d i load d 800ma - 3% +3% dropout resistance r drop ou t 4 0 0 500 m : dynamic voltage slew rate v slew 0.975 1.5 2.025 v/ ms continuous output current i out - 20c d t a d +85c - 40c d t a d +85c 8 00 750 ma shut - down current i sd enable = low 0.75 p a pfet ocp threshold i lim 1000 m a feedback pin voltage v fb 0.6 03 v feedback pin input current i fb 100 na www.altera.com/enpirion page 4 02377 october 11, 2013 rev d
ep5388qi parameter sym bol test conditions min typ max units vs0 - vs1, enable voltage threshold v th pin = low pin = high 0.0 1.4 0.4 v in vs0 - vs2 pin input current i vsx 1 na operating frequency f osc 4 mhz pfet on resistance r ds(on) 340 m ? ? soft - start operation soft - start slew rate v ss vid programming mode 0.975 1.5 2.025 v/ms v out rise time t ss vfb programming mode 0. 784 1. 2 1.628 ms typical performance characteristics efficiency , v in = 3. 3 v, v out = 1.2v, 1.5v, 1.8v, 2.5v . efficiency , v in = 3.7v, v out = 1.2v, 1.5v,1.8v, 2.5v . efficiency , v in = 5 v, v out = 1.2v, 1.5v,1.8v, 2.5v , 3.3v . output ripple , v in = 5 v, v out = 1.2v; load = 500ma. 50 55 60 65 70 75 80 85 90 95 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 load current (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 load current (a) efficiency (%) 50 55 60 65 70 75 80 85 90 95 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 load current (a) efficiency (%) www.altera.com/enpirion page 5 02377 october 11, 2013 rev d
ep5388qi output ripple , v in = 5 v, v out = 1.8v; load = 500ma. output ripple , v in = 5 v, v out = 2.5 v ; load = 500ma. output ripple , v in = 5 v, v out = 3.3 v ; load = 500ma. output ripple , v in = 3.3 v, v out = 1.2v; load = 500ma. output ripple , v in = 3.3 v, v out = 1.8 v ; load = 500ma. output ripple , v in = 3.3 v, v out = 2.5 v ; load = 500ma. www.altera.com/enpirion page 6 02377 october 11, 2013 rev d
ep5388qi transient, v in = 5.0 v, v out = 1.2v, load = 0 -8 00ma . transient, v in = 5.0 v, v out = 3.3 v, load = 0 -8 00ma . transient, v in = 3.3 v, v out = 1.2v, load = 0 -8 00ma . transient, v in = 3.3 v, v out = 1.8 v, load = 0 -8 00ma . startup, v in = 3.6v, v out = 1.5v, load = 500ma . shutdown , v in = 3.6v, v out = 1.5v, load = 500ma . enable in light blue; vout in dark blue. enable in light blue; vout in dark blue. www.altera.com/enpirion page 7 02377 october 11, 2013 rev d
ep5388qi detailed description functional overview the ep5388qi is a complete dcdc converter solution requiring only two low cost mlcc capacitors. mosfet switches, pwm controller, gate - drive, compensation, and inductor are integrated into the tiny 3mm x 3mm x 1. 1 mm package to provide the smallest footprint possible w hile maintaining high efficiency, low ripple, and high performance. the converter uses voltage mode control to provide the simplest implementation and high noise immunity. the device operates at a 4mhz switching frequency. the high switching frequency allows for a wide control loop bandwidth providing excellent transient performance. the high switching frequency further enables the use of very small components making possible this unprecedented level of integration. altera ?s proprietary power mosfet techno logy provides very low switching loss at frequencies of 4 mhz and higher, allowing for the use of very small internal components, and high performance. integration of the magnetics virtually eliminates the design/layout issues normally associated with swi tch - mode dcdc converters. all of this enables much easier and faster incorporation into various applications to meet demanding emi requirements. output voltage is chosen from seven preset values via a three pin vid voltage select scheme. an external div ider option enables the selection of any voltage in v in to 0.6v range. this reduces the number of components that must be qualified and reduces inventory burden. the vid pins can be toggled on the fly to implement glitch free dynamic voltage scaling. pro tection features include under - voltage lock - out (uvlo), over - current protection (ocp), short circuit protection, and thermal overload protection. integrated inductor altera has introduced the world?s first product family featuring integrated inductors. the ep5388qi utilizes a proprietary low loss integrated inductor. the use of an internal inductor localizes the noises associated with the output loop currents. the inherent shielding and compact construction of the integrated inductor reduces the radiate d noise that couples into the traces of the circuit board. further, the package layout is optimized to reduce the electrical path length for the ac ripple currents that are a major source of radiated emissions from dcdc converters. the integrated inducto r significantly reduces parasitic effects that can harm loop stability, and makes layout very simple. stable over wide range of operating conditions the ep53 8 8qi utilizes an internal type iii compensation network and is designed to provide a high degree o f stability over a wide range of operating conditions. the device operates over the entire input and output voltage range with no external modifications required. the very high switching frequency allows for a very wide control loop bandwidth. soft start internal soft start circuits limit in - rush current when the device starts up from a power down condition or when the ?enable? pin is asserted ?high?. digital control circuitry limits the v out ramp rate to levels that are safe for the power mosfets and th e integrated inductor. the ep53 8 8qi has two soft start operating modes. when vout is programmed using a preset voltage in vid mode, the device has a constant slew rate. when the ep53 8 8q i is configured in external resistor divider mode, the device has a c onstant vout ramp time. www.altera.com/enpirion page 8 02377 october 11, 2013 rev d
ep5388qi output voltage slew rate and ramp time is given in the electrical characteristics table. excess bulk capacitance on the output of the device can cause an over - current condition at startup. when operating in vid mode, the maximum total capacitance on the output, including the output filter capacitor and bulk and decoupling capacitance, at the load, is given as: c out_total_max = c out _fi lter + c out _bulk = 700uf when the ep53 8 8qi output voltage is programmed using and external resistor divider the maximum total capacitance on the output is given as: c out_total_max = 1.2 51 x10 -3 /v out farads the above number and formula assume a no load condition at startup. over current/short circuit protection the current limit function is achieved by sensing the current flowing through a sense p - mosfet which is compared to a reference current. when this level is exceeded the p - fet is turned off and the n - fet is turned on, pulling v out low. this condition is maintained for a period of 1ms and then a normal soft start is initiated. if the over current condition still persists, this cycle will repeat in a ? hiccup ? mode. under voltage lockout during initial power up an under voltage lockout circuit will hold - off the switching circuitry until the input voltage reaches a sufficient level to insure proper operation. if the voltage drops below the uvlo threshold the lockout circuitry will again disable the switching. hysteresis is included to prevent chattering between states. enable the enabl e pin provides a means to shut down the converter or enable normal operation. a logic low will disable the converter and cause it to shut down. a logic high will enable the converter into normal operation. in shutdown mode, the device quiescent current wi ll be less than 1 ua. note: this pin must not be left floating. thermal shutdown when excessive power is dissipated in the chip, the junction temperature rises. once the junction temperature exceeds the thermal shutdown temperature the thermal shutdown circuit turns off the converter output voltage thus allowing the device to cool. when the junction temperature decreases by 15c , the device will go through the normal startup process. application information output voltage select to provide the highest degree of flexibility in choosing output voltage, the ep5388qi uses a 3 pin vid, or voltage id, output voltage select arrangement. this allows the designer to choose one of seven preset voltages, or to use an externa l voltage divider. internally, the output of the vid multiplexer sets the value for the voltage reference dac, which in turn is connected to the non - inverting input of the error amplifier. this allows the use of a single feedback divider with constant loop gain and optimum compensation, independent of the output voltage selected. table 1 shows the various vs0 - vs2 pin logic states and the associated output voltage levels. a logic ?1? indicates a connection to v in or to a ?high? logic voltage level. a lo gic ?0? indicates a connection to ground or to a ?low? logic voltage level. these pins can be either hardwired to v in or gnd or alternatively can be driven by standard logic levels. logic low is www.altera.com/enpirion page 9 02377 october 11, 2013 rev d
ep5388qi defined as v low 0.4v. logic high is defined as v high 1 .4v. any level between these two values is indeterminate. these pins must not be left floating. vs2 vs1 vs0 v out 0 0 0 3.3v 0 0 1 2.5v 0 1 0 1.8v 0 1 1 1.5v 1 0 0 1.25v 1 0 1 1.2v 1 1 0 0.8v 1 1 1 user selectable external voltage divider as described above, the external voltage divider option is chosen by connecting the vs0, vs1, and vs2 pins to vin or logic ?high?. the ep5388qi uses a separate feedback pin, v fb , when using the external divider. vsense must be connected to v out as indicated in figure 4. v in v sense v in v s1 v s2 v s0 ep 5388 qi 47 f 1206 4.7 uf 0603 v out v out gnd enable ra rb v fb figure 4. external divider application circuit . the output voltage is selected by the following formula: ( ) rb ra out v v + = 1603.0 r a must be chosen as 200k ? to maintain loop gain. then r b is given as: ? ? = 603.0 10206.1 5 out b v x r v out can be programmed over the range of 0.6v to v in -0. 5v. dynamically adjustable output the ep5388qi is designed to allow for dynamic switching between the predefi ned vid voltage levels . the inter - voltage slew rate is optimized to prevent excess undershoot or overshoot as the output voltage levels transition. the slew rate is identical to the soft - start slew rate of 1.5v/ms. dynamic transitioning between internal vid settings and the external divider is not allowed. power - up /down sequencing during power - up, enable should not be asserted before vin . during power down, the vin should not be powered down before the enable . tying pvin and enable together during power - up or power - down meets this requirement . pre - bias start - up the ep5388qi does not support startup into a pre - biased condition. be sure the output capacitors are not charged or the output of the ep5388qi is not pre - biased when the ep5388qi is first enabled. input and output capacitors the input capacitance requirement is 4.7uf 0603 ml cc . altera recommends that a low esr mlcc capacitor be used. the input capacitor must use a x5r or x7r or equivalent dielectric formulation. y5v or equivalent dielectric formul ations lose capacitance with frequency, bias, and with temperature, and are not suitable for switch - mode dc - dc converter input filter applications. a variety of output capacitor configurations are possible depending on footprint and ripple requirements . for applications where v in range is up to 5 .5 v, it is recommended to use a single 47uf 1206 ml c c capacitor. ripple performance can be improved by using 2 x 22 uf 0805 mlc c capacitors. table 1 . vid voltage select settings. www.altera.com/enpirion page 10 02377 october 11, 2013 rev d
ep5388qi a single 10uf 0805 mlcc can be used if v out programming is accomplished using an external divider, with the addition of a 10pf phase lead capacitor as shown in figure 5. note that in this configuration, v sense should not be connected to v out . as described in the soft start section, there is a limi tation on the maximum bulk capacitance that can be placed on the output of this device. please refer to that section for more details. the output capacitor must use a x5r or x7r or equivalent dielectric formulation. y5v or equivalent dielectric formulations lose capacitance with frequency, bias, and temperature and are not suitable for switch - mode dc - dc converter output filter applications. v in v sense v in v s1 v s2 v s0 ep 5388 qi 10 f 0805 4.7 uf 0603 v out v out gnd enable ra rb v fb 10pf figure 5. ap plications circuit for c out = 1 x 10uf 0805 . layout considerations* *optimized pcb layout file is downloadable from the altera website to assure first pass design success. refer to figure 6 for the following layout recommendations. recommendation 1: the input and output filter c apacitors should be placed as close to the ep5388qi as possible to reduce emi from input and output loop ac currents. this reduces the physical area of these ac current loops. recommendation 2: the system ground plane should be the first layer immediate ly below the surface layer (pcb layer 2). if it is not possible to make pcb layer 2 the system ground plane, a local ground island should be created on pcb layer 2 under the altera enpirion device and including the area under the input and output filter c apacitors. this ground plane, or ground island, should be continuous and uninterrupted underneath the altera enpirion device and the input and output filter capacitors. recommendation 3 : the surface layer ground pour should include a ?slit? as shown in figure 6 to separate the input and output ac loop currents. this will help reduce noise coupling from the input current loop to the output current loop. recommendation 4 : multiple small vias (approximately 0.25mm finished diameter) should be used to co nnect the ground terminals of the input and output capacitors, and the surface ground pour under the device, to the system ground plane. if a local ground island is used on pcb layer 2, the vias should connect to the ground island and continue down to the pcb system ground plane. recommendation 5: the agnd pin should be connected to the system ground plane using a via as described in recommendation 4. agnd must not be connected to the surface layer ground pour. recommendation 6: as with any switch - mod e dc - dc converter, do not run any sensitive signal or control lines under the converter package. www.altera.com/enpirion page 11 02377 october 11, 2013 rev d
ep5388qi figure 6 . pcb layout recommendation. recommended pcb footprint figure 7 . recommended pcb footprint. www.altera.com/enpirion page 12 02377 october 11, 2013 rev d
ep5388qi package dimensions figure 8. ep5388qi package dimensions. contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 408 -544-7000 www.altera.com ? 2013 altera corporation ? confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. altera warrants performance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. www.altera.com/enpirion page 13 02377 october 11, 2013 rev d

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