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engineering specification type 14.1 xga color tft/lcd module model name:IAXG15S document control number : oem i-915s-01 note:specification is subject to change without notice. consequently it is better to contact to international display technology before proceeding with the design of your product incorporating this module. sales support international display technology engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 1/27
i contents i contents ii record of revision 1.0 handling precautions 2.0 general description 2.1 characteristics 2.2 functional block diagram 3.0 absolute maximum ratings 4.0 optical characteristics 5.0 signal interface 5.1 connectors 5.2 interface signal connector 5.3 interface signal description 5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver 5.4.2 lvds receiver internal circuit 5.4.3 recommended guidelines for motherboard pcb design and cable selection 5.5 signal for lamp connector 6.0 pixel format image 7.0 parameter guide line for cfl inverter 8.0 interface timings 8.1 timing characteristics 8.2 timing definition 9.0 power consumption 10.0 power on/off sequence 11.0 mechanical characteristics 12.0 national test lab requirement engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 2/27
ii record of revision first edition for customer. based on internal spec. as of august 7,2002. (cable length : 25mm) all oem i-915s-01 november 5,2002 summary page document revision date engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 3/27
1.0 handling precautions if any signals or power lines deviate from the power on/off sequence, it may cause shorten the life of the lcd module. the lcd panel and the cfl are made of glass and may break or crack if dropped on a hard surface, so please handle them with care. cmos ics are included in the lcd panel. they should be handled with care, to prevent electrostatic discharge. do not press the reflector sheet at the lcd module to any directions. do not stick the adhesive tape on the reflector sheet at the back of the lcd module. please handle with care when mount in the system cover. mechanical damage for lamp cable/lamp connector may cause safety problems. small amount of materials having no flammability grade is used in the lcd module. the lcd module should be supplied by power complied with requirements of limited power source (2.5, iec60950 or ul60950), or be applied exemption conditions of flammability requirements (4.7.3.4, iec60950 or ul60950) in an end product. the lcd module is designed so that the cfl in it is supplied by limited current circuit (2.4, iec60950 or ul60950). the fluorescent lamp in the liquid crystal display(lcd) contains mercury. do not put it in trash that is disposed of in landfills. dispose of it as required by local ordinances or regulations. never apply detergent or other liquid directly to the screen. wipe off water drop immediately. long contact with water may cause discoloration or spots. when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents or abrasives. do not touch the front screen surface in your system, even bezel. gently wipe the covers and the screen with a soft cloth. the information contained herein may be changed without prior notice. it is therefore advisable to contact international display technology before proceeding with the design of equipment incorporating this product. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by international display technology for any infringements of patents or other right of the third partied which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of international display technology or others. engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 4/27
2.0 general description this specification applies to the type 14.1 color tft/lcd module 'IAXG15S'. this module is designed for a display unit of a notebook style personal computer. the screen format and electrical interface are intended to support the xga (1024(h) x 768(v)) screen. support color is native 262k colors ( rgb 6-bit data driver ). all input signals are lvds(low voltage differential signaling) interface compatible. this module does not contain an inverter card for backlight. 2.1 characteristics the following items are characteristics summary on the table under 25 degree c condition: 0 to +50 (operating) -20 to +60 (storage, shipping) temperature range [deg. c] native 262k colors ( rgb 6-bit data driver ) support color 4 pairs lvds(r/g/b data (6-bit), 3 sync signals, clock) electrical interface 25mm ccfl cable length [mm] 299.0(w) x 226.5(h) x 5.2(d) typ. physical size [mm] 380 min., 400 typ.,420 max. weight [grams] 3.8 typ.(@cfl current 6.0ma without inverter loss) backlight power consumption [watt] 1.2 typ. (vdd)(all black pattern) logic power consumption [watt] +3.3 typ. (+3.0 to +3.6:vdd) nominal input voltage [volt] 45 typ. , 50 max. optical rise time+fall time [msec] 200 : 1 typ. contrast ratio 150 typ. (center) @ cfl current =6.0ma white luminance [cd/m 2 ] normally white display mode r.g.b. vertical stripe pixel arrangement 0.279(per one triad) x 0.279 pixel pitch [mm] 1024(x3) x 768 pixels h x v [pixels] 285.7(h) x 214.3(v) active area [mm] 35.7 screen diagonal [cm] specifications characteristics items engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 5/27
2.2 functional block diagram the following diagram shows the functional block of the type 14.1 color tft/lcd module. tft array/cell vdd lcd controller lcd drive card backlight unit 1024(r/g/b) x 768 gnd dc-dc converter ref circuit y-driver x-driver <4 pairs lvds> rxin1 rxin0 rxin2 rxclkin fi-xb30sl-hf10 bhsr-02vs-1 (jst) ccfl high voltate ccfl low voltage signal connector ccfl connector vdd vdd vdd engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 6/27
3.0 absolute maximum ratings absolute maximum ratings of the module is as follows : rectangle wave g ms 50 18 shock g hz 1.5 10-200 vibration (note 2) %rh 95 5 hst storage relative humidity (note 2) deg.c +60 -20 tst storage temperature (note 2) %rh 95 8 hop operating relative humidity (note 2) deg.c +50 0 top operating temperature ta = 25 [deg.c] (note 1) marms 20 - icflp cfl peak inrush current marms 7 - icfl cfl current ta = 0 [deg.c] vrms +1,650 - vcfl lamp ignition voltage v vdd+0.3 -0.3 other inputs input voltage of signal v +4.0 -0.3 vdd supply voltage conditions unit max min s y mbol item note : 1. duration : 50 [msec] max. 2. maximum wet-bulb should be 39 degree c and no condensation. engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 7/27
4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 degree c condition: - 150typ. center 140typ. 5 points average white luminance (cd/m 2 ) icfl 6.0 ma - 0.329 white y - 0.313 white x - 0.124 blue y - 0.158 blue x - 0.544 green y - 0.310 green x (cie) - 0.338 red y chromaticity - 0.577 red x color (ms) 50 max. 45 rising + falling response time - 200 contrast ratio - - 15 30 vertical (upper) k 10 (lower) k:contrast ratio - - 40 40 horizontal (right) k 10 (left) viewing angle (degrees) note typ. specification conditions item anti glare treatment : display surface treatment of this lcd module is nitto denko arc150t. engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 8/27
5.0 signal interface 5.1 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. fi-x30m, fi-x30c2l mating type / part number fi-xb30sl-hf10 type / part number jae manufacturer for signal connector connector name / designation sm02b-bhss-1 mating type / part number bhsr-02vs-1 type / part number jst manufacturer for lamp connector connector name / designation engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 9/27
5.2 interface signal connector signal connector pin assignment fg (gnd) 32 rxin2+ (note 2) 16 reserved (note 1) 31 rxin2- (note 2) 15 reserved (note 1) 30 gnd 14 gnd 29 rxin1+ (note 2) 13 reserved (note 1) 28 rxin1- (note 2) 12 reserved (note 1) 27 gnd 11 gnd 26 rxin0+ (note 2) 10 reserved (note 1) 25 rxin0- (note 2) 9 reserved (note 1) 24 reserved (note 1) 8 gnd 23 reserved (note 1) 7 reserved (note 1) 22 reserved (note 1) 6 reserved (note 1) 21 reserved (note 1) 5 gnd 20 vdd 4 rxclkin+ (note 2) 19 vdd 3 rxclkin- (note 2) 18 gnd 2 gnd 17 fg (gnd) 1 signal name pin # signal name pin # note : 1. 'reserved' pins are not allowed to connect any other line. 2. voltage levels of all input signals are lvds compatible. refer to "signal electrical characteristics for lvds", for voltage levels of all input signals. engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 10/27
5.3 interface signal description signal description ground gnd +3.3v power supply vdd lvds differential clock input rxclkin+, rxclkin- lvds differential data input (blue2-blue5, hsync, vsync, dsptmg) rxin2+, rxin2- lvds differential data input (green1-green5,blue0-blue1) rxin1+, rxin1- lvds differential data input (red0-red5, green0) rxin0+, rxin0- description signal name note : the module uses a 100ohm resistor between positive and negative data lines of each receiver input. input signals shall be low or hi-z state when vdd is off. engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 11/27
the signal is synchronized to -dtclk . horizontal sync hsync the signal is synchronized to -dtclk . vertical sync vsync this signal is strobed at te falling edge of -dtclk. when the signal is high, the pixel data shall be valid to be displayed. display timing dsptmg the typical frequency is 65.0 mhz. the signal is used to strobe the pixel data and dsptmg signals. all pixel data shall be valid at the falling edge when the dsptmg signal is high. data clock -dtclk blue-pixel data each blue pixel's brightness data consists of these 6 bits pixel data. blue data 5 (msb) blue data 4 blue data 3 blue data 2 blue data 1 blue data 0 (lsb) +blue 5 +blue 4 +blue 3 +blue 2 +blue 1 +blue 0 green-pixel data each green pixel's brightness data consists of these 6 bits pixel data. green data 5 (msb) green data 4 green data 3 green data 2 green data 1 green data 0 (lsb) +green 5 +green 4 +green 3 +green 2 +green 1 +green 0 red-pixel data each red pixel's brightness data consists of these 6 bits pixel data. red data 5 (msb) red data 4 red data 3 red data 2 red data 1 red data 0 (lsb) +red5 +red4 +red3 +red2 +red1 +red0 description signal name note : output signals from any system shall be low or hi-z state when vdd is off. engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 12/27
5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver the lvds receiver equipped in this lcd module is compatible with ansi/tia/tia-644 standard. electrical characteristics vth - vtl = 200mv mv +50 -50 vcm common mode voltage offset vth - vtl = 200mv v 1.4 1.2 1.0 vcm common mode voltage mv 600 100 |vid| magnitude differential input voltage vcm=+1.2v mv -100 vtl differential input low threshold vcm=+1.2v mv +100 vth differential input high threshold conditions unit max typ min symbol parameter note : input signals shall be low or hi-z state when vdd is off. all electrical characteristics for lvds signal are defined and shall be measured at the interface connector of lcd. voltage definitions engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 13/27
timming requirements fc = 65mhz, tsu=thd=900ps ps/clk 20 tcjavg cycle modulation rate (note 4) fc = 65mhz, tsu=thd=900ps ps +150 -150 tccj cycle-to-cycle jitter (note 3) ps 600 thd data hold time (note 2) fc = 65mhz, tccj < 50ps, vth-vtl = 400mv, vcm = 1.2v, vcm = 0 ps 600 tsu data setup time (note 1) ns 20.00 15.38 14.93 tc cycle time mhz 67 65 50 fc clock frequency conditions unit max typ min symbol parameter note : 1. all values are at vdd=3.3v, ta=25 degree c. 2. see figure " timing definition " and " timing definition(detail a) " for definition. 3. jitter is the magnitude of the change in input clock period. 4. this specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100 clock cycles. figure " cycle modulation rate " illustrates a case against this requirement. this specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps. timing definition engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 14/27
timing definition(detail a) note: tsu and thd are internal data sampling window of receiver. trskm is the system skew margin; i.e., the sum of cable skew, source clock jitter, and other inter-symbol interference, shall be less than trskm. cycle modulation rate engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 15/27
5.4.2 lvds receiver internal circuit the following figure shows the internal block diagram of the lvds receiver. this lcd module equips termination resistors for lvds link. 5.4.3 recommended guidelines for motherboard pcb design and cable selection following the suggestions below will help to achieve optimal results. use controlled impedance media for lvds signals. they should have a matched differential impedance of 100ohm. match electrical lengths between traces to minimize signal skew. isolate ttl signals from lvds signals. for cables, twisted pair, twinax, or flex circuit with close coupled differential traces are recommended. engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 16/27
5.5 signal for lamp connector lamp low voltage 2 lamp high voltage 1 signal name pin # engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 17/27
6.0 pixel format image following figure shows the relationship of the input signals and lcd pixel format image. even and odd pair of rgb data are sampled at a time . 0 r 1 1022 1023 1st line 768th line g b r g r g b b rg b r gb rg b r g b r g b engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 18/27
7.0 parameter guide line for cfl inverter ta=25[deg. c] (note 4) [w] 4.2 3.8 cfl power consumption pcfl ta=25[deg. c] [vrms] 640 cfl voltage (reference) vcfl ta=0[deg. c] [vrms] 1,600 inverter ignition voltage vcfli ta=25[deg. c] (note 3) [khz] 70 40 cfl frequency fcfl ta=25[deg. c] (note2,6) [ma] 20 cfl peak inrush current icflp ta=25[deg. c] (note2,5) [marms] 7.0 6.0 4.0 cfl current icfl ta=25[deg. c] [cd/m 2 ] [cd/m 2 ] - - 150 140 - - white luminance (center) (5 points average) (l63) condition units max d.p-1 note1 min parameter symbol note : 1. design point-1 2. if it exceeds min/max values, then"cfl life" , "on/off cycle", and "safety" will not be guaranteed. 3. cfl frequency should be carefully determined to avoid interference between inverter and tft lcd. 4. calculated value for reference (icfl x vcfl = pcfl). 5. it should be employed the inverter which has `duty dimming`, if icfl is less than 4[ma]. 6. duration: 50msec max engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 19/27
the following chart is luminance versus lamp current for your reference. engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 20/27 tbd
8.0 interface timings basically, interface timings should match the vesa 1024x768 / 60 hz (vg901101) manufacturing guide line timing. these timings described here are not actual input timings of lcd module but output timings of sn75lvds86dgg(texas instruments) or equivalent. 8.1 timing characteristics timing characteristics (based on vesa 1024 x 768 / 60hz) 1 [tx] 63 29 7 v-sync back porch vbp [tx] 3 1 v-sync front porch vfp [tx] 6 1 v-sync width vw [hz] 61 60 50 frame rate vsync [tx] 768 768 768 y active time tacy [tx] 1023 806 777 y total time ty [tck] 24 0 h front porch hfp 2 [tck] 160 8 h back porch hbp 2 [tck] 136 8 h-sync width hsw [khz] 48.363 h frequency hsync [tck] 1024 1024 1024 x active time tacx [tck] 2047 1344 1206 x total time tx [nsec] 20.00 15.38 14.93 dtclk cycle time tck [mhz] 67.00 65.00 50.00 dtclk frequency fdck note unit max typ min symbol note : 1. vbp should be static 2. hsw + hbp >= 32 [tck] 3. when there are invalid timing, display appears black pattern. synchronous signal defects and enter auto refresh for lcd module protection mode. engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 21/27
8.2 timing definition 1344 dot 136 dot 160 dot 24 dot 1024 dot h-sync dsptmg 38h 3h 29h 6h 768h v-sync dsptmg engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 22/27
9.0 power consumption input power specifications are as follows; [mvp-p] 100 allowable logic/lcd drive ri pp le volta ge vddrp all black pattern, vdd=3.3[v] [ma] 360 vdd current idd max pattern, vdd=3.6[v] [ma] 530 vdd current idd all black pattern, vdd=3.3[v] [w] 1.2 vdd power pdd max. pattern, vdd=3.6[v] [w] 1.91 vdd power pdd load capacitance 20[uf] [v] 3.6 3.3 3.0 logic/lcd drive volta g e vdd condition units max t yp min parameter symbol engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 23/27
10.0 power on/off sequence vdd power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vdd is off. 90% 10% 10% 10% 90% 0.1ms min. 0 min. 0 min. 0 v 0 v vdd signals 10% 10% 200ms min. 0 min. 0 v lamp on 10% 10% 30ms max. 30ms min. engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 24/27
11.0 mechanical characteristics engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 25/27
engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 26/27
12.0 national test lab requirement the display module is authorized to apply the ul recognized mark. conditions of acceptability conditions of acceptability - when installed on the end-product, consideration shall be given to the following; 1. this component has been judged on the basis of the required spacings in the standard for safety of information technology equipment, csa/ ul60950, third edition, dated december 1,2000, sub-clause 2.10, which would cover the component itself if submitted for listing. 2. the unit is intended to be supplied by selv and limited power source. also separated from electrical parts, which may produce high temperature that could cause ignition by as least 13mm of air or by a solid barrier of material of v-1 minimum. 3. the terminals and connectors are suitable for factory wiring only. 4. a suitable electrical enclosure shall be provided. ****** end of page ****** engineering specification (c) copyright international display technology 2002 all rights reserved. november 5,2002 oem i-915s-01 27/27

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