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unisonic technologies co., ltd us12231 preliminary cmos ic www.unisonic.com.tw 1 of 15 copyright ? 2014 unisonic technologies co., ltd qw-r502-a82.a expresscard tm power interface switch ? description the utc us12231 expresscard tm power interface switches are designed to meet the expresscard tm specification. the utc us12231 distribute 3.3v, aux, and 1.5v to the single-slot expresscard|34 or expresscard|54 sockets. each voltage rail is protected with integrat ed current-limiting circuitry, other functions include thermal protection circuit turns off switches to prevent device from damage when heavy overloads or short circuits, the utc us12231 can use in notebook computers, desktop computers, pdas, and digital cameras. ? features * meets the expresscard tm standard (expresscard|34 or expresscard|54) * compliant with the expresscard tm compliance checklists * fully satisfies the expresscard tm implementation guidelines * supports systems with wake function * ttl-logic compatible inputs * short circuit and thermal protection * -40c ~ 85c ambient operating temperature range tssop-20 ? ordering information ordering number package packing lead free halogen free us12231l-p20-t US12231G-P20-T tssop-20 tube us12231l-p20-r us12231g-p20-r tssop-20 tape reel expresscard is a trademark of personal comput er memory card international association.
us12231 preliminary cmos ic unisonic technologies co., ltd 2 of 15 www.unisonic.com.tw qw-r502-a82.a ? marking information package marking tssop-20 ? pin configuration ? pin description pin no. pin name i/o description 1 sysrst i system reset input ? active low, logic level signal. internally pulled up to auxin. 2 shdn i shutdown input ? active low, logic level signal. internally pulled up to auxin. 3 stby i standby input ? active low, logic level signal. internally pulled up to auxin. 4, 5 3.3v in i 3.3-v input for 3.3vout 6, 7 3.3v out o switched output that delivers 0 v, 3.3 v or high impedance to card 8 perst o a logic level power good to slot 0 (with delay) 9 nc no connection 10 gnd ground 11 cpusb i card present input for usb cards. internally pulled up to auxin. 12 cppe i card present input for pci expresscards tm . internally pu lled up to auxin 13, 14 1.5v out o switched output that delivers 0 v, 1.5 v or high impedance to card 15,16 1.5v in i 1.5-v input for 1.5vout 17 aux out o switched output that delivers 0 v, aux or high impedance to card 18 aux in i aux input for auxout and chip power 19 rclken i/o reference clock enable signal. as an output, a logic level power good to host for slot 0 (no delay ? open drain). as an input, if kept inactive (low) by the host, prevents perst from being de-asserted. internally pulled up to auxin. 20 oc o overcurrent status output for slot 0 (open drain)
us12231 preliminary cmos ic unisonic technologies co., ltd 3 of 15 www.unisonic.com.tw qw-r502-a82.a ? block diagram 3.3v in aux in 1.5v in cpusb cppe stby shdn gnd control logic s1 s2 s3 s4 s5 s6 current limit thermal shutdown delay auxin auxin sysrst perst rclken oc 1.5v out aux out 3.3v out uvlo uvlo uvlo current limit current limit pg 3 2 1 8 19 20 13/ 14 17 6/7 4/5 18 15/ 16 12 11 10
us12231 preliminary cmos ic unisonic technologies co., ltd 4 of 15 www.unisonic.com.tw qw-r502-a82.a ? absolute maximum rating (over operating free-air temperature range (unless otherwise noted) parameter symbol test conditions ratings unit input voltage range for card power v in 1.5v in -0.3~6 v 3.3v in -0.3~6 aux in -0.3~6 logic input/output volt age -0.3~6 v output voltage range v out 1.5v in -0.3~6 v 3.3v in -0.3~6 aux in -0.3~6 continuous total power dissipation see dissipation rating table output current i out 1.5v in internally limited 3.3v in internally limited aux in internally limited oc sink current 10 ma perst sink/source current 10 ma operating virtual juncti on temperature range t j -40~+120 c storage temperature range t stg -55~+150 c note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. ? dissipation ratings (thermal resistance=c/w) parameter symbol ratings unit power rating (t a 25c) 704.2 mw note: these devices are mounted on a jedec low-k board (2 -oz. traces on surface), (the table is assuming that the maximum junction temperature is 120c). ? recommended operating conditions parameter symbol test conditions min typ max unit input voltage v in 1.5v in 1.5v in is only required for its respective functions 1.35 1.65 v 3.3v in 3.3v in is only required for its respective functions 3 3.6 aux in a u x in is required for all circuit operations 3 3.6 continuous output current i out 1.5v out 0 650 ma 3.3v out 0 1.3 a aux out 0 275 ma operating virtual junction temperature t j -40 120 c
us12231 preliminary cmos ic unisonic technologies co., ltd 5 of 15 www.unisonic.com.tw qw-r502-a82.a ? electrical characteristics t j =25c, v i(3.3vin) =v i(auxin) =3.3v, v i(1.5vin) =1.5v, v i(/shdnx) , v i(/stbyx) =3.3v, v i(/cppex) =v i(/cpusbx) =0v, v i(/sysrst) =3.3v, ocx and rclkenx and perstx are open, all voltage outputs unloaded (unless otherwise noted) parameter symbol test conditions min typ max unit power switch resistance 1.5v in ~1.5v out r ds t j =25c, i=650ma each 46 m ? t j =100c, i=650ma each 70 3.3v in ~3.3v out t j =25c, i=1300ma each 45 m ? t j =100c, i=1300ma each 68 a ux in ~aux out t j =25c, i=275ma each 120 m ? t j =100c, i=275ma each 200 discharge resistance on 3.3v/1.5v/aux outputs r ( dis _ fet ) v i ( /shdnx ) =0v, i ( dischar g e ) =1ma 100 500 ? short -circuit output current (note 1) steady-state value 1.5v out i os t j (-40~120c), output powered into a short 0.67 1 1.3 a 3.3v out 1.35 2 2.5 a a ux out 275 450 600 ma thermal shutdown trip point, t j t j rising temperature, not in overcurrent condition 155 165 c t j _ oc overcurrent condition 120 130 hysteresis ? t 10 c current -limit response time from short to the 1 st threshold within 1.1times of final current limit, t j =25c v o ( 3.3vout ) with 100-m ? short 43 100 s v o ( 1.5vout ) with 100-m ? short 100 140 v o(auxout) with 100-m ? short 38 100 operation input quiescent current normal operation 1.5v in i i outputs are unloaded, t j (?40, 120c) (does not include cppex and cpusbx logic pullup currents) 2.5 10 a 3.3v in 10 15 a ux in 85 150 total input quiescent current normal operation 1.5v in i i outputs are unloaded, t j (?40, 120c) (include cppex and cpusbx logic pullup currents) 2.5 10 a 3.3v in 10 15 a ux in 120 210 shutdown mode 1.5v in cpusb = cppe =0v, shdn =0v (discharge fets are on) (include cppex and cpusbx logic pullup currents and shdn pullup current) t j (?40, 120c) 0.5 10 a 3.3v in 3.5 10 a ux in 144 270 forward leakage current 1.5v in i lkg(fwd) shdn =3.3v, cpusb = cppe = 3.3v (no card present, discharge fets are on), current measured at input pins, t j =120c, includes rclken pullup current 0.1 50 a 3.3v in 0.1 50 a ux in 20 50 reverse leakage current t j =25c 1.5v in i lkg(rvs) v o(auxout) =v o(3.3vout) =3.3v, v o(1.5vout) =1.5v, all voltage inputs are grounded (current measured from output pins going in) 0.1 10 a t j =120c 50 t j =25c 3.3v in 0.1 10 a t j =120c 50 t j =25c a ux in 0.1 10 a t j =120c 50
us12231 preliminary cmos ic unisonic technologies co., ltd 6 of 15 www.unisonic.com.tw qw-r502-a82.a ? electrical characteristics(cont.) parameter symbol test conditions min typ max unit logic section ( sysrst , shdnx , stbyx , perstx , rclkenx, ocx , cpusbx , cppex ) logic input supply current input ) sysrst ( i sysrst =3.6v, sinking 0 1 a input ) sysrst ( i sysrst =0v, sourcing 0 1 a 10 30 input ) shdnx ( i shdnx =3.6v, sinking 0 1 a shdnx =0v, sourcing 10 30 input ) stbyx ( i stbyx =3.6v, sinking 0 1 a stbyx =0v, sourcing 10 30 input i ( rclkenx ) rclkenx=0v, sourcing 10 30 a inputs ) cpusbx ( i or ) cppex ( i cpusb or cppe =0v, sinking 0 1 a cpusb or cppe =3.6v, sourcing 10 30 logic input voltage high level v ih 2 v low level v il 0.8 rclen output low voltage output v ol ( rclen ) i o ( rclken ) =60 a 0.4 v perst assertion threshold of output voltage ( perst asserted when any output voltage falls below the threshold) v pg(3.3vin) 3.3v out falling 2.7 3 v v pg(auxin) aux out falling 2.7 3 v pg(1.5vin) 1.5v out falling 1.2 1.35 perst assertion delay from output voltage ) perst ( fd t 3.3v out , aux out , or 1.5v out falling 500 ns perst de-assertion delay from output voltage ) perst ( rd t 3.3v out , auxout, and 1.5v out rising within tolerance 4 10 20 ms perst assertion delay from sysrst ) perst ( fd t 2 max time from sysrst asserted or de-asserted 500 ns perst minimum pulse width ) perst ( w t 3.3v out , aux out , or 1.5v out falling out of tolerance or triggered by sysrst 100 250 s perst output low voltage ) perst ( ol v i o(perst) =500 a 0.4 v perst output high voltage ) perst ( oh v 2.4 v oc output low voltage ) oc ( ol v i o(/oc) =2ma 0.4 v oc leakage current ) oc ( ikg i v o(/oc) =3.6v 1 a oc deglitch ) oc ( d t falling into or out of an overcurrent condition 6 20 ms undervoltage lockout (uvlo) 3.3v in uvlo v uvlo(3.3vin) 3.3v in level, below which 3.3v in and 1.5v in switches are off 2.6 2.9 v 1.5v in uvlo v uvlo(1.5vin) 1.5v in level, below which 3.3v in and 1.5v in switches are off 1 1.25 aux in uvlo v uvlo(auxin) aux in level, below which all switches are off 2.6 2.9 uvlo hysteresis ? v uvlo 100 mv note: pulse-testing techniques maintain junction temperature close to am bient temperature; thermal effects must be taken into account separately. electrical characteristics(cont.)
us12231 preliminary cmos ic unisonic technologies co., ltd 7 of 15 www.unisonic.com.tw qw-r502-a82.a ? switching characteristics t j =25c, v i(3.3vin) =v i(auxin) =3.3v, v i(1.5vin) =1.5v, v i(/shdnx) , v i(/stbyx) =3.3v, v i(/cppex) =v i(/cpusbx) =0v, v i(/sysrst) =3.3v, ocx and rclkenx and perstx are open, all volta ge outputs unloaded (unl ess otherwise noted) parameter symbol test conditions min typ max unit output rise times 3.3v in to 3.3v out t r c l ( 3.3vout ) =0.1 f, i o ( 3.3vout ) =0a 0.1 3 ms a u x in to aux out c l ( auxout ) =0.1 f, i o ( auxout ) =0a 0.1 3 1.5v in to 1.5v out c l ( 1.5vout ) =0.1 f, i o ( 1.5vout ) =0a 0.1 3 3.3v in to 3.3v out c l ( 3.3vout ) =100 f, r l =v i ( 3.3vin ) /1a 0.1 6 a u x in to aux out c l ( auxout ) =100 f, r l =v i ( auxin ) /0.250a 0.1 6 1.5v in to 1.5v out c l ( 1.5vout ) =100 f, r l =v i ( 1.5vin ) /0.500a 0.1 6 output fall times when card removed (both cpusb and cppe de-asserted) 3.3v in to 3.3v out t f c l ( 3.3vout ) =0.1 f, i o ( 3.3vout ) =0a 10 150 s a u x in to vaux out c l ( auxout ) =0.1 f, i o ( auxout ) =0a 10 150 1.5v in to 1.5v out c l ( 1.5vout ) =0.1 f, i o ( 1.5vout ) =0a 10 150 3.3v in to 3.3v out c l ( 3.3vout ) =20 f, i o ( 3.3vout ) =0a 2 30 ms a u x in to vaux out c l ( auxout ) =20 f, i o ( auxout ) =0a 2 30 1.5v in to 1.5v out c l ( 1.5vout ) =20 f, i o ( 1.5vout ) =0a 2 30 output fall times when shdn asserted (card is present) 3.3v in to 3.3v out t f c l ( 3.3vout ) =0.1 f, i o ( 3.3vout ) =0a 10 150 s a u x in to vaux out c l ( auxout ) =0.1 f, i o ( auxout ) =0a 10 150 1.5v in to 1.5v out c l ( 1.5vout ) =0.1 f, i o ( 1.5vout ) =0a 10 150 3.3v in to 3.3v out c l ( 3.3vout ) =100 f, r l =v i ( 3.3vin ) /1a 0.1 5 ms a u x in to vaux out c l ( auxout ) =100 f, r l =v i ( auxin ) /0.250a 0.1 5 1.5v in to 1.5v out c l ( 1.5vout ) =100 f, r l =v i ( 1.5vin ) /0.500a 0.1 5 turn-on propagation delay 3.3vi n to 3.3v out t pd(on) c l ( 3.3vout ) =0.1 f, i o ( 3.3vout ) =0a 0.1 1 ms a u x in to vaux out c l ( auxout ) =0.1 f, i o ( auxout ) =0a 0.05 0.5 1.5v in to 1.5v out c l ( 1.5vout ) =0.1 f, i o ( 1.5vout ) =0a 0.1 1 3.3v in to 3.3v out c l ( 3.3vout ) =100 f, r l =v i ( 3.3vin ) /1a 0.1 1.5 a u x in to vaux out c l ( auxout ) =100 f, r l =v i ( auxin ) /0.250a 0.05 1 1.5v in to 1.5v out c l ( 1.5vout ) =100 f, r l =v i ( 1.5vin ) /0.500a 0.1 1.5 turn-off propagation delay 3.3v in to 3.3v out t pd(off) c l ( 3.3vout ) =0.1 f, i o ( 3.3vout ) =0a 0.1 1.5 ms a u x in to vaux out c l ( auxout ) =0.1 f, i o ( auxout ) =0a 0.05 0.5 1.5v in to 1.5v out c l ( 1.5vout ) =0.1 f, i o ( 1.5vout ) =0a 0.1 1.5 3.3v in to 3.3v out c l ( 3.3vout ) =100 f, r l =v i ( 3.3vin ) /1a 0.1 1.5 a u x in to vaux out c l ( auxout ) =100 f, r l =v i ( auxin ) /0.250a 0.05 0.5 1.5v in to 1.5v out c l ( 1.5vout ) =100 f, r l =v i ( 1.5vin ) /0.500a 0.1 1
us12231 preliminary cmos ic unisonic technologies co., ltd 8 of 15 www.unisonic.com.tw qw-r502-a82.a ? functional truth tables table 1. truth table for voltage outputs voltage inputs (note 1) logic inputs voltage outputs (note 2) mode (note 3) aux in 3.3v in 1.5v in shdn stby cp (note 4) aux out 3.3v out 1.5v out off x x x x x off off off off on x x 0 x x gnd gnd gnd shutdown on x x 1 x 1 gnd gnd gnd no card on on on 1 0 0 on off off standby on on on 1 1 0 on on on card inserted notes: 1. for input voltages, on means the respective input voltage is higher than it s turnon threshold voltage; otherwise, the voltage is off (for aux input, off means the voltage is close to zero volt.) 2. for output voltages, on means the respective powe r switch is turned on so the input voltage is connected to the output; off means the power switch and its output discharge fet are both off; gnd means the power switch is off but the output discharge fet is on so the voltage on the output is pulled down to 0v. 3. mode assigns each set of input conditions and respecti ve output voltage results to a different name. these modes are referred to as input conditions in the following truth table for logic outputs. 4. cp = cpusb and cppe -equal to 1 when both cpusb and cppe signals are logic high, or equal to 0 when either cpusb or cppe is low. table 2. truth table for logic outputs input conditions logic outputs mode sysrst rclken (note 1) perst rclken (note 2) off x x 0 0 shutdown no card standby card inserted 0 hi-z 0 1 0 0 0 0 1 hi-z 1 1 1 0 0 0 notes: 1. rclken as a logic input in this column. rclken is an i/o pin and it can be driven low externally, left open, or connected to high-impedance terminals, such as t he gate of a mosfet. it must not be driven high externally. 2. rclken as a logic output in this column.
us12231 preliminary cmos ic unisonic technologies co., ltd 9 of 15 www.unisonic.com.tw qw-r502-a82.a ? power states off mode if aux in is not present, then all input-to-output power switches are kept off (off mode). shutdown mode if aux in is present and shdn is asserted (logic low), then all input-to -output power switches are kept off and the output discharge fets are turned on (shutdown mode). if shdn is asserted and then de-asserted, the state on the outputs is restored to the state prior to shdn __________ assertion. no card mode if 3.3v in , aux in and 1.5v in are present at the input of the power switch and no card is inserted, then all input-to-output power switches are k ept off and the output discharge fets are turned on (no card mode). card inserted mode if 3.3v in , aux in and 1.5v in are present at the input of the power swit ch prior to a card being inserted, then all input-to-output power switches are tur ned on once a card-present signal ( cpusb and/or cppe ) is detected (card inserted mode). standby mode if a card is present and all output voltages are being applied, then the stby is asserted (logic low); the aux out voltage is provided to the card, and the 3.3v out and 1.5v out switches are turned off (standby mode). if a card is present and all output voltages are being applied, then the 1.5v in , or 3.3v in is removed from the input of the power switch; the aux out voltage is provided to the card and the 3.3v out and 1.5v out switches are turned off (standby mode). if prior to the insertion of a card, the aux in is available at the input of the power switch and 3.3v in and/or 1.5v in are not, or if stby is asserted (logic low), then no power is made available to the card (off mode). if 1.5v in and 3.3v in are made available at the input of the powe r switch after the card is inserted and stby is not asserted, all the output voltages are made available to the card (card inserted mode). ? discharge fets the discharge fets on the outputs are ac tivated whenever the device detects t hat a card is not present (no card mode). activation occurs after the input-t o-output power switches are turned off (break before make). the discharge fets de-activate if either of the card-p resent lines go active low, unless the shdn pin is asserted. the discharge fets are also activated whenever the shdn input is asserted and stay asserted until shdn is de-asserted.
us12231 preliminary cmos ic unisonic technologies co., ltd 10 of 15 www.unisonic.com.tw qw-r502-a82.a ? application information introduction to expresscard tm an expresscard module is an add-in card with a serial interface based on pci express and/or universal serial bus (usb) technologies. an expresscard tm comes in two form factors defined as expresscard|34 or expresscard|54. the difference, as defined by the name, is the width of the module, 34mm or 54mm, respectively. host systems supporting the expresscard tm module can support either the expresscard|34 or expresscard|54 or both. expresscard tm power requirements regardless of which expresscard tm module is used, the power requirem ents as defined in the expresscard tm standard apply to both on an individual slot basis. the host system is required to supply 3.3v, 1.5v, and aux to each of the expresscard tm slots. however, the voltage is only applied after an expresscard tm is inserted into the slot. the expresscard tm connector has two pins, cppe and cpusb , which are used to signal the host when a card is inserted. if the expresscard tm module itself connects the cppe to ground, the logic lo w level on that signal indicates to the host that a card supp orting pci express has been inserted. if cpusb is connected to ground, then the expresscard tm module supports the usb interface. if bot h pci express and usb are supported by the expresscard tm module, then both signals, cppe and cpusb , must be connected to ground. in addition to the card present signals ( cppe and cpusb ), the host system determine s when to apply power to the expresscard tm module based on the state of the system. the state of the system is defined by the state of the 3.3 v, 1.5v, and aux input volt age rails. for the sake of simplicity, t he 3.3v and 1.5v rails are defined as the primary voltage rails as oppose to the auxiliary voltage rail, aux. expresscard tm power switch operation the expresscard power switch resides on the host, and its main function is to control when to send power to the expresscard tm slot. the expresscard tm power switch makes decisions based on the card present inputs and on the state of the host system as defined by the primary and auxiliary voltage rails. the following conditions define the oper ation of the host power controller: 1. when both primary power and auxiliary po wer at the input of the expresscard tm power switch are off, then all power to the expresscard tm connector is off regardless of whether a card is present. 2. when both primary power and auxiliary po wer at the input of the expresscard tm power switch are on, then power is only applied to the expresscard tm after the expresscard tm power switch detects that a card is present. 3. when primary power (either +3.3v or +1 .5v) at the input of the expresscard tm power switch is off and auxiliary power at the input of the expresscard tm power switch is on, then the expresscard tm power switch behaves in the following manner: (a) if neither of the card present inputs is detected (no card inserted) , then no power is applied to the expresscard tm slot. (b) if the card is inserted after the system has entered this power state, then no power is applied to the expresscard tm slot. (c) if the card is inserted prior to t he removal of the primary power (either +3 .3v or +1.5v or both) at the input of the expresscard tm power switch, then only the primary power (both +3.3v and +1.5v) is removed and the auxiliary power is sent to the expresscard tm slot. figure 2 through figure 7 illustrate the timing relationships between power/logic inputs and outputs of expresscard tm .
us12231 preliminary cmos ic unisonic technologies co., ltd 11 of 15 www.unisonic.com.tw qw-r502-a82.a ? test circuits and voltage waveforms
us12231 preliminary cmos ic unisonic technologies co., ltd 12 of 15 www.unisonic.com.tw qw-r502-a82.a ? express card timing diagrams host power (auxin, 3.3v in , and 1.5v in ) card power (auxin, 3.3v out , and 1.5v out ) sysrst cpxx rclken perst a b f c d e tpd a b c d e f min max units s system dependent 100 system dependent figure 2. timing signals - card present before host power is on s ms ms 100 4 20 10
us12231 preliminary cmos ic unisonic technologies co., ltd 13 of 15 www.unisonic.com.tw qw-r502-a82.a ? express card timing diagrams(cont.) sysrst cpxx card power (auxin, 3.3v out , and 1.5v out ) host power (aux in ) rclken perst note: once 3.3v and 1.5v are applied, the power switch follows the power-up sequence of figure 2 or figure 3. figure 4. timing signals - host system in standby prior to card insertion host power (3.3vin, and 1.5v in ) tpd min max units a b c d system dependent load dependent sysrst cpxx card power (aux out , 3.3v out , and 1.5v out ) host power (aux in , 3.3v in , and 1.5v in ) rclken perst b a d c figure 5. timing signals - host - controlled power down 500 500 ns ns
us12231 preliminary cmos ic unisonic technologies co., ltd 14 of 15 www.unisonic.com.tw qw-r502-a82.a ? express card timing diagrams(cont.) tpd min max units a b c 500 500 ns ns figure 7. timing signals ? surprise card removal load dependent perst rclken sysrst cpxx card power (aux out , 3.3v out , and 1.5v out ) host power aux in , 3.3v in , and 1.5v in a c b
us12231 preliminary cmos ic unisonic technologies co., ltd 15 of 15 www.unisonic.com.tw qw-r502-a82.a ? typical application circuit 3.3v out aux out 1.5v out utc us12331g aux in 3.3v in 1.5v in shdn stby sysrst oc gnd perst cppe cpusb rclken refclk express card 3.3v out aux out 1.5v out perst cppe cpusb aux in 3.3v in 1.5v in shdn stby sysrst oc utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.

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