cystech electronics corp. spec. no. : c877j3 issued date : 2014.12.25 revised date : 2014.12.26 page no. : 1/9 mtb09p04dj3 cystek product specification p-channel enhancement mode power mosfet mtb09p04dj3 features ? single drive requirement ? low on-resistance ? fast switching characteristic ? pb-free lead plating and halogen-free package symbol outline ordering information device package shipping MTB09P04DJ3-0-T3-G to-252 (pb-free lead plating and halogen-free package) 2500 pcs / tape & reel to-252(dpak) mtb09p04dj3 g gate d drain s source bv dss -40v i d @v gs =-10v, t c =25 c -50a i d @v gs =-10v, t a =25 c -13.7a r ds(on) @v gs =-10v, i d =-25a 5.2m (typ) r ds(on) @v gs =-4.5v, i d =-15a 6.9m (typ) g d s environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t3 : 2500 pcs / tape & reel, 13? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c877j3 issued date : 2014.12.25 revised date : 2014.12.26 page no. : 2/9 mtb09p04dj3 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds -40 gate-source voltage v gs 20 v continuous drain current @v gs =-10v, t c =25 c (package limit) -50 continuous drain current @v gs =-10v, t c =25 c (silicon limit) -74 continuous drain current @v gs =-10v, t c =100 c(silicon limit) i d -52 continuous drain current @v gs =-10v, t a =25 c -13.7 continuous drain current @v gs =-10v, t a =100 c i dsm -8.7 pulsed drain current i dm -200 *1 a t c =25 94 *4 t c =100 p d 47 *4 t a =25 2.5 *3 power dissipation t a =100 p dsm 1.0 *3 w single pulse avalanche energy e as 625 *2 mj single pulse avalanche current i as -50 a operating junction and storage temperature tj, tstg -55~+175 c thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 1.6 c/w thermal resistance, junction-to-ambient, max r th,j-a 50 *3 c/w note : *1. pulse width limited by safe operating area. *2 . tj=25 c, v dd =-15v, l=0.5mh, r g =25 . *3 . the value of rt h,j-a is measured with the device mounted on 1 in 2 fr-4 board with 2 oz. copper, in a still air environment with t a =25 c . the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c . the value in any given applicati on depends on the user?s specific board design, and the maximum temperature of 175 c may be used if the pcb allows it. *4 . the power dissipation p d is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. it is used to determined the current rating, when this rating falls below the package limit. characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss -40 - - v v gs =0v, i d =-250 a v gs(th) -0.8 - -2.0 v v ds = v gs , i d =-250 a g fs - 55 - s v ds =-5v, i d =-25a i gss - - 100 na v gs = 20v i dss - - -1 v ds =-32v, v gs =0v i dss - - -25 a v ds =-32v, v gs =0v, tj=70 c *r ds(on) - 5.2 7 v gs =-10v, i d =-25a *r ds(on) - 6.9 10.5 m v gs =-4.5v, i d =-15a
cystech electronics corp. spec. no. : c877j3 issued date : 2014.12.25 revised date : 2014.12.26 page no. : 3/9 mtb09p04dj3 cystek product specification dynamic *qg - 121 - *qgs - 19 - *qgd - 20 - nc i d =-25a, v ds =-20v, v gs =-10v *t d(on) - 20 - *tr - 22 - *t d(off) - 135 - *t f - 33 - ns v ds =-20v, v gs =-10v, r g =3.3 , i d =-25a ciss - 6433 - coss - 501 - crss - 258 - pf v gs =0v, v ds =-25v, f=1mhz rg - 3.5 - f=1mhz source-drain diode *i s - - -50 a *v sd - -0.83 -1.2 v i s =-25a, v gs =0v *trr - 24 - ns *qrr - 17 - nc i s =-25a, v gs =0, di/dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2% recommended soldering footprint
cystech electronics corp. spec. no. : c877j3 issued date : 2014.12.25 revised date : 2014.12.26 page no. : 4/9 mtb09p04dj3 cystek product specification typical characteristics typical output characteristics 0 40 80 120 160 200 01234 5 brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) -bv dss , normalized drain-source breakdown voltage i d =-250 a, v gs =0v 10v,9v,8v,7v,6v,5v -v ds , drain-source voltage(v) -i d , drain current(a) -v gs =4v -v gs =3v -v gs =2v -v gs =2.5v static drain-source on-state resistance vs drain current 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 100 -i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) in descending order v gs =-2.5v -3v -4.5v -10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 0 2 4 6 8 10 12 14 16 18 20 -i dr , reverse drain current(a) -v sd , source-drain voltage(v) tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 10 20 30 40 50 60 70 80 90 100 024681 0 drain-source on-state resistance vs junction tempearture 0 0.5 1 1.5 2 2.5 3 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =-10v, i d =-25a r ds( on) @tj=25c : 5.2m typ -v gs , gate-source voltage(v) r ds(on ), static drain-source on- state resistance(m) i d =-25a
cystech electronics corp. spec. no. : c877j3 issued date : 2014.12.25 revised date : 2014.12.26 page no. : 5/9 mtb09p04dj3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 100 1000 10000 01 02 0 3 0 threshold voltage vs junction tempearture 0.2 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) -v gs(th) , normalized threshold voltage i d =-250 a i d =-1ma ciss -v ds , drain-source voltage(v) capacitance---(pf) c oss f=1mhz crss maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 -v ds , drain-source voltage(v) -i d , drain current (a) r ds( on) limited dc 10ms 100ms 1ms 100 s 1s t c =25c, tj=175c, v gs =-10v, r jc =1.6c/w, single pulse gate charge characteristics 0 2 4 6 8 10 0 20 40 60 80 100 120 140 160 qg, total gate charge(nc) -v gs , gate-source voltage(v) i d =-25a v ds =-10v v ds =-20v vds=-40v maximum drain current vs case temperature 0 10 20 30 40 50 60 70 80 90 25 50 75 100 125 150 175 200 t c , case temperature(c) -i d , maximum drain current(a) v gs =-10v, tj(max)=175c, r jc =1.6c/w, single pulse silicon limit package limit forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 -i d , drain current(a) g fs , forward transfer admittance(s) v ds =-5v pulsed ta=25c
cystech electronics corp. spec. no. : c877j3 issued date : 2014.12.25 revised date : 2014.12.26 page no. : 6/9 mtb09p04dj3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 20 40 60 80 100 120 140 160 180 200 012345 -v gs , gate-source voltage(v) -i d , drain current(a) v ds =-10v power derating curve 0 20 40 60 80 100 0 25 50 75 100 125 150 175 200 t c , case temperature() p d , power dissipation(w) transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =1.6c/w
cystech electronics corp. spec. no. : c877j3 issued date : 2014.12.25 revised date : 2014.12.26 page no. : 7/9 mtb09p04dj3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c877j3 issued date : 2014.12.25 revised date : 2014.12.26 page no. : 8/9 mtb09p04dj3 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak 10-30 seconds 20-40 seconds temperature(tp) ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. issued date : 2014.12.25 revised date : 2014.12.26 page no. : 9/9 spec. no. : c877j3 mtb09p04dj3 cystek product specification to-252 dimension inches marking: device n ame date code b09 p04d 1 2 3 4 style: pin 1.gate 2.drain 3.source 4.drain 3-lead to-252 plastic surface mount package cystek package code: j3 millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.087 0.094 2.200 2.400 e 0.086 0.094 2.186 2.386 a1 0.000 0.005 0.000 0.127 e1 0.172 0.188 4.372 4.772 b 0.039 0.048 0.990 1.210 h 0.163 ref 4.140 ref b 0.026 0.034 0.660 0.860 k 0.190 ref 4.830 ref b1 0.026 0.034 0.660 0.860 l 0.386 0.409 9.800 10.400 c 0.018 0.023 0.460 0.580 l1 0.114 ref 2.900 ref c1 0.018 0.023 0.460 0.580 l2 0.055 0.067 1.400 1.700 d 0.256 0.264 6.500 6.700 l3 0.024 0.039 0.600 1.000 d1 0.201 0.215 5.100 5.460 p 0.026 ref 0.650 ref e 0.236 0.244 6.000 6.200 v 0.211 ref 5.350 ref notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead : pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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