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fedl610q479-03 issue date:jul.31, 2014 ml610q477/ml610q478/ML610Q479 8-bit microcontroller with a built-in lcd driver general description this lsi is a high performance cmos 8-bit microcontroller equipped with an 8-bit cpu nx-u8/100 and integrated with peripheral functions such as the uart, rc oscillation type a/d converter, and lcd driver. the cpu nx-u8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel processing. additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits leak current at high temperatures, and is most suitable for battery-driven applications. mtp version can rewrite programs on-board, which can contribute to reduction in product development tat. the flash memory incorporated into this mtp version implements the mask rom-equivalent low-voltage operation (1.25v or higher) and low-power consumption (typically 5ua at low-speed operation), enabling volume production by the mtp version. for industrial use, ml610q477p/ml610q478p/ML610Q479p with the extended operating ambient temperature ranging from -40c to 85c are available. features ? cpu - 8-bit risc cpu (cpu name: nx-u8/100) - instruction system: 16-bit length instruction - instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on - on-chip debug function - minimum instruction execution time 30.5 s (@ 32.768 khz system clock) 2 s (@ 500 khz system clock) 0.5 s (@ 2 mhz system clock) ? internal memory - internal 24kbyte flash memory (12k x 16 bits) (including unusable 1k byte test area) - internal 2kbyte ram (2048 x 8 bits) ? interrupt controller - 1 non-maskable interrupt source: internal source: 1 (watchdog timer) - 25 maskable interrupt sources: internal source: 13 (timer0, timer1, timer 2, timer 3, timer c, timer d, uart0, rc a/d converter, tbc128hz, tbc32hz, tbc16hz, tbc2hz, analog comparator) external source: 12 (p00, p01, p02, p03, p50, p51, p52, p53, p54, p55, p56, p57) (one interrupt request is generated from p50 to p57 interrupt sources.) ? time base counter - low-speed time base counter x 1 channel frequency compensation (compensation range: approx. -488ppm to +488ppm. compensation accuracy: approx. 0.48ppm) - high-speed time base counter x 1 channel ? watchdog timer - non-maskable interrupt and reset - free running - overflow period: 4 types selectable (125ms, 500ms, 2s, 8s)
fedl610q479-03 ml610q477/ml610q478/ML610Q479 2/31 ? timers - 8 bits x 6 channels [also available is 16-bit x 3 configuration (using timers 0-1, 2-3, or c-d) ] - clock frequency measurement function mode (16-bit configuration using timers 2 and 3 x 1 channel only) - the timer c and timer d are controlled by the external trigger. - the timer c and timer d are used for the one-shot timer mode. ? capture - time base capture x 2 channels (4096 hz to 32 hz) ? uart - txd/rxd 1 channel - bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits - positive logic/negative logic selectable - built-in baud rate generator ? rc oscillation type a/d converter - 16-bit counter - time division x 1 channels ? analog comparator - operating voltage: v dd =1.8v 3.6v - common mode input voltage: 0.2v vdd 1.0v - input offset voltage: 50mv(max) - interrupt allow edge selection and sampling selection - the rc discharged type a/d convertor is configured with the timers c and d. - the temperature measurement function using built-in temperature sensor. temperature measurement range: -40c to +85c , default measurement accuracy: 2c - the reference voltage can be switched between cmpp0, cmpp1, cmpm0, cmpm1, temperature sensor and the internal 0.7v voltage source. ? general-purpose ports - input-only port: 4 channels (including secondary functions) - output-only port ml610q477: 10 channels (including secondary functions) ml610q478: 6 channels (including secondary functions) ML610Q479: 2 channels (including secondary functions) - input/output port: 15 channels (including secondary functions) ? lcd driver - number of segments ml610q477: up to 135 dots (select among 27 segments x 5 commons, 28 segments x 4 commons, 29 segments x 3 commons, and 30 segments x 2 commons) ml610q478: up to 155 dots (select among 31 segments x 5 commons, 32 segments x 4 commons, 33 segments x 3 commons, and 34 segments x 2 commons) ML610Q479: up to 175 dots (select among 35 segments x 5 commons, 36 segments x 4 commons, 37 segments x 3 commons, and 38 segments x 2 commons) - 1/1 to 1/5 duty - 1/2 or 1/3 bias (built-in bias generation circuit) - frame frequency selectable (approx. 64 hz, 73 hz, 85 hz, and 102 hz) - bias voltage multiplying clock selectable (8 types) - lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable ? reset - reset through the reset_n pin - power-on reset generation when powered on - reset by the watchdog timer (wdt) overflow
fedl610q479-03 ml610q477/ml610q478/ML610Q479 3/31 ? clock - low-speed clock (operation of this lsi is not guaranteed under a condition with no supply of low-speed crystal oscillation clock) crystal oscillation (32.768 khz) - high-speed clock built-in rc oscillation (500 khz, 2 mhz) ? power management - halt mode: suspends the instruction execution by cpu (peripheral circuits are in operating states) - stop mode: stops the low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) - high-speed clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) - block control function: completely stops the operation of any function block circuit that is not used (resets registers and stops clock) ? guaranteed operation range ? operating temperature: -20c to +70c (p version: -40c to +85c) ? operating voltage: v dd = 1.25v to 3.6v
fedl610q479-03 ml610q477/ml610q478/ML610Q479 4/31 ? product name ? s upported function lcd bias - chip (die) - 1/2 1/3 operating temperature product availability ml610q477- wa yes yes -20c to +70c yes ml610q478- wa yes yes -20c to +70c yes ML610Q479- wa yes yes -20c to +70c yes ml610q477p- wa yes yes -40c to +85c yes ml610q478p- wa yes yes -40c to +85c yes ML610Q479p- wa yes yes -40c to +85c yes lcd bias -80-pin plastic tqfp - 1/2 1/3 operating temperature product availability ml610q477- tb yes yes -20c to +70c - ml610q478- tb yes yes -20c to +70c - ML610Q479- tb yes yes -20c to +70c - ml610q477p- tb yes yes -40c to +85c - ml610q478p- tb yes yes -40c to +85c - ML610Q479p- tb yes yes -40c to +85c - xxx: rom code number q: mtp version p: wide range temperature version(p version) wa: chip (die) tb: tqfp
fedl610q479-03 ml610q477/ml610q478/ML610Q479 5/31 block diagram block diagram of ml610q477/ml610q478/ML610Q479 * secondary function or tertiary function (*1) select among 27 segments x 5 commons, 28 segments x 4 commons, 29 segments x 3 commons, and 30 segments x 2 commons with the register (*2) select among 31 segments x 5 commons, 32 segments x 4 commons, 33 segments x 3 commons, and 34 segments x 2 commons with the register (*3) select among 35 segments x 5 commons, 36 segments x 4 commons, 37 segments x 3 commons, and 38 segments x 2 commons with the register figure 1 ml610q477/ml610q478/ML610Q479 block diagram program memory (flash) 24kbyte ram 2k byte interrupt controller cpu (nx-u8/100) timing controller ea sp on-chip ice instruction decoder bus controller instruction register tbc int 4 int 1 wdt int 6 8bit timer 6 capture 2 gpio int 5 data-bus test0 reset_n osc xt0 xt1 lsclk* power v ddx lcd driver lcd bias v l1 , v l2 , v l3 c1 , c2 rc-adc rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 ? 3 psw elr1 ? ? ? 15 v pp v dd v ss int 1 display register 190bit com0 to com4 ( *1 )( *2 )( *3 ) seg0 to seg29 (ml610q477) (*1) seg0 to seg33 (ml610q478) (*2) seg0 to seg37 ( ML610Q479 ) ( *3 ) p00 to p03 p20 , p21 p35 p42 to p47 p60 to p67 (ml610q477) p60 to p63 (ml610q478) uart int 1 rxd0* txd0* analog comparator cmpp0* cmpm0* int 1 cmpp1* cmpm1* p50 to p57 ch1 , ch2 v ddl
fedl610q479-03 ml610q477/ml610q478/ML610Q479 6/31 pin configuration ml610q477 chip pad layout & dimension chip size: 2.36mm 2.31mm pad count: 76 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: vss level. figure 8 ml610q477 chip pin layout & dimension 1 p57 2 p56 3 p55 4 p54 5 v dd 6 v ss 7 v ddl 8 ch1 9 ch2 10 v dd x 11 xt0 12 xt1 13 reset_n 14 test0 15 p44 16 p45 17 p46 18 p47 19 p35 20 c1 21 c2 22 v l1 23 v l2 24 v l3 25 com0 26 com1 27 com2/seg0 28 com3/seg1 29 com4/seg2 30 seg3 31 seg4 32 seg5 33 seg6 34 seg7 35 seg8 36 seg9 37 seg10 38 seg11 39 seg12 46 seg19 45 seg18 44 seg17 43 seg16 42 seg15 41 seg14 40 seg13 53 seg26 52 seg25 51 seg24 50 seg23 49 seg22 48 seg21 47 seg20 56 seg29 55 seg28 54 seg27 58 p66 57 p67 78 v pp 77 p03 76 p02 75 p01 74 p00 73 v ss 72 p21 71 p20 70 p43 69 p42 68 p50 67 p51 66 p52 65 p53 64 p60 63 p61 62 p62 61 p63 60 p64 59 p65 2.36 mm 2.31 mm x y
fedl610q479-03 ml610q477/ml610q478/ML610Q479 7/31 ml610q478 chip pad layout & dimension chip size: 2.36mm 2.31mm pad count: 76 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 9 ml610q478 chip pin layout & dimension 1 p57 2 p56 3 p55 4 p54 5 v dd 6 v ss 7 v ddl 8 ch1 9 ch2 10 v dd x 11 xt0 12 xt1 13 reset_n 14 test0 15 p44 16 p45 17 p46 18 p47 19 p35 20 c1 21 c2 22 v l1 23 v l2 24 v l3 25 com0 26 com1 27 com2/seg0 28 com3/seg1 29 com4/seg2 30 seg3 31 seg4 32 seg5 33 seg6 34 seg7 35 seg8 36 seg9 37 seg10 38 seg11 39 seg12 46 seg19 45 seg18 44 seg17 43 seg16 42 seg15 41 seg14 40 seg13 53 seg26 52 seg25 51 seg24 50 seg23 49 seg22 48 seg21 47 seg20 56 seg29 55 seg28 54 seg27 58 seg31 57 seg30 78 v pp 77 p03 76 p02 75 p01 74 p00 73 v ss 72 p21 71 p20 70 p43 69 p42 68 p50 67 p51 66 p52 65 p53 64 p60 63 p61 62 p62 61 p63 60 seg33 59 seg32 2.36 mm 2.31 mm x y
fedl610q479-03 ml610q477/ml610q478/ML610Q479 8/31 ML610Q479 chip pad layout & dimension chip size: 2.36mm 2.31mm pad count: 76 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 10 ML610Q479 chip pin layout & dimension 1 p57 2 p56 3 p55 4 p54 5 v dd 6 v ss 7 v ddl 8 ch1 9 ch2 10 v dd x 11 xt0 12 xt1 13 reset_n 14 test0 15 p44 16 p45 17 p46 18 p47 19 p35 20 c1 21 c2 22 v l1 23 v l2 24 v l3 25 com0 26 com1 27 com2/seg0 28 com3/seg1 29 com4/seg2 30 seg3 31 seg4 32 seg5 33 seg6 34 seg7 35 seg8 36 seg9 37 seg10 38 seg11 39 seg12 46 seg19 45 seg18 44 seg17 43 seg16 42 seg15 41 seg14 40 seg13 53 seg26 52 seg25 51 seg24 50 seg23 49 seg22 48 seg21 47 seg20 56 seg29 55 seg28 54 seg27 58 seg31 57 seg30 78 v pp 77 p03 76 p02 75 p01 74 p00 73 v ss 72 p21 71 p20 70 p43 69 p42 68 p50 67 p51 66 p52 65 p53 64 seg37 63 seg36 62 seg35 61 seg34 60 seg33 59 seg32 2.36 mm 2.31 mm x y
fedl610q479-03 ml610q477/ml610q478/ML610Q479 9/31 pad coordinates ml610q477/ml610q478/ml 610q479 pad coordinates table 1 ml610q477/ml610q478/ML610Q479 pad coordinates chip center: x=0,y=0 ml610q477/8/9 ml610q477/8/9 pad no. pad name x (m) y (m) pad no. pad name x (m) y (m) 1 p57 -870 -1049 45 seg18 440 1049 2 p56 -790 -1049 46 seg19 360 1049 3 p55 -710 -1049 47 seg20 280 1049 4 p54 -630 -1049 48 seg21 200 1049 5 v dd -550 -1049 49 seg22 120 1049 6 v ss -470 -1049 50 seg23 40 1049 7 v ddl -390 -1049 51 seg24 -40 1049 8 ch1 -270 -1049 52 seg25 -120 1049 9 ch2 -190 -1049 53 seg26 -200 1049 10 v ddx -70 -1049 54 seg27 -280 1049 11 xt0 90 -1049 55 seg28 -360 1049 12 xt1 250 -1049 56 seg29 -440 1049 13 reset_n 330 -1049 p67 (*1) 14 test0 410 -1049 57 seg30 (*2) (*3) -680 1049 15 p44 510 -1049 p66 (*1) 16 p45 590 -1049 58 seg31 (*2) (*3) -760 1049 17 p46 670 -1049 p65 (*1) 18 p47 750 -1049 59 seg32 (*2) (*3) -1074 805 19 p35 850 -1049 p64 (*1) 20 c1 1074 -785 60 seg33 (*2) (*3) -1074 725 21 c2 1074 -705 p63 (*1) (*2) 22 v l1 1074 -625 61 seg34 (*3) -1074 645 23 v l2 1074 -545 p62 (*1) (*2) 24 v l3 1074 -465 62 seg35 (*3) -1074 565 25 com0 1074 -255 p61 (*1) (*2) 26 com1 1074 -175 63 seg36 (*3) -1074 485 27 com2/seg0 1074 -95 p60 (*1) (*2) 28 com3/seg1 1074 -15 64 seg37 (*3) -1074 405 29 com4/seg2 1074 65 65 p53 -1074 305 30 seg3 1074 145 66 p52 -1074 225 31 seg4 1074 225 67 p51 -1074 145 32 seg5 1074 305 68 p50 -1074 65 33 seg6 1074 385 69 p42 -1074 -15 34 seg7 1074 465 70 p43 -1074 -95 35 seg8 1074 545 71 p20 -1074 -195 36 seg9 1074 625 72 p21 -1074 -275 37 seg10 1074 705 73 v ss -1074 -375 38 seg11 1074 785 74 p00 -1074 -475 39 seg12 1074 865 75 p01 -1074 -555 40 seg13 840 1049 76 p02 -1074 -635 41 seg14 760 1049 77 p03 -1074 -715 42 seg15 680 1049 78 v pp -1074 -795 43 seg16 600 1049 44 seg17 520 1049 (*1) pad for ml610q477 . (*2) pad for ml610q478. (*3) pad for ML610Q479.
fedl610q479-03 ml610q477/ml610q478/ML610Q479 10/31 pin list primary function secondary function pin no. pad no. pin name i/o function pin name i/o function 6, 75 6, 73 vss ? negative power supply pin ? ? ? 5 5 v dd ? positive power supply pin ? ? ? 7 7 v ddl ? power supply pin for internal logic (internally generated) ? ? ? 10 10 v ddx ? power supply pin for low-speed oscillation (internally generated) ? ? ? 80 78 v pp ? power supply pin for flash rom ? ? ? 23 22 v l1 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*1) ? ? ? 24 23 v l2 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*1) ? ? ? 25 24 v l3 ? power supply pin for lcd bias (internally generated) ? ? ? 21 20 c1 ? capacitor connection pin for lcd bias generation ? ? ? 22 21 c2 ? capacitor connection pin for lcd bias generation ? ? ? 8 8 ch1 ? capacitor connection pin for halver circuit ? ? ? 9 9 ch2 ? capacitor connection pin for halver circuit ? ? ? 15 14 test0 i/o test pin ? ? ? 14 13 reset_n i reset input pin ? ? ? 11 11 xt0 i low-speed clock oscillation pin ? ? ? 13 12 xt1 o low-speed clock oscillation pin ? ? ? 76 74 p00/exi0/ cap0/tprun0 i input port, external interrupt, capture 0 input timer c/timer d external trigger input ? ? ? 77 75 p01/exi1/ cap1/tprun1 i input port, external interrupt, capture 1 input timer c/timer d external trigger input ? ? ? 78 76 p02/exi2/ rxd0/tprun2 i input port, external interrupt, uart0 received data timer c/timerd external trigger input ? ? ? 79 77 p03/exi3/ tprun3 i input port, external interrupt timer c/timer d external trigger input ? ? ? 73 71 p20/led0 o output port lsclk o low-speed clock output 74 72 p21/led1 o output port outclk o high-speed clock output 20 19 p35 i/o input/output port rcm o rc type adc oscillation monitor 71 69 p42 i/o input/output port rxd0 i uart data input 72 70 p43 i/o input/output port txd0 o uart data output 16 15 p44/t02ck/ tcdrun i/o input/output port, timer 0/timer 2 external clock input timer c/timer d external trigger input in1 i rc type adc1 oscillation input pin 17 16 p45/t13ck/ tcdrun i/o input/output port, timer 1/timer 3 external clock input timer c/timer d external trigger input cs1 o rc type adc1 reference capacitor connection pin 18 17 p46/tcck i/o input/output port timer c/timer d external clock input rs1 o rc type adc1 reference resistor connection pin 19 18 p47/tdck i/o input/output port timer c/timerd external clock input rt1 o rc type adc1 measurement resistor sensor connection pin 70 68 p50/exi8 i/o input/output port, external interrupt ? ? ? 69 67 p51/exi8 i/o input/output port, external interrupt ? ? ?
fedl610q479-03 ml610q477/ml610q478/ML610Q479 11/31 primary function secondary function pin no. pad no. pin name i/o function pin name i/o function 68 66 p52/exi8 i/o input/output port, external interrupt ? ? ? 67 65 p53/exi8 i/o input/output port, external interrupt ? ? ? 4 4 p54/exi8/ cmpp0 i/o input/output port, external interrupt analog comparator noninverting input0 pin ? ? ? 3 3 p55/exi8/ cmpp1 i/o input/output port, external interrupt analog comparator noninverting input1 pin ? ? ? 2 2 p56/exi8/ cmpm0 i/o input/output port, external interrupt analog comparator inverting input0 pin ? ? ? 1 1 p57/exi8/ cmpm1 i/o input/output port, external interrupt analog comparator inverting input1 pin ? ? ?
fedl610q479-03 ml610q477/ml610q478/ML610Q479 12/31 primary function secondary function pin no. pad no. pin name i/o function pin name i/o function 26 25 com0 o lcd common pin ? ? ? 27 26 com1 o lcd common pin ? ? ? 28 27 com2/seg0 o lcd common/segment pin ? ? ? 29 28 com3/seg1 o lcd common/segment pin ? ? ? 30 29 com4/seg2 o lcd common/segment pin ? ? ? 31 30 seg3 o lcd segment pin ? ? ? 32 31 seg4 o lcd segment pin ? ? ? 33 32 seg5 o lcd segment pin ? ? ? 34 33 seg6 o lcd segment pin ? ? ? 35 34 seg7 o lcd segment pin ? ? ? 36 35 seg8 o lcd segment pin ? ? ? 37 36 seg9 o lcd segment pin ? ? ? 38 37 seg10 o lcd segment pin ? ? ? 39 38 seg11 o lcd segment pin ? ? ? 40 39 seg12 o lcd segment pin ? ? ? 41 40 seg13 o lcd segment pin ? ? ? 42 41 seg14 o lcd segment pin ? ? ? 43 42 seg15 o lcd segment pin ? ? ? 44 43 seg16 o lcd segment pin ? ? ? 45 44 seg17 o lcd segment pin ? ? ? 46 45 seg18 o lcd segment pin ? ? ? 47 46 seg19 o lcd segment pin ? ? ? 48 47 seg20 o lcd segment pin ? ? ? 49 48 seg21 o lcd segment pin ? ? ? 50 49 seg22 o lcd segment pin ? ? ? 51 50 seg23 o lcd segment pin ? ? ? 52 51 seg24 o lcd segment pin ? ? ? 53 52 seg25 o lcd segment pin ? ? ? 54 53 seg26 o lcd segment pin ? ? ? 55 54 seg27 o lcd segment pin ? ? ? 56 55 seg28 o lcd segment pin ? ? ? 57 56 seg29 o lcd segment pin ? ? ? p67(*2) o output port ? ? ? 59 57 seg30(*3) (*4) o lcd segment pin ? ? ? p66(*2) o output port ? ? ? 60 58 seg31(*3) (*4) o lcd segment pin ? ? ? p65(*2) o output port ? ? ? 61 59 seg32(*3) (*4) o lcd segment pin ? ? ? p64(*2) o output port ? ? ? 62 60 seg33(*3) (*4) o lcd segment pin ? ? ? p63(*2) (*3) o output port ? ? ? 63 61 seg34(*4) o lcd segment pin ? ? ? p62(*2) (*3) o output port ? ? ? 64 62 seg35(*4) o lcd segment pin ? ? ? p61(*2) (*3) o output port ? ? ? 65 63 seg36(*4) o lcd segment pin ? ? ? p60(*2) (*3) o output port ? ? ? 66 64 seg37(*4) o lcd segment pin ? ? ? (*1) internally generated, or connect to either positive power supply pin (v dd ) or power supply pin for internal logic (v ddl ). for details, see user?s manual. (*2) pad for ml610q477. (*3) pad for ml610q478. (*4) pad for ML610Q479.
fedl610q479-03 ml610q477/ml610q478/ML610Q479 13/31 pin description pin name i/o description primary/ secondary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal resonator is connected to this pin. capacitors c dl and c gl are connected across this pin and v ss . (see appendix c measuring circuit 1) ? ? lsclk o low-speed clock output. assigned to the secondary function of the p20 pin. secondary ? outclk o high-speed clock output pin. this pin is used as the secondary function of the p21 pin. secondary ? general-purpose input port p00 to p03 i general-purpose input port. primary positive general-purpose output port p20, p21 o general-purpose output port. this cannot be used as the general output port when used as the secondary function. primary positive general-purpose input/output port p35 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary function. primary positive p42 to p47 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary or tertiary function. primary positive p50 to p57 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary function. primary positive p60 to p63 o general-purpose output port. incorporated only into ml610q477/ml610q478, and not into ML610Q479. primary positive p64 to p67 o general-purpose output port. incorporated only into ml610q477, and not into ml610q478/ ML610Q479. primary positive
fedl610q479-03 ml610q477/ml610q478/ML610Q479 14/31 pin name i/o description primary/ secondary logic uart txd0 o uart data output pin. this pin is used as the secondary function of the p43 pin. secondary positive rxd0 i uart data input pin. this pin is used as the secondary function of the p42 or the primary function of the p02 pin. primary/ secondary positive external interrupt exi0-3 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p00 to p03 pins. primary positive/ negative exi8 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. assigned to the primary function of the p50 to p57 pins. primary positive/ negative capture cap0 i primary positive/ negative cap1 i capture trigger input pins. the value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. these pins are used as the primary functions of the p00 pin(cap0) and p01 pin(cap1). primary positive/ negative timer t02ck i external clock input pin used for both timer 0 and timer 2. this pin is used as the primary function of the p44 pin. primary ? t13ck i external clock input pin used for both timer 1 and timer 3. this pin is used as the primary function of the p45 pin. primary ? tcck i external clock input pin used for timer c. this pin is used as the primary function of the p46 pin. primary ? tdck i external clock input pin used for timer d. this pin is used as the primary function of the p47 pin. primary ? tcdrun i external trigger input pin used for timer c or timer d. this pin is used as the primary function of the p44 pin or the p45 pin. primary ? tprun0 i external trigger input pin used for timer c or timer d. this pin is used as the primary function of the p00 pin. primary ? tprun1 i external trigger input pin used for timer c or timer d. this pin is used as the primary function of the p01 pin. primary ? tprun2 i external trigger input pin used for timer c or timer d. this pin is used as the primary function of the p02 pin. primary ? tprun3 i external trigger input pin used for timer c or timer d. this pin is used as the primary function of the p03 pin. primary ? led drive led0, led1 o n-channel open drain output pins to drive led. this pin is used as the primary function of the p20 and the p21 pins. primary positive /negative
fedl610q479-03 ml610q477/ml610q478/ML610Q479 15/31 pin name i/o description primary/ secondary logic rc oscillation type a/d converter rcm o rc oscillation monitor pin. this pin is used as the secondary function of the p35 pin. secondary ? in1 i oscillation input pin of channel 1. this pin is used as the secondary function of the p44 pin. secondary ? cs1 o reference capacitor connection pin of channel 1. this pin is used as the secondary function of the p45 pin. secondary ? rs1 o reference resistor connection pin of channel 1. this pin is used as the secondary function of the p46 pin. secondary ? rt1 o resistor sensor connection pin for measurement of channel 1. this pin is used as the secondary function of the p47 pin. secondary ? analog comparator cmpp0 i analog comparator noninverting input0 pin. this pin is used as the secondary function of the p54. primary ? cmpp1 i analog comparator noninverting input1 pin. this pin is used as the secondary function of the p55. primary ? cmpm0 i analog comparator inverting input0 pin. this pin is used as the secondary function of the p56. primary ? cmpm1 i analog comparator inverting input1 pin. this pin is used as the secondary function of the p57. primary ? lcd drive signal com0 to com4 o common output pins. com2, com3, and com4 can be switched to seg0, seg1, and seg2, respectively, through the register setting. to change the setting, switch between com4 and seg2 for one pin and switch between com3, com4 and seg1, seg2 for two pins. ? ? seg0 to seg29 o segment output pin. the seg0, seg1, and seg2 pins are for switching the register setting with the com2, com3, and com4. ? ? seg30 to seg33 o segment output pin. incorporated into ml610q478/ML610Q479, not into ml610q477. ? ? seg34 to seg37 o segment output pin. incorporated into ML610Q479, not into ml610q477/ml610q478. lcd driver power supply v l1 ? ? ? v l2 ? ? ? v l3 ? power supply pin for lcd bias (internally generated) or power supply connection pin. depending on lcd bias setting and v dd voltage level, v dd or v ddl or capacitor is connected. for details of the connection method, see chapter 20, "lcd drivers". ? ? c1 ? ? ? c2 ? power supply pins for lcd bias (internally generated). capacitor c 12 (see appendix c measuring circuit 1) is connected between c1 and c2. ? ?
fedl610q479-03 ml610q477/ml610q478/ML610Q479 16/31 pin name i/o description primary/ secondary logic test test0 i/o pin for testing. a pull-down resistor is internally connected. ? positive power supply v ss ? negative power supply pin. ? ? v dd ? positive power supply pin. ? ? v ddl ? positive power supply pin (internally generated) for internal logic. capacitors c l (see appendix c measuring circuit 1) are connected between this pin and v ss . ? ? v ddx ? positive power supply pin (internally generated) for low-speed oscillation. capacitor c x (see measuring circuit 1) should be connected between this pin and v ss . ? ? ch1 ? ? ? ch2 ? capacitor connection pin for halver circuit. capacitor c h12 (see appendix c measuring circuit 1) are connected between ch1 and ch2. ? ? v pp ? power supply pin for programming flash rom. a pull-down resistor is internally connected. ? ?
fedl610q479-03 ml610q477/ml610q478/ML610Q479 17/31 termination of unused pins table 2 shows methods of terminating the unused pins. table 2 termination of unused pins pin recommended pin handling vpp open vl1 open vl2 open vl3 open c1, c2 open reset_n open test0 pull down(1k ? to vss) p00 to p03 vdd or vss p20, p21 open p35 open p42 to p47 open p50 to p57 open p60 to p67 open com0 to com 4 open seg0 to seg 37 open note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
fedl610q479-03 ml610q477/ml610q478/ML610Q479 18/31 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta=25c -0.3 to +4.6 v power supply voltage 2 v pp ta=25c -0.3 to +9.5 v power supply voltage 3 v ddl ta=25c -0.3 to +3.6 v power supply voltage 4 v l1 ta=25c -0.3 to +2.0 v power supply voltage 5 v l2 ta=25c -0.3 to +4.0 v power supply voltage 6 v l3 ta=25c -0.3 to +6.0 v input voltage v in ta=25c -0.3 to v dd +0.3 v output voltage v out ta=25c -0.3 to v dd +0.3 v output current 1 i out1 port 3 to 6, ta=25c -12 to +11 ma output current 2 i out2 port 2, ta=25c -12 to +20 ma power dissipation pd ta=25c 0.9 w storage temperature t stg D -55 to +150 c recommended operating conditions (v ss = 0v) parameter symbol condition range unit without p version -20 to +70 operating temperature t op p version -40 to +85 c f op =30k to 625khz 1.25 to 3.6 operating voltage v dd f op =30k to 2.5mhz 1.8 to 3.6 v v dd =1.25 to 3.6v 30k to 625k operating frequency (cpu) f op v dd =1.8 to 3.6v 30k to 2.5m hz low-speed crystal oscillation frequency f xtl D 32.768k hz c dl D 3 to 18 low-speed crystal oscillation external capacitance c gl D 3 to 18 pf v dd pin external capacitance c v D 1.030% to 2.230% * 1 f v ddl pin external capacitance c l D 0.4730% to 2.230% * 2 f v ddx pin external capacitance c x D 0.1530% f v l1, 2, or 3 pin external capacitance c a,b,c D 0.130% f pin-to-pin (c1 to c2) external capacitance c 12 D 0.4730% f pin-to-pin (ch1 to ch2) external capacitance c h12 D 0.06830% f * 1 : please select as c v is larger than c l or same as c l . * 2 : when the load of vdd is small and the power rise time is too short, it may happen that the power-on reset is not generated. in this case please select c l with larger capacitance
fedl610q479-03 ml610q477/ml610q478/ML610Q479 19/31 operating conditions of flashrom (vss= 0v) parameter symbol condition range unit operating temperature t op at write/erase 0 to +40 c v dd at write/erase 2.75 to 3.6 v ddl at write/erase *1 2.5 to 2.75 operating voltage v pp at write/erase 7.7 to 8.3 v rewrite count c ep D 80 cycles data retention y dr D 10 years *1 : when writing to and erasing on the flash memory, the voltage in the specified range needs to be supplied to the v ddl pin. the v pp pin has an internal pull-down resistor. operation conditions of comparator (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measurement circuit common-mode input voltage cmv in v dd =1.8 to 3.6v 0.2 D v dd - 1 v analog comparator input offset voltage v cmpof v dd =1.8 to 3.6v,ta=25 c -30 D 30 mv analog comparator response time t cmp v dd =1.8 to 3.6v,ta=25 c, overdrive=100ma D D 1 s analog comparator supply current i cmp v dd =1.8 to 3.6v,ta=25 c D 15 30 a temperature sensor output voltage v tmp ta = +25c D 610 D mv ta = -40 to +25c D -1.820 D temperature sensor output voltage (temperature property) ? v tmp ta = 25 to 85c D -1.913 D mv/c temperature sensor supply current i tmp v dd =1.8 to 3.6v,ta=25 c D 70 100 a 0.7v voltage source output voltage v ref v dd =1.8 to 3.6v,ta=25 c 0.693 0.700 0.707 v 0.7v voltage source temperature deviation ? v ref D D 0 D %/c 0.7v voltage source supply current i ref v dd =1.8 to 3.6v,ta=25 c D 6.5 10 a 1
fedl610q479-03 ml610q477/ml610q478/ML610Q479 20/31 dc characteristics (1/5) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ta=25c typ. -10% 500 typ. +10% khz v dd =1.25 to 3.6v * 2 typ. -25% 500 typ. +25% khz ta=25 c typ. -10% 2.0 typ. +10% mhz 500khz/2mhz rc oscillation frequency f rc v dd =1.8 to 3.6v * 3 typ. -25% 2.0 typ. +25 % mhz low-speed crystal oscillation start time* 1 t xtl D D 0.6 2 s 500khz/2mhz rc oscillation start time t rc D D D 3 s reset pulse width p rst D 200 D D reset noise elimination pulse width p nrst D D D 0.3 s power-on reset generated power rise time t por D D D 10 ms 1 * 1 : 32.768khz crystal resonator dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf). * 2 : recommended operating temperature (ta=-20 to 70c, ta=-40 to 85c for p version) reset reset_n reset_n pin reset vdd 0.9xv dd 0.1xv dd t por power on reset p rst vil1 vil1
fedl610q479-03 ml610q477/ml610q478/ML610Q479 21/31 dc characteristics (2/5) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit fop=30k to 625khz 1.1 1.2 1.3 v ddl voltage v ddl fop=30k to 2.5mhz 1.35 1.5 1.65 v v ddl temperature deviation * 1 ? v ddl v dd =3.0v D -1 D mv/c v ddl voltage dependency * 1 ? v ddl D D 5 20 mv/v 1 * 1 : the maximum v ddl voltage becomes the v dd voltage level when the v ddl voltage determined by the temperature and voltage deviations mathematically exceeds the v dd voltage. dc characteristics (3/5) (vdd=3.0v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ta=25c D 0.32 0.8 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. * 5 D D 8 a ta=25c D 0.8 1.3 supply current 2 idd2 cpu: in halt state. (ltbc, wdt: operating)* 3 * 4 . high-speed 500khz oscillation: stopped. lcd/bias circuits: operating * 6 * 5 D D 9 a ta=25c D 4.5 8 supply current 3 idd3 cpu: in 32.768khz operating state.* 1 * 3 high-speed 500khz oscillation: stopped, lcd/bias circuits: operating * 2 * 5 D D 15 a ta=25c D 75 100 supply current 4-1 idd4-1 cpu: in 500khz rc operating state. lcd/bias circuits: operating.* 2 * 5 D D 120 a ta=25c D 300 350 supply current 4-2 idd4-2 cpu: in 2mhz rc operating state. lcd/bias circuits: operating.* 2 * 5 D D 400 a 1 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : all segs: off waveform, no lcd panel load, 1/3 bias, 1/3 duty, frame frequency: approx. 64 hz, bias voltage multiplying clock : 1/128 lsclk (256hz) * 3 : 32.768khz crystal resonator dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf) * 4 : significant bits of blkcon0 to blkcon4 registers are all ?1? except dlcd bit on blkcon4. * 5 : recommended operating temperature (ta=-20 to 70c, ta=-40 to 85c for p version) * 6 : lcd stop mode, 1/3 bias, bias voltage multiplying clock: 1/128 lsclk (256hz)
fedl610q479-03 ml610q477/ml610q478/ML610Q479 22/31 dc characteristics (4/5) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ioh1=-0.5ma, v dd =1.8 to 3.6v v dd -0.5 D D voh1 ioh1=-0.03ma, v dd =1.25 to 3.6v v dd -0.3 D D iol1=+0.5ma, v dd =1.8 to 3.6v D D 0.5 output voltage 1 (p20, p21 (n-channel open drain output mode is not selected)) (p35) (p42 to p47) (p50 to p53) (p60 to p63) *2 (p60 to p67) *1 vol1 iol1=+0.1ma, v dd =1.25 to 3.6v D D 0.3 output voltage 2 (p20, p21 (n-channel open drain output mode is selected)) vol2 iol2=+5ma, v dd =1.8 to 3.6v D D 0.5 voh3 ioh3=-0.05ma, vl1=1.2v v l3 -0.2 D D voml3 ioml3=+0.05ma, vl1=1.2v D D v l2 +0.2 voml3s ioml3s=-0.05ma, vl1=1.2v v l2 -0.2 D D volm3 iolm3=+0.05ma, vl1=1.2v D D v l1 +0.2 volm3s iolm3s=-0.05ma, vl1=1.2v v l1 -0.2 D D output voltage 3 (com0 to 4) (seg0 to 29) *1 (seg0 to 33) *2 (seg0 to 37) *3 vol3 iol3=+0.05ma, vl1=1.2v D D 0.2 v 2 iooh voh=v dd (in high-impedance state) D D 1 output leakage (p20, p21) (p35) (p42 to p47) (p50 to p53) (p60 to p63) *2 (p60 to p67) *1 iool vol=v ss (in high-impedance state) -1 D D a 3 iih1 vih1=v dd D D 1 input current 1 (reset_n, test1_n) iil1 vil1=v ss -600 -300 -2 iih2 vih2=v dd 2 300 600 input current 2 (test0) iil2 vil2=v ss -1 D D vih3=v dd, v dd =1.8 to 3.6v (when pulled-down) 2 30 200 iih3 vih3=v dd, v dd =1.25 to 3.6v (when pulled-down) 0.01 30 200 vil3=v ss, v dd =1.8 to 3.6v (when pulled-up) -200 -30 -2 iil3 vil3=v ss, v dd =1.25 to 3.6v (when pulled-up) -200 -30 -0.01 iih3z vih3=v dd (in high-impedance state) D D 1 input current 3 (p00 to p03) (p35) (p42 to p47) (p50 to p53) iil3z vil3=v ss (in high-impedance state) -1 D D a 4 * 1 : characteristics for ml610q477. * 2 : characteristics for ml610q478. * 3 : characteristics for ML610Q479.
fedl610q479-03 ml610q477/ml610q478/ML610Q479 23/31 dc characteristics (5/5) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit vih1 D 0.7 v dd D v dd input voltage 1 (reset_n) (test0) (p00 to p03) (p35) (p42 to p47) (p50 to p53) vil1 v dd =1.25 to 3.6v 0 D 0.2 v dd v 5 input pin capacitance (p00 to p03) (p35) (p42 to p47) (p50 to p53) cin f=10khz v rms =50mv ta=25c D D 5 pf D
fedl610q479-03 ml610q477/ml610q478/ML610Q479 24/31 measuring circuits measuring circuit 1 measuring circuit 2 input pin v v dd v ddl v l1 v l2 v l3 v ss vih vil output pin *1: input logic circuit to determine the specified measuring conditions. (note 2) repeats for the specified output pin (note 2) (note 1) v ddx xt0 xt1 a v dd v ddl c l v l1 c a v l2 v l3 c c v ss c2 c1 c 12 c v : 1f c l : 2.2uf cx : 0.15f c a ,c b ,c c : 0.1f c 12 : 0.47f c h12 :0.068f 32.768khz crystal resonator : dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) c gl , c dl : 6pf c v c dl 32.768khz crystal resonator v ddx c x c h12 ch2 ch1
fedl610q479-03 ml610q477/ml610q478/ML610Q479 25/31 measuring circuit 3 measuring circuit 4 input pin a v dd v ddl v l1 v l2 v l3 v ss output pin (note 3) repeats for the specified input pin (note 3) v ddx input pin a v dd v ddl v l1 v l2 v l3 v ss vih vil output pin *1: input logic circuit to determine the specified measuring conditions. (note 2) repeats for the specified output pin (note 2) (note 1) v ddx
fedl610q479-03 ml610q477/ml610q478/ML610Q479 26/31 measuring circuit 5 input pin v dd v ddl v l1 v l2 v l3 v ss vih vil output pin *1: input logic circuit to determine the specified measurin g conditions. (note 1) waveform observation v ddx
fedl610q479-03 ml610q477/ml610q478/ML610Q479 27/31 ac characteristics (external interrupt) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 76.8 D 106.8 s ac characteristics (uart) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit transmit baud rate t tbrt D D brt* 1 D s receive baud rate t rbrt D brt* 1 -3% brt* 1 brt* 1 +3% s * 1 : baud rate period (including the error of the clock frequency selected) set with the uart baud rate register (ua0brtl,h) and the uart mode register 0 (ua0mod0). t rbrt txd0* rxd0* *: indicates the secondary function of the port. t tbrt t nul p00?p07 (rising-edge interrupt) p00?p07 (falling-edge interrupt) p00?p07 (both-edge interrupt) t nul t nul
fedl610q479-03 ml610q477/ml610q478/ML610Q479 28/31 ac characteristics (rc oscillation a/d converter) condition for v dd =1.8 to 3.6v (v dd =1.8 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs1,rt1 cs0, ct0, cs1 740pf 1 D D k ? f osc1 resistor for oscillation=1k ? 457.3 525.2 575.1 khz f osc2 resistor for oscillation=10k ? 53.48 58.18 62.43 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=100k ? 5.43 5.89 6.32 khz kf1 rt1=1k ? 7.972 9.028 9.782 ? kf2 rt1=10k ? 0.981 1 1.019 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt1=100k ? 0.099 0.101 0.104 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt1-cs1 oscillation) kfx = f oscx (rs1-cs1 oscillation) , ( x = 1, 2, 3 ) v dd v ddl c l v ss c v rt1: 1k ? /10k ? /100k ? rs1: 10k ? cs1: 560pf cvr1: 820pf rcm frequency measurement (f oscx ) input pin vih vil *1: input logic circuit to determine the spec ifi ed m easu rin g co n d i t i o n s . in1 cs1 rs1 rt1 cs1 rs1 rt1 cvr1 (note 1)
fedl610q479-03 ml610q477/ml610q478/ML610Q479 29/31 condition for v dd =1.25 to 3.6v (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs1,rt1 cs1 740pf 1 D D k ? f osc1 resistor for oscillation=6k ? 81.93 93.16 101.2 khz f osc2 resistor for oscillation=15k ? 35.32 38.75 41.48 khz oscillation frequency v dd = 1.5v f osc3 resistor for oscillation=105k ? 5.22 5.65 6.03 khz kf1 rt1=1k ? 2.139 2.381 2.632 ? kf2 rt1=10k ? 0.973 1 1.028 ? rs to rt oscillation frequency ratio *1 v dd = 1.5v kf3 rt1=100k ? 0.142 0.147 0.152 ? f osc1 resistor for oscillation=6k ? 85.28 94.58 103.3 khz f osc2 resistor for oscillation=15k ? 35.72 38.87 41.78 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=105k ? 5.189 5.622 6.012 khz kf1 rt1=1k ? 2.227 2.432 2.626 ? kf2 rt1=10k ? 0.982 1 1.018 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt1=100k ? 0.141 0.145 0.149 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt1-cs1 oscillation) kfx = f oscx (rs1-cs1 oscillation) , ( x = 1, 2, 3 ) note: ? please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and in1 pin), including cvr1. especially, do not have long wiring between in1 and rs1. the coupling capacitance on the wires may occur incorr ect a/d conversion. also, please do not have signals which may be a source of noise around the node. ? when rt1 (thermistor and etc.) requires long wiring due to the restricted placement, please have v ss (gnd) trace next to the signal. ? please make wiring to components (capacitor, resistor, and so on) n ecessary for objective measurement. wiring to reserved components may affect to the a/d conversion operation by noise the components itself may have. rt1: 1k /10k /100k ra1: 5k rs1: 15k cs1: 560pf cvr1: 820pf frequency measurement (f oscx ) input pin *1: input logic circuit to determine the specified measuring conditions . (note 1) v dd v ddl c l v ss c v rcm vih vil in1 cs1 rs1 rt1 cs1 rs1 cvr1 ra1 rt1
fedl610q479-03 ml610q477/ml610q478/ML610Q479 30/31 revesion history page document no. date previous edition current edition description fedl610q479-01 mar.26,2011 ? ? formally edition 1.0 fedl610q479-02 jul.18,2011 3, 32 3, 32 the package dimension was changed. 19, 19 the pull down register(1k ? to vss) was added to test0. 20 20 the notes about c v , c l were added. fedl610q479-03 jul.31,2014 3, 5, 6, 7, 32 3,4 deleted package product
fedl610q479-03 ml610q477/ml610q478/ML610Q479 31/31 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. examples of application circuits, circuit constants and any othe r information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accord ance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controlle r or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011 ? 2014 lapis semiconductor co., ltd. 2-4-8 shinyokohama, kouhoku-ku, yokohama 222-8575, japan http://www.lapis-semi.com/en/

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