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| this is information on a product in full production. december 2014 docid025409 rev 2 1/124 stm32f334x4 stm32f334x6 stm32f334x8 arm ? cortex ? -m4 32b mcu+fpu,up to 64kb flash,16kb sram, 2 adcs,3 dacs,3 comp.,op-amp ,10-ch. high-resolution timer datasheet ? production data features ? core: arm ? cortex ? -m4 32-bit cpu with fpu (72 mhz max), single-cyc le multiplication and hw division, dsp instruction ? memories ? up to 64 kb of flash memory ? up to 12 kb of sram with hw parity check ? routine booster: 4 kb of sram on instruction and data bus with hw parity check (ccm) ? crc calculation unit ? reset and supply management ?v dd, v dda voltage range: 2.0 to 3.6 v ? power-on/power-down reset (por/pdr) ? programmable voltage detector (pvd) ? low-power modes: sleep,stop,standby ?v bat supply for rtc and backup registers ? clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc (up to 64 mhz with pll option) ? internal 40 khz oscillator ? up to 51 fast i/o por ts, all mappable on external interrupt vectors, several 5 v-tolerant ? interconnect matrix ? 7-channel dma controller ? up to two adc 0.20 s (up to 21 channels) with selectable resolution of 12/10/8/6 bits, 0 to 3.6 v conversion range, single- ended/differential mode, separate analog supply from 2.0 to 3.6 v ? temperature sensor ? up to three 12-bit dac channels with analog supply from 2.4 v to 3.6 v ? three ultra-fast rail-to-rail analog comparators with analog supply from 2 v to 3.6 v ? one operational amplifiers that can be used in pga mode, all terminals accessible with analog supply from 2.4 to 3.6 v ? up to 18 capacitive sensing channels supporting touchkeys, linear and rotary touch sensors ? up to 12 timers ? hrtim: 6 x16-bit counters, 217 ps resolution, 10 pwm, 5 fault inputs, 10 ext event input, 1 synchro. input,1 synchro. out ? one 32-bit timer and one 16-bit timer with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? one 16-bit 6-channel advanced-control timer, with up to 6 pwm channels, deadtime generation and emergency stop ? one 16-bit timer with 2 ic/ocs, 1 ocn/pwm, deadtime generation, emergency stop ? two 16-bit timers with ic/oc/ocn/pwm, deadtime generation and emergency stop ? two watchdog timers (independent, window) ? systick timer: 24-bit downcounter ? up to two 16-bit basic timers to drive dac ? calendar rtc with ala rm, periodic wakeup from stop ? communication interfaces ? can interface (2.0 b active) and one spi ?one i 2 c with 20 ma current sink to support fast mode plus, smbus/pmbus ? up to 3 usarts, one with iso/iec 7816 interface, lin, irda, modem control ? debug mode: serial wire debug (swd), jtag ? 96-bit unique id ? all packages ecopack ? 2 table 1. device summary reference part number stm32f334kx stm32f334k4/k6/k8 stm32f334cx stm32f334c4/c6/c8 stm32f334rx stm32f334r4/r6/r8 lqfp32 (7 x 7 mm) lqfp48 (7 x 7 mm) lqfp64 (10 x 10 mm) www.st.com
contents stm32f334x4 stm32f334x6 stm32f334x8 2/124 docid025409 rev 2 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 arm ? cortex ? -m4 core with fpu with embedded flash ? and sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.2 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.3 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.3 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 14 3.4 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 19 3.9.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 19 3.10 fast analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10.2 internal voltage reference (vrefint) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10.3 v bat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.10.4 opamp2 reference voltage (vopamp2) . . . . . . . . . . . . . . . . . . . . . . . . 21 3.11 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12 operational amplifier (opamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.13 ultra-fast comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 docid025409 rev 2 3/124 stm32f334x4 stm32f334x6 stm32f334x8 contents 4 3.14.1 high-resolution timer (hrtim 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.2 advanced timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.3 general-purpose timers (tim2, tim3, tim15, tim16, tim17) . . . . . . . . 24 3.14.4 basic timers (tim6 and tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14.5 independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14.6 window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14.7 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.15 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25 3.16 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.16.1 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.16.2 universal synchronous/asynchronous receiver transmitters (usarts) . 27 3.16.3 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.16.4 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.17 infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.18 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.19 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.19.1 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 30 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 56 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 56 contents stm32f334x4 stm32f334x6 stm32f334x8 4/124 docid025409 rev 2 6.3.4 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.6 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.10 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.16 high-resolution timer (hrtim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.3.17 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.18 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.19 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.3.20 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6.3.21 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.3.22 operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.3.23 temperature sensor (ts) characteristics . . . . . . . . . . . . . . . . . . . . . . . 109 6.3.24 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 7 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 7.2.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 121 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 docid025409 rev 2 5/124 stm32f334x4 stm32f334x6 stm32f334x8 list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f334x4/6/8 family device features and pe ripheral counts . . . . . . . . . . . . . . . . . . . . 10 table 3. v dda ranges for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. stm32f334x4/6/8 peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7. stm32f334x4/6/8 i 2 c implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 8. usart features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. stm32f334x4/6/8 spi implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10. capacitive sensing gpios available on stm32f334x4/6/8 devices . . . . . . . . . . . . . . . . . 29 table 11. no. of capacitive sensing channels available on stm32f334x4/6/8 devices. . . . . . . . . . . 29 table 12. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. stm32f334x4/6/8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 15. stm32f334x4/6/8 peripheral register boundary addr esses. . . . . . . . . . . . . . . . . . . . . . . . 48 table 16. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 17. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 18. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 19. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 20. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 21. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 22. programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 23. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 table 24. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 25. typical and maximum current consumption from v dd supply at v dd = 3.6v . . . . . . . . . . . 59 table 26. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 61 table 27. typical and maximum v dd consumption in stop and standby modes. . . . . . . . . . . . . . . . 61 table 28. typical and maximum v dda consumption in stop and standby modes. . . . . . . . . . . . . . . 62 table 29. typical and maximum current consumption from v bat supply. . . . . . . . . . . . . . . . . . . . . . 62 table 30. typical current consumption in run mode, code with data processing running from flash 64 table 31. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 65 table 32. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 33. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 34. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 35. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 36. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 37. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 38. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 39. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 40. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 41. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 42. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 43. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 44. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 45. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 46. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 47. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 48. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 list of tables stm32f334x4 stm32f334x6 stm32f334x8 6/124 docid025409 rev 2 table 49. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 50. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 51. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 52. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 53. hrtim1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 54. hrtim output response to fault pr otection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 55. hrtim output response to external events 1 to 5 (low latency mode). . . . . . . . . . . . . . . 88 table 56. hrtim output response to external events 1 to 10 (synchronous mode ) . . . . . . . . . . . . . 88 table 57. hrtim synchronization input / output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 58. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 59. iwdg min./max. timeout period at 40 khz (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 60. wwdg min./max. timeout value at 72 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 61. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 62. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 63. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 64. maximum adc rain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 65. adc accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 66. adc accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 67. adc accuracy at 1msps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 68. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 69. comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 70. operational amplifier characteristic s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 71. temperature sensor (ts) characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 72. temperature sensor (ts) calibra tion values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 73. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 74. lqfp32 ? 7 x 7mm, 32-pin low-profile quad flat package mechanical data. . . . . . . . . . . 111 table 75. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . 114 table 76. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . 117 table 77. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 78. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 79. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 docid025409 rev 2 7/124 stm32f334x4 stm32f334x6 stm32f334x8 list of figures 7 list of figures figure 1. stm32f334x4/6/8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 3. infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 4. lqfp32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 5. lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 6. lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 7. stm32f334x4/6/8 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 8. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 9. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 10. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 11. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 12. typical v bat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) . . . . . . . . . . . 63 figure 13. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 14. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 15. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 16. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 17. hsi oscillator accuracy char acterization results for soldered parts . . . . . . . . . . . . . . . . . . 75 figure 18. tc and tta i/o input characteristics - cmos port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 19. tc and tta i/o input characteri stics - ttl port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 20. five volt tolerant (ft and ftf) i/o input char acteristics - cmos port. . . . . . . . . . . . . . . . . 83 figure 21. five volt tolerant (ft and ftf) i/o input charac teristics - ttl port . . . . . . . . . . . . . . . . . . . 83 figure 22. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 23. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 24. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 25. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 26. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 27. adc typical current consumption in single-end ed and differential modes . . . . . . . . . . . . . 96 figure 28. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 29. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 30. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 31. opamp voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 32. lqfp32 ? 7 x 7mm, 32-pin low-profile quad fl at package outline . . . . . . . . . . . . . . . . . . 111 figure 33. lqfp32 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 figure 34. lqfp32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 35. lqfp48 ? 7 x 7mm, 48-pin low-profile quad fl at package outline . . . . . . . . . . . . . . . . . . 114 figure 36. lqfp48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 figure 37. lqfp48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 38. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 117 figure 39. lqfp64 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8 figure 40. lqfp64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 introduction stm32f334x4 stm32f334x6 stm32f334x8 8/124 docid025409 rev 2 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the stm32f334x4/6/8 microcontrollers. this stm32f334x4/6/8 datasheet should be read in conjunction with the stm32f303xx rm0364 available from the stmicroelectronics website www.st.com . for information on the cortex ? -m4 core with fpu, please refer to: ? arm ? cortex ? -m4 processor technical reference manual available from the www.arm.com website. ? stm32f3xxx and stm32f4xxx cortex ? -m4 programming manual (pm0214) available from the www.st.com website. docid025409 rev 2 9/124 stm32f334x4 stm32f334x6 stm32f334x8 description 49 2 description the stm32f334x4/6/8 family is based on the high-performance arm ? 32-bit cortex ? -m4 risc core operating at a frequency of up to 72 mhz, and embedding a floating point unit (fpu). the stm32f334x4/6/8 family in corporates high-speed embedded memories ? (up to 64 kbytes of flash memory, up to 12 kbytes of sram), and an extensive range of enhanced i/os and peripherals connected to two apb buses. the stm32f334x4/6/8 devices offer a high resolution timer, two fast 12-bit adcs (5 msps), up to three ultra-fast comparators, an operational amplifier, three dac channels, a low- power rtc, one high-resolution timer, one general-purpose 32-bit timer, one timer dedicated to motor control, and four general-purpose 16-bit timers. they also feature standard and advanced communication interfaces: one i 2 c, one spi, up to three usarts and one can. the stm32f334x4/6/8 family operates in the ?40 to +85 c and ?40 to +105 c temperature ranges from a 2.0 to 3.6 v powe r supply. a comprehensive set of power-saving mode allows the design of low-power applications. the stm32f334x4/6/8 family offers devices in 32, 48 and 64-pin packages. the set of included peripherals changes with the device chosen. description stm32f334x4 stm32f334x6 stm32f334x8 10/124 docid025409 rev 2 table 2. stm32f334x4/6/8 family device features and peripheral counts peripheral stm32f334kx stm32f334cx stm32f334rx flash (kbytes) 16 32 64 16 32 64 16 32 64 sram on data bus (kbytes) 12 core coupled memory sram on instruction bus (ccm sram) (kbytes) 4 timers high-resolution timer 1 (16-bit / 10 channels) advanced control 1 (16-bit) general purpose 4 (16-bit) 1 (32 bit) basic 2 (16-bit) systick timer 1 watchdog timers (independent, window) 2 pwm channels (all) (1) 20 26 28 pwm channels (except complementary) 14 20 22 comm. interfaces spi 1 i 2 c1 usart 2 3 can 1 gpios normal i/os (tc, tta) 10 20 26 5-volt tolerant i/os (ft,ftf) 15 17 25 capacitive sensing channels 14 17 18 docid025409 rev 2 11/124 stm32f334x4 stm32f334x6 stm32f334x8 description 49 dma channels 7 12-bit adcs ? number of channels 2 9 2 15 2 21 12-bit dac channels 3 ultra-fast analog comparator 2 3 operational amplifiers 1 cpu frequency 72 mhz operating voltage 2.0 to 3.6 v operating temperature ambient operating temperature: - 40 to 85 c / - 40 to 105 c junction temperature: - 40 to 125 c packages lqfp32 lqfp48 lqfp64 1. this total considers also the pwms generated on the complementary output channels. table 2. stm32f334x4/6/8 family device features and peripheral counts (continued) peripheral stm32f334kx stm32f334cx stm32f334rx description stm32f334x4 stm32f334x6 stm32f334x8 12/124 docid025409 rev 2 figure 1. stm32f334x4/6/8 block diagram 1. af: alternate function on i/o pins. # 9 ' ' 0 6 y 9 ( ; 7 , 7 : l q : $ 7 & + ' 2 * - 7 ' , - 7 & . 6 : & / . - 7 0 6 6 : ' $ 7 - 7 5 6 7 - 7 ' 2 7 5 $ & ( 6 : 2 1 5 ( 6 ( 7 9 ' ' w r 9 x s w r o l q h v $ + % : . 8 3 ) p d [ 0 + ] 9 6 6 9 5 ( ) * 3 ' 0 $ ; 7 $ / 2 6 & 0 + ] 2 6 & b , 1 2 6 & b 2 8 7 2 6 & b 2 8 7 2 6 & b , 1 $ + % 3 & / . + & / . $ 3 % 3 & / . 9 ' ' 3 2 : ( 5 % d f n x s l q w h u i d f h d v $ ) % x v 0 d w u l [ & 2 5 7 ( ; 0 & 3 8 8 6 $ 5 7 8 6 $ 5 7 f k d q q h o v 6 & / 6 ' $ 6 0 % $ d v $ ) 5 ; 7 ; & 7 6 5 7 6 7 h p s v h q v r u 9 5 ( ) 3 ' & k d q q h o v ( 7 5 ) & / . 6 w d q g e \ , q g : ' * . 6 8 3 3 / < # 9 ' ' 9 ' ' $ 9 6 6 $ 9 % $ 7 w r 9 6 p d u w & d u g d v $ ) 5 ; 7 ; & 7 6 5 7 6 6 p d u w & d u g d v $ ) 5 ; 7 ; & 7 6 5 7 6 6 p d u w & d u g d v $ ) 1 9 , & 6 3 , 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) l q w h u i d f h # 9 ' ' $ 6 8 3 ( 5 9 , 6 , 2 1 5 h v h w , q w $ + % $ 3 % $ 3 % 3 2 5 $ 1 7 , 7 $ 0 3 5 ( 6 ( 7 & / 2 & . & 7 5 / $ 3 % 3 & / . ' $ & b 2 8 7 d v $ ) ' $ & b 2 8 7 d v $ ) 8 6 $ 5 7 & / . , & & / . $ ' & $ ' & & 5 & $ + % ' ( & 2 ' ( 5 * 3 , 2 3 2 5 7 $ d v $ ) 7 , 0 7 , 0 f k d q q h o v f k d q q h o f k d q q h o f r p s o f k d q q h o % 5 . d v $ ) f r p s o f k d q q h o % 5 . d v $ ) f r p s o f k d q q h o % 5 . d v $ ) 7 , 0 # 9 ' ' $ 6 < 6 & ) * & 7 / * u r x s v r i & k d q q h o v d v $ ) 7 , 0 f k d q q h o v f r p s o f k d q q h o ( 7 5 % 5 . d v $ ) ) 3 8 7 3 , 8 6 : - 7 $ * , 1 0 , 1 3 2 8 7 d v $ ) * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 & * 3 , 2 3 2 5 7 ' 3 & > @ 3 % > @ 3 $ > @ , e x v ' e x v 6 \ v w h p e x v ) o d v k . % e l w v ) o d v k l q w h u i d f h 2 e o 7 r x f k 6 h q v l q j & r q w u r o o h u 7 , 0 , ) e l w $ ' & , ) , ) e l w $ ' & , ) # 9 ' ' $ 9 2 / 7 5 ( * 9 7 2 9 3 2 5 3 ' 5 3 9 ' 5 & + 6 0 + ] 5 & / 6 3 / / ; 7 $ / n + ] 5 7 & $ : 8 % d f n x s u h j % 7 , 0 * 3 & r p s d u d w r u , ) 2 s d p s , ) # 9 ' ' $ , ) e l w ' $ & f k d q q h o , ) , & 8 6 $ 5 7 # 9 ' ' $ ' e x v 6 5 $ 0 . % & $ 1 b 7 ; & $ 1 b 5 ; $ 3 % ) p d [ 0 + ] $ 3 % ) p d [ 0 + ] & k d q q h o v ( 7 5 d v $ ) 7 , 0 e l w 3 : 0 7 , 0 + 5 7 , 0 3 ) > @ * 3 , 2 3 2 5 7 ) i d x o w l q s x w v d v $ ) 3 : 0 r x w s x w v h [ w h y h q w l q s x w v v \ q f k u r l q s x w v \ q f k u r r x w s x w e l w ' $ & f k d q q h o , ) ' $ & b 2 8 7 d v $ ) , ) e l w ' $ & f k d q q h o , ) * 3 & r p s d u d w r u * 3 & r p s d u d w r u , 1 0 , 1 3 2 8 7 d v $ ) & & 0 6 5 $ 0 . % % [ & $ 1 docid025409 rev 2 13/124 stm32f334x4 stm32f334x6 stm32f334x8 functional overview 49 3 functional overview 3.1 arm ? cortex ? -m4 core with fpu with embedded flash ? and sram the arm cortex-m4 processor with fpu is the late st generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? 32-bit cortex-m4 risc proc essor with fpu features exce ptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu speeds up software development by using metalanguage development tools, while avoiding saturation. with its embedded arm core, the stm32f334x4/6/ 8 family is compatible with all arm tools and software. figure 1 shows the general block diagrams of the stm32f334x4/6/8 family devices. 3.2 memories 3.2.1 embedded flash memory all stm32f334x4/6/8 devices feature up to 64 kbytes of embedded flash memory available for storing programs and data. the flas h memory access time is adjusted to the cpu clock frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). 3.2.2 embedded sram the stm32f334x4/6/8 devices feature up to 12 kbytes of embedded sram with hardware parity check. the memory can be accessed in read/write at cpu clock speed with 0 wait states, allowing the cpu to achieve 90 dhrystone mips at 72 mhz when running code from ccm (core coupled memory) ram. the sram is organized as follows: ? 4 kbytes of sram on instruction and data bu s with parity check (core coupled memory or ccm) and used to execute critical routines or to access data ? 12 kbytes of sram with parity check mapped on the data bus. functional overview stm32f334x4 stm32f334x6 stm32f334x8 14/124 docid025409 rev 2 3.2.3 boot modes at startup, boot0 pin and boot1 option bit are used to select one of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10), usart2 (pa2/pa3), i2c1 (pb6/pb7). 3.3 cyclic redundancy che ck calculation unit (crc) the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compar ed with a reference signature generated at linktime and stored at a given memory location. 3.4 power management 3.4.1 power supply schemes ? v ss , v dd = 2.0 to 3.6 v : external power supply for i/os and the internal regulator. it is provided externally through v dd pins. ? v ssa , v dda = 2.0 to 3.6 v: external analog power supply for adc, dacs, comparators operational amplifiers, reset blocks, rcs and pll.the minimum vo ltage to be applied to v dda differs from one analog peripherals to another. see the table below, summarizing the v dda ranges for analog peripherals. the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. ? v bat = 1.65 to 3.6 v: power supply for rt c, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. 3.4.2 power supply supervisor the device has an integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device table 3. v dda ranges for analog peripherals analog peripheral min v dda supply max v dda supply adc/comp 2 v 3.6 v dac/opamp 2.4 v 3.6 v docid025409 rev 2 15/124 stm32f334x4 stm32f334x6 stm32f334x8 functional overview 49 remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. ? the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . ? the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the app lication design ensures that v dda is higher than or equal to v dd . the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.4.3 voltage regulator the regulator has three operation modes: main (mr), low-power (lpr), and power-down. ? the mr mode is used in the nominal regulation mode (run) ? the lpr mode is used in stop mode. ? the power-down mode is used in standby mo de: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. the voltage regulator is always enabled after reset. it is disabled in standby mode. 3.4.4 low-power modes the stm32f334x4/6/8 supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled . the voltage regulator can also be put either in normal or in low-power mode. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external li nes, the pvd output, the rtc alarm, compx, i2c or usartx. ? standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillato rs are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), an iwdg reset, a rising edge on the wkup pin, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode. functional overview stm32f334x4 stm32f334x6 stm32f334x8 16/124 docid025409 rev 2 3.5 interconnect matrix several peripherals have direct connecti ons between them. this allows autonomous communication between peripherals, savi ng cpu resources thus power supply consumption. in addition, these hardware co nnections allow fast and predictable latency. note: for more details about the interconnect action s, please refer to the corresponding sections in the rm0316 reference manual. table 4. stm32f334x4/6/8 peripheral interconnect matrix interconnect source interconnect destination interconnect action timx timx timers synchronization or chaining adcx dacx conversion triggers dma memory to memory transfer trigger compx comparator output blanking compx timx timer input: ocrefclear input, input capture adcx tim/hrtim1 timer triggered by analog watchdog gpio rtcclk hse/32 mc0 tim16 clock source used as input channel for hsi and lsi calibration css cpu (hard fault) ram (parity error) compx pvd gpio tim1 tim15, 16, 17 timer break gpio timx external trigger, timer break adcx dacx conversion external trigger dacx compx comparator inverting input hrtim1 dacx/adcx conversion trigger compx hrtim1 compx output is an input event or a fault input for hrtim1 opamp2 hrtim1 opamp2 output is an input event for hrtim1 gpio hrtim1 external fault/even t/ synchro inputs for hrtim1 hrtim1 gpio synchro output for hrtim1 docid025409 rev 2 17/124 stm32f334x4 stm32f334x6 stm32f334x8 functional overview 49 3.6 clocks and startup system clock selection is perf ormed on startup, however the in ternal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for fa ilure. if failure is detected, th e system automatically switches back to the internal rc oscillator. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers allow to configure the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domain s. the maximum fr equency of the ah b and the high speed apb domains is 72 mhz, while the maximum allowed fr equency of t he low speed apb domain is 36 mhz. tim1and hrtim1 maximum frequency is 144 mhz. functional overview stm32f334x4 stm32f334x6 stm32f334x8 18/124 docid025409 rev 2 figure 2. clock tree 0 6 9 l?? er?? d , , ^ k ^ k ^ z / e k ^ z k h d k ^ ??z / e k ^ ??z k h d ? d , , ^ / z / t ' > < ?} / t ' w > > ??u??uxx ? w > > d h > d k d]v o}l }??? , l? w > > > < , ^ / , ^ w ?? ?o ? lu?ueu?u , > < w > > > < ?} , ?u }? u u u}?? v d > ^ > ^ / , ^ / , ^ / , ^ ?} z d w > > ^ z ^ t d k l? ^ z ^ > < z d > < z d ^ >?w? ^ z ^ > < ?} d / d ?u ?u u /( ~ w ?? ?o ? a ? o? ?? & > / d & > < ?} &o?z ??}p?uu]vp ]v? ?( > ^ / ?} /? ?} h ^ z d? ~? a u ?u ? > ^ , ^ / ^ z ^ > < l? w > < ^ z ^ > < , ^ / w > < ?} }?? ? ^??? u ?]u ? & , > < }?? ? (? ?vv]vp o}l ?} w ? ?]?z ?o? , ?? ?o ? lu?uxx?? ^ ^ l?ul?uxxx l > ^ k ^ ??x?l , > ^ / z el , w ? ?? ?o ? lu?ueu?u ?} d / d ?uu /( ~ w ? ?? ?o ? a ? o? ?? w > <? ?} w ? ? ?]?z ?o? d / dl , z d / d w? ?o ? lu?ue ?} ? ~? a u ? w? ?o ? lu?ueuu?uu?uu ??ueu??u?? ?? lu?ueu xxx?? d k w z w > > e k / s docid025409 rev 2 19/124 stm32f334x4 stm32f334x6 stm32f334x8 functional overview 49 3.7 general-purpose inputs/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current capable except for analog inputs. the i/os alternate function configuration c an be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling allows i/o toggling up to 36 mhz. 3.8 direct memory access (dma) the flexible general-purpose dma is able to manage memory-to-memory, peripheral-to- memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrup ts when the controller reaches the end of the buffer. each of the 7 dma channels is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose timers, high-resolution timer, dac and adc. 3.9 interrupts and events 3.9.1 nested vectored interrupt controller (nvic) the stm32f334x4/6/8 devices em bed a nested vectored interrupt controller (nvic) able to handle up to 60 maskable interrupt channels and 16 priority levels. the nvic benefits are the following: ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead the nvic hardware block provides flexible interrupt management features with minimal interrupt latency. 3.9.2 extended interrupt/event controller (exti) the external interrupt/event controller consists of 27 edge detector lines used to generate interrupt/event requ ests and wake-up the system. ea ch line can be independently configured to select the trig ger event (rising edge, falling edge, both) and can be masked functional overview stm32f334x4 stm32f334x6 stm32f334x8 20/124 docid025409 rev 2 independently. a pending register maintains t he status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 51 gpios can be connected to the 16 external interrupt lines. 3.10 fast analog-to-digital converter (adc) two 5 msps fast analog-to-digital converters, with selectable resolution between 12 and 6 bit, are embedded in the stm32f334x4/6/8 family devices. the adcs have up to 21 external channels. some of the external channels are shared between adc1 and adc2, performing conversions in single-shot or scan modes. the channels can be configured to be either single-ended input or differential i nput. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adcs also have internal channels: temperature sensor connected to adc1 channel 16, v bat /2 connected to adc1 channel 17, voltage reference v refint connected to both adc1 and adc2 channel 18 and vopamp2 connected to adc2 channel 17. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? interleaved sample and hold ? single-shunt phase current reading techniques. three analog watchdogs are available per adc. the adc can be served by the dma controller. the analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interr upt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers (tim2, tim3, tim6, tim15), the advanced-control timer (tim1) and the high-re solution timer (hrtim1) can be internally connected to the adc start trigger and injection trigger, respectively, to allow the application to synchronize a/d conversion and timers. 3.10.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc1_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.10.2 internal voltage reference (vrefint) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally connected to the adc1_in18 and adc2_in18 docid025409 rev 2 21/124 stm32f334x4 stm32f334x6 stm32f334x8 functional overview 49 input channels. the precise voltage of v refint is individually measured for each part by st during production test and stored in the system memory area. it is a ccessible in read-only mode. 3.10.3 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc1_in17. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a bridge divider by 2. as a consequence, the converted digital value is half the v bat voltage. 3.10.4 opamp2 referenc e voltage (vopamp2) opamp2 reference voltage can be measured using adc2 internal channel 17. 3.11 digital-to-analog converter (dac) one 12-bit buffered dac channel (dac1_out1) and two 12-bit unbuffered dac channels (dac1_out2 and dac2_out1) can be used to convert digital signals into analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in inve rting configuration. this digital interface supp orts the following features: ? three dac output channels ? 8-bit or 12-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation (only on dac1) ? triangular-wave generation (only on dac1) ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion 3.12 operational amplifier (opamp) the stm32f334x4/6/8 embeds an operational amp lifier (opamp2) with ex ternal or internal follower routing and pga capab ility (or even amplifier and f ilter capability with external components). when an operational amplifier is selected, an external adc channel is used to enable output measurement. the operational amplifier features: ? 8 mhz gbp ? 0.5 ma output capability ? rail-to-rail input/output ? in pga mode, the gain can be programmed to 2, 4, 8 or 16. functional overview stm32f334x4 stm32f334x6 stm32f334x8 22/124 docid025409 rev 2 3.13 ultra-fast comparators (comp) the stm32f334x4/6/8 devices em bed three ultra-fast rail-to-rail comparators (comp2/4/6) which offer the features below: ? programmable internal or external reference voltage ? selectable output polarity. the reference voltage can be one of the following: ? external i/o ? dac output ? internal reference voltage or submultiple (1/4, 1/2, 3/4). refer to table 23: embedded internal reference voltage for values and parameters of the internal reference voltage. all comparators can wake up from stop mode, generate interrupts and breaks for the timers. 3.14 timers and watchdogs the stm32f334x4/6/8 includes advanced cont rol timer, 5 general-purpose timers, basic timer, two watchdog timers and a systick timer. the table below compares the features of the advanced control, general purpose and basic timers. table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs high- resolution timer hrtim1 (1) 16-bit up /1 /2 /4 (x2 x4 x8 x16 x32, with dll) yes 10 yes advanced control tim1 (1) 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes general- purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim3 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim15 16-bit up any integer between 1 and 65536 yes 2 1 general- purpose tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 1 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no 1. tim1 can be clocked from the pll x 2 running at 144 mhz . docid025409 rev 2 23/124 stm32f334x4 stm32f334x6 stm32f334x8 functional overview 49 3.14.1 high-resolution timer (hrtim1) the high-resolution timer (hrtim1) allows g enerating digital signals with high-accuracy timings, such as pwm or phase-shifted pulses. it consists of 6 timers, 1 master and 5 slaves , totaling 10 high-resolution outputs, which can be coupled by pairs for deadtime insertion. it also features 5 fault inputs for protection purposes and 10 inputs to handle external events such as current limitation, zero voltage or zero current switching. hrtim1 timer is made of a digital kernel cl ocked at 144 mhz followed by delay lines. delay lines with closed loop control guarantee a 217 ps resolution whatever the voltage, temperature or chip-to-chip manufacturing process deviation. th e high-resolution is available on the 10 outputs in all operating modes: variable duty cycle, variable frequency, and constant on time. the slave timers can be combined to contro l multiswitch complex converters or operate independently to manage multiple independent converters. the waveforms are defined by a combination of user-defined timings and external events such as analog or digital feedbacks signals. hrtim1 timer includes options for blanking and f iltering out spurious events or faults. it also offers specific modes and features to offloa d the cpu: dma requests, burst mode controller, push-pull and resonant mode. it supports many topologies including llc, full bridge phase shifted, buck or boost converters, either in voltage or current mode, as well as lighting applic ation (fluorescent or led). it can also be used as a general purpose timer, for instance to achieve high-resolution pwm-emulated dac. in debug mode, the hrtim1 counters can be frozen and the pwm outputs enter safe state. 3.14.2 advanced timer (tim1) the advanced-control timer can be seen as a three-phase pwm multiplexed on 6 channels. they have complementary pwm outputs with pr ogrammable inserted dead-times. they can also be seen as complete general-purpose timers. the 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or ce nter-aligned modes) with fu ll modulation capability (0-100%) ? one-pulse mode output in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switches driven by these outputs. many features are shared with those of the general-purpose tim timers (described in section 3.14.3 using the same architecture, so t he advanced-control timers can work together with the tim timers via the timer link feature for synchronization or event chaining. functional overview stm32f334x4 stm32f334x6 stm32f334x8 24/124 docid025409 rev 2 3.14.3 general-purpose timers (tim 2, tim3, tim15, tim16, tim17) there are up to three synchronizable general-purpose timers embedded in the stm32f334x4/6/8 (see table 5 for differences). each general-purpose timer can be used to generate pwm outputs, or act as a simple time base. ? tim2 and tim3 they are full-featured general-purpose timers: ? tim2 has a 32-bit auto-reload up/down counter and 32-bit prescaler ? tim3 has a 16-bit auto-reload up/down counter and 16-bit prescaler. these timers feature 4 independent channels for input capture/output compare, pwm or one-pulse mode output. they can work to gether, or with the other general-purpose timers via the timer link feature fo r synchronization or event chaining. the counters can be frozen in debug mode. all have independent dma request generat ion and support quadrature encoders. ? tim15, 16 and 17 these three timers general-purpose timers with mid-range features: they have 16-bit auto-reload upcounters and 16-bit prescalers. ? tim15 has 2 channels and 1 complementary channel ? tim16 and tim17 have 1 channel and 1 complementary channel all channels can be used for input capture/output compare, pwm or one-pulse mode output. the timers can work together via the timer link feature for synchronization or event chaining. the timers have independent dma request generation. the counters can be frozen in debug mode. 3.14.4 basic timers (tim6 and tim7) the basic timers are mainly used for dac tri gger generation. they can also be used as generic 16-bit timebases. 3.14.5 independent watchdog the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and stan dby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.14.6 window watchdog the window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. docid025409 rev 2 25/124 stm32f334x4 stm32f334x6 stm32f334x8 functional overview 49 3.14.7 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0. ? programmable clock source 3.15 real-time clock (rtc ) and backup registers the rtc and the 5 backup registers are supplied through a switch that takes power from either the v dd supply when present or the vbat pin. the backup registers are five 32-bit registers used to store 20 bytes of user application data when v dd power is not present. they are not reset by a system or power rese t, or when the device wakes up from standby mode. the rtc is an independent bcd timer/count er. it supports the following features: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? automatic correction for 28, 29 (leap year), 30, and 31 days of the month. ? two programmable alarms with wake up fr om stop and standb y mode capability. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? digital calibration circuit with 1 ppm resolu tion, to compensate for quartz crystal inaccuracy. ? two anti-tamper detection pins with prog rammable filter. the mcu can be woken up from stop and standby modes on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. ? 17-bit auto-reload counter for periodic interrupt with wakeup from stop/standby capability. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32. functional overview stm32f334x4 stm32f334x6 stm32f334x8 26/124 docid025409 rev 2 3.16 communication interfaces 3.16.1 inter-integrated circuit interface (i 2 c) the devices feature an i 2 c bus interface which can operate in multimaster and slave mode. it can support standard (up to 100 khz), fast (up to 400 khz) and fast mode + (up to 1 mhz) modes. it supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). it also includes programmable analog and digital noise filters. in addition, it provides har dware support for sm bus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) gener ation/verification, timeouts verifications and alert protocol management. it also has a clock domain independent from the cpu clock, allowing the i2c1 to wake up the mcu from stop mode on address match. the i2c interface can be served by the dma controller. refer to table 7 for the features available in i2c1. table 6. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes ? 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. table 7. stm32f334x4/6/8 i 2 c implementation i2c features (1) 1. x = supported. i2c1 7-bit addressing mode x 10-bit addressing mode x standard mode (up to 100 kbit/s) x fast mode (up to 400 kbit/s) x fast mode plus with 20ma output drive i/os (up to 1 mbit/s) x independent clock x smbus x wakeup from stop x docid025409 rev 2 27/124 stm32f334x4 stm32f334x6 stm32f334x8 functional overview 49 3.16.2 universal synchronous/asynchronous receiver transm itters (usarts) the stm32f334x4/6/8 devices have three em bedded universal synchronous receiver transmitters (usart1, usart2 and usart3). the usart interfaces are able to communicate at speeds of up to 9 mbits/s. usart1 provides hardware management of the cts and rts signals. it supports irda sir endec, the multiprocessor communication mode, the single-wire half-duplex communication mode and has lin master/sla ve capability. all usart interfaces can be served by the dma controller. refer to table 8 for the features available in the usart interfaces. 3.16.3 serial peripheral interface (spi) a spi interface allows to communicate up to 18 mbits/s in slave and master modes in full- duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. refer to table 9 for the features available in spi1. table 8. usart features usart modes/features (1) 1. x = supported. usart1 usart2 usart3 hardware flow control for modem x x continuous communication using dma x x multiprocessor communication x x synchronous mode x x smartcard mode x - single-wire half-duplex communication x x irda sir endec block x - lin mode x - dual clock domain and wakeup from stop mode x - receiver timeout interrupt x - modbus communication x - auto baud rate detection x - driver enable x x table 9. stm32f334x4/6/8 spi implementation spi features (1) spi1 hardware crc calculation x rx/tx fifo x functional overview stm32f334x4 stm32f334x6 stm32f334x8 28/124 docid025409 rev 2 3.16.4 controller area network (can) the can is compliant with specif ications 2.0a and b (active) wit h a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks. 3.17 infrared transmitter the stm32f334x4/6/8 devices provide an infrared transmitter solution. the solution is based on internal connections between tim16 and tim17 as shown in the figure below. tim17 is used to provide the carrier frequenc y and tim16 provides the main signal to be sent. the infrared output signal is available on pb9 or pa13. to generate the infrared remote control sign als, tim16 channel 1 and tim17 channel 1 must be properly configured to generate correct waveforms. all standard ir pulse modulation modes can be obtained by programming t he two timers output compare channels. figure 3. infrared transmitter 3.18 touch sensing controller (tsc) the stm32f334x4/6/8 devices provide a simple solution for adding capacitive sensing functionality to any application. these device s offer up to 18 capacitive sensing channels distributed over 6 analog i/os group. capacitive sensing technology is able to detect the presence of a finger near an electrode which is protected from direct touch by a dielectric (glass, plastic, ...). the capacitive variation introduced by the finger (or any co nductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. it consists of nss pulse mode x ti mode x 1. x = supported. table 9. stm32f334x4/6/8 spi implementation (continued) spi features (1) spi1 7 , 0 ( 5 i r u h q y h o r s 7 , 0 ( 5 i r u f d u u l h u 2 & 2 & 3 % 3 $ 0 6 9 docid025409 rev 2 29/124 stm32f334x4 stm32f334x6 stm32f334x8 functional overview 49 charging the electrode capacitance and then tr ansferring a part of the accumulated charges into a sampling capacitor unt il the voltage across this capa citor has reached a specific threshold. to limit the cpu bandwidth usage th is acquisition is dire ctly managed by the hardware touch sensing controller and only r equires few external components to operate. the touch sensing controller is fully supported by the stmtouch touch sensing firmware library which is free to use and allows touch se nsing functionality to be implemented reliably in the end application. table 10. capacitive sensing gpios available on stm32f334x4/6/8 devices group capacitive sensing group name pin name group capacitive sensing group name pin name 1 tsc_g1_io1 pa0 4 tsc_g4_io1 pa9 tsc_g1_io2 pa1 tsc_g4_io2 pa10 tsc_g1_io3 pa2 tsc_g4_io3 pa13 tsc_g1_io4 pa3 tsc_g4_io4 pa14 2 tsc_g2_io1 pa4 5 tsc_g5_io1 pb3 tsc_g2_io2 pa5 tsc_g5_io2 pb4 tsc_g2_io3 pa6 tsc_g5_io3 pb6 tsc_g2_io4 pa7 tsc_g5_io4 pb7 3 tsc_g3_io1 pc5 6 tsc_g6_io1 pb11 tsc_g3_io2 pb0 tsc_g6_io2 pb12 tsc_g3_io3 pb1 tsc_g6_io3 pb13 tsc_g3_io1 pc5 tsc_g6_io4 pb14 table 11. no. of capacitive sensing channels available on stm32f334x4/6/8 devices analog i/o group number of capacitive sensing channels stm32f334xrx stm32f334xcx stm32f334xkx g1 3 3 3 g2 3 3 3 g3 3 2 2 g4 3 3 3 g5 3 3 3 g6 3 3 0 number of capacitive sensing channels 18 17 14 functional overview stm32f334x4 stm32f334x6 stm32f334x8 30/124 docid025409 rev 2 3.19 development support 3.19.1 serial wire jt ag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared re spectively with swdio and swclk and a specific sequence on the tms pin is us ed to switch between jtag-dp and sw-dp. docid025409 rev 2 31/124 stm32f334x4 stm32f334x6 stm32f334x8 pinouts and pin description 49 4 pinouts and pin description figure 4. lqfp32 pinout figure 5. lqfp48 pinout 0 6 9 9 6 6 b % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 9 ' ' b 3 ) 2 6 & b , 1 3 $ / 4 ) 3 3 $ 1 5 6 7 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 9 6 6 b 9 ' ' b 3 ) 2 6 & b 2 8 7 9 ' ' $ 9 5 ( ) 3 $ 3 $ 3 $ 0 6 y 9 s z s ^ ^z w ? w ? k k d w w w ? w e w ? w ? w e e? e e e? ee e? e? e e ?? ?? ? s d ? s z? w ? ??? s ^ ^ z? w el k ^ ??z / e ??e w ? e?? w ? w &l k ^ z / e ??? w > y & we? ? w e z ^ d ? w ? s ^ ^ l s z &r ??? w ? ??? w ? w ? w e ? w ? ? ?? w ? ? e ? ? ? ? ? ?? ?? ?e w ? w e w ? w w w w w ? w w s ^ ^z? s z? w ?l k ^ ??z k h d w &l k ^ z k h d s l s z &= w w ? pinouts and pin description stm32f334x4 stm32f334x6 stm32f334x8 32/124 docid025409 rev 2 figure 6. lqfp64 pinout 0 6 9 9 ' ' b 9 6 6 b 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' b 9 6 6 b 3 $ 3 $ 3 $ 3 $ 3 $ / 4 ) 3 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 $ 9 6 6 b 9 ' ' b 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 3 % 3 % 3 % 9 6 6 b 9 ' ' b 3 ) 2 6 & b , 1 3 & 3 & 3 $ 3 $ 3 $ 9 % $ 7 3 & 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 3 ) 2 6 & b 2 8 7 1 5 6 7 3 & 3 & 9 6 6 $ 9 5 ( ) 9 ' ' $ 9 5 ( ) docid025409 rev 2 33/124 stm32f334x4 stm32f334x6 stm32f334x8 pinouts and pin description 49 table 12. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tt 3.3 v tolerant i/o tc standard 3.3 v i/o b dedicated boot0 pin rst bi-directional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected thro ugh gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers table 13. stm32f334x4/6/8 pin definitions pin number pin name (function after reset) pin type i/o structure pin functions lqfp 32 lqfp 48 lqfp 64 alternate functions additional functions - 1 1 vbat s - backup power supply -22 pc13 (1) i/o tc tim1_ch1n rtc_tamp1/rtc_ts/ rtc_out/wkup2 - 3 3 pc14 / osc32_in (1) i/o tc - osc32_in -44 pc15 / osc32_out (1) i/o tc - osc32_out 2 5 5 pf0 / osc_in i/o ft tim1_ch3n osc_in 3 6 6 pf1 / osc_out i/o ft - osc_out pinouts and pin description stm32f334x4 stm32f334x6 stm32f334x8 34/124 docid025409 rev 2 4 7 7 nrst i/o rst device reset input / internal reset output (active low) - - 8 pc0 i/o tta eventout, tim1_ch1 adc12_in6 - - 9 pc1 i/o tta eventout, tim1_ch2 adc12_in7 - - 10 pc2 i/o tta eventout, tim1_ch3 adc12_in8 - - 11 pc3 i/o tta eventout, tim1_ch4, tim1_bkin2 adc12_in9 8 12 vssa/vref- s - analog ground/negative reference voltage 5 9 13 vdda/vref+ s - analog power supply/positive reference voltage 6 10 14 pa0 i/o tta tim2_ch1/ tim2_etr, tsc_g1_io1, usart2_cts, eventout adc1_in1, rtc_tamp2/wkup1 7 11 15 pa1 i/o tta tim2_ch2, tsc_g1_io2, usart2_rts_de , tim15_ch1n, eventout adc1_in2, rtc_refin 8 12 16 pa2 i/o tta tim2_ch3, tsc_g1_io3, usart2_tx, comp2_out, tim15_ch1, eventout adc1_in3, comp2_inm 9 13 17 pa3 i/o tta tim2_ch4, tsc_g1_io4, usart2_rx, tim15_ch2, eventout adc1_in4 - - 18 vss s - - - --19 vdd s - - - table 13. stm32f334x4/6/8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure pin functions lqfp 32 lqfp 48 lqfp 64 alternate functions additional functions docid025409 rev 2 35/124 stm32f334x4 stm32f334x6 stm32f334x8 pinouts and pin description 49 10 14 20 pa4 (2) i/o tta tim3_ch2, tsc_g2_io1, spi1_nss, usart2_ck, eventout adc2_in1, dac1_out1, comp2_inm4, comp4_inm4, comp6_inm4 11 15 21 pa5 (2) i/o tta tim2_ch1/ tim2_etr, tsc_g2_io2, spi1_sck, eventout adc2_in2, dac1_out2, opamp2_vinm 12 16 22 pa6 (2) i/o tta tim16_ch1, tim3_ch1, tsc_g2_io3, spi1_miso, tim1_bkin, opamp2_dig, eventout adc2_in3, dac2_out1, opamp2_vout 13 17 23 pa7 i/o tta tim17_ch1, tim3_ch2, tsc_g2_io4, spi1_mosi, tim1_ch1n, eventout adc2_in4, comp2_inp, opamp2_vinp - - 24 pc4 i/o tta eventout, tim1_etr, usart1_tx adc2_in5 - - 25 pc5 i/o tta eventout, tim15_bkin, tsc_g3_io1, usart1_rx adc2_in11, opamp2_vinm 14 18 26 pb0 i/o tta tim3_ch3, tsc_g3_io2, tim1_ch2n, eventout adc1_in11, comp4_inp, opamp2_vinp 15 19 27 pb1 i/o tta tim3_ch4, tsc_g3_io3, tim1_ch3n, comp4_out, hrtim1_scout, eventout adc1_in12 table 13. stm32f334x4/6/8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure pin functions lqfp 32 lqfp 48 lqfp 64 alternate functions additional functions pinouts and pin description stm32f334x4 stm32f334x6 stm32f334x8 36/124 docid025409 rev 2 - 20 28 pb2 i/o tta tsc_g3_io4, hrtim_scin, eventout adc2_in12, comp4_inm - 21 29 pb10 i/o tt tim2_ch3, tsc_sync, usart3_tx, hrtim1_flt3, eventout - - 22 30 pb11 i/o tta tim2_ch4, tsc_g6_io1, usart3_rx, hrtim1_flt4, eventout comp6_inp 16 23 31 vss s - digital ground 17 24 32 vdd s - digital power supply - 25 33 pb12 i/o tta tsc_g6_io2, tim1_bkin, usart3_ck, hrtim1_chc1, eventout adc2_in13 - 26 34 pb13 i/o tta tsc_g6_io3, tim1_ch1n, usart3_cts, hrtim1_chc2, eventout adc1_in13 - 27 35 pb14 i/o tta tim15_ch1, tsc_g6_io4, tim1_ch2n, usart3_rts_de , hrtim1_chd1, eventout adc2_in14, opamp2_vinp - 28 36 pb15 i/o tta tim15_ch2, tim15_ch1n, tim1_ch3n, hrtim1_chd2, eventout adc2_in15, comp6_inm, rtc_refin table 13. stm32f334x4/6/8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure pin functions lqfp 32 lqfp 48 lqfp 64 alternate functions additional functions docid025409 rev 2 37/124 stm32f334x4 stm32f334x6 stm32f334x8 pinouts and pin description 49 - - 37 pc6 i/o ft eventout, tim3_ch1, hrtim1_eev10, comp6_out - - - 38 pc7 i/o ft eventout, tim3_ch2, hrtim1_flt5 - - - 39 pc8 i/o ft eventout, tim3_ch3, hrtim1_che1 - - - 40 pc9 i/o ft eventout, tim3_ch4, hrtim1_che2 - 18 29 41 pa8 i/o ft mco, tim1_ch1, usart1_ck, hrtim1_cha1, eventout - 19 30 42 pa9 i/o ft tsc_g4_io1, tim1_ch2, usart1_tx, tim15_bkin, tim2_ch3, hrtim1_cha2, eventout - 20 31 43 pa10 i/o ft tim17_bkin, tsc_g4_io2, tim1_ch3, usart1_rx, comp6_out, tim2_ch4, hrtim1_chb1, eventout - 21 32 44 pa11 i/o ft tim1_ch1n, usart1_cts, can_rx, tim1_ch4, tim1_bkin2, hrtim1_chb2, eventout - table 13. stm32f334x4/6/8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure pin functions lqfp 32 lqfp 48 lqfp 64 alternate functions additional functions pinouts and pin description stm32f334x4 stm32f334x6 stm32f334x8 38/124 docid025409 rev 2 22 33 45 pa12 i/o ft tim16_ch1, tim1_ch2n, usart1_rts_de , comp2_out, can_tx, tim1_etr, hrtim1_flt1, eventout - 23 34 46 pa13 i/o ft jtms/swdat, tim16_ch1n, tsc_g4_io3, ir_out, usart3_cts, eventout - - 35 47 vss s - - - -3648 vdd s - - - 24 37 49 pa14 i/o ftf jtck/swclk, tsc_g4_io4, i2c1_sda, tim1_bkin, usart2_tx, eventout - 25 38 50 pa15 i/o ftf jtdi, tim2_ch1/tim2_ etr, tsc_sync, i2c1_scl, spi1_nss, usart2_rx, tim1_bkin, hrtim1_flt2, eventout - - - 51 pc10 i/o ft eventout, usart3_tx - - - 52 pc11 i/o ft eventout, hrtim1_eev2, usart3_rx - - - 53 pc12 i/o ft eventout, hrtim1_eev1, usart3_ck - table 13. stm32f334x4/6/8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure pin functions lqfp 32 lqfp 48 lqfp 64 alternate functions additional functions docid025409 rev 2 39/124 stm32f334x4 stm32f334x6 stm32f334x8 pinouts and pin description 49 - - 54 pd2 i/o ft eventout, tim3_etr - 26 39 55 pb3 i/o ft jtdo/trace swo, tim2_ch2, tsc_g5_io1, spi1_sck, usart2_tx, tim3_etr, hrtim1_scout, hrtim1_eev9, eventout - 27 40 56 pb4 i/o ft njtrst, tim16_ch1, tim3_ch1, tsc_g5_io2, spi1_miso, usart2_rx, tim17_bkin, hrtim1_eev7, eventout - 28 41 57 pb5 i/o ft tim16_bkin, tim3_ch2, i2c1_smba, spi1_mosi, usart2_ck, tim17_ch1, hrtim1_eev6, eventout - 29 42 58 pb6 i/o ftf tim16_ch1n, tsc_g5_io3, i2c1_scl, usart1_tx, hrtim1_scin, hrtim1_eev4, eventout - 30 43 59 pb7 i/o ftf tim17_ch1n, tsc_g5_io4, i2c1_sda, usart1_rx, tim3_ch4, hrtim1_eev3, eventout - table 13. stm32f334x4/6/8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure pin functions lqfp 32 lqfp 48 lqfp 64 alternate functions additional functions pinouts and pin description stm32f334x4 stm32f334x6 stm32f334x8 40/124 docid025409 rev 2 31 44 60 boot0 i b - - 45 61 pb8 i/o ftf tim16_ch1, tsc_sync, i2c1_scl, usart3_rx, can_rx, tim1_bkin, hrtim1_eev8, eventout - - 46 62 pb9 i/o ftf tim17_ch1, i2c1_sda, ir_out, usart3_tx, comp2_out, can_tx, hrtim1_eev5, eventout - 32 47 63 vss s - - - 14864 vdd s - - - 1. pc13, pc14 and pc15 are supplied through the power switch. sinc e the switch sinks only a limited amount of current (3 ma), the use of gpio pc13 to pc15 in output mode is limited: ? - the speed should not exceed 2 mhz with a maximum load of 30 pf ? - these gpios must not be used as current sources (e.g. to drive an led). ? after the first backup domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the backup registers which is not reset by the ma in reset. for details on how to manage these gpios, refer to the battery backup domain and bkp register des cription sections in the reference manual. 2. these gpios offer a reduced touch sensing sensitivity. it is thus recommended to use t hem as sampling capacitor i/o. table 13. stm32f334x4/6/8 pin definitions (continued) pin number pin name (function after reset) pin type i/o structure pin functions lqfp 32 lqfp 48 lqfp 64 alternate functions additional functions stm32f334x4 stm32f334x6 stm32f334x8 pinouts and pin description docid025409 rev 2 41/124 table 14. alternate functions port af0 af1 af2 af3 af4 af5 af6 af7 af8 a f9 af10 af11 af12 af13 af14 af15 sys_a f tim2/ti m15/ ? tim16/ tim17/ event tim1/t im3/ ? tim15/ ? tim16 hrtim 1/tsc i2c1/ti m1 spi1/inf rared tim1/in frared usart 1/usar t2/usa rt3/gp comp6 gpco mp2/ ? gpco mp4/ ? gpco mp6 can/ti m1/ ? tim15 tim2/ tim3/ tim1 7 tim1 hrtim 1/ ? tim1 hrti m1/ ? opam p2 even t port a pa0 - tim2_c h1/tim 2_etr - tsc_g 1_io1 --- usart 2_cts ------- even tout pa1 - tim2_c h2 - tsc_g 1_io2 --- usart 2_rts_ de - tim15_ ch1n -- - - - even tout pa2 - tim2_c h3 - tsc_g 1_io3 --- usart 2_tx comp2 _out tim15_ ch1 -- - -- even tout pa3 - tim2_c h4 - tsc_g 1_io4 --- usart 2_rx - tim15_ ch2 -- - -- even tout pa4 - - tim3_ ch2 tsc_g 2_io1 - spi1_n ss - usart 2_ck ------- even tout pa5 - tim2_c h1/tim 2_etr - tsc_g 2_io2 - spi1_s ck -- ------- even tout pa6 - tim16_ ch1 tim3_ ch1 tsc_g 2_io3 - spi1_m iso tim1_ bkin ------ opam p2_di g - even tout pa7 - tim17_ ch1 tim3_ ch2 tsc_g 2_io4 - spi1_m osi tim1_ ch1n --- ---- even tout pa8 mco - - - - tim1_ ch1 usart 1_ck ----- hrti m1_c ha1 - even tout pa9 - - - tsc_g 4_io1 -- tim1_ ch2 usart 1_tx - tim15_ bkin tim2 _ch3 -- hrti m1_c ha2 - even tout pinouts and pin description stm32f334x4 stm32f334x6 stm32f334x8 42/124 docid025409 rev 2 port a pa1 0 - tim17_ bkin - tsc_g 4_io2 -- tim1_ ch3 usart 1_rx comp6 _out tim2 _ch4 -- hrti m1_c hb1 even tout pa11 - - - - - - tim1_ ch1n usart 1_cts - can_r x - tim1_ ch4 tim1_ bkin2 hrti m1_c hb2 even tout pa1 2 - tim16_ ch1 -- - - tim1_ ch2n usart 1_rts_ de comp2 _out can_t x - tim1_ etr - hrti m1_f lt1 even tout pa1 3 jtms/s wdat tim16_ ch1n - tsc_g 4_io3 -ir_out- usart 3_cts ------- even tout pa1 4 jtck/s wclk -- tsc_g 4_io4 i2c1_s da - tim1_ bkin usart 2_tx ------ even tout pa1 5 jtdi tim2_c h1/ ? tim2_e tr - tsc_s ync i2c1_s cl spi1_n ss usart 2_rx - tim1_ bkin -- - hrti m1_f lt2 even tout port b pb0 - - tim3_ ch3 tsc_g 3_io2 -- tim1_ ch2n -------- even tout pb1 - - tim3_ ch4 tsc_g 3_io3 - tim1_ ch3n - comp4 _out ---- hrti m1_s cout - even tout pb2 - - - tsc_g 3_io4 - --- ---- hrti m1_s cin - even tout table 14. alternate functions (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 a f9 af10 af11 af12 af13 af14 af15 sys_a f tim2/ti m15/ ? tim16/ tim17/ event tim1/t im3/ ? tim15/ ? tim16 hrtim 1/tsc i2c1/ti m1 spi1/inf rared tim1/in frared usart 1/usar t2/usa rt3/gp comp6 gpco mp2/ ? gpco mp4/ ? gpco mp6 can/ti m1/ ? tim15 tim2/ tim3/ tim1 7 tim1 hrtim 1/ ? tim1 hrti m1/ ? opam p2 even t stm32f334x4 stm32f334x6 stm32f334x8 pinouts and pin description docid025409 rev 2 43/124 port b pb3 jtdo/t races wo tim2_c h2 - tsc_g 5_io1 - spi1_s ck - usart 2_tx -- tim3 _etr - hrtim 1_sco ut hrti m1_e ev9 - even tout pb4 njtrs t tim16_ ch1 tim3_ ch1 tsc_g 5_io2 - spi1_m iso - usart 2_rx -- tim1 7_bki n -- hrti m1_e ev7 - even tout pb5 - tim16_ bkin tim3_ ch2 - i2c1_s mba spi1_m osi - usart 2_ck -- tim1 7_ch 1 -- hrti m1_e ev6 - even tout pb6 - tim16_ ch1n - tsc_g 5_io3 i2c1_s cl -- usart 1_tx --- - hrtim 1_sci n hrti m1_e ev4 - even tout pb7 - tim17_ ch1n - tsc_g 5_io4 i2c1_s da -- usart 1_rx -- tim3 _ch4 -- hrti m1_e ev3 - even tout pb8 - tim16_ ch1 - tsc_s ync i2c1_s cl -- usart 3_rx - can_r x -- tim1_ bkin hrti m1_e ev8 - even tout pb9 - tim17_ ch1 -- i2c1_s da - ir_ou t usart 3_tx comp2 _out can_t x -- - hrti m1_e ev5 - even tout pb1 0 - tim2_c h3 - tsc_s ync --- usart 3_tx ----- hrti m1_f lt3 - even tout pb1 1 - tim2_c h4 - tsc_g 6_io1 --- usart 3_rx ----- hrti m1_f lt4 - even tout table 14. alternate functions (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 a f9 af10 af11 af12 af13 af14 af15 sys_a f tim2/ti m15/ ? tim16/ tim17/ event tim1/t im3/ ? tim15/ ? tim16 hrtim 1/tsc i2c1/ti m1 spi1/inf rared tim1/in frared usart 1/usar t2/usa rt3/gp comp6 gpco mp2/ ? gpco mp4/ ? gpco mp6 can/ti m1/ ? tim15 tim2/ tim3/ tim1 7 tim1 hrtim 1/ ? tim1 hrti m1/ ? opam p2 even t pinouts and pin description stm32f334x4 stm32f334x6 stm32f334x8 44/124 docid025409 rev 2 port b pb1 2 --- tsc_g 6_io2 -- tim1_ bkin usart 3_ck ----- hrti m1_c hc1 - even tout pb1 3 --- tsc_g 6_io3 -- tim1_ ch1n usart 3_cts ----- hrti m1_c hc2 - even tout pb1 4 - tim15_ ch1 - tsc_g 6_io4 -- tim1_ ch2n usart 3_rts_ de ----- hrti m1_c hd1 - even tout pb1 5 - tim15_ ch2 tim15 _ch1 n - tim1_c h3n --- ----- hrti m1_c hd2 - even tout port c pc0 - event out tim1_ ch1 -- --- -------- ------ --- -------- pc2 - event out tim1_ ch3 -- --- -------- pc3 - event out tim1_ ch4 -- - tim1_ bkin2 --------- pc4 - event out tim1_ etr -- -- usart 1_tx -------- pc5 - event out tim15 _bkin tsc_g 3_io1 --- usart 1_rx -------- table 14. alternate functions (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 a f9 af10 af11 af12 af13 af14 af15 sys_a f tim2/ti m15/ ? tim16/ tim17/ event tim1/t im3/ ? tim15/ ? tim16 hrtim 1/tsc i2c1/ti m1 spi1/inf rared tim1/in frared usart 1/usar t2/usa rt3/gp comp6 gpco mp2/ ? gpco mp4/ ? gpco mp6 can/ti m1/ ? tim15 tim2/ tim3/ tim1 7 tim1 hrtim 1/ ? tim1 hrti m1/ ? opam p2 even t stm32f334x4 stm32f334x6 stm32f334x8 pinouts and pin description docid025409 rev 2 45/124 port c pc6 - event out tim3_ ch1 hrtim 1_eev 10 --- comp6 _out -------- pc7 - event out tim3_ ch2 hrtim 1_flt5 - --- -------- pc8 - event out tim3_ ch3 hrtim 1_che 1 - --- -------- pc9 - event out tim3_ ch4 hrtim 1_che 2 - --- -------- pc1 0 - event out -- - - - usart 3_tx -------- pc1 1 - event out - hrtim 1_eev 2 --- usart 3_rx -------- pc1 2 - event out - hrtim 1_eev 1 --- usart 3_ck ----- -- pc1 3 ---- tim1_c h1n --- -------- pc1 4 ----- --- -------- port c pc1 5 ----- --- -------- table 14. alternate functions (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 a f9 af10 af11 af12 af13 af14 af15 sys_a f tim2/ti m15/ ? tim16/ tim17/ event tim1/t im3/ ? tim15/ ? tim16 hrtim 1/tsc i2c1/ti m1 spi1/inf rared tim1/in frared usart 1/usar t2/usa rt3/gp comp6 gpco mp2/ ? gpco mp4/ ? gpco mp6 can/ti m1/ ? tim15 tim2/ tim3/ tim1 7 tim1 hrtim 1/ ? tim1 hrti m1/ ? opam p2 even t pinouts and pin description stm32f334x4 stm32f334x6 stm32f334x8 46/124 docid025409 rev 2 port d pd2 - event out tim3_ etr -- --- -------- port f pf0 - - - - - - tim1_ ch3n --------- pf1----- --- -------- table 14. alternate functions (continued) port af0 af1 af2 af3 af4 af5 af6 af7 af8 a f9 af10 af11 af12 af13 af14 af15 sys_a f tim2/ti m15/ ? tim16/ tim17/ event tim1/t im3/ ? tim15/ ? tim16 hrtim 1/tsc i2c1/ti m1 spi1/inf rared tim1/in frared usart 1/usar t2/usa rt3/gp comp6 gpco mp2/ ? gpco mp4/ ? gpco mp6 can/ti m1/ ? tim15 tim2/ tim3/ tim1 7 tim1 hrtim 1/ ? tim1 hrti m1/ ? opam p2 even t docid025409 rev 2 47/124 stm32f334x4 stm32f334x6 stm32f334x8 memory mapping 49 5 memory mapping figure 7. stm32f334x4/6/8 memory map [ ) ) ) ) ) ) ) ) [ ( [ & [ $ [ [ [ [ [ & r u w h [ 0 z l w k ) 3 8 , q w h u q d o 3 h u l s k h u d o v 3 h u l s k h u d o v 6 5 $ 0 & 2 ' ( 2 s w l r q e \ w h v 6 \ v w h p p h p r u \ & & 0 5 $ 0 ) o d v k p h p r u \ ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q % 2 2 7 f r q i l j x u d w l r q $ + % $ + % $ 3 % $ 3 % [ [ [ [ ) ) [ [ & [ [ $ [ [ ) ) ) ) ) ) ) [ ) ) ) ) [ ) ) ) ' [ [ [ [ [ [ 5 h v h u y h g 0 6 y 9 $ + % [ ) ) 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g memory mapping stm32f334x4 stm32f334x6 stm32f334x8 48/124 docid025409 rev 2 table 15. stm32f334x4/6/8 peripheral register boundary addresses bus boundary address size (bytes) peripheral ahb3 0x5000 0000 - 0x5000 03ff 1 k adc1 - adc2 0x4800 1800 - 0x4fff ffff ~132 m reserved ahb2 0x4800 1400 - 0x4800 17ff 1 k gpiof 0x4800 1000 - 0x4800 13ff 1 k reserved ahb2 0x4800 0c00 - 0x4800 0fff 1 k gpiod 0x4800 0800 - 0x4800 0bff 1 k gpioc 0x4800 0400 - 0x4800 07ff 1 k gpiob 0x4800 0000 - 0x4800 03ff 1 k gpioa 0x4002 4400 - 0x47ff ffff ~128 m reserved ahb1 0x4002 4000 - 0x4002 43ff 1 k tsc 0x4002 3400 - 0x4002 3fff 3 k reserved 0x4002 3000 - 0x4002 33ff 1 k crc 0x4002 2400 - 0x4002 2fff 3 k reserved 0x4002 2000 - 0x4002 23ff 1 k flash interface 0x4002 1400 - 0x4002 1fff 3 k reserved 0x4002 1000 - 0x4002 13ff 1 k rcc 0x4002 0400 - 0x4002 0fff 3 k reserved 0x4002 0000 - 0x4002 03ff 1 k dma1 0x4001 8000 - 0x4001 ffff 32 k reserved apb2 0x4001 7400 - 0x4001 77ff 1 k hrtim1 apb2 0x4001 4c00 - 0x4001 73ff 12 k reserved 0x4001 4800 - 0x4001 4bff 1 k tim17 0x4001 4400 - 0x4001 47ff 1 k tim16 0x4001 4000 - 0x4001 43ff 1 k tim15 0x4001 3c00 - 0x4001 3fff 1 k reserved 0x4001 3800 - 0x4001 3bff 1 k usart1 0x4001 3400 - 0x4001 37ff 1 k reserved 0x4001 3000 - 0x4001 33ff 1 k spi1 0x4001 2c00 - 0x4001 2fff 1 k tim1 0x4001 0800 - 0x4001 2bff 9 k reserved 0x4001 0400 - 0x4001 07ff 1 k exti 0x4001 0000 - 0x4001 03ff 1 k syscfg + comp + opamp 0x4000 9c00 - 0x4000 ffff 25 k reserved docid025409 rev 2 49/124 stm32f334x4 stm32f334x6 stm32f334x8 memory mapping 49 apb1 0x4000 9800 - 0x4000 9bff 1 k dac2 0x4000 7800 - 0x4000 97ff 8 k reserved 0x4000 7400 - 0x4000 77ff 1 k dac1 0x4000 7000 - 0x4000 73ff 1 k pwr 0x4000 6800 - 0x4000 6fff 2 k reserved 0x4000 6400 - 0x4000 67ff 1 k bxcan 0x4000 5800 - 0x4000 63ff 3 k reserved 0x4000 5400 - 0x4000 57ff 1 k i2c1 0x4000 4c00 - 0x4000 53ff 2 k reserved 0x4000 4800 - 0x4000 4bff 1 k usart3 0x4000 4400 - 0x4000 47ff 1 k usart2 0x4000 3400 - 0x4000 43ff 2 k reserved 0x4000 3000 - 0x4000 33ff 1 k iwdg 0x4000 2c00 - 0x4000 2fff 1 k wwdg 0x4000 2800 - 0x4000 2bff 1 k rtc 0x4000 1800 - 0x4000 27ff 4 k reserved 0x4000 1400 - 0x4000 17ff 1 k tim7 0x4000 1000 - 0x4000 13ff 1 k tim6 0x4000 0800 - 0x4000 0fff 2 k reserved 0x4000 0400 - 0x4000 07ff 1 k tim3 0x4000 0000 - 0x4000 03ff 1 k tim2 0x2000 3000 - 3fff ffff ~512 m reserved 0x2000 0000 - 0x2000 2fff 12 k sram 0x1fff f800 - 0x1fff ffff 2 k option bytes 0x1fff d800 - 0x1fff f7ff 8 k system memory 0x1000 2000 - 0x1fff d7ff ~256 m reserved 0x1000 0000 - 0x1000 0fff 4 k ccm ram 0x0804 0000 - 0x0fff ffff ~128 m reserved 0x0800 0000 - 0x0800 ffff 64 k main flash memory 0x0004 0000 - 0x07ff ffff ~128 m reserved 0x0000 000 - 0x0000 ffff 64 k main flash memory, system memory or sram depending on boot configuration table 15. stm32f334x4/6/8 peripheral re gister boundary addresses (continued) bus boundary address size (bytes) peripheral electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 50/124 docid025409 rev 2 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ? ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 3.3 v, v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ? ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 8 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 9 . figure 8. pin loading conditions figure 9. pin input voltage 0 6 9 0 & 8 s l q & s ) 0 6 9 0 & 8 s l q 9 , 1 docid025409 rev 2 51/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 6.1.6 power supply scheme figure 10. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc..) must be decoupled with filtering ceramic capacitors as shown above. these capa citors must be placed as close as possible to, or below the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 0 6 9 . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v % d f n x s f l u f x l w u \ / 6 ( 5 7 & % d f n x s u h j l v w h u v : d n h x s o r j l f $ ' & ' $ & / h y h o v k l i w h u , 2 / r j l f 9 ' ' 9 9 % $ 7 3 r z h u v z l w f k [ 9 ' ' [ 9 6 6 9 ' ' $ 9 5 ( ) 9 5 ( ) 9 6 6 $ 9 ' ' $ * 3 , 2 v 2 8 7 , 1 [ q ) [ ? ) q ) ? ) $ q r o r j 5 & v 3 / / f r p s d u d w r u v 2 3 $ 0 3 5 h j x o d w r u electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 52/124 docid025409 rev 2 6.1.7 current consumption measurement figure 11. current consumption measurement scheme 0 6 9 9 % $ 7 9 ' ' 9 ' ' $ , ' ' , ' ' $ , ' ' b 9 % $ 7 docid025409 rev 2 53/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 16: voltage characteristics , table 17: current characteristics , and table 18: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. table 16. voltage characteristics (1) symbol ratings min. max. unit v dd ?v ss external main supply voltage (including v dda, v bat and v dd ) -0.3 4.0 v v dd ?v dda allowed voltage difference for v dd > v dda -0.4 v in (2) input voltage on ft and ftf pins v ss ? 0.3 v dd + 4.0 input voltage on tta and tt pins v ss ? 0.3 4.0 input voltage on any other pin v ss ?? 0.3 4.0 input voltage on boot0 pin 0 9 | ? v ddx | variations between different v dd power pins - 50 mv |v ssx ?? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.12: electrical sensitivity characteristics 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. the following relationship must be respected between v dda and v dd : ? v dda must power on before or at the same time as v dd in the power up sequence. ? v dda must be greater than or equal to v dd. 2. v in maximum must always be respected. refer to table 17: current characteristics for the maximum allowed injected current values. electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 54/124 docid025409 rev 2 table 17. current characteristics symbol ratings max. unit ? i vdd total current into sum of all vdd_x power lines (source) (1) 140 ma ? i vss total current out of sum of all vss_x ground lines (sink) (1) -140 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss _x ground line (sink) (1) 100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin -25 ? i io(pin) total output current sunk by su m of all i/os and control pins (2) 80 total output current sourced by su m of all i/os and control pins (2) -80 i inj(pin) injected current on tt, ft, ftf and b pins (3) -5 /+0 injected current on tc and rst pin (4) 5 injected current on tta pins (5) 5 ? i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (v dd , v dda ) and ground (v ss and v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins.the total output current must not be sunk/sourced between two c onsecutive power supply pins referrin g to high pin count lqfp packages. 3. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 16: voltage characteristics for the maximum allowed input voltage values. 5. a positive injection is induced by v in > v dda while a negative injection is induced by v in < v ss . i inj (pin) must never be exceeded. refer also to table 16: voltage characteristics for the maximum allowed input voltage values. negative injection disturbs the analog performance of the device. see note 2. below table 63 . 6. when several inputs are submitted to a current injection, the maximum ? i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 18. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c docid025409 rev 2 55/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 6.3 operating conditions 6.3.1 general operating conditions table 19. general operating conditions symbol parameter cond itions min. max. unit f hclk internal ahb clock frequency - 0 72 mhz f pclk1 internal apb1 clock frequency - 0 36 f pclk2 internal apb2 clock frequency - 0 72 v dd standard operating voltage - 2 3.6 v v dda analog operating voltage ? (opamp and dac not used) must have a potential equal to or higher than v dd 23.6 analog operating voltage ? (opamp and dac used) 2.4 3.6 v bat backup operating voltage - 1.65 3.6 v v in i/o input voltage tc i/o ?0.3 v dd +0.3 v tt i/o -0.3 3.6 tta i/o ?0.3 v dda +0.3 ft and ftf i/o (1) 1. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pull-down resistors must be disabled. ?0.3 5.5 boot0 0 5.5 pd power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (2) 2. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax (see section table 77.: package thermal characteristics ). lqfp64 - 444 mw pd power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (2) lqfp48 - 364 mw pd power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 lqfp32 - 333 mw t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low power dissipation (3) 3. in low power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.2: thermal characteristics ). ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low power dissipation (3) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125 electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 56/124 docid025409 rev 2 6.3.2 operating conditions at power-up / power-down the parameters given in table 20 are derived from tests performed under the ambient temperature condition summarized in table 19 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 21 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 19 . table 20. operating conditions at power-up / power-down symbol parameter conditions min. max. unit t vdd v dd rise time rate - 0 ? s/v v dd fall time rate 20 ? t vdda v dda rise time rate - 0 ? v dda fall time rate 20 ? table 21. embedded reset and power control block characteristics symbol parameter conditions min. typ. max. unit v por/pdr (1) 1. the pdr detector monitors v dd and also v dda (if kept enabled in the option bytes). the por detector monitors only v dd . power on/power down reset threshold falling edge 1.8 (2) 2. the product behavior is guaranteed by design down to the minimum v por/pdr value. 1.88 1.96 v rising edge 1.84 1.92 2.0 v v pdrhyst (1) pdr hysteresis - - 40 - mv t rsttempo (3) 3. guaranteed by design, not tested in production. por reset temporization - 1.5 2.5 4.5 ms docid025409 rev 2 57/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 table 22. programmable voltage detector characteristics symbol parameter conditions min. (1) 1. data based on characterization results only, not tested in production. typ. max. (1) unit v pvd0 pvd threshold 0 rising edge 2.1 2.18 2.26 v falling edge 2 2.08 2.16 v pvd1 pvd threshold 1 rising edge 2.19 2.28 2.37 falling edge 2.09 2.18 2.27 v pvd2 pvd threshold 2 rising edge 2.28 2.38 2.48 falling edge 2.18 2.28 2.38 v pvd3 pvd threshold 3 rising edge 2.38 2.48 2.58 falling edge 2.28 2.38 2.48 v pvd4 pvd threshold 4 rising edge 2.47 2.58 2.69 falling edge 2.37 2.48 2.59 v pvd5 pvd threshold 5 rising edge 2.57 2.68 2.79 falling edge 2.47 2.58 2.69 v pvd6 pvd threshold 6 rising edge 2.66 2.78 2.9 falling edge 2.56 2.68 2.8 v pvd7 pvd threshold 7 rising edge 2.76 2.88 3 falling edge 2.66 2.78 2.9 v pvdhyst (2) 2. guaranteed by design, not tested in production. pvd hysteresis - - 100 - mv idd(pvd) pvd current ? consumption - - 0.15 0.26 a electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 58/124 docid025409 rev 2 6.3.4 embedded reference voltage the parameters given in table 23 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 19 . 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. ? the current consumption is measured as described in figure 11: current consumption measurement scheme . ? all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. note: the total current consumptio n is the sum of idd and idda. typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz,1 wait state from 24 to 48 mhz and 2 wait states from 48 to 72 mhz) ? prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) ? when the peripherals are enabled f pclk2 = f hclk and f pclk1 = f hclk/2 table 23. embedded internal reference voltage symbol parameter conditions min. typ. max. unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.2 1.25 v ?40 c < t a < +85 c 1.16 1.2 1.24 (1) 1. data based on characterization results, not tested in production. v t s_vrefint adc sampling time when reading the internal reference voltage -2.2--s v rerint internal reference voltage spread over the temperature range v dd = 31.8 v 10 mv - - 10 (2) 2. guaranteed by design, not tested in production. mv t coeff temperature coefficient - - - 100 (2) ppm/c table 24. internal reference voltage calibration values calibration value name description memory address v refint_cal raw data acquired at temperature of 30 c ? v dda = 3.3 v 0x1fff f7ba - 0x1fff f7bb docid025409 rev 2 59/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 ? when f hclk > 8 mhz, the pll is on and the pll input is equal to hsi/2 (4 mhz) or hse (8 mhz) in bypass mode. the parameters given in table 25 to table 29 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 19 . table 25. typical and maximum current consumption from v dd supply at v dd = 3.6v symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ. max. @ t a (1) typ. max. @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c i dd supply current in run mode, executing from flash external clock (hse bypass) 72 mhz 71.4 77.9 79.1 80.0 27.1 32.2 32.4 32.4 ma 64 mhz 63.9 70.6 71.3 71.5 24.2 27.0 27.5 27.7 48 mhz 49.5 56.6 57.1 57.7 18.7 21.4 21.6 21.9 32 mhz 34.0 38.6 38.9 39.2 12.9 14.6 14.9 15.9 24 mhz 25.9 30.2 30.4 30.6 10.0 11.1 11.2 12.3 8 mhz 9.3 14.1 14.3 14.4 3.3 4.0 4.4 5.1 1 mhz 3.5 8.9 9.1 9.5 0.7 0.9 1.0 1.2 internal clock (hsi) 64 mhz 61.6 68.1 68.8 70.1 24.1 27.0 27.1 27.2 48 mhz 48.1 54.6 54.8 55.1 18.6 21.6 21.7 21.9 32 mhz 33.3 37.8 37.9 38.0 12.7 14.4 14.9 16.0 24 mhz 25.7 29.8 29.8 30.0 10.0 11.1 11.2 12.3 8 mhz 9.7 12.2 12.3 12.8 3.4 3.8 4.2 5.0 supply current in run mode, executing from ram external clock (hse bypass) 72 mhz 71.3 77.8 (2) 78.7 78.9 (2) 27.6 32.1 (2) 32.2 32.3 (2) 64 mhz 63.8 70.5 70.7 70.9 24.5 27.2 27.6 27.7 48 mhz 49.3 56.5 56.9 57.4 18.1 21.6 21.8 21.8 32 mhz 33.9 37.7 37.9 38.0 12.9 14.9 14.9 15.9 24 mhz 25.8 28.8 29.0 29.2 9.8 11.1 11.3 11.5 8 mhz 9.0 13.2 13.3 13.8 3.2 3.6 4.0 4.6 1 mhz 3.2 7.6 7.8 8.0 0.3 0.4 0.8 1.2 internal clock (hsi) 64 mhz 61.3 66.9 67.3 67.8 24.1 26.9 27.0 27.1 48 mhz 48.0 52.4 52.6 53.1 19.1 21.6 21.6 22.1 32 mhz 33.1 35.6 35.8 36.6 12.6 14.8 14.9 15.9 24 mhz 25.6 28.5 28.7 28.8 9.8 11.1 11.3 11.5 8 mhz 9.7 11.6 11.6 11.7 3.0 3.1 4.1 4.7 electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 60/124 docid025409 rev 2 i dd supply current in sleep mode, executing from flash or ram external clock (hse bypass) 72 mhz 55.5 58.7 (2) 61.1 61.9 (2) 7.0 7.3 (2) 8.4 8.5 (2) ma 64 mhz 49.8 52.7 54.5 54.8 6.3 6.7 7.0 7.8 48 mhz 38.5 40.6 41.7 41.8 4.6 5.1 5.6 5.9 32 mhz 26.9 28.8 29.2 29.5 3.0 3.3 4.0 4.5 24 mhz 19.1 23.2 23.7 23.9 2.4 2.5 3.2 3.8 8 mhz 7.1 11.5 11.7 11.9 0.6 0.9 1.2 2.1 1 mhz 3.0 7.4 7.7 7.9 0.3 0.3 0.4 1.2 internal clock (hsi) 64 mhz 47.7 52.4 52.6 52.8 5.4 6.5 6.8 7.5 48 mhz 35.0 40.4 40.6 40.8 4.3 4.7 5.2 5.7 32 mhz 23.7 27.7 28.3 28.8 2.9 3.1 3.2 4.4 24 mhz 18.5 23.8 24.0 24.2 1.3 1.7 2.2 2.7 8 mhz 7.5 9.6 9.7 9.7 0.5 0.7 1.1 2.0 1. data based on characterization results, not tested in production unless otherwise specified. 2. data based on characterization results and test ed in production with code executing from ram. table 25. typical and maximum current consumption from v dd supply at v dd = 3.6v (continued) symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ. max. @ t a (1) typ. max. @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c docid025409 rev 2 61/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 table 26. typical and maximum current consumption from the v dda supply symbol parameter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit typ. max. @ t a (2) typ. max. @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run/sleep mode, code executing from flash or ram hse bypass 72 mhz 224 252 (3) 265 269 (3) 245 272 (3) 288 295 (3) a 64 mhz 196 225 237 241 214 243 257 263 48 mhz 147 174 183 186 159 186 196 201 32 mhz 100 126 133 135 109 133 142 145 24 mhz 79 102 107 108 85 108 113 116 8 mhz 3 5 5 6 4 6 6 7 1 mhz 3 5 5 6 3 5 6 6 hsi clock 64 mhz 259 288 304 309 285 315 332 338 48 mhz 208 239 251 254 230 258 271 277 32 mhz 162 190 198 202 179 206 216 219 24 mhz 140 168 175 178 155 181 188 191 8 mhz 62 85 88 89 71 94 96 98 1. current consumption from the v dda supply is independent of whether the peripherals are on or off. furthermore when the pll is off, i dda is independent from the frequency. 2. data based on characterization results, not tested in production. 3. data based characterization results and test ed in production with code executing from ram. table 27. typical and maximum v dd consumption in stop and standby modes symbol parameter conditions typ. @v dd (v dd =v dda ) max. (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dd supply ? current in stop mode regulator in run mode, all oscillators off 17.51 17.68 17.84 18.17 18.57 19.39 30.6 232.5 612.2 a regulator in low-power mode, all oscillators off 6.44 6.51 6.60 6.73 6.96 7.20 20.0 246.4 585.0 supply ? current in ? standby ? mode lsi on and iwdg on 0.73 0.89 1.02 1.14 1.28 1.44 - - - lsi off and iwdg off 0.55 0.66 0.75 0.85 0. 93 1.01 4.9 7.0 7.9 1. data based on characterization results, not tested in production unless otherwise specified. electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 62/124 docid025409 rev 2 table 28. typical and maximum v dda consumption in stop and standby modes symbol parameter conditions typ. @v dd (v dd = v dda )max. (1) unit 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dda supply ? current in stop mode v dda supervisor on regulator in run/low-power mode, all oscillators off 1.67 1.79 1.91 2.04 2.19 2.35 2.5 5.9 6.2 a supply ? current in ? standby ? mode lsi on and iwdg on 2.06 2.24 2.41 2.60 2.80 3.04 - - - lsi off and iwdg off 1.54 1.68 1.78 1.92 2.06 2.22 2.6 3.0 3.8 supply ? current in stop mode v dda supervisor off regulator in run/low-power mode, all oscillators off 0.97 0.99 1.03 1.07 1.14 1.22 - - - supply ? current in standby mode lsi on and iwdg on 1.36 1.44 1.52 1.62 1.76 1.91 - - - lsi off and iwdg off 0.86 0.88 0.91 0.95 1.03 1.09 - - - 1. data based on characterization re sults, not tested in production. table 29. typical and maximum current consumption from v bat supply symbol para meter conditions (1) typ.@v bat max. @v bat = 3.6v (2) unit 1.65 v 1.8v 2v 2.4v 2.7v 3v 3.3v 3.6v t a = 25 c t a = 85 c t a = 105 c i dd_vba t backup domain supply current lse & rtc on; ?xtal ? mode? lower driving ? capability; ? lsedrv[1:0] = '00' 0.42 0.44 0.47 0.54 0.60 0.66 0.74 0.82 - - - a lse & rtc on; ?xtal ? mode? higher driving ? capability; ? lsedrv[1:0] = '11' 0.71 0.74 0.77 0.85 0.91 0.98 1.06 1.16 - - - 1. crystal used: abracon abs07-120-32.768 khz-t with a cl of 6 pf for typical values. 2. data based on characterization results, not tested in production. docid025409 rev 2 63/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 figure 12. typical v bat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) typical current consumption the mcu is placed under the following conditions: ? v dd = v dda = 3.3 v ? all i/o pins available on each packag e are in analog input configuration ? the flash access time is adjusted to f hclk frequency (0 wait states from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states from 48 mhz to 72 mhz), and flash prefetch is on ? when the peripherals are enabled, f apb1 = f ahb/2 , f apb2 = f ahb ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 mhz, 2 mhz, 1 mhz, 500 khz and 125 khz respectively. 0 6 9 ? & ? & ? & ? & , 9 % $ 7 ? $ 7 ? & 9 9 9 9 9 9 9 9 $ electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 64/124 docid025409 rev 2 table 30. typical current consumption in run m ode, code with data processing running from flash symbol parameter conditions f hclk typ. unit peripherals enabled peripherals disabled i dd supply current in ? run mode from ? v dd supply running from hse crystal clock 8 mhz, code executing from flash 72 mhz 70.6 25.2 ma 64 mhz 60.3 22.6 48 mhz 46.0 17.3 32 mhz 31.3 12.0 24 mhz 25.0 9.3 16 mhz 16.2 6.5 8 mhz 8.4 3.55 4 mhz 4.75 2.21 2 mhz 2.81 1.52 1 mhz 1.82 1.17 500 khz 1.34 0.94 125 khz 0.93 0.82 i dda (1) (2) supply current in run mode from v dda supply 72 mhz 240.0 234.0 a 64 mhz 209.9 208.6 48 mhz 154.5 153.5 32 mhz 104.1 103.6 24 mhz 80.2 80.0 16 mhz 56.8 56.6 8 mhz 1.14 1.14 4 mhz 1.14 1.14 2 mhz 1.14 1.14 1 mhz 1.14 1.14 500 khz 1.14 1.14 125 khz 1.14 1.14 1. v dda supervisor is off. 2. when peripherals are enabled, the power consumption of the anal og part of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tabl es of characteristics in the subsequent sections. docid025409 rev 2 65/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 49: i/o static characteristics . table 31. typical current consumption in sl eep mode, code running from flash or ram symbol parameter conditions f hclk typ. unit peripherals enabled peripherals disabled i dd supply current in ? sleep mode from ? v dd supply running from hse crystal clock 8 mhz, code executing from flash or ram 72 mhz 51.8 6.3 ma 64 mhz 46.4 5.7 48 mhz 35.0 4.40 32 mhz 23.7 3.13 24 mhz 18.0 2.49 16 mhz 12.2 1.85 8 mhz 6.2 0.99 4 mhz 3.68 0.88 2 mhz 2.26 0.80 1 mhz 1.55 0.76 500 khz 1.20 0.74 125 khz 0.89 0.72 i dda (1) (2) supply current in sleep mode from v dda supply 72 mhz 239.0 236.7 a 64 mhz 209.4 207.8 48 mhz 154.0 152.9 32 mhz 103.7 103.2 24 mhz 80.1 79.8 16 mhz 56.7 56.6 8 mhz 1.14 1.14 4 mhz 1.14 1.14 2 mhz 1.14 1.14 1 mhz 1.14 1.14 500 khz 1.14 1.14 125 khz 1.14 1.14 1. v dda supervisor is off. 2. when peripherals are enabled, the power consumption of the anal og part of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tables of characteristics in the subsequent sections. electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 66/124 docid025409 rev 2 for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 33: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capaci tive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext+cs the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c ? ? = docid025409 rev 2 67/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 on-chip peripheral current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input configuration ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature at 25c and v dd = v dda = 3.3 v table 32. switching output i/o current consumption symbol parameter conditions (1) 1. cs = 5 pf (estimated value). i/o toggling frequency (f sw ) typ. unit i sw i/o current consumption v dd = 3.3 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.90 ma 4 mhz 0.93 8 mhz 1.16 18 mhz 1.60 36 mhz 2.51 v dd = 3.3 v c ext = 10 pf c = c int + c ext +c s 2 mhz 0.93 4 mhz 1.06 8 mhz 1.47 18 mhz 2.26 36 mhz 3.39 v dd = 3.3 v c ext = 22 pf c = c int + c ext +c s 2 mhz 1.03 4 mhz 1.30 8 mhz 1.79 18 mhz 3.01 36 mhz 5.99 v dd = 3.3 v c ext = 33 pf c = c int + c ext + c s 2 mhz 1.10 4 mhz 1.31 8 mhz 2.06 18 mhz 3.47 36 mhz 8.35 v dd = 3.3 v c ext = 47 pf c = c int + c ext + c s 2 mhz 1.20 4 mhz 1.54 8 mhz 2.46 18 mhz 4.51 36 mhz 9.98 electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 68/124 docid025409 rev 2 table 33. peripheral current consumption peripheral typical consumption (1) unit i dd busmatrix (2) 11.1 a/mhz dma1 8.0 crc 2.1 gpioa 8.7 gpiob 8.4 gpioc 8.4 gpiod 2.6 gpiof 1.7 tsc 4.7 adc1&2 17.4 apb2-bridge (3) 3.3 syscfg 4.2 tim1 32.3 tim1 8.2 usart1 20.3 tim15 13.8 tim16 9.7 tim17 10.3 hrtim 324.2 apb1-bridge (3) 5.3 tim2 43.4 tim3 34.0 tim6 9.7 tim7 10.3 wwdg 6.9 usart2 18.8 usart3 19.1 i2c1 13.3 can 31.3 a/mhz pwr 4.7 dac 15.4 dac2 8.6 spi1 8.2 docid025409 rev 2 69/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 6.3.6 wakeup time from low-power mode the wakeup times given in table 34 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep mode: the wakeup event is wfe. ? wkup1 (pa0) pin is used to wakeup from standby, stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 19 . 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillato r is switched off and the inpu t pin is a standard gpio. the external clock signal has to re spect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 13 . 1. the power consumption of the analog part (i dda ) of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tables of characteristics in the subsequent sections. 2. busmatrix is automatically active when at least one master is on (cpu or dma1). 3. the apbx bridge is automatically active when at least one peripheral is on on the same bus. table 34. low-power mode wakeup timings symbol parameter conditions typ. @v dd, v dd = v dda max. unit 2.0 v 2.4 v 2.7 v 3 v 3.3 v 3.6 v t wustop wakeup from stop mode regulator in run mode 4.3 4.1 4.0 3.9 3.8 3.7 4.5 s regulator in low-power mode 7.8 6.7 6.1 5.9 5.5 5.3 9 t wustandby (1) wakeup from standby mode lsi and iwdg off 74.4 64.3 60.0 56.9 54.3 51.1 103 t wusleep wakeup from sleep mode -6- cpu clock cycles 1. data based on characterization re sults, not tested in production. electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 70/124 docid025409 rev 2 figure 13. high-speed external clock source ac timing diagram low-speed external user clock generated from an external source in bypass mode the lse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to re spect the i/o characteristics in section 6.3.14 . however, the recommended clock input waveform is shown in figure 14 table 35. high-speed external user clock characteristics symbol parameter conditions min. typ. max. unit f hse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. - 1832mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hseh) t w(hsel) osc_in high or low time (1) 15 - - ns t r(hse) t f(hse) osc_in rise or fall time (1) --20 table 36. low-speed external user clock characteristics symbol parameter conditions min. typ. max. unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. - - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lseh) t w(lsel) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 0 6 9 9 + 6 ( + w i + 6 ( 7 + 6 ( w w u + 6 ( 9 + 6 ( / w z + 6 ( + w z + 6 ( / docid025409 rev 2 71/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 figure 14. low-speed external clock source ac timing diagram high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 37 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). table 37. hse oscillator characteristics symbol parameter conditions (1) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. min. (2) 2. guaranteed by design, not tested in production. typ. max. (2) unit f osc_in oscillator frequency - 4 8 32 mhz r f feedback resistor - - 200 - k ? i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time. --8.5 ma v dd = 3.3 v, rm= 30 ? , cl=10 pf@8 mhz -0.4- v dd = 3.3 v, rm= 45 ? , cl=10 pf@8 mhz -0.5- v dd = 3.3 v, rm= 30 ? , cl=10 pf@32 mhz -0.8- v dd = 3.3 v, rm= 30 ? , cl=10 pf@32 mhz -1- v dd = 3.3 v, rm= 30 ? , cl=10 pf@32 mhz -1.5- g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal res onator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 2 - ms 0 6 9 9 / 6 ( + w i / 6 ( 7 / 6 ( w w u / 6 ( 9 / 6 ( / w z / 6 ( + w z / 6 ( / electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 72/124 docid025409 rev 2 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-freque ncy applications, and selected to match the requirements of the crystal or resonator (see figure 15 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 15. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 38 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 5 ) % l d v f r q w u r o o h g j d l q i + 6 ( 5 ( ; 7 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / docid025409 rev 2 73/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . table 38. lse oscillato r characteristics (f lse = 32.768 khz) symbol parameter conditions (1) 1. refer to the note and caution paragraphs below the table, and to the applicat ion note an2867 ?oscillator design guide for st microcontrollers?. min. (2) 2. guaranteed by design, not tested in production. typ. max. ( 2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability -0.50.9 a lsedrv[1:0]=01 medium low driving capability --1 lsedrv[1:0]=10 medium high driving capability --1.3 lsedrv[1:0]=11 higher driving capability --1.6 g m oscillator ? transconductance lsedrv[1:0]=00 lower driving capability 5- - a/v lsedrv[1:0]=01 medium low driving capability 8- - lsedrv[1:0]=10 medium high driving capability 15 - - lsedrv[1:0]=11 higher driving capability 25 - - t su(lse) (3) 3. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation is reached. this value is meas ured for a standard crystal and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 2 - s electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 74/124 docid025409 rev 2 figure 16. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. 6.3.8 internal clock source characteristics the parameters given in table 39 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 19 . high-speed internal (hsi) rc oscillator 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 ' u l y h s u r j u d p p d e o h d p s o l i l h u i + 6 ( n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / table 39. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min. typ. max. unit f hsi frequency - - 8 - mhz trim hsi user trimming step - - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle - 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator (factory calibrated) t a = ?40 to 105 c ?2.8 (3) 3. data based on characterization results, not tested in production. -3.8 (3) % t a = ?10 to 85 c ?1.9 (3) -2.3 (3) t a = 0 to 85 c -1.9 (3) 2 (3) t a = 0 to 70 c -1.3 (3) -2 (3) t a = 0 to 55 c ?1 (3) -2 (3) t a = 25 c (4) 4. factory calibrated, parts not soldered ?1 - 1 t su(hsi) hsi oscillator startup time -1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption - - 80 100 (2) a docid025409 rev 2 75/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 figure 17. hsi oscillator accuracy characterization results for soldered parts low-speed internal (lsi) rc oscillator 6.3.9 pll characteristics the parameters given in table 41 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 19 . table 40. lsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min. typ. max. unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dd(lsi) (2) lsi oscillator power consumption - 0.75 1.2 a 0 6 9 5 < ? $ > " . " 9 . * / table 41. pll characteristics symbol parameter value unit min. typ. max. f pll_in pll input clock (1) 1. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 1 (2) -24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) -72mhz t lock pll lock time - - 200 (2) s jitter cycle-to-cycle jitter - - 300 (2) 2. guaranteed by design, not tested in production. ps electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 76/124 docid025409 rev 2 6.3.10 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. table 42. flash memory characteristics symbol parameter conditions min. typ. max. (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a ??? ?40 to +105 c 20 - 40 s t erase page (2 kb) erase time t a ?? ?40 to +105 c 20 - 40 ms t me mass erase time t a ?? ?40 to +105 c 20 - 40 ms i dd supply current write mode - - 10 ma erase mode - - 12 ma table 43. flash memory endurance and data retention symbol parameter conditions value unit min. (1) 1. data based on characterization results, not tested in production. n end endurance ta = ?40 to +85 c (6 suffix versions) ta = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 docid025409 rev 2 77/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 6.3.11 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 44 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) table 44. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, lqfp64, t a = +25c, ? f hclk = 72 mhz ? conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, lqfp64, t a = +25c, ? f hclk = 72 mhz ? conforms to iec 61000-4-4 4a electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 78/124 docid025409 rev 2 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 45. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/72 mhz s emi peak level v dd ?? 3.6 v, t a ? 25 c, ? lqfp64 package ? compliant with iec 61967-2 0.1 to 30 mhz 5 dbv 30 to 130 mhz 9 130 mhz to 1ghz 31 sae emi level 4 - table 46. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm ) electrostatic discharge voltage (human body model) t a ?? +25 c, conforming to jesd22- a114 22000 v v esd(cd m) electrostatic discharge voltage (charge device model) t a ?? +25 c, conforming to jesd22- c101 ii 250 docid025409 rev 2 79/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or other functional failu re (for example reset occurrence or oscillator frequency deviation). the te st results are given in table 48: i/o current injection susceptibility . table 47. electrical sensitivities symbol parameter conditions class lu static latch-up class t a ?? +105 c conforming to jesd78a ii level a electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 80/124 docid025409 rev 2 note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 49 are derived from tests performed under the conditions summarized in table 19 . all i/os are cmos and ttl compliant. table 48. i/o current in jection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 -0 na ma injected current on pc0, pc1, pc2, pc3 (tta pins) and pf1 pin (ft pin) , -0 +5 injected current on pa0 , pa1, pa2, pa3, pa4, pa5, pa6, pa7, pc4, pc5, pb0 , pb1, pb2, pb12, pb13, pb14, pb15 with induced leakage current on other pins from this group less than -100 a or more than +900 a -5 +5 injected current on pb11, other tt, ft, and ftf pins -5 na injected current on all other tc, tt a and reset pins -5 +5 table 49. i/o static characteristics symbol parameter conditions min. typ. max. unit v il low level input voltage tt, tc and tta i/o - - 0.3 v dd +0.07 (1) v ft and ftf i/o - - 0.475 v dd -0.2 (1) boot0 - - 0.3 v dd ?0.3 (1) all i/os except boot0 - - 0.3 v dd (2) v ih high level input voltage tta and tt i/o 0.445 v dd +0.398 (1) -- ft and ftf i/o 0.5 v dd+0.2 (1) -- boot0 0.2 v dd +0.95 (1) -- all i/os except boot0 0.7 v dd (2) -- docid025409 rev 2 81/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. the coverage of these requirements is shown in figure 18 and figure 19 for standard i/os. v hys schmitt trigger hysteresis tt, tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - i lkg input leakage current (3) tc, ft, tt, ftf and tta i/o in digital mode v ss ?? v in ?? v dd --0.1 a tta i/o in digital mode v dd ?? v in ?? v dda --1 tta i/o in analog mode v ss ?? v in ?? v dda --0.2 ft and ftf i/o (4) v dd ?? v in ?? 5 v --10 r pu weak pull-up equivalent resistor (5) v in ?? v ss 25 40 55 k ? r pd weak pull-down equivalent resistor (5) v in ?? v dd 25 40 55 k ? c io i/o pin capacitance - - 5 - pf 1. data based on design simulation. 2. tested in production. 3. leakage could be higher than the maximum value. if n egative current is injected on adjacent pins. refer to table 48: i/o current injection susceptibility . 4. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pull-down resistors must be disabled. 5. pull-up and pull-down resistors are designed with a true re sistance in series with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimum (~10% order). table 49. i/o static characteristics (continued) symbol parameter conditions min. typ. max. unit electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 82/124 docid025409 rev 2 figure 18. tc and tta i/o input characteristics - cmos port figure 19. tc and tta i/o input characteristics - ttl port 0 6 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g 7 h v w h g l q s u r g x f w l r q 7 h v w h g l q s u r g x f w l r q % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 0 6 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 9 , / p d [ 9 ' ' 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v docid025409 rev 2 83/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 figure 20. five volt tole rant (ft and ftf) i/o input characteristics - cmos port figure 21. five volt tolerant (ft and ftf) i/o input characteristics - ttl port output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol/ v oh ). in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating ? i vdd (see table 17 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating ? i vss (see table 17 ). output voltage levels unless otherwise specified, the parameters given in table 46: esd absolute maximum ratings are derived from tests performed under ambient temperature and v dd supply 0 6 9 9 ' ' 9 9 , / 9 , + 9 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v 7 h v w h g l q s u r g x f w l r q & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 7 h v w h g l q s u r g x f w l r q 0 6 9 9 ' ' 9 9 , / 9 , + 9 9 , / p l q 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 7 7 / v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 84/124 docid025409 rev 2 voltage conditions summarized in table 19 . all i/os (ft, tta and tc unless otherwise specified) are cmos and ttl compliant. input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 22 and table 65 , respectively. unless otherwise specified, th e parameters given are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 19 . table 50. output voltage characteristics symbol parameter con ditions min. max. unit v ol (1) output low level voltage for an i/o pin cmos port (2) i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v v oh (3) output high level voltage for an i/o pin v dd ?0.4 - v ol (1) output low level voltage for an i/o pin ttl port (2) i io = +8 ma 2.7 v < v dd < 3.6 v -0.4 v oh (3) output high level voltage for an i/o pin 2.4 - v ol (1)(4) output low level voltage for an i/o pin i io = +20 ma 2.7 v < v dd < 3.6 v -1.3 v oh (3)(4) output high level voltage for an i/o pin v dd ?1.3 - v ol (1)(4) output low level voltage for an i/o pin i io = +6 ma 2 v < v dd < 2.7 v -0.4 v oh (3)(4) output high level voltage for an i/o pin v dd ?0.4 - v olfm+ (1)(4) output low level voltage for an ftf i/o pin in fm+ mode i io = +20 ma 2.7 v < v dd < 3.6 v -0.4 1. the i io current sunk by the device must always res pect the absolute maximum rating specified in table 17 and the sum of i io (i/o ports and control pins) must not exceed ? i io(pin) . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. the i io current sourced by the device must always re spect the absolute maximu m rating specified in table 17 and the sum of i io (i/o ports and control pins) must not exceed ? i io(pin) . 4. data based on design simulation. table 51. i/o ac characteristics (1) ospeedry [1:0] value (1) symbol parameter conditions min. max. unit x0 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 2 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v -125 (3) ns t r(io)out output low to high level rise time -125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v - 10 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 2 v to 3.6 v -25 (3) ns t r(io)out output low to high level rise time -25 (3) docid025409 rev 2 85/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 figure 22. i/o ac charac teristics definition 11 f max(io)out maximum frequency (2) c l = 30 pf, v dd = 2.7 v to 3.6 v - 50 (3) mhz c l = 50 pf, v dd = 2.7 v to 3.6 v - 30 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 20 (3) t f(io)out output high to low level fall time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) ns c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) t r(io)out output low to high level rise time c l = 30 pf, v dd = 2.7 v to 3.6 v - 5 (3) c l = 50 pf, v dd = 2.7 v to 3.6 v - 8 (3) c l = 50 pf, v dd = 2 v to 2.7 v - 12 (3) fm+ configuration (4) f max(io)out maximum frequency (2) c l = 50 pf, v dd = 2 v to 3.6 v -2 (4) mhz t f(io)out output high to low level fall time -12 (4) ns t r(io)out output low to high level rise time -34 (4) -t extipw pulse width of external signals detected by the exti controller -10 (3) -ns 1. the i/o speed is configured using the ospeedrx[1:0] bits . refer to the rm0364 reference manual for a description of gpio port configuration register. 2. the maximum frequency is defined in figure 22 . 3. guaranteed by design, not tested in production. 4. the i/o speed configuration is bypassed in fm+ i/o mode. refer to the rm0364 reference manual for a description of fm+ i/o mode configuration. table 51. i/o ac characteristics (1) (continued) ospeedry [1:0] value (1) symbol parameter conditions min. max. unit d l g w u , 2 r x w 2 8 7 3 8 7 ( ; 7 ( 5 1 $ / 2 1 & / 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w u w i ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ & / v s h f l i l h g l q w k h w d e o h 3 , 2 $ & f k d u d f w h u l v w l f v 7 w i , 2 r x w electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 86/124 docid025409 rev 2 6.3.15 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 49 ). unless otherwise specified, the parameters given in table 52 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 19 . figure 23. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 52 . otherwise the reset will not be taken into account by the device. 6.3.16 high-resolution timer (hrtim) the parameters given in table 53 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 19 . table 52. nrst pin characteristics symbol parameter conditions min. typ. max. unit v il(nrst) (1) nrst input low level voltage - - - 0.3v dd + 0.07 (1) v v ih(nrst) (1) nrst input high level voltage - 0.445v dd + 0.398 (1) -- v hys(nrst) nrst schmitt trigger voltage hysteresis - - 200 - mv r pu weak pull-up equivalent resistor (2) v in ?? v ss 25 40 55 k ? v f(nrst) (1) nrst input filtered pulse - - - 100 (1) ns v nf(nrst) (1) nrst input not filtered pulse - 500 (1) --ns 1. guaranteed by design, not tested in production. 2. the pull-up is designed with a true resistance in se ries with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . 0 6 9 ( [ w h u q d o u h v h w f l u f x l w u \ 1 5 6 7 ? ) 9 ' ' 5 3 8 ) l o w h u , q w h u q d o u h v h w docid025409 rev 2 87/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 table 53. hrtim1 characteristics symbol parameter conditions min. typ. max. unit t a timer ambient temperature range f hrtim =144mhz (1) 1. using hse with 8mhz xtal as clock source, co nfiguring pll to get pllclk=144mhz, and selecting pllclkx2 as hrtim clock source. (refer to reset and clock control section in rm0364.) -40 - 105 c f hrtim =128mhz (2) 2. using hsi (internal 8mhz rc oscillator), configuring pll to get pllclk=128mhz, and selecting pllclkx2 as hrtim clock source. (refer to reset and clock control section in rm0364. -10 - 105 c f hrtim hrtim input clock for dll calibration as per t a conditions 128 - 144 mhz t hrtim 6.9 - 7.8 ns t res(hrtim) timer resolution time f hrtim =144mhz (1) , ta from -40 to 105c -217- ps f hrtim =128mhz (2) ,ta from -10 to 105c -244- ps res hrtim timer resolution - - - 16 bit t dtg dead time generator clock period - 0.125 - 16 t hrtim f hrtim =144mhz (1) 0.868 - 111.10 ns |t dtr| / | t dtf| max dead time range (absolute value) ---511t dtg f hrtim =144mhz (1) - - 56.77 s f chpfrq chopper stage clock frequency - 1/256 - 1/16 f hrtim f hrtim =144mhz (1) 0.562 - 9 mhz t 1stpw chopper first pulse length -16-256t hrtim f hrtim =144mhz (1) 0.111 - 1.77 s table 54. hrtim output response to fault protection (1) symbol parameter conditions min typ. max. (2) unit t lat(df) digital fault response latency propagation delay from hrtim1_fltx digital input to hrtim_chxy output pin -1225 ns t w(flt) minimum fault pulse width -12.5-- t lat(af) analog fault response latency propagation delay from comparator compx_inp input pin to hrtim_chxy output pin -2543 1. refer to fault paragraph in hrtim section of rm0364. 2. data based on characterization results, not tested in production electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 88/124 docid025409 rev 2 table 55. hrtim output response to external events 1 to 5 (low latency mode (1) ) symbol parameter conditions min typ. max. (2) unit t lat(deev) digital external event response latency propagation delay from hrtim1_eevx digital input to hrtim_chxy output pin (30pf load) -1225 ns t w(flt) minimum external event pulse width -12.5--ns t lat(aeev) analog external event response latency propagation delay from comparator compx_inp input pin to hrtim_chxy output pin (30pf load) -2543 ns t jit(eev) external event response jitter jitter of the delay from hrtim1_eevx digital input or compx_inp input pin to hrtim_chxy output pin --0t hrtim (3) t jit(pw) jitter on output pulse width in response to an external event ---1t hrtim (3) 1. eexfast bit in hrtim_eecr1 register is set (low lat ency mode). this functionality is available on external events channels 1 to 5. refer to latency to exter nal events paragraph in hrtim section of rm0364. 2. data based on characterization results, not tested in production. 3. t hrtim = 1 / f hrtim with f hrtim = 144 mhz or f hrtim = 128 mhz depending on the clock controller configuration. (refer to reset and clock control section in rm0364.) table 56. hrtim output response to external events 1 to 10 (synchronous mode (1) ) symbol parameter conditions min. typ. max. (2) unit t prop(hrti m) external event response latency in hrtim hrtim internal propagation delay (3) 6- 7t hrtim t lat(deev) digital external event response latency propagation delay from hrtim1_eevx digital input to hrtim_chxy output pin (30pf load) (4) -6172 ns t lat(aeev) analog external event response latency propagation delay from compx_inp input pin to hrtim_chxy output pin (30pf load) (4) -8194 ns t w(flt) minimum external event pulse width - 12.5 - - ns t jit(eev) external event response jitter jitter of the delay from hrtim1_eevx digital input or compx_inp to hrtim_chxy output pin --1 t hrtim (5) t jit(pw) jitter on output pulse width in response to an external event - --0 t hrtim (5) 1. eexfast bit in hrtim_eecr1 or hrtim_eecr2 register is cleared (synchronous mode). external event filtering is disabled, i.e. eexf[3:0]=0000 in hrtim_eecr2 register. refer to latency to external events paragraph in hrtim section of rm0364. 2. data based on characterization re sults, not tested in production. docid025409 rev 2 89/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 3. this parameter does not take into account latency in troduced by gpio or comparator. refer to deerl or sacrl parameter for complete latency. 4. this parameter is given for f hrtim = 144 mhz. 5. t hrtim = 1 / f hrtim with f hrtim = 144 mhz or f hrtim = 128 mhz depending on the clock controll er configuration. (refer to reset and clock control section in rm0364.) table 57. hrtim synchroni zation input / output (1) 1. guaranteed by design, not tested in production. symbol parameter conditions min. typ. max. unit t w(synci n) minimum pulse width on syncin inputs, including hrtim1_scin -2--t hrtim t lat(df) response time to external synchronization request ---1t hrtim t lat(af) pulse width on hrtim1_scout output --16-t hrtim f hrtim =144 mhz - 111.1 - ns electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 90/124 docid025409 rev 2 6.3.17 timer characteristics the parameters given in table 58 are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). table 58. timx (1)(2) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim3,tim15, tim16 and tim17 timers. 2. guaranteed by design, not tested in production. symbol parameter conditions min. max. unit t res(tim) timer resolution time -1- t timxcl k f timxclk = 72 mhz ? 13.9 - ns f tim1clk = 144 mhz 6.95 - ns f ext timer external clock frequency on ch1 to ch4 -0f timxclk /2 mhz f timxclk = 72 mhz 0 36 mhz res tim timer resolution timx (except tim2) - 16 bit tim2 - 32 t counter 16-bit counter clock period - 1 65536 t timxcl k f timxclk = 72 mhz 0.0139 910 s f tim1clk = 144 mhz 0.0069 455 s t max_coun t maximum possible count with 32-bit counter - - 65536 65536 t timxcl k f timxclk = 72 mhz - 59.65 s f tim1clk = 144 mhz - 29.825 s docid025409 rev 2 91/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 table 59. iwdg min./max. timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 kh z clock but the microcontroller?s in ternal rc frequency can vary from 30 to 60 khz. moreover, given an exact rc oscillator frequency, the exact timings still depend on the phasing of the apb interface clock versus the lsi clock so t hat there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min. timeout (ms) rl[11:0]= 0x000 max. timeout (ms) rl[11:0]= 0xfff /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 table 60. wwdg min./max. timeout value at 72 mhz (pclk) (1) 1. guaranteed by design, not tested in production. prescaler wdgtb min. timeout value max. timeout value 1 0 0.05687 3.6409 2 1 0.1137 7.2817 4 2 0.2275 14.564 8 3 0.4551 29.127 electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 92/124 docid025409 rev 2 6.3.18 communications interfaces i 2 c interface characteristics the i2c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1 mbit/s. the i2c timings requirements are guaranteed by design when the i2c peripheral is properly configured (refer to reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not "true" open-drain. when configured as open-drain, the pmos connected between the i/o pin and vdd is disabled, but is still present. only ftf i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.14: i/o port characteristics for the i2c i/o characteristics. all i2c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: spi characteristics unless otherwise specified, the parameters given in table 52 for spi are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 19: general operating conditions . refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi). table 61. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min. max. unit t af maximum pulse width of spikes that are suppressed by the analog filter. 50 (2) 2. spikes with width below t af (min.) are filtered. 260 (3) 3. spikes with width above t af (max.) are not filtered. ns table 62. spi characteristics (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master mode 2.7 electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 94/124 docid025409 rev 2 figure 25. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at 0.5v dd and with external c l = 30 pf. figure 26. spi timing diagram - master mode (1) 1. measurement points are done at 0.5v dd and with external c l = 30 pf. 1. measurement points are done at 0.5vdd and with external cl=30 pf. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. 1. measurement points are done at 0.5vdd and with external cl=30 pf. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. d l ^ < /v?? w , a d k ^ / / e w h d d / ^ k k h d w h d w , a d ^ k h d d ^ / e / d k h d > ^ / e > ^ k h d w k >a w k >a / d / e ? ^ h~ e ^ ^ ? ~ ^ < ? z~ e ^ ^ ? ~ ^ k ? ~ ^ > , ? ~ ^ > > ? ~ ^ k ? z~ ^ k ? ?~ ^ > ? (~ ^ > ? ]?~ ^ k ? ?~ ^ / ? z~ ^ / e ^ ^ ]v?? d l 9 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ 0 6 % , 1 0 6 % 2 8 7 % , 7 , 1 / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 docid025409 rev 2 95/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 can (controller area network) interface refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). 6.3.19 adc characteristics unless otherwise specified, the parameters given in table 63 to table 66 are guaranteed by design, with conditio ns summarized in table 19 . table 63. adc characteristics symbol parameter conditions min. typ. max. unit v dda analog supply voltage for adc -2-3.6v i dda adc current consumption ( figure 27 ) single ended mode, 5 msps, - 1011.3 1172.0 a single ended mode, 1 msps - 214.7 322.3 single ended mode, 200 ksps - 54.7 81.1 differential mode,5 msps, - 1061.5 1243.6 differential mode, 1 msps - 246.6 337.6 differential mode, 200 ksps - 56.4 83.0 f adc adc clock frequency - 0.14 - 72 mhz f s (1) sampling rate resolution = 12 bits, fast channel 0.01 - 5.14 msps resolution = 10 bits, fast channel 0.012 - 6 resolution = 8 bits, fast channel 0.014 - 7.2 resolution = 6 bits, fast channel 0.0175 - 9 f trig (1) external trigger frequency f adc = 72 mhz resolution = 12 bits - - 5.14 mhz resolution = 12 bits - - 14 1/f adc v ain conversion voltage range - 0 - v dda v r ain (1) external input impedance - - - 100 ?? c adc (1) internal sample and hold capacitor --5-pf t cal (1) calibration time f adc = 72 mhz 1.56 s - 112 1/f adc electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 96/124 docid025409 rev 2 figure 27. adc typical current consumption in single-ended and differential modes t latr (1) trigger conversion latency ? regular and injected channels without conversion abort ckmode = 00 1.5 2 2.5 1/f adc ckmode = 01 - - 2 1/f adc ckmode = 10 - - 2.25 1/f adc ckmode = 11 - - 2.125 1/f adc t latrinj (1) trigger conversion latency ? injected channels aborting a regular conversion ckmode = 00 2.5 3 3.5 1/f adc ckmode = 01 - - 3 1/f adc ckmode = 10 - - 3.25 1/f adc ckmode = 11 - - 3.125 1/f adc t s (1) sampling time f adc = 72 mhz 0.021 - 8.35 s - 1.5 - 601.5 1/f adc tadcvreg _stup (1) adc voltage regulator start-up time ---10s t conv (1) total conversion time (including sampling time) f adc = 72 mhz resolution = 12 bits 0.19 - 8.52 s resolution = 12 bits 14 to 614 (t s for sampling + 12.5 for successive approximation) 1/f adc 1. data guaranteed by design, not tested in production. table 63. adc characteristics (continued) symbol parameter conditions min. typ. max. unit 0 6 9 $ ' & f x u u h q w f r q v x p s w l r q ? $ & o r f n i u h t x h q f \ 0 6 3 6 docid025409 rev 2 97/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 table 64. maximum adc r ain (1) resolution sampling cycle @ 72 mhz sampling time [ns] @ 72 mhz r ain max. (k ? ) fast channels (2) slow channels other channels (3) 12 bits 1.5 20.83 0.018 na na 2.5 34.72 0.150 na 0.022 4.5 62.50 0.470 0.220 0.180 7.5 104.17 0.820 0.560 0.470 19.5 270.83 2.70 1.80 1.50 61.5 854.17 8.20 6.80 4.70 181.5 2520.83 22.0 18.0 15.0 601.5 8354.17 82.0 68.0 47.0 10 bits 1.5 20.83 0.082 na na 2.5 34.72 0.270 0.082 0.100 4.5 62.50 0.560 0.390 0.330 7.5 104.17 1.20 0.82 0.68 19.5 270.83 3.30 2.70 2.20 61.5 854.17 10.0 8.2 6.8 181.5 2520.83 33.0 27.0 22.0 601.5 8354.17 100.0 82.0 68.0 8 bits 1.5 20.83 0.150 na 0.039 2.5 34.72 0.390 0.180 0.180 4.5 62.50 0.820 0.560 0.470 7.5 104.17 1.50 1.20 1.00 19.5 270.83 3.90 3.30 2.70 61.5 854.17 12.00 12.00 8.20 181.5 2520.83 39.00 33.00 27.00 601.5 8354.17 100.00 100.00 82.00 6 bits 1.5 20.83 0.270 0.100 0.150 2.5 34.72 0.560 0.390 0.330 4.5 62.50 1.200 0.820 0.820 7.5 104.17 2.20 1.80 1.50 19.5 270.83 5.60 4.70 3.90 61.5 854.17 18.0 15.0 12.0 181.5 2520.83 56.0 47.0 39.0 601.5 8354.17 100.00 100.0 100.0 1. data based on characterization results, not tested in production . electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 98/124 docid025409 rev 2 2. all fast channels, expect channel on pa6. 3. channels available on pa6. table 65. adc accuracy - limited test conditions (1)(2) symbol parameter conditions min (3) typ max (3) unit et to ta l unadjusted error adc clock freq. ? 72 mhz sampling freq. ? 5 msps v dda = 3.3 v 25c single ended fast channel 5.1 ms - 4 4.5 lsb slow channel 4.8 ms - 5.5 6 differential fast channel 5.1 ms - 3.5 4 slow channel 4.8 ms - 3.5 4 eo offset error single ended fast channel 5.1 ms - 2 2 slow channel 4.8 ms - 1.5 2 differential fast channel 5.1 ms - 1.5 2 slow channel 4.8 ms - 1.5 2 eg gain error single ended fast channel 5.1 ms - 3 4 slow channel 4.8 ms - 5 5.5 differential fast channel 5.1 ms - 3 3 slow channel 4.8 ms - 3 3.5 ed differential linearity error single ended fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1 differential fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1 el integral linearity error single ended fast channel 5.1 ms - 1.5 2 slow channel 4.8 ms - 2 3 differential fast channel 5.1 ms - 1.5 1.5 slow channel 4.8 ms - 1.5 2 enob (4) effective number of bits single ended fast channel 5.1 ms 10.8 10.8 - bit slow channel 4.8 ms 10.8 10.8 - differential fast channel 5.1 ms 11.2 11.3 - slow channel 4.8 ms 11.2 11.3 - sinad (4) signal-to- noise and distortion ratio single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - docid025409 rev 2 99/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 snr (4) signal-to- noise ratio adc clock freq. ??? 72 mhz sampling freq ??? 5 msps v dda = 3.3 v 25c single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - thd (4) to ta l harmonic distortion single ended fast channel 5.1 ms - -80 -80 slow channel 4.8 ms - -78 -77 differential fast channel 5.1 ms - -83 -82 slow channel 4.8 ms - -81 -80 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. ? any positive injection current wi thin the limits specified for i inj(pin) and ? i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. data based on characterization re sults, not tested in production. 4. value measured with a -0.5 db full scale 50 khz sine wave input signal. table 65. adc accuracy - limited test conditions (1)(2) (continued) symbol parameter conditions min (3) typ max (3) unit electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 100/124 docid025409 rev 2 table 66. adc accuracy (1)(2)(3) symbol parameter conditions min (4) max (4) unit et to ta l unadjusted error adc clock freq. ??? 72 mhz, sampling freq. ??? 5 msps 2.0 v ??? v dda ?? 3.6 v single ended fast channel 5.1 ms - 6.5 lsb slow channel 4.8 ms - 6.5 differential fast channel 5.1 ms - 4 slow channel 4.8 ms - 4.5 eo offset error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3 differential fast channel 5.1 ms - 2.5 slow channel 4.8 ms - 2.5 eg gain error single ended fast channel 5.1 ms - 6 slow channel 4.8 ms - 6 differential fast channel 5.1 ms - 3.5 slow channel 4.8 ms - 4 ed differential linearity error single ended fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 differential fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 el integral linearity error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3.5 differential fast channel 5.1 ms - 2 slow channel 4.8 ms - 2.5 enob (5) effective number of bits single ended fast channel 5.1 ms 10.4 - bits slow channel 4.8 ms 10.4 - differential fast channel 5.1 ms 10.8 - slow channel 4.8 ms 10.8 - sinad (5) signal-to- noise and distortion ratio single ended fast channel 5.1 ms 64 - db slow channel 4.8 ms 63 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - docid025409 rev 2 101/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 snr (5) signal-to- noise ratio adc clock freq. ??? 72 mhz, sampling freq ??? 5 msps, 2.0 v ??? v dda ?? 3.6 v single ended fast channel 5.1 ms 64 - db slow channel 4.8 ms 64 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - thd (5) to ta l harmonic distortion single ended fast channel 5.1 ms - -75 slow channel 4.8 ms - -75 differential fast channel 5.1 ms - -79 slow channel 4.8 ms - -78 1. adc dc accuracy values are m easured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pins should be avoided as this significantly reduces the ac curacy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. ? any positive injection current wi thin the limits specified for i inj(pin) and ? i inj(pin) in section 6.3.14 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization results, not tested in production. 5. value measured with a -0.5 db full scale 50 khz sine wave input signal. table 66. adc accuracy (1)(2)(3) (continued) symbol parameter conditions min (4) max (4) unit table 67. adc accuracy (1)(2) at 1msps symbol parameter test conditions typ max (3) unit et total unadjusted error adc freq 72 mhz ? sampling freq 1msps ? 2.4 v v dda = v ref+ 3.6 v single-ended mode fast channel 2.5 5 lsb slow channel 3.5 5 eo offset error fast channel 1 2.5 slow channel 1.5 2.5 eg gain error fast channel 2 3 slow channel 3 4 ed differential linearity error fast channel 0.7 2 slow channel 0.7 2 el integral linearity error fast channel 1 3 slow channel 1.2 3 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negativ e current on any analog input pi ns should be avoided as this significantly reduces the ac curacy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentia lly inject negative current.. any positive injection current within the limits specified for iinj(pin) and iinj(pin) in section 6.3.14: i/o port characteristics does not affect the adc accuracy. 3. data based on characterization results, not tested in production. electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 102/124 docid025409 rev 2 figure 28. adc accuracy characteristics figure 29. typical connecti on diagram using the adc 1. refer to table 63 for the values of r ain . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 10: power supply scheme . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. ( 2 ( * / 6 % , ' ( $ / ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h ( 7 7 r w d o 8 q d g m x v w h g ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g w k h l g h d o w u d q v i h u f x u y h v ( 2 2 i i v h w ( u u r u g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l w l r q d q g w k h i l u v w l g h d o r q h ( * * d l q ( u u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g w k h l g h d o r q h ( / , q w h j u d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q o l q h ( 7 ( ' ( / 9 ' ' $ 9 6 6 $ 9 ' ' $ / 6 % , ' ( $ / 0 6 9 0 6 9 9 ' ' $ , 1 [ , / ? ? $ 9 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 9 7 5 $ ' & & $ ' & c j u d p o w f s u f s 4 b n q m f b o e i p m e " % $ d p o w f s u f s docid025409 rev 2 103/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 6.3.20 dac electri cal specifications table 68. dac characteristics symbol parameter conditions min. typ. max. unit v dda analog supply voltage dac output buffer on 2.4 - 3.6 v r load (1) resistive load dac output buffer on 5 - - k ? r o (1) output impedance dac output buffer off - - 15 k ? c load (1) capacitive load dac output buffer on - - 50 pf v dac_out ( 1) voltage on dac_out output corresponds to 12-bit input code (0x0e0) to (0xf1c) at v dda = 3.6 v and (0x155) and (0xeab) at v dda = 2.4 v 0.2 - v dda ? 0.2 v dac output buffer off -0.5 - mv --v dda ? 1lsb v i dda (3) dac dc current consumption in quiescent mode (2) with no load, middle code (0x800) on the input - - 380 a with no load, worst code (0xf1c) on the input. - - 480 a dnl (3) differential non linearity difference between two consecutive code-1lsb) given for a 10-bit input code dac1 channel 1 -- 0.5 lsb given for a 12-bit input code dac1 channel 1 -- 2 lsb given for a 10-bit input code dac1 channel 2 & dac2 channel 1 ---0.75/+0.25lsb given for a 12-bit input code dac1 channel 2 & dac2 channel 1 -- -3/+1lsb inl (3) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095) given for a 10-bit input code - - 1 lsb given for a 12-bit input code - - 4 lsb offset (3) offset error (difference between measured value at code (0x800) and the ideal value = v dda /2) ---10mv given for a 10-bit input code at ? v dda = 3.6 v -- 3lsb given for a 12-bit input code - - 12 lsb gain error (3) gain error given for a 12-bit input code - - 0.5 % electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 104/124 docid025409 rev 2 figure 30. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external oper ational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. t settling (3 ) settling time (full scale: for a 12-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb c load ? 50 pf, r load ? 5 k ? -3 4 s update rate (3) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) c load ? 50 pf, r load ? 5 k ? -- 1 ms/ s t wakeup (3) wakeup time from off state (setting the enx bit in the dac control register) c load ? 50 pf, r load ? 5 k ? -6.5 10 s psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement no r load , c load = 50 pf - ?67 ?40 db 1. guaranteed by design, not tested in production. 2. quiescent mode refers to the state of the dac a keeping steady value on the output, so no dynamic consumption is involved. 3. data based on characterization results, not tested in production. table 68. dac characteristics (continued) symbol parameter conditions min. typ. max. unit 5 / 2 $ ' & / 2 $ ' % x i i h u h g 1 r q e x i i h u h g ' $ & ' $ & [ b 2 8 7 % x i i h u e l w g l j l w d o w r d q d o r j f r q y h u w h u d l docid025409 rev 2 105/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 6.3.21 comparator characteristics table 69. comparator characteristics (1) symbol parameter conditions min. typ. max. unit v dda analog supply voltage - 2 - 3.6 v v in comparator input voltage range -0-v dda v bg scaler input voltage - - v refinit - v sc scaler offset voltage - - 5 10 mv t s_sc scaler startup time from power down ---1s t start comparator startup time v dda ? 2.7 v - - 4 s v dda ? 2.7 v - - 10 t d propagation delay for ? 200 mv step with 100 mv overdrive v dda ? 2.7 v - 25 28 ns ? v dda ? 2.7 v - 28 30 propagation delay for full range step with 100 mv overdrive v dda ? 2.7 v - 32 35 ? v dda ? 2.7 v - 35 40 v offset comparator offset error v dda ? 2.7 v - ? 5 ? 10 mv ? v dda ? 2.7 v - - ? 25 tv offset total offset variation full temperature range - - 3 mv i dd(comp) comp current consumption - - 400 600 a 1. guaranteed by design, not tested in production. electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 106/124 docid025409 rev 2 6.3.22 operational am plifier char acteristics table 70. operational amplifier characteristics (1) symbol parameter condition min. typ. max. unit v dda analog supply voltage - 2.4 - 3.6 v cmir common mode input range - 0 - v dda v vi offset input offset voltage maximum ? calibration range 25c, no load on output. --4 mv all voltage/temp. --6 after offset ? calibration 25c, no load on output. --1.6 all voltage/temp. --3 ? vi offset input offset voltage drift - - 5 - v/c i load drive current - - - 500 a iddopamp consumption no load, ? quiescent mode - 690 1450 a cmrr common mode rejection ratio - - 90 - db psrr power supply rejection ratio dc 73 117 - db gbw bandwidth - - 8.2 - mhz sr slew rate - - 4.7 - v/s r load resistive load - 4 - - k ? c load capacitive load - - - 50 pf voh sat high saturation voltage r load = min, input at v dda . - - 100 mv r load = 20k, input at v dda . --20 vol sat low saturation voltage r load = min, input at 0 v - - 100 r load = 20k, input at 0 v. --20 ? m phase margin - - 62 - t offtrim offset trim time: during calibration, ? minimum time needed between two ? steps to have 1 mv accuracy ---2ms t wakeup wake up time from off state. c load ?? 50 pf, ? r load ? 4 k ??? follower configuration -2.85s t s_opam_vout adc sampling time when reading the opamp output 400 - - ns docid025409 rev 2 107/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 pga gain non inverting gain value - -2-- -4-- -8-- -16-- r network r2/r1 internal resistance values in pga mode (2) gain=2 - 5.4/5.4 - k ? gain=4 - 16.2/5.4 - gain=8 - 37.8/5.4 - gain=16 - 40.5/2.7 - pga gain error pga gain error - -1% - 1% i bias opamp input bias current - - - ? 0.2 (3) a pga bw pga bandwidth for different non inverting gain pga gain = 2, c load = 50pf, r load = 4 k ? -4- mhz pga gain = 4, c load = 50pf, r load = 4 k ? -2- pga gain = 8, c load = 50pf, r load = 4 k ? -1- pga gain = 16, c load = 50pf, r load = 4 k ? -0.5- en voltage noise density @ 1khz, output loaded with 4 k ? -109- @ 10khz, output loaded with 4 k ? -43- 1. guaranteed by design, not tested in production. 2. r2 is the internal resistance between opamp output and opamp inverting input. ? r1 is the internal resistance between opamp inverting input and ground. ? the pga gain =1+r2/r1 3. mostly tta i/o leakage, when used in analog mode. table 70. operational amplifier characteristics (1) (continued) symbol parameter condition min. typ. max. unit nv hz ----------- electrical characteristics stm32f334x4 stm32f334x6 stm32f334x8 108/124 docid025409 rev 2 figure 31. opamp voltage noise versus frequency docid025409 rev 2 109/124 stm32f334x4 stm32f334x6 stm32f334x8 electrical characteristics 109 6.3.23 temperature sens or (ts) characteristics 6.3.24 v bat monitoring characteristics table 71. temperature sensor (ts) characteristics symbol parameter min. typ. max. unit t l (1) 1. guaranteed by design, not tested in production. v sense linearity with temperature - ? 1 ? 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 voltage at 25 c 1.34 1.43 1.52 v t start (1) startup time 4 - 10 s t s_temp (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 2.2 - - s table 72. temperature sensor (ts) calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, ? v dda = 3.3 v 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at temperature of 110 c ? v dda = 3.3 v 0x1fff f7c2 - 0x1fff f7c3 table 73. v bat monitoring characteristics symbol parameter min. typ. max. unit r resistor bridge for v bat -50-k ? qratio on v bat measurement - 2 - er (1) 1. guaranteed by design, not tested in production. error on q -1 - +1 % t s_vbat (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the v bat 1mv accuracy 2.2 - - s package characteristics stm32f334x4 stm32f334x6 stm32f334x8 110/124 docid025409 rev 2 7 package characteristics 7.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. docid025409 rev 2 111/124 stm32f334x4 stm32f334x6 stm32f334x8 package characteristics 121 figure 32. lqfp32 ? 7 x 7mm, 32-pin low-profile quad flat package outline 1. drawing is not to scale. table 74. lqfp32 ? 7 x 7mm, 32-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.300 0.370 0.450 0.0118 0.0146 0.0177 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 ' ' ' ( ( ( $ / / . $ $ $ f e * $ 8 * ( 3 / $ 1 ( p p 6 ( $ 7 , 1 * 3 / $ 1 ( & 3 , 1 , ' ( 1 7 , ) , & $ 7 , 2 1 f f f & 7 @ . & @ 7 h package characteristics stm32f334x4 stm32f334x6 stm32f334x8 112/124 docid025409 rev 2 figure 33. lqfp32 recommended footprint 1. drawing is not to scale. 2. dimensions are expr essed in millimeters. d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.600 - - 0.2205 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.600 - - 0.2205 - e - 0.800 - - 0.0315 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.100 - - 0.0039 1. values in inches are converted fr om mm and rounded to 4 decimal digits. table 74. lqfp32 ? 7 x 7mm, 32-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. 9 b ) 3 b 9 docid025409 rev 2 113/124 stm32f334x4 stm32f334x6 stm32f334x8 package characteristics 121 marking of engineering samples figure 34. lqfp32 marking example (package top view) 1. parts marked as ?es?,?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 6 7 0 ) . 7 < : : 5 3 u r g x f w , g h q w l i l f d w l r q 5 h y l v l r q f r g h 3 l q l q g h q w l i l h u package characteristics stm32f334x4 stm32f334x6 stm32f334x8 114/124 docid025409 rev 2 figure 35. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package outline 1. drawing is not to scale. % b 0 ( b 9 3 , 1 , ' ( 1 7 , ) , & $ 7 , 2 1 f f f & & ' p p * $ 8 * ( 3 / $ 1 ( e $ $ $ f $ / / ' ' ( ( ( h 6 ( $ 7 , 1 * 3 / $ 1 ( . table 75. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - docid025409 rev 2 115/124 stm32f334x4 stm32f334x6 stm32f334x8 package characteristics 121 figure 36. lqfp48 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 75. lqfp48 ? 7 x 7 mm, 48-pin low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max d l g package characteristics stm32f334x4 stm32f334x6 stm32f334x8 116/124 docid025409 rev 2 marking of engineering samples figure 37. lqfp48 marking example (package top view) 1. parts marked as ?es?,?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 6 7 0 ) & 7 < : : 5 3 u r g x f w , g h q w l i l f d w l r q 5 h y l v l r q f r g h 3 l q l q g h q w l i l h u docid025409 rev 2 117/124 stm32f334x4 stm32f334x6 stm32f334x8 package characteristics 121 figure 38. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package outline 1. drawing is not to scale. : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p table 76. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 11.800 12.000 - - 0.4724 - d1 9.800 10.000 - - 0.3937 - e - 12.000 - - 0.4724 - e1 - 10.000 - - 0.3937 - e - 0.500 - - 0.0197 - ? 0 3.5 7 0 3.5 7 l 0.450 0.600 0.750 0.0177 0.0236 0.0295 package characteristics stm32f334x4 stm32f334x6 stm32f334x8 118/124 docid025409 rev 2 figure 39. lqfp64 recommended footprint 1. drawing is not to scale. 2. dimensions are in millimeters. l1 - 1.000 - - 0.0394 - n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits. table 76. lqfp64 ? 10 x 10 mm, 64-pin low-profile quad flat pack age mechanical data (continued) symbol millimeters inches (1) min typ max min typ max d l f docid025409 rev 2 119/124 stm32f334x4 stm32f334x6 stm32f334x8 package characteristics 121 marking of engineering samples figure 40. lqfp64 marking example (package top view) 1. parts marked as ?es?,?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 5 6 7 0 ) 5 7 < : : ( q j l q h h u l q j 6 d p s o h p d u n l q j 5 h y l v l r q f r g h 3 l q l q g h q w l i l h u package characteristics stm32f334x4 stm32f334x6 stm32f334x8 120/124 docid025409 rev 2 7.2 thermal characteristics the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ? ja ) where: ? t a max is the maximum ambient temperature in ? c, ?? ja is the package junction-to-ambient thermal resistance, in ? c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = ?? (v ol i ol ) + ? ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org. table 77. package thermal characteristics symbol parameter value unit ? ja thermal resistance junction-ambient ? lqfp64 - 10 10 mm / 0.5 mm pitch 45c/w c/w ? ja thermal resistance junction-ambient ? lqfp48 - 7 7 mm / 0.5 mm pitch 55c/w c/w ? ja thermal resistance junction-ambient ? lqfp32 - 7 7 mm / 0.8 mm pitch 60c/w c/w docid025409 rev 2 121/124 stm32f334x4 stm32f334x6 stm32f334x8 package characteristics 121 7.2.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in table 78: ordering information scheme . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a spec ific maximum junction temperature. as applications do not commonly use the stm32f 334x4/6/8 at maximum dissipation, it is useful to calculate the exact power consumpt ion and junction temperature to determine which temperature range will be best suit ed to the application. the following examples show how to calculat e the temperature range needed for a given application. example: high-performance application assuming the following ap plication conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 20 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 8 i/os used at the same time in output mode at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v = 175 mw p iomax = 20 8 ma 0.4 v + 8 20 ma 1.3 v = 272 mw this gives: p intmax = 175 mw and p iomax = 272 mw p dmax = 175 + 272 = 447 mw thus: p dmax = 447 mw using the values obtained in table 77 t jmax is calculated as follows: ? for lqfp64, 45 c/w t jmax = 82 c + (45 c/w 447 mw) = 82 c + 20.1 c = 102.1 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at leas t with the temperature range suffix 6 (see table 78: ordering information scheme ). part numbering stm32f334x4 stm32f334x6 stm32f334x8 122/124 docid025409 rev 2 8 part numbering table 78. ordering information scheme example: stm32 f 334 c 8 t 6 xxx device family stm32 = arm ? -based 32-bit microcontroller product type f = general-purpose device subfamily 334 = stm32f334xx pin count k = 32 pins c = 48 r = 64 pins flash memory size 4 = 16 kbytes of flash memory 6 = 32 kbytes of flash memory 8 = 64 kbytes of flash memory package t = lqfp temperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105 c options xxx = programmed parts tr = tape and reel docid025409 rev 2 123/124 stm32f334x4 stm32f334x6 stm32f334x8 revision history 123 9 revision history table 79. document revision history date revision changes 19-jun-2014 1 initial release. 09-dec-2014 2 updated: table 58: timx characteristics table 13: stm32f334x4/6/8 pin definitions table 63: adc characteristics table 33: peripheral current consumption table 39: hsi oscillator characteristics figure 17: hsi oscillator accuracy characterization results for soldered parts table 2: stm32f334x4/6/8 fa mily device features and peripheral counts stm32f334x4 stm32f334x6 stm32f334x8 124/124 docid025409 rev 2 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved |
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